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Initial upload of KL520 SDK 2.2

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Dereck Hao 2025-12-17 15:55:25 +08:00
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185
app/demo_customize_inf_multiple_models.c Normal file
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/*
* Kneron Application general functions
*
* Copyright (C) 2021 Kneron, Inc. All rights reserved.
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "model_type.h"
#include "model_res.h"
#include "kmdw_console.h"
#include "kmdw_inference_app.h"
#include "kmdw_fifoq_manager.h"
#include "demo_customize_inf_multiple_models.h"
#define TY_MAX_BOX_NUM (50)
#define FACE_SCORE_THRESHOLD 0.8f
// for face detection result, should be in DDR
static struct yolo_result_s *fd_result = NULL;
static int inference_face_detection(demo_customize_inf_multiple_models_header_t *input_header,
struct yolo_result_s *fd_result /* output */)
{
// config image preprocessing and model settings
kmdw_inference_app_config_t inf_config;
memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false'
// image buffer address should be just after the header
inf_config.num_image = 1;
inf_config.image_list[0].image_buf = (void *)((uint32_t)input_header + sizeof(demo_customize_inf_multiple_models_header_t));
inf_config.image_list[0].image_width = input_header->width;
inf_config.image_list[0].image_height = input_header->height;
inf_config.image_list[0].image_channel = 3; // assume RGB565
inf_config.image_list[0].image_format = KP_IMAGE_FORMAT_RGB565; // assume RGB565
inf_config.image_list[0].image_resize = KP_RESIZE_ENABLE; // enable resize
inf_config.image_list[0].image_padding = KP_PADDING_CORNER; // enable padding on corner
inf_config.image_list[0].image_norm = KP_NORMALIZE_KNERON; // this depends on model
inf_config.model_id = KNERON_FD_MASK_MBSSD_200_200_3; // this depends on model
// set up fd result output buffer for ncpu/npu
inf_config.ncpu_result_buf = (void *)fd_result;
return kmdw_inference_app_execute(&inf_config);
}
static int inference_face_landmarks(demo_customize_inf_multiple_models_header_t *input_header,
struct bounding_box_s *face_box,
kp_landmark_result_t *lm_result /* output */)
{
// config image preprocessing and model settings
kmdw_inference_app_config_t inf_config;
memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false'
int32_t left = (int32_t)(face_box->x1);
int32_t top = (int32_t)(face_box->y1);
int32_t right = (int32_t)(face_box->x2);
int32_t bottom = (int32_t)(face_box->y2);
// image buffer address should be just after the header
inf_config.model_id = KNERON_LM_5PTS_ONET_56_56_3; // this depends on model
inf_config.num_image = 1;
inf_config.image_list[0].image_buf = (void *)((uint32_t)input_header + sizeof(demo_customize_inf_multiple_models_header_t));
inf_config.image_list[0].image_width = input_header->width;
inf_config.image_list[0].image_height = input_header->height;
inf_config.image_list[0].image_channel = 3; // assume RGB565
inf_config.image_list[0].image_format = KP_IMAGE_FORMAT_RGB565; // assume RGB565
inf_config.image_list[0].image_norm = KP_NORMALIZE_KNERON; // this depends on model
inf_config.image_list[0].image_resize = KP_RESIZE_ENABLE; // enable resize
inf_config.image_list[0].image_padding = KP_PADDING_CORNER; // enable padding on corner
inf_config.image_list[0].enable_crop = true; // enable crop image in ncpu/npu
// set crop box
inf_config.image_list[0].crop_area.crop_number = 0;
inf_config.image_list[0].crop_area.x1 = left;
inf_config.image_list[0].crop_area.y1 = top;
inf_config.image_list[0].crop_area.width = right - left;
inf_config.image_list[0].crop_area.height = bottom - top;
// set up landmark result output buffer for ncpu/npu
inf_config.ncpu_result_buf = (void *)lm_result;
return kmdw_inference_app_execute(&inf_config);
}
static bool init_temp_buffer()
{
// allocate DDR memory for ncpu/npu output restult
fd_result = (struct yolo_result_s *)kmdw_ddr_reserve(sizeof(struct yolo_result_s) + TY_MAX_BOX_NUM * sizeof(struct bounding_box_s));
if (fd_result == NULL) {
return false;
}
return true;
}
void demo_customize_inf_multiple_models(uint32_t job_id, int num_input_buf, void **inf_input_buf_list)
{
if (1 != num_input_buf) {
kmdw_inference_app_send_status_code(job_id, KP_FW_WRONG_INPUT_BUFFER_COUNT_110);
return;
}
// 'inf_input_buf' and 'inf_result_buf' are provided by kdp2 middleware
// the content of 'inf_input_buf' is transmitted from host SW = header + image
// 'inf_result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu)
// now get an available free result buffer
// normally the begin part of result buffer should contain app-defined result header
// and the rest is for ncpu/npu inference output data
int inf_status;
int result_buf_size;
void *inf_result_buf = kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size);
demo_customize_inf_multiple_models_header_t *input_header = (demo_customize_inf_multiple_models_header_t *)inf_input_buf_list[0];
demo_customize_inf_multiple_models_result_t *output_result = (demo_customize_inf_multiple_models_result_t *)inf_result_buf;
// pre set up result header stuff
// header_stamp is a must to correctly transfer result data back to host SW
output_result->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE;
output_result->header_stamp.total_size = sizeof(demo_customize_inf_multiple_models_result_t);
output_result->header_stamp.job_id = job_id;
// this app needs extra DDR buffers for ncpu result
static bool is_init = false;
if (!is_init) {
int status = init_temp_buffer();
if (!status) {
// notify host error !
output_result->header_stamp.status_code = KP_FW_DDR_MALLOC_FAILED_102;
kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false);
return;
}
is_init = true;
}
// do face detection
inf_status = inference_face_detection(input_header, fd_result);
if (inf_status != KP_SUCCESS) {
// notify host error !
output_result->header_stamp.status_code = inf_status;
kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false);
return;
}
int face_cnt = 0;
int max_face = (fd_result->box_count > FD_MAX) ? FD_MAX : fd_result->box_count;
for (int i = 0; i < max_face; i++) {
struct bounding_box_s *face_box = &fd_result->boxes[i];
kp_landmark_result_t *face_lm_result = &output_result->faces[face_cnt].lm;
if (FACE_SCORE_THRESHOLD < face_box->score) {
// do face landmark for each faces
inf_status = inference_face_landmarks(input_header, face_box, face_lm_result);
if (KP_SUCCESS != inf_status) {
// notify host error !
output_result->header_stamp.status_code = inf_status;
kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false);
return;
}
// skip it if face lm is not good
if (0.99f > face_lm_result->score) {
continue;
}
memcpy(&output_result->faces[face_cnt].fd, face_box, sizeof(kp_bounding_box_t));
face_cnt++;
}
}
output_result->face_count = face_cnt;
output_result->header_stamp.status_code = KP_SUCCESS;
kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false);
}

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#pragma once
#define DEMO_KL520_CUSTOMIZE_INF_MULTIPLE_MODEL_JOB_ID 1001
#define FD_MAX 10
typedef struct
{
kp_bounding_box_t fd; /**< fd result */
kp_landmark_result_t lm; /**< lm result */
} __attribute__((aligned(4))) one_person_face_data_t;
typedef struct
{
/* header stamp is necessary for data transfer between host and device */
kp_inference_header_stamp_t header_stamp;
uint32_t width;
uint32_t height;
} __attribute__((aligned(4))) demo_customize_inf_multiple_models_header_t;
// result (header + data) for 'Kneron APP Yolo Inference'
typedef struct
{
/* header stamp is necessary for data transfer between host and device */
kp_inference_header_stamp_t header_stamp;
uint32_t face_count;
one_person_face_data_t faces[FD_MAX];
} __attribute__((aligned(4))) demo_customize_inf_multiple_models_result_t;
void demo_customize_inf_multiple_models(uint32_t job_id, int num_input_buf, void **inf_input_buf_list);

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/*
* Kneron Application general functions
*
* Copyright (C) 2021 Kneron, Inc. All rights reserved.
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "model_type.h"
#include "kmdw_console.h"
#include "kmdw_inference_app.h"
#include "kmdw_fifoq_manager.h"
#include "demo_customize_inf_single_model.h"
/**
* @brief describe a yolo post-process configurations for yolo v5 series
*/
typedef struct
{
float prob_thresh;
float nms_thresh;
uint32_t max_detection_per_class;
uint16_t anchor_row;
uint16_t anchor_col;
uint16_t stride_size;
uint16_t reserved_size;
uint32_t data[40];
} __attribute__((aligned(4))) kp_app_yolo_post_proc_config_t;
static kp_app_yolo_post_proc_config_t post_proc_params_v3 = {
.prob_thresh = 0.2,
.nms_thresh = 0.45,
.max_detection_per_class = YOLO_GOOD_BOX_MAX,
.anchor_row = 3,
.anchor_col = 6,
.stride_size = 3,
.reserved_size = 0,
.data = {
// anchors[3][6]
81, 82, 135, 169, 344, 319,
23, 27, 37, 58, 81, 82,
0, 0, 0, 0, 0, 0, // -> not used in tiny yolo v3 post-proc
// strides[3] -> not used in tiny yolo v3 post-proc
8, 16, 32,
},
};
void demo_customize_inf_single_model(uint32_t job_id, int num_input_buf, void **inf_input_buf_list)
{
if (1 != num_input_buf) {
kmdw_inference_app_send_status_code(job_id, KP_FW_WRONG_INPUT_BUFFER_COUNT_110);
return;
}
// 'inf_input_buf' and 'inf_result_buf' are provided by kdp2 middleware
// the content of 'inf_input_buf' is transmitted from host SW = header + image
// 'inf_result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu)
// now get an available free result buffer
// normally the begin part of result buffer should contain app-defined result header
// and the rest is for ncpu/npu inference output data
int result_buf_size;
void *inf_result_buf = kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size);
demo_customize_inf_single_model_header_t *input_header = (demo_customize_inf_single_model_header_t *)inf_input_buf_list[0];
demo_customize_inf_single_model_result_t *output_result = (demo_customize_inf_single_model_result_t *)inf_result_buf;
// config image preprocessing and model settings
kmdw_inference_app_config_t inf_config;
memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false'
// image buffer address should be just after the header
inf_config.num_image = 1;
inf_config.image_list[0].image_buf = (void *)((uint32_t)input_header + sizeof(demo_customize_inf_single_model_header_t));
inf_config.image_list[0].image_width = input_header->width;
inf_config.image_list[0].image_height = input_header->height;
inf_config.image_list[0].image_channel = 3; // assume RGB565
inf_config.image_list[0].image_format = KP_IMAGE_FORMAT_RGB565; // assume RGB565
inf_config.image_list[0].image_norm = KP_NORMALIZE_KNERON; // this depends on model
inf_config.image_list[0].image_resize = KP_RESIZE_ENABLE; // enable resize
inf_config.image_list[0].image_padding = KP_PADDING_CORNER; // enable padding on corner
inf_config.model_id = TINY_YOLO_V3_224_224_3; // this depends on model
inf_config.ncpu_result_buf = (void *)&(output_result->yolo_result); // give result buffer for ncpu/npu, callback will carry it
inf_config.user_define_data = (void *)&post_proc_params_v3; // yolo post-process configurations for yolo v3 series
// run preprocessing and inference, trigger ncpu/npu to do the work
// if enable_parallel=true (works only for single model), result callback is needed
// however if inference error then no callback will be invoked
int inf_status = kmdw_inference_app_execute(&inf_config);
// header_stamp is a must to correctly transfer result data back to host SW
output_result->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE;
output_result->header_stamp.total_size = sizeof(demo_customize_inf_single_model_result_t);
output_result->header_stamp.job_id = job_id;
output_result->header_stamp.status_code = inf_status;
// send output result buffer back to host SW
kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false);
}

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#pragma once
#define DEMO_KL520_CUSTOMIZE_INF_SINGLE_MODEL_JOB_ID 1000
#define YOLO_BOX_MAX 100 /**< maximum number of bounding boxes for Yolo models */
/**
* @brief describe a yolo output result after post-processing
*/
typedef struct
{
uint32_t class_count; /**< total class count */
uint32_t box_count; /**< boxes of all classes */
kp_bounding_box_t boxes[YOLO_BOX_MAX]; /**< box information */
} __attribute__((aligned(4))) kp_custom_yolo_result_t;
typedef struct
{
/* header stamp is necessary for data transfer between host and device */
kp_inference_header_stamp_t header_stamp;
uint32_t width;
uint32_t height;
} __attribute__((aligned(4))) demo_customize_inf_single_model_header_t;
// result (header + data) for 'Kneron APP Yolo Inference'
typedef struct
{
/* header stamp is necessary for data transfer between host and device */
kp_inference_header_stamp_t header_stamp;
kp_custom_yolo_result_t yolo_result;
} __attribute__((aligned(4))) demo_customize_inf_single_model_result_t;
void demo_customize_inf_single_model(uint32_t job_id, int num_input_buf, void **inf_input_buf_list);

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/*
* Kneron Application general functions
*
* Copyright (C) 2021 Kneron, Inc. All rights reserved.
*
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "kmdw_console.h"
#include "kmdw_inference_app.h"
#include "kmdw_fifoq_manager.h"
#include "kdp2_inf_app_yolo.h"
#include "model_type.h"
static kp_app_yolo_post_proc_config_t post_proc_params_v5s = {
.prob_thresh = 0.15,
.nms_thresh = 0.5,
.max_detection_per_class = YOLO_GOOD_BOX_MAX,
.anchor_row = 3,
.anchor_col = 6,
.stride_size = 3,
.reserved_size = 0,
.data = {
// anchors[3][6]
10, 13, 16, 30, 33, 23,
30, 61, 62, 45, 59, 119,
116, 90, 156, 198, 373, 326,
// strides[3]
8, 16, 32,
},
};
static kp_app_yolo_post_proc_config_t post_proc_params_v5s6_480_256_3 = {
.prob_thresh = 0.3,
.nms_thresh = 0.65,
.max_detection_per_class = YOLO_GOOD_BOX_MAX,
.anchor_row = 3,
.anchor_col = 6,
.stride_size = 3,
.reserved_size = 0,
.data = {
// anchors[3][6]
7, 7, 13, 9, 9, 20,
19, 15, 30, 24, 18, 45,
48, 34, 90, 61, 156, 131,
// strides[3]
8, 16, 32,
},
};
static kp_app_yolo_post_proc_config_t post_proc_params_v5m = {
.prob_thresh = 0.3,
.nms_thresh = 0.45,
.max_detection_per_class = YOLO_GOOD_BOX_MAX,
.anchor_row = 3,
.anchor_col = 6,
.stride_size = 3,
.reserved_size = 0,
.data = {
// anchors[3][6]
10, 13, 16, 30, 33, 23,
30, 61, 62, 45, 59, 119,
116, 90, 156, 198, 373, 326,
// strides[3]
8, 16, 32,
},
};
static kp_app_yolo_post_proc_config_t post_proc_params_v3 = {
.prob_thresh = 0.2,
.nms_thresh = 0.45,
.max_detection_per_class = YOLO_GOOD_BOX_MAX,
.anchor_row = 3,
.anchor_col = 6,
.stride_size = 3,
.reserved_size = 0,
.data = {
// anchors[3][6]
81, 82, 135, 169, 344, 319,
23, 27, 37, 58, 81, 82,
4, 9, 13, 24, 24, 50, // -> not used in tiny yolo v3 post-proc
// strides[3] -> not used in tiny yolo v3 post-proc
8, 16, 32,
},
};
typedef struct
{
int model_id;
int param_size;
void *post_proc_params;
} map_model_post_proc_t;
#define MAX_MODEL_PAIRS 4
static map_model_post_proc_t model_pp[MAX_MODEL_PAIRS] = {0}; // 4 pairs of modle-post_proc enough ?
static map_model_post_proc_t get_model_post_proc_param(int model_id)
{
map_model_post_proc_t mapping = {0};
// looking for model's post-proc params, if none apply some defaults
for (int i = 0; i < MAX_MODEL_PAIRS; i++)
{
if (model_pp[i].model_id == model_id)
{
// found matched model id with post-proc params
mapping = model_pp[i];
break;
}
else if (model_pp[i].model_id == 0)
{
// register some default settings
model_pp[i].model_id = model_id;
switch (model_id)
{
case KNERON_YOLOV5S_COCO80_640_640_3:
case KNERON_YOLOV5S_PersonBottleChairPottedplant4_640_288_3:
model_pp[i].param_size = sizeof(post_proc_params_v5s);
model_pp[i].post_proc_params = (void *)&post_proc_params_v5s;
break;
case KNERON_YOLOV5S_PersonBicycleCarMotorcycleBusTruck6_480_256_3:
model_pp[i].param_size = sizeof(post_proc_params_v5s6_480_256_3);
model_pp[i].post_proc_params = (void *)&post_proc_params_v5s6_480_256_3;
break;
case KNERON_YOLOV5m_COCO80_640_640_3:
case KNERON_PERSONDETECTION_YOLOV5s_480_256_3:
case KNERON_PERSONDETECTION_YOLOV5sParklot_480_256_3:
model_pp[i].param_size = sizeof(post_proc_params_v5m);
model_pp[i].post_proc_params = (void *)&post_proc_params_v5m;
break;
case TINY_YOLO_V3_224_224_3:
case TINY_YOLO_V3_416_416_3:
case TINY_YOLO_V3_608_608_3:
model_pp[i].param_size = sizeof(post_proc_params_v3);
model_pp[i].post_proc_params = (void *)&post_proc_params_v3;
break;
default:
// cannot find matched post-proc config
break;
}
mapping = model_pp[i];
break;
}
}
return mapping;
}
void kdp2_app_yolo_config_post_process_parameters(uint32_t job_id, int num_input_buf, void **inf_input_buf_list)
{
if (1 != num_input_buf) {
kmdw_inference_app_send_status_code(job_id, KP_FW_WRONG_INPUT_BUFFER_COUNT_110);
return;
}
kdp2_ipc_app_yolo_post_proc_config_t *yolo_pp_config = (kdp2_ipc_app_yolo_post_proc_config_t *)inf_input_buf_list[0];
if (yolo_pp_config->set_or_get == 1)
{
// setting post-proc configs with specified model_id
for (int i = 0; i < MAX_MODEL_PAIRS; i++)
{
if (model_pp[i].model_id == yolo_pp_config->model_id || model_pp[i].model_id == 0)
{
model_pp[i].model_id = yolo_pp_config->model_id; // for model_pp[i].model_id == 0
if (model_pp[i].post_proc_params == NULL || yolo_pp_config->param_size > model_pp[i].param_size)
{
model_pp[i].post_proc_params = malloc(yolo_pp_config->param_size);
if (model_pp[i].post_proc_params == NULL)
{
kmdw_printf("[app_yolo]: error ! no memory for malloc post-proc parameters\n");
kmdw_inference_app_send_status_code(job_id, KP_FW_CONFIG_POST_PROC_ERROR_MALLOC_FAILED_105);
return; // failed return
}
model_pp[i].param_size = yolo_pp_config->param_size;
}
memcpy(model_pp[i].post_proc_params, (void *)yolo_pp_config->param_data, yolo_pp_config->param_size);
kmdw_inference_app_send_status_code(job_id, KP_SUCCESS);
return; // sucessful return
}
}
kmdw_inference_app_send_status_code(job_id, KP_FW_CONFIG_POST_PROC_ERROR_NO_SPACE_106);
return; // failed return
}
else
{
// getting post-proc configs with specified model_id
// get a result buffer to save pp parameters
int result_buf_size;
kdp2_ipc_app_yolo_post_proc_config_t *return_pp_config = (kdp2_ipc_app_yolo_post_proc_config_t *)kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size);
map_model_post_proc_t mapping = get_model_post_proc_param(yolo_pp_config->model_id);
return_pp_config->header_stamp = yolo_pp_config->header_stamp;
return_pp_config->header_stamp.status_code = KP_SUCCESS;
return_pp_config->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_post_proc_config_t);
return_pp_config->set_or_get = 0;
return_pp_config->model_id = yolo_pp_config->model_id;
return_pp_config->param_size = mapping.param_size;
if (mapping.param_size > 0)
memcpy((void *)return_pp_config->param_data, mapping.post_proc_params, mapping.param_size);
// send pp params back to host SW
kmdw_fifoq_manager_result_enqueue((void *)return_pp_config, result_buf_size, false);
}
}
void kdp2_app_yolo_result_callback(int status, void *inf_result_buf, int inf_result_buf_size, void *ncpu_result_buf)
{
// when ncpu has done post-process then it comes to here with inference result buffer filled
// 'inf_result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu)
// 'ncpu_result_buf' is post-processing result buffer done by ncpu
// normally 'inf_result_buf' contains 'ncpu_result_buf', and user should send 'inf_result_buf' to host SW
kdp2_ipc_app_yolo_result_t *app_yolo_result = (kdp2_ipc_app_yolo_result_t *)inf_result_buf;
kp_app_yolo_result_t *yolo_data = (kp_app_yolo_result_t *)ncpu_result_buf;
if (status != KP_SUCCESS)
{
app_yolo_result->header_stamp.status_code = status;
app_yolo_result->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_result_t) - sizeof(kp_app_yolo_result_t);
// send error status result back to host
kmdw_fifoq_manager_result_enqueue((void *)inf_result_buf, inf_result_buf_size, false);
return;
}
if (yolo_data->box_count > YOLO_GOOD_BOX_MAX)
{
kmdw_printf("[app_yolo]: error ! too many bounding boxes = %d!!!\n", yolo_data->box_count);
yolo_data->box_count = YOLO_GOOD_BOX_MAX;
}
app_yolo_result->header_stamp.status_code = KP_SUCCESS;
app_yolo_result->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_result_t) - sizeof(kp_app_yolo_result_t) +
sizeof(yolo_data->class_count) + sizeof(yolo_data->box_count) + yolo_data->box_count * sizeof(kp_bounding_box_t);
// send output result buffer back to host SW
kmdw_fifoq_manager_result_enqueue((void *)inf_result_buf, inf_result_buf_size, false);
}
void kdp2_app_yolo_inference(uint32_t job_id, int num_input_buf, void **inf_input_buf_list)
{
if (1 != num_input_buf) {
kmdw_inference_app_send_status_code(job_id, KP_FW_WRONG_INPUT_BUFFER_COUNT_110);
return;
}
// 'inf_input_buf' and 'inf_result_buf' are provided by kdp2 middleware
// the content of 'inf_input_buf' is transmitted from host SW = header + image
// 'inf_result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu)
// now get an available free result buffer
// normally the begin part of result buffer should contain app-defined result header
// and the rest is for ncpu/npu inference output data
int result_buf_size;
void *inf_result_buf = kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size);
kdp2_ipc_app_yolo_inf_header_t *app_yolo_header = (kdp2_ipc_app_yolo_inf_header_t *)inf_input_buf_list[0];
kdp2_ipc_app_yolo_result_t *app_yolo_result = (kdp2_ipc_app_yolo_result_t *)inf_result_buf;
// config image preprocessing and model settings
kmdw_inference_app_config_t inf_config;
memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false'
// image buffer address should be just after the header
inf_config.num_image = 1;
inf_config.image_list[0].image_buf = (void *)((uint32_t)app_yolo_header + sizeof(kdp2_ipc_app_yolo_inf_header_t));
inf_config.image_list[0].image_width = app_yolo_header->width;
inf_config.image_list[0].image_height = app_yolo_header->height;
inf_config.image_list[0].image_channel = app_yolo_header->channel;
inf_config.image_list[0].image_format = app_yolo_header->image_format;
inf_config.image_list[0].image_norm = app_yolo_header->model_normalize;
inf_config.image_list[0].image_resize = KP_RESIZE_ENABLE; // enable resize
inf_config.image_list[0].image_padding = KP_PADDING_CORNER; // enable padding on corner
inf_config.image_list[0].pad_value = NULL;
inf_config.model_id = app_yolo_header->model_id;
inf_config.enable_parallel = true; // only works for single model and post-process in ncpu
inf_config.inf_result_buf = inf_result_buf; // for callback
inf_config.inf_result_buf_size = result_buf_size; //
inf_config.ncpu_result_buf = (void *)&(app_yolo_result->yolo_data); // give result buffer for ncpu/npu, callback will carry it
inf_config.result_callback = kdp2_app_yolo_result_callback;
map_model_post_proc_t mapping = get_model_post_proc_param(inf_config.model_id);
inf_config.user_define_data = mapping.post_proc_params; // FIXME: if NULL what happen ?
// pre-set something for result output
// header_stamp is a must to correctly transfer result data back to host SW
app_yolo_result->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE;
app_yolo_result->header_stamp.total_size = 0;
app_yolo_result->header_stamp.job_id = job_id;
app_yolo_result->inf_number = app_yolo_header->inf_number; // sync the inference number
// run preprocessing and inference, trigger ncpu/npu to do the work
// if enable_parallel=true (works only for single model), result callback is needed
// however if inference error then no callback will be invoked
int ret = kmdw_inference_app_execute(&inf_config);
if (ret != KP_SUCCESS)
{
// some sort of inference error
app_yolo_result->header_stamp.status_code = ret;
app_yolo_result->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_result_t) - sizeof(kp_app_yolo_result_t);
// send error status result back to host
kmdw_fifoq_manager_result_enqueue((void *)inf_result_buf, result_buf_size, false);
}
}

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#pragma once
#define KDP2_INF_ID_APP_YOLO 11
#define KDP2_JOB_ID_APP_YOLO_CONFIG_POST_PROC 100 // handle set or get
typedef struct
{
uint32_t model_id; // specify model id
kp_normalize_mode_t model_norm; // specify model normalization
} __attribute__((aligned(4))) kp_app_yolo_config_t;
/**
* @brief describe a yolo post-process configurations for yolo v5 series
*/
typedef struct
{
float prob_thresh;
float nms_thresh;
uint32_t max_detection_per_class;
uint16_t anchor_row;
uint16_t anchor_col;
uint16_t stride_size;
uint16_t reserved_size;
uint32_t data[40];
} __attribute__((aligned(4))) kp_app_yolo_post_proc_config_t;
#define YOLO_GOOD_BOX_MAX 100 /**< maximum number of bounding boxes for Yolo models */
/**
* @brief describe a yolo output result after post-processing
*/
typedef struct
{
uint32_t class_count; /**< total class count */
uint32_t box_count; /**< boxes of all classes */
kp_bounding_box_t boxes[YOLO_GOOD_BOX_MAX]; /**< box information */
} __attribute__((aligned(4))) kp_app_yolo_result_t;
/********** KDP2_INF_ID_APP_YOLO **********/
// post-proc config data struct shared for setting or getting
typedef struct
{
/* header stamp is necessary for data transfer between host and device */
kp_inference_header_stamp_t header_stamp;
uint32_t set_or_get; // get = 0, set = 1
uint32_t model_id;
uint32_t param_size;
uint8_t param_data[200]; // contains kp_app_yolo_post_proc_config_*** body
} __attribute__((aligned(4))) kdp2_ipc_app_yolo_post_proc_config_t;
// input header for 'Kneron APP Yolo Inference'
typedef struct
{
/* header stamp is necessary for data transfer between host and device */
kp_inference_header_stamp_t header_stamp;
uint32_t inf_number;
uint32_t width;
uint32_t height;
uint32_t channel;
uint32_t model_id;
uint32_t image_format; // kp_image_format_t
uint32_t model_normalize; // kp_normalize_mode_t
} __attribute__((aligned(4))) kdp2_ipc_app_yolo_inf_header_t;
// result (header + data) for 'Kneron APP Yolo Inference'
typedef struct
{
/* header stamp is necessary for data transfer between host and device */
kp_inference_header_stamp_t header_stamp;
uint32_t inf_number;
kp_app_yolo_result_t yolo_data;
} __attribute__((aligned(4))) kdp2_ipc_app_yolo_result_t;
void kdp2_app_yolo_config_post_process_parameters(uint32_t job_id, int num_input_buf, void **inf_input_buf_list);
void kdp2_app_yolo_inference(uint32_t job_id, int num_input_buf, void **inf_input_buf_list);

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/* --------------------------------------------------------------------------
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Name: main.c
* Purpose: RTX for Kneron
*
*---------------------------------------------------------------------------*/
#include <stdio.h>
#include <string.h>
#include "project.h"
#include "kdrv_cmsis_core.h"
#include "kdrv_system.h"
#include "kdrv_uart.h"
#include "kdrv_adc.h"
void myADCtest(void)
{
kdrv_adc_initialize();
}
/**
* @brief main, main dispatch function
*/
int main(void)
{
kdrv_system_init();
kdrv_uart_initialize();
kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // for log
SystemCoreClockUpdate(); // System Initialization
myADCtest();
while(1);
}

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/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*=============================================================================
mdw setting
=============================================================================*/
/* scpu/ncpu image size */
#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

162
build/example_kdrv/adc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s Normal file
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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

89
build/example_kdrv/adc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c Normal file
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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
// #include "ARMCM4.h"
#include "kdrv_cmsis_core.h"
#elif defined (ARMCM4_FP)
// #include "ARMCM4_FP.h"
#include "kdrv_cmsis_core.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifdef KL520
#define XTAL (200000000UL) /* Oscillator frequency */
#else
#define XTAL (50000000UL) /* Oscillator frequency */
#endif
#define SYSTEM_CLOCK XTAL
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

55
build/example_kdrv/adc/sn52096/scpu_keil/mozart_96.sct Normal file
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#!armcc -E
#define IRAM_START 0x10102000
#define IRAM_SIZE 0x00016000
#define DRAM_START 0x10200000
#define DRAM_SIZE 0x00016000
LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region
ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;ENTRANCE_SECTION0_TEXT +0 {
; .ANY (entr_section0)
;}
ENTRANCE_SECTION1_TEXT +0 {
.ANY (entr_section1)
}
ENTRANCE_SECTION2_TEXT +0 {
.ANY (entr_section2)
}
ENTRANCE_SECTION3_TEXT +0 {
.ANY (entr_section3)
}
ENTRANCE_SECTION4_TEXT +0 {
.ANY (entr_section4)
}
ENTRANCE_SECTION5_TEXT +0 {
.ANY (entr_section5)
}
ENTRANCE_SECTION6_TEXT +0 {
.ANY (entr_section6)
}
EXIT_SECTION_TEXT +0 {
.ANY (exit_section)
}
INIT_TEXT +0 {
.ANY (init_text)
}
FINI_TEXT +0 {
.ANY (fini_text)
}
INIT_DATA +0 {
.ANY (init_data)
}
RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 AlignExpr(+0,8) {
.ANY (misc_data)
}
}

370
build/example_kdrv/adc/sn52096/scpu_keil/scpu.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>200000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
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624
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@ -0,0 +1,624 @@
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</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10100000</TextAddressRange>
<DataAddressRange>0x10200000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\mozart_96.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>main</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>2</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\scpu\\lib\kapp\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>project.h</FileName>
<FileType>5</FileType>
<FilePath>..\project.h</FilePath>
</File>
<File>
<FileName>ex_adc_main.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\ex_adc_main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>mdw</GroupName>
<Files>
<File>
<FileName>kmdw_console.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\mdw\console\kmdw_console.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<File>
<FileName>kdrv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</FilePath>
</File>
<File>
<FileName>kdrv_system.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</FilePath>
</File>
<File>
<FileName>kdrv_power.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</FilePath>
</File>
<File>
<FileName>kdrv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</FilePath>
</File>
<File>
<FileName>kdrv_adc.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_adc.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</api>
</apis>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.1"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config_USB.h" version="6.2.0">
<instance index="0" removed="1">RTE\File_System\FS_Config_USB_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="USB" Cvendor="Keil" Cversion="6.12.0" condition="File System and USB Host MSC" maxInstances="2"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config.c" version="5.2.1">
<instance index="0" removed="1">RTE\USB\USBH_Config_0.c</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_CustomClass.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_CustomClass.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="Custom Class" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_MSC.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_MSC.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="MSC" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance, Host Driver and File System USB Drive"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

6
build/example_kdrv/adc/sn52096/scpu_keil/vtor.ini Normal file
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@ -0,0 +1,6 @@
MEMSET(0x10200000, 0x10000, 0)
MEMSET(0x10210000, 0x08000, 0)
_WDWORD(0xE000ED08, 0x10102000);
SP=_RDWORD(0x10102000) // Set Stack Pointer
PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler
BS main

57
build/example_kdrv/basic/main_scpu/ex_basic_main.c Normal file
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@ -0,0 +1,57 @@
/* --------------------------------------------------------------------------
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Name: main.c
* Purpose: RTX for Kneron
*
*---------------------------------------------------------------------------*/
#include <stdio.h>
#include <string.h>
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
#include "project.h"
#include "kdrv_system.h"
#include "kmdw_console.h"
#include "kdrv_cmsis_core.h"
/**
* @brief main, main dispatch function
*/
int main(void)
{
osKernelInitialize(); // Initialize CMSIS-RTOS
/* below is some primiary system init settings */
kdrv_system_init(); // primary system init
/* below is some middleware init settings */
kdrv_uart_initialize(); // for log printing
kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL);
DSG("\nStart...");
DSG("Kneron");
DSG("examples");
if (osKernelGetState() == osKernelReady) {
osKernelStart();
}
while(1) {
}
}

163
build/example_kdrv/basic/sn52096/project.h Normal file
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@ -0,0 +1,163 @@
/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*=============================================================================
mdw setting
=============================================================================*/
/* scpu/ncpu image size */
#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
// #include "ARMCM4.h"
#include "kdrv_cmsis_core.h"
#elif defined (ARMCM4_FP)
// #include "ARMCM4_FP.h"
#include "kdrv_cmsis_core.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifdef KL520
#define XTAL (200000000UL) /* Oscillator frequency */
#else
#define XTAL (50000000UL) /* Oscillator frequency */
#endif
#define SYSTEM_CLOCK XTAL
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

55
build/example_kdrv/basic/sn52096/scpu_keil/mozart_96.sct Normal file
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#!armcc -E
#define IRAM_START 0x10102000
#define IRAM_SIZE 0x00016000
#define DRAM_START 0x10200000
#define DRAM_SIZE 0x00016000
LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region
ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;ENTRANCE_SECTION0_TEXT +0 {
; .ANY (entr_section0)
;}
ENTRANCE_SECTION1_TEXT +0 {
.ANY (entr_section1)
}
ENTRANCE_SECTION2_TEXT +0 {
.ANY (entr_section2)
}
ENTRANCE_SECTION3_TEXT +0 {
.ANY (entr_section3)
}
ENTRANCE_SECTION4_TEXT +0 {
.ANY (entr_section4)
}
ENTRANCE_SECTION5_TEXT +0 {
.ANY (entr_section5)
}
ENTRANCE_SECTION6_TEXT +0 {
.ANY (entr_section6)
}
EXIT_SECTION_TEXT +0 {
.ANY (exit_section)
}
INIT_TEXT +0 {
.ANY (init_text)
}
FINI_TEXT +0 {
.ANY (fini_text)
}
INIT_DATA +0 {
.ANY (init_data)
}
RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 AlignExpr(+0,8) {
.ANY (misc_data)
}
}

370
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>200000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\vtor.ini</tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>d</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>0</SubType>
<ItemText>0x62ec1762</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<MemoryWindow2>
<Mm>
<WinNumber>2</WinNumber>
<SubType>2</SubType>
<ItemText>0x61000000</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow2>
<MemoryWindow3>
<Mm>
<WinNumber>3</WinNumber>
<SubType>2</SubType>
<ItemText>0xa0000000</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow3>
<MemoryWindow4>
<Mm>
<WinNumber>4</WinNumber>
<SubType>2</SubType>
<ItemText>0</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow4>
<ScvdPack>
<Filename>C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd</Filename>
<Type>ARM.CMSIS.5.6.0</Type>
<SubType>1</SubType>
</ScvdPack>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>main</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\main_scpu\ex_basic_main.c</PathWithFileName>
<FilenameWithoutPath>ex_basic_main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\project.h</PathWithFileName>
<FilenameWithoutPath>project.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>mdw</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\mdw\console\kmdw_console.c</PathWithFileName>
<FilenameWithoutPath>kmdw_console.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>driver</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c</PathWithFileName>
<FilenameWithoutPath>kdrv_ddr.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</PathWithFileName>
<FilenameWithoutPath>kdrv_clock.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</PathWithFileName>
<FilenameWithoutPath>kdrv_system.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</PathWithFileName>
<FilenameWithoutPath>kdrv_power.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</PathWithFileName>
<FilenameWithoutPath>kdrv_uart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

623
build/example_kdrv/basic/sn52096/scpu_keil/scpu.uvprojx Normal file
View File

@ -0,0 +1,623 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM4_FP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.6.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>companion</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin"</UserProg1Name>
<UserProg2Name>post_build.bat</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>1</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4100</DriverSelection>
</Flash1>
<bUseTDR>0</bUseTDR>
<Flash2>Segger\JL2CM3.dll</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>0</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x10102000</StartAddress>
<Size>0x16000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10200000</StartAddress>
<Size>0x16000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--gnu</MiscControls>
<Define>ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10100000</TextAddressRange>
<DataAddressRange>0x10200000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\mozart_96.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>main</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>2</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\scpu\lib\kapp\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>ex_basic_main.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\ex_basic_main.c</FilePath>
</File>
<File>
<FileName>project.h</FileName>
<FileType>5</FileType>
<FilePath>..\project.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>mdw</GroupName>
<Files>
<File>
<FileName>kmdw_console.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\mdw\console\kmdw_console.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<File>
<FileName>kdrv_ddr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c</FilePath>
</File>
<File>
<FileName>kdrv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</FilePath>
</File>
<File>
<FileName>kdrv_system.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</FilePath>
</File>
<File>
<FileName>kdrv_power.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</FilePath>
</File>
<File>
<FileName>kdrv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</api>
</apis>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.1"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config_USB.h" version="6.2.0">
<instance index="0" removed="1">RTE\File_System\FS_Config_USB_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="USB" Cvendor="Keil" Cversion="6.12.0" condition="File System and USB Host MSC" maxInstances="2"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config.c" version="5.2.1">
<instance index="0" removed="1">RTE\USB\USBH_Config_0.c</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_CustomClass.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_CustomClass.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="Custom Class" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_MSC.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_MSC.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="MSC" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance, Host Driver and File System USB Drive"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

6
build/example_kdrv/basic/sn52096/scpu_keil/vtor.ini Normal file
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@ -0,0 +1,6 @@
MEMSET(0x10200000, 0x10000, 0)
MEMSET(0x10210000, 0x08000, 0)
_WDWORD(0xE000ED08, 0x10102000);
SP=_RDWORD(0x10102000) // Set Stack Pointer
PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler
BS main

104
build/example_kdrv/camera/dvp/main_scpu/board_kl520_dvp_example.h Normal file
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@ -0,0 +1,104 @@
#ifndef __BOARD_KDP520_DVP_H__
#define __BOARD_KDP520_DVP_H__
#define IMGSRC_IN_0 YES
#define IMGSRC_IN_1 NO
#if (IMGSRC_IN_0 == YES)
#define IMGSRC_IN_0_PORT IMGSRC_IN_PORT_DPI
#define IMGSRC_0_SENSORID SENSOR_ID_EXTERN
#define IMGSRC_0_FORMAT IMG_FORMAT_RAW8
#define IMGSRC_0_TYPE IMG_TYPE_RGB
#define IMGSRC_0_RES SENSOR_RES_640_480
#define IMGSRC_0_WIDTH 640
#define IMGSRC_0_HEIGHT 480
#define IMGSRC_0_TILE_AVG 0
#define IMGSRC_0_MIPI_LANE 2
#else
#define IMGSRC_IN_0_PORT IMGSRC_IN_PORT_NONE
#define IMGSRC_0_SENSORID SENSOR_ID_NONE
#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565
#define IMGSRC_0_TYPE IMG_TYPE_RGB
#define IMGSRC_0_RES SENSOR_RES_640_480
#define IMGSRC_0_WIDTH 640
#define IMGSRC_0_HEIGHT 480
#define IMGSRC_0_TILE_AVG 0
#define IMGSRC_0_MIPI_LANE 2
#endif
#if (IMGSRC_IN_1 == YES)
#define IMGSRC_IN_1_PORT IMGSRC_IN_PORT_MIPI
#define IMGSRC_1_SENSORID SENSOR_ID_SC132GS
#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8
#define IMGSRC_1_TYPE IMG_TYPE_IR
#define IMGSRC_1_RES SENSOR_RES_480_640
#define IMGSRC_1_WIDTH 480
#define IMGSRC_1_HEIGHT 640
#define IMGSRC_1_TILE_AVG 1
#define IMGSRC_1_MIPI_LANE 2
#else
#define IMGSRC_IN_1_PORT IMGSRC_IN_PORT_NONE
#define IMGSRC_1_SENSORID SENSOR_ID_NONE
#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8
#define IMGSRC_1_TYPE IMG_TYPE_IR
#define IMGSRC_1_RES SENSOR_RES_480_640
#define IMGSRC_1_WIDTH 480
#define IMGSRC_1_HEIGHT 640
#define IMGSRC_1_TILE_AVG 1
#define IMGSRC_1_MIPI_LANE 2
#endif
#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_MIPI || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_MIPI)
#define IMGSRC_IN_HAS_MIPI
#define MIPI_LANE_RGB 2
#define MIPI_LANE_NIR 2
#endif
#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_DPI || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_DPI)
#define IMGSRC_IN_HAS_DPI
#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_DPI)
#define IMAGE_DVP_PORT_NO 0
#else
#define IMAGE_DVP_PORT_NO 1
#endif
#endif
#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_UVC || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_UVC)
#define IMGSRC_IN_HAS_UVC
#endif
#if (IMGSRC_IN_0 && IMGSRC_IN_1 && IMGSRC_IN_2)
#define CAM_ID_MAX 3
#elif (IMGSRC_IN_0 && IMGSRC_IN_1)
#define CAM_ID_MAX 2
#elif (IMGSRC_IN_0 || IMGSRC_IN_1)
#define CAM_ID_MAX 1
#else
#define CAM_ID_MAX 0
#endif
#define IMGSRC_NUM CAM_ID_MAX
#define MIPI_CAM_RGB 0
#define MIPI_CAM_NIR 1
#define LCDC_WIDTH 640
#define LCDC_HEIGHT 480
#define RGB_IMG_SOURCE_W IMGSRC_0_WIDTH
#define RGB_IMG_SOURCE_H IMGSRC_0_HEIGHT
#define NIR_IMG_SOURCE_W IMGSRC_1_WIDTH
#define NIR_IMG_SOURCE_H IMGSRC_1_HEIGHT
#define PANEL_TYPE PANEL_MZT_480X272
#define DISPLAY_DEVICE DISPLAY_DEVICE_LCDC
#define CAM_CLK_MS 2
#define CAM_CLK_NS 242
#define CAM_CLK_PS 2
#define CSI0_TXESC 4
#define CSI0_CSI 11
#define CSI0_VC0 5
#define CSI1_TXESC 4
#define CSI1_CSI 7
#define CSI1_VC0 1
#endif // __BOARD_KDP520_DVP_H__

161
build/example_kdrv/camera/dvp/main_scpu/ex_camera_main.c Normal file
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@ -0,0 +1,161 @@
/* --------------------------------------------------------------------------
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Name: main.c
* Purpose: RTX for Kneron
*
*---------------------------------------------------------------------------*/
#include <string.h>
#include "project.h"
#include "kdrv_cmsis_core.h"
#include "kdrv_pinmux.h"
#include "kdrv_ddr.h"
#include "kdrv_system.h"
#include "kdrv_uart.h"
#include "kdrv_i2c.h"
#include "kmdw_memory.h"
#include "kmdw_console.h"
#include "kmdw_camera.h"
static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY;
typedef struct myCamera_ctx {
bool init;
enum camera_state state;
uint32_t width;
uint32_t height;
uint32_t pixelformat;
} myCamera_exp_ctx;
myCamera_exp_ctx m_kdp_cam_exp_ctx[IMGSRC_NUM + 2] = {
{false, CAMERA_STATE_IDLE, 0, 0, 0},
{false, CAMERA_STATE_IDLE, 0, 0, 0},
};
static uint32_t myCamera_example_open(uint8_t cam_idx)
{
uint32_t ret;
struct cam_capability cap;
struct cam_format fmt;
char fmtstr[8];
memset(&cap, 0, sizeof(cap));
memset(&fmt, 0, sizeof(fmt));
if (0 != (ret = kmdw_camera_open(cam_idx)))
return ret;
if (0 != (ret = kmdw_camera_get_device_info(cam_idx, &cap)))
return ret;
fmt.width = m_kdp_cam_exp_ctx[cam_idx].width;
fmt.height = m_kdp_cam_exp_ctx[cam_idx].height;
fmt.pixelformat = m_kdp_cam_exp_ctx[cam_idx].pixelformat;
kmdw_printf("[%s] cam_idx:%d, width:%d, height:%d, pixelformat: %d\n", __func__, cam_idx, fmt.width, fmt.height, fmt.pixelformat);
if (0 != (ret = kmdw_camera_set_frame_format(cam_idx, (struct cam_format *)&fmt)))
return ret;
if (0 != (ret = kmdw_camera_get_frame_format(cam_idx, &fmt)))
return ret;
memset(fmtstr, 0, 8);
memcpy(fmtstr, &fmt.pixelformat, 4);
// two buffers for MIPI camera
uint32_t buffer_addr[2] = {0};
buffer_addr[0] = kmdw_ddr_reserve(1024*1024);
buffer_addr[1] = kmdw_ddr_reserve(1024*1024);
if (0 != (ret = kmdw_camera_buffer_init(cam_idx, buffer_addr[0], buffer_addr[1])))
return ret;
m_kdp_cam_exp_ctx[cam_idx].state = CAMERA_STATE_INITED;
return 0;
}
static uint32_t myCamera_example_setting(uint8_t cam_idx, unsigned int width, unsigned int height, unsigned int pixelformat)
{
if(true == m_kdp_cam_exp_ctx[cam_idx].init) {
kmdw_printf("[%s] camera index %d is already initialized\n", __func__, cam_idx);
return 1;
}
m_kdp_cam_exp_ctx[cam_idx].init = true;
m_kdp_cam_exp_ctx[cam_idx].width = width;
m_kdp_cam_exp_ctx[cam_idx].height = height;
m_kdp_cam_exp_ctx[cam_idx].pixelformat = pixelformat;
return 0;
}
static uint32_t myCamera_example_start(uint32_t cam_idx)
{
uint32_t ret;
if (0 != (ret = kmdw_camera_start(cam_idx, NULL))) {
return ret;
}
m_kdp_cam_exp_ctx[cam_idx].state = CAMERA_STATE_RUNNING;
return 0;
}
void myCameratest()
{
#if (IMGSRC_IN_0)
myCamera_example_setting(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT);
myCamera_example_open(0);
myCamera_example_start(0);
#endif
kmdw_printf("============================================================================================\n");
kmdw_printf("Camera dvp example :\n");
kmdw_printf("Use customer's evb board to transfer color bar Raw8 yuv image to Kneron's evb board.\n");
kmdw_printf("Please use keil command window to input save image cmd to store image from rgb/nir sensor.\n");
kmdw_printf(" ex: save rgb.hex 0x62f42800, 0x62f42800+(640*480*2)\n");
kmdw_printf("Then use thirdparty's tool to verify image.\n");
kmdw_printf("rgb sensor : size 640*480*2, with color bar image \n");
kmdw_printf("============================================================================================\n");
}
int main(void)
{
SystemCoreClockUpdate();
osKernelInitialize();
kdrv_system_init();
kdrv_system_init_ncpu();
kdrv_ddr_system_init(DDR_INIT_ALL);
kdrv_pinmux_initialize(PIN_NUM, pinmux_array);
kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END);
kdrv_uart_initialize();
kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL);
kmdw_console_set_log_level_scpu(LOG_PROFILE);
kmdw_camera_init();
myCameratest();
if (osKernelGetState() == osKernelReady)
{
osKernelStart();
}
while (1)
{
}
}

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/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_SD_CLK_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_SD_CMD_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
#//define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

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build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s Normal file
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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

89
build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c Normal file
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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
// #include "ARMCM4.h"
#include "kdrv_cmsis_core.h"
#elif defined (ARMCM4_FP)
// #include "ARMCM4_FP.h"
#include "kdrv_cmsis_core.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifdef KL520
#define XTAL (200000000UL) /* Oscillator frequency */
#else
#define XTAL (50000000UL) /* Oscillator frequency */
#endif
#define SYSTEM_CLOCK XTAL
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

24
build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/_Target-SCPU/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'scpu'
* Target: 'Target-SCPU'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM4_FP.h"
/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#endif /* RTE_COMPONENTS_H */

24
build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/_scpu/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'scpu'
* Target: 'scpu'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM4_FP.h"
/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#endif /* RTE_COMPONENTS_H */

55
build/example_kdrv/camera/dvp/sn520ev/scpu_keil/mozart_96.sct Normal file
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#!armcc -E
#define IRAM_START 0x10102000
#define IRAM_SIZE 0x00016000
#define DRAM_START 0x10200000
#define DRAM_SIZE 0x00016000
LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region
ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;ENTRANCE_SECTION0_TEXT +0 {
; .ANY (entr_section0)
;}
ENTRANCE_SECTION1_TEXT +0 {
.ANY (entr_section1)
}
ENTRANCE_SECTION2_TEXT +0 {
.ANY (entr_section2)
}
ENTRANCE_SECTION3_TEXT +0 {
.ANY (entr_section3)
}
ENTRANCE_SECTION4_TEXT +0 {
.ANY (entr_section4)
}
ENTRANCE_SECTION5_TEXT +0 {
.ANY (entr_section5)
}
ENTRANCE_SECTION6_TEXT +0 {
.ANY (entr_section6)
}
EXIT_SECTION_TEXT +0 {
.ANY (exit_section)
}
INIT_TEXT +0 {
.ANY (init_text)
}
FINI_TEXT +0 {
.ANY (fini_text)
}
INIT_DATA +0 {
.ANY (init_data)
}
RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 AlignExpr(+0,8) {
.ANY (misc_data)
}
}

534
build/example_kdrv/camera/dvp/sn520ev/scpu_keil/scpu.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>200000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\vtor.ini</tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U63680012 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0</Name>
</SetRegEntry>
<SetRegEntry>
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</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x10102000</StartAddress>
<Size>0x16000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10200000</StartAddress>
<Size>0x16000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--gnu</MiscControls>
<Define>ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE,BOARD_DVP_EXAMPLE</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\dev\include;..\..\..\..\..\..\mdw\include;..\..\..\..\..\..\include;..\;..\..\main_scpu</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10100000</TextAddressRange>
<DataAddressRange>0x10200000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\mozart_96.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>main</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>2</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\scpu\lib\kapp\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>ex_camera_main.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\ex_camera_main.c</FilePath>
</File>
<File>
<FileName>project.h</FileName>
<FileType>5</FileType>
<FilePath>..\project.h</FilePath>
</File>
<File>
<FileName>board_kl520_dvp_example.h</FileName>
<FileType>5</FileType>
<FilePath>..\..\main_scpu\board_kl520_dvp_example.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>mdw</GroupName>
<Files>
<File>
<FileName>kmdw_console.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\console\kmdw_console.c</FilePath>
</File>
<File>
<FileName>kmdw_camera.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\camera\kmdw_camera.c</FilePath>
</File>
<File>
<FileName>kmdw_camera_kl520.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\camera\kmdw_camera_kl520.c</FilePath>
</File>
<File>
<FileName>kmdw_sensor.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\camera\kmdw_sensor.c</FilePath>
</File>
<File>
<FileName>kmdw_memory.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\memory\kmdw_memory.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<File>
<FileName>kdrv_pinmux.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c</FilePath>
</File>
<File>
<FileName>kdrv_ddr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c</FilePath>
</File>
<File>
<FileName>kdrv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</FilePath>
</File>
<File>
<FileName>kdrv_system.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</FilePath>
</File>
<File>
<FileName>kdrv_power.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</FilePath>
</File>
<File>
<FileName>kdrv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</FilePath>
</File>
<File>
<FileName>kdrv_dpi2ahb.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c</FilePath>
</File>
<File>
<FileName>kdrv_mipicsirx.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c</FilePath>
</File>
<File>
<FileName>kdrv_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>dev</GroupName>
<Files>
<File>
<FileName>kdev_sensor_gc2145.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c</FilePath>
</File>
<File>
<FileName>kdev_sensor_sc132gs.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</api>
</apis>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.1"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config_USB.h" version="6.2.0">
<instance index="0" removed="1">RTE\File_System\FS_Config_USB_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="USB" Cvendor="Keil" Cversion="6.12.0" condition="File System and USB Host MSC" maxInstances="2"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config.c" version="5.2.1">
<instance index="0" removed="1">RTE\USB\USBH_Config_0.c</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_CustomClass.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_CustomClass.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="Custom Class" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_MSC.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_MSC.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="MSC" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance, Host Driver and File System USB Drive"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

6
build/example_kdrv/camera/dvp/sn520ev/scpu_keil/vtor.ini Normal file
View File

@ -0,0 +1,6 @@
MEMSET(0x10200000, 0x10000, 0)
MEMSET(0x10210000, 0x08000, 0)
_WDWORD(0xE000ED08, 0x10102000);
SP=_RDWORD(0x10102000) // Set Stack Pointer
PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler
BS main

164
build/example_kdrv/camera/mipi/main_scpu/ex_camera_main.c Normal file
View File

@ -0,0 +1,164 @@
/* --------------------------------------------------------------------------
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Name: main.c
* Purpose: RTX for Kneron
*
*---------------------------------------------------------------------------*/
#include <string.h>
#include "kdrv_cmsis_core.h"
#include "project.h"
#include "kdrv_ddr.h"
#include "kdrv_system.h"
#include "kdrv_uart.h"
#include "kdrv_i2c.h"
#include "kmdw_memory.h"
#include "kmdw_console.h"
#include "kmdw_camera.h"
typedef struct myCamera_ctx {
bool init;
enum camera_state state;
uint32_t width;
uint32_t height;
uint32_t pixelformat;
} myCamera_exp_ctx;
myCamera_exp_ctx m_kdp_cam_exp_ctx[IMGSRC_NUM + 2] = {
{false, CAMERA_STATE_IDLE, 0, 0, 0},
{false, CAMERA_STATE_IDLE, 0, 0, 0},
};
static uint32_t myCamera_example_open(uint8_t cam_idx)
{
uint32_t ret;
struct cam_capability cap;
struct cam_format fmt;
char fmtstr[8];
memset(&cap, 0, sizeof(cap));
memset(&fmt, 0, sizeof(fmt));
if (0 != (ret = kmdw_camera_open(cam_idx)))
return ret;
if (0 != (ret = kmdw_camera_get_device_info(cam_idx, &cap)))
return ret;
fmt.width = m_kdp_cam_exp_ctx[cam_idx].width;
fmt.height = m_kdp_cam_exp_ctx[cam_idx].height;
fmt.pixelformat = m_kdp_cam_exp_ctx[cam_idx].pixelformat;
kmdw_printf("[%s] cam_idx:%d, width:%d, height:%d, pixelformat: %d\n", __func__, cam_idx, fmt.width, fmt.height, fmt.pixelformat);
if (0 != (ret = kmdw_camera_set_frame_format(cam_idx, (struct cam_format *)&fmt)))
return ret;
if (0 != (ret = kmdw_camera_get_frame_format(cam_idx, &fmt)))
return ret;
memset(fmtstr, 0, 8);
memcpy(fmtstr, &fmt.pixelformat, 4);
// two buffers for MIPI camera
uint32_t buffer_addr[2] = {0};
buffer_addr[0] = kmdw_ddr_reserve(1024*1024);
buffer_addr[1] = kmdw_ddr_reserve(1024*1024);
if (0 != (ret = kmdw_camera_buffer_init(cam_idx, buffer_addr[0], buffer_addr[1])))
return ret;
m_kdp_cam_exp_ctx[cam_idx].state = CAMERA_STATE_INITED;
return 0;
}
static uint32_t myCamera_example_setting(uint8_t cam_idx, unsigned int width, unsigned int height, unsigned int pixelformat)
{
if(true == m_kdp_cam_exp_ctx[cam_idx].init) {
kmdw_printf("[%s] camera index %d is already initialized\n", __func__, cam_idx);
return 1;
}
m_kdp_cam_exp_ctx[cam_idx].init = true;
m_kdp_cam_exp_ctx[cam_idx].width = width;
m_kdp_cam_exp_ctx[cam_idx].height = height;
m_kdp_cam_exp_ctx[cam_idx].pixelformat = pixelformat;
return 0;
}
static uint32_t myCamera_example_start(uint32_t cam_idx)
{
uint32_t ret;
if (0 != (ret = kmdw_camera_start(cam_idx, NULL))) {
return ret;
}
m_kdp_cam_exp_ctx[cam_idx].state = CAMERA_STATE_RUNNING;
return 0;
}
void myCameratest()
{
#if (IMGSRC_IN_0)
myCamera_example_setting(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT);
myCamera_example_open(0);
myCamera_example_start(0);
#endif
#if (IMGSRC_IN_1)
myCamera_example_setting(1, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, IMGSRC_1_FORMAT);
myCamera_example_open(1);
myCamera_example_start(1);
#endif
kmdw_printf("============================================================================================\n");
kmdw_printf("Camera example :\n");
kmdw_printf("Please use keil command window to input save image cmd to store image from rgb/nir sensor.\n");
kmdw_printf(" ex: save rgb.hex 0x62f42800, 0x62f42800+(640*480*2)\n");
kmdw_printf(" save nir.hex 0x62979250, 0x62979250+(640*480)\n");
kmdw_printf("Then use thirdparty's tool to verify image.\n");
kmdw_printf("rgb sensor : size 640*480*2, with color bar image \n");
kmdw_printf("nir sensor : size 480*640, with gray bar image\n");
kmdw_printf("============================================================================================\n");
}
int main(void)
{
SystemCoreClockUpdate();
osKernelInitialize();
kdrv_system_init();
kdrv_system_init_ncpu();
kdrv_ddr_system_init(DDR_INIT_ALL);
kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END);
kdrv_uart_initialize();
//kmdw_console_init(UART0_DEV);
kdrv_uart_console_init(COMM_PORT_ID_0, COMM_UART_BAUDRATE_115200, NULL);
kmdw_console_set_log_level_scpu(LOG_PROFILE);
kdrv_i2c_initialize(KDRV_I2C_CTRL_0, KDRV_I2C_SPEED_400K);
kmdw_camera_init();
myCameratest();
if (osKernelGetState() == osKernelReady)
{
osKernelStart();
}
while (1)
{
}
}

184
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/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
CAM setting
=============================================================================*/
//project.h
#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565
#define IMGSRC_0_TYPE IMG_TYPE_RGB
#define IMGSRC_0_RES SENSOR_RES_640_480
#define IMGSRC_0_WIDTH 640
#define IMGSRC_0_HEIGHT 480
#define IMGSRC_0_TILE_AVG 0
#define IMGSRC_0_MIPI_LANE 2
#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8
#define IMGSRC_1_TYPE IMG_TYPE_IR
#define IMGSRC_1_RES SENSOR_RES_480_640
#define IMGSRC_1_WIDTH 480
#define IMGSRC_1_HEIGHT 640
#define IMGSRC_1_TILE_AVG 1
#define IMGSRC_1_MIPI_LANE 2
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
#//define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*=============================================================================
mdw setting
=============================================================================*/
/* scpu/ncpu image size */
#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

162
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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

89
build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c Normal file
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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
// #include "ARMCM4.h"
#include "kdrv_cmsis_core.h"
#elif defined (ARMCM4_FP)
// #include "ARMCM4_FP.h"
#include "kdrv_cmsis_core.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifdef KL520
#define XTAL (200000000UL) /* Oscillator frequency */
#else
#define XTAL (50000000UL) /* Oscillator frequency */
#endif
#define SYSTEM_CLOCK XTAL
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

24
build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'scpu'
* Target: 'Target-SCPU'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM4_FP.h"
/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#endif /* RTE_COMPONENTS_H */

24
build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h Normal file
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/*
* Auto generated Run-Time-Environment Configuration File
* *** Do not modify ! ***
*
* Project: 'scpu'
* Target: 'scpu'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
/*
* Define the Device Header File:
*/
#define CMSIS_device_header "ARMCM4_FP.h"
/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */
#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */
#define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */
#endif /* RTE_COMPONENTS_H */

55
build/example_kdrv/camera/mipi/sn52096/scpu_keil/mozart_96.sct Normal file
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#!armcc -E
#define IRAM_START 0x10102000
#define IRAM_SIZE 0x00016000
#define DRAM_START 0x10200000
#define DRAM_SIZE 0x00016000
LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region
ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;ENTRANCE_SECTION0_TEXT +0 {
; .ANY (entr_section0)
;}
ENTRANCE_SECTION1_TEXT +0 {
.ANY (entr_section1)
}
ENTRANCE_SECTION2_TEXT +0 {
.ANY (entr_section2)
}
ENTRANCE_SECTION3_TEXT +0 {
.ANY (entr_section3)
}
ENTRANCE_SECTION4_TEXT +0 {
.ANY (entr_section4)
}
ENTRANCE_SECTION5_TEXT +0 {
.ANY (entr_section5)
}
ENTRANCE_SECTION6_TEXT +0 {
.ANY (entr_section6)
}
EXIT_SECTION_TEXT +0 {
.ANY (exit_section)
}
INIT_TEXT +0 {
.ANY (init_text)
}
FINI_TEXT +0 {
.ANY (fini_text)
}
INIT_DATA +0 {
.ANY (init_data)
}
RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 AlignExpr(+0,8) {
.ANY (misc_data)
}
}

481
build/example_kdrv/camera/mipi/sn52096/scpu_keil/scpu.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>200000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>4</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile>.\vtor.ini</tIfile>
<pMon>Segger\JL2CM3.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name>d</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>JL2CM3</Key>
<Name>-U63680012 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<WatchWindow1>
<Ww>
<count>0</count>
<WinNumber>1</WinNumber>
<ItemText>fbp</ItemText>
</Ww>
</WatchWindow1>
<MemoryWindow1>
<Mm>
<WinNumber>1</WinNumber>
<SubType>0</SubType>
<ItemText>0x62f42800</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow1>
<MemoryWindow2>
<Mm>
<WinNumber>2</WinNumber>
<SubType>2</SubType>
<ItemText>0x61000000</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow2>
<MemoryWindow3>
<Mm>
<WinNumber>3</WinNumber>
<SubType>2</SubType>
<ItemText>0xa0000000</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow3>
<MemoryWindow4>
<Mm>
<WinNumber>4</WinNumber>
<SubType>2</SubType>
<ItemText>0</ItemText>
<AccSizeX>0</AccSizeX>
</Mm>
</MemoryWindow4>
<ScvdPack>
<Filename>C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd</Filename>
<Type>ARM.CMSIS.5.6.0</Type>
<SubType>1</SubType>
</ScvdPack>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>1</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>main</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\main_scpu\ex_camera_main.c</PathWithFileName>
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<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\scpu\lib\kapp\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>ex_camera_main.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\ex_camera_main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>mdw</GroupName>
<Files>
<File>
<FileName>kmdw_console.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\console\kmdw_console.c</FilePath>
</File>
<File>
<FileName>kmdw_camera.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\camera\kmdw_camera.c</FilePath>
</File>
<File>
<FileName>kmdw_camera_kl520.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\camera\kmdw_camera_kl520.c</FilePath>
</File>
<File>
<FileName>kmdw_sensor.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\camera\kmdw_sensor.c</FilePath>
</File>
<File>
<FileName>kmdw_memory.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\mdw\memory\kmdw_memory.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<File>
<FileName>kdrv_ddr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c</FilePath>
</File>
<File>
<FileName>kdrv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</FilePath>
</File>
<File>
<FileName>kdrv_system.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</FilePath>
</File>
<File>
<FileName>kdrv_power.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</FilePath>
</File>
<File>
<FileName>kdrv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</FilePath>
</File>
<File>
<FileName>kdrv_dpi2ahb.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c</FilePath>
</File>
<File>
<FileName>kdrv_mipicsirx.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c</FilePath>
</File>
<File>
<FileName>kdrv_i2c.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>dev</GroupName>
<Files>
<File>
<FileName>kdev_sensor_sc132gs.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c</FilePath>
</File>
<File>
<FileName>kdev_sensor_gc2145.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</api>
</apis>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.1"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config_USB.h" version="6.2.0">
<instance index="0" removed="1">RTE\File_System\FS_Config_USB_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="USB" Cvendor="Keil" Cversion="6.12.0" condition="File System and USB Host MSC" maxInstances="2"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config.c" version="5.2.1">
<instance index="0" removed="1">RTE\USB\USBH_Config_0.c</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_CustomClass.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_CustomClass.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="Custom Class" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_MSC.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_MSC.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="MSC" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance, Host Driver and File System USB Drive"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

6
build/example_kdrv/camera/mipi/sn52096/scpu_keil/vtor.ini Normal file
View File

@ -0,0 +1,6 @@
MEMSET(0x10200000, 0x10000, 0)
MEMSET(0x10210000, 0x08000, 0)
_WDWORD(0xE000ED08, 0x10102000);
SP=_RDWORD(0x10102000) // Set Stack Pointer
PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler
BS main

994
build/example_kdrv/ddr/main_scpu/ex_ddr_main.c Normal file
View File

@ -0,0 +1,994 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
#include "project.h"
#include "kdrv_ddr.h"
#include "kdrv_system.h"
#include "kmdw_console.h"
#include "io.h"
#include "kdrv_uart.h"
#include "kdrv_pwm.h"
#include "kdrv_timer.h"
#include "kdrv_clock.h"
#include "kdrv_cmsis_core.h"
extern void kdrv_system_init(void);
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
#define MEM_BASE (DDR_MEM_BASE)
#define MEM_SIZE (0x4000000)//(0x80000)//
#define MEM_BASE4NPU (MEM_BASE)
#define PATTERN_LENGTH (17*16)
#define PATTERN1(i) ((i^0x55aa)+((i^0xaa55)<<16))
#define MOD_SZ 20
#define ITER_CNT 2//
typedef enum {
MEMTEST86_ID_1 = 1,
MEMTEST86_ID_2,
MEMTEST86_ID_3,
MEMTEST86_ID_4,
MEMTEST86_ID_5,
MEMTEST86_ID_6,
MEMTEST86_ID_7,
MEMTEST86_ID_8,
MEMTEST86_ID_9,
MEMTEST86_ID_10,
MEMTEST86_ID_11,
FARADAY_MEMTEST,
MEMTEST_ID_MAX,
}MEMTEST_ID;
typedef int (*ddr_cmd_func)(void);
struct ddr_cmd_info
{
char *desc;
};
struct ddr_cmd_info ddr_cmd_array[MEMTEST_ID_MAX-1] = {
{"MEMTEST86_ID_1 : Address test, walking ones"},
{"MEMTEST86_ID_2 : Address test, own address"},
{"MEMTEST86_ID_3 : Moving inversions, all ones and zeros"},
{"MEMTEST86_ID_4 : Moving inversions, 8 bit walking ones and zeros"},
{"MEMTEST86_ID_5 : Moving inversions, 32 bit shifting pattern"},
{"MEMTEST86_ID_6 : Random Data"},
{"MEMTEST86_ID_7 : Random Data Sequence"},
{"MEMTEST86_ID_8 : Bit fade test"},
{"MEMTEST86_ID_9 : Modulo 20 check, Random pattern"},
{"MEMTEST86_ID_10 : Modulo 20 check, all ones and zeros"},
{"MEMTEST86_ID_11 : Modulo 20 check, 8 bit pattern"},
{"FARADAY_MEMTEST : Faraday's ddr memory test"},
};
uint32_t pftimerid;
uint32_t static ddr_sram_rw_verify(void)
{
int i, j, k, len, test_loop;
k=0;
int test1_err_cnt = 0;
int test2_err_cnt = 0;
int test3_err_cnt = 0;
test_loop = 50;
DSG("Test mem 1\n");
for (k = 0; k < test_loop; k++)
{
for (i = 0; i < MEM_SIZE / 4; i++)
{
outw(MEM_BASE+4 * i, PATTERN1(i));
}
len = 0;
for (i=0; i < MEM_SIZE / 4; i++)
{
j = inw(MEM_BASE+4*i);
if (j != PATTERN1(i))
{
test1_err_cnt++;
DSG("%d> Test mem 1 failed ev=%08x, av=%08x\n", i, PATTERN1(i), j);
len++;
if(len > 10)
{
DSG("%d> exit\n");
return (1);
}
}
}
DSG("Test loop %d/%d\n", k, test_loop);
}
DSG("Test mem 2\n");
for (k = 0; k < test_loop; k++)
{
for (i = 0; i < MEM_SIZE / 4; i++)
{
outw(MEM_BASE + 4 * i, (i << 16) + ((i^0xffff)));
}
len = 0;
for(i = 0; i < MEM_SIZE / 4; i++)
{
j = inw(MEM_BASE + 4 * i);
if ( j != ((i << 16) + (i^0xffff)))
{
test2_err_cnt++;
DSG("Test mem 2 failed ev=%08x, av=%08x\n", (i<<16)+((i^0xffff)), j);
len++;
if(len>10)
{
DSG("%d> exit\n");
return (1);
}
}
}
DSG("Test loop %d/%d\n", k, test_loop);
}
DSG("Test mem 3\n");
for(k = 0; k < test_loop; k++)
{
for(i = 0; i < MEM_SIZE / 4; i++)
{
outw(MEM_BASE + 4 * i, 0);
}
len=0;
for(i = 0; i < MEM_SIZE / 4; i++)
{
j = inw(MEM_BASE + 4 * i);
if ( j != (0))
{
test3_err_cnt++;
DSG("Test mem 3 failed ev=%08x, av=%08x\n", 0, j);
len++;
if (len > 10)
{
DSG("%d> exit\n");
return (1);
}
}
}
DSG("Test loop %d/%d\n", k, test_loop);
}
DSG("End of test\n");
DSG("Test result mem1_test %d/%d, mem2_test=%d/%d, mem3_test=%d/%d\n",
test_loop - test1_err_cnt, test_loop,
test_loop - test2_err_cnt, test_loop,
test_loop - test3_err_cnt, test_loop);
return 0;
}
uint32_t roundup(uint32_t value, uint32_t mask)
{
return (value + mask) & ~mask;
}
/*
* Memory address test, walking ones
*/
uint32_t ddr_addr_tst1()
{
int32_t i, j, k;
volatile uint32_t *p, *pt, *end, *start;
uint32_t mask, bank, p1;
/* Test the global address bits */
for (p1=0, j=0; j<2; j++)
{
/* Set pattern in our lowest multiple of 0x20000 */
start = (uint32_t *)MEM_BASE;
end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4);
p = (uint32_t *)roundup((uint32_t)start, 0x1ffff);
*p = p1;
p1 = ~p1;
for (i=0; i<100; i++)
{
mask = 4;
do{
pt = (uint32_t *)((uint32_t)p | mask);
if (pt == p)
{
mask = mask << 1;
continue;
}
if (pt >= end)
{
break;
}
*pt = p1;
if ((*p) != ~p1)
{
return 1;
}
mask = mask << 1;
} while(mask);
}
}
/* Now check the address bits in each bank */
/* If we have more than 8mb of memory then the bank size must be */
/* bigger than 256k. If so use 1mb for the bank size. */
if ((uint32_t)end > (0x800000 >> 12))
{
bank = 0x100000;
}
else
{
bank = 0x40000;
}
for (p1=0, k=0; k<2; k++)
{
p = start;
/* Force start address to be a multiple of 256k */
p = (uint32_t *)roundup((uint32_t)p, bank - 1);
/* Redundant checks for overflow */
while (p < end && p >= start && p != 0)
{
*p = p1;
p1 = ~p1;
for (i=0; i<50; i++)
{
mask = 4;
do{
pt = (uint32_t *)((uint32_t)p | mask);
if (pt == p)
{
mask = mask << 1;
continue;
}
if (pt >= end)
{
break;
}
*pt = p1;
if ((*p) != ~p1)
{
return 1;
}
mask = mask << 1;
} while(mask);
}
if (p + bank > p)
{
p += bank;
}
else
{
p = end;
}
p1 = ~p1;
}
p1 = ~p1;
}
return 0;
}
/*
* Memory address test, own address
*/
uint32_t ddr_addr_tst2()
{
int32_t done;
uint32_t *p, *pe, *end, *start;
/* Write each address with it's own address */
start = (uint32_t *)MEM_BASE;
end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4);
pe = (uint32_t *)end;
p = start;
done = 0;
do{
for (; p <= pe; p++)
{
*p = (uint32_t)p;
}
if (p >= pe)
{
done++;
}
} while (!done);
/* Each address should have its own address */
pe = end;
p = start;
done = 0;
do{
for (; p <= pe; p++)
{
if((*p) != (uint32_t)p)
{
return 1;
}
}
if (p >= pe)
{
done++;
}
} while (!done);
return 0;
}
/*
* Test all of memory using a "half moving inversions" algorithm using random
* numbers and their complment as the data pattern. Since we are not able to
* produce random numbers in reverse order testing is only done in the forward
* direction.
*/
uint32_t ddr_movinvr()
{
int32_t i, done;
uint32_t *p;
uint32_t *pe;
uint32_t *start,*end;
uint32_t num;
uint32_t random_number;
uint32_t perftime, time;
/* Initialize memory with initial sequence of random numbers. */
start = (uint32_t *)MEM_BASE;
end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4);
srand(kdrv_timer_perf_get_instant(&pftimerid, &perftime, &time));
random_number = rand();
pe = end;
p = start;
done = 0;
do {
for (; p <= pe; p++)
{
*p = random_number;
}
if (p >= end)
{
done++;
}
} while (!done);
/* Do moving inversions test. Check for initial pattern and then
* write the complement for each memory location.
*/
for (i=0; i<2; i++) {
pe = end;
p = start;
done = 0;
do {
for (; p <= pe; p++)
{
num = random_number;
if (i)
{
num = ~num;
}
if ((*p) != num)
{
return 1;
}
*p = ~num;
}
if (p >= end)
{
done++;
}
} while (!done);
}
return 0;
}
/*
* Test all of memory using a "moving inversions" algorithm using the
* pattern in p1 and it's complement in p2.
*/
uint32_t ddr_movinv1 (uint32_t iter, uint32_t p1, uint32_t p2)
{
int32_t i, done;
uint32_t *p, *pe, *start, *end;
start = (uint32_t *)MEM_BASE;
end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4);
/* Initialize memory with the initial pattern. */
pe = end;
p = start;
done = 0;
do{
for (; p <= pe; p++)
{
*p = p1;
}
if (p >= pe)
{
done++;
}
} while (!done);
/* Do moving inversions test. Check for initial pattern and then
* write the complement for each memory location. Test from bottom
* up and then from the top down. */
for (i=0; i<iter; i++)
{
pe = end;
p = start;
done = 0;
do{
for (; p <= pe; p++)
{
if ((*p) != p1)
{
return 1;
}
*p = p2;
}
if (p >= end)
{
done++;
}
} while (!done);
pe = start;
p = end;
done = 0;
do
{
do
{
if ((*p) != p2)
{
return 1;
}
*p = p1;
} while (--p >= pe);
if (p <= end)
{
done++;
}
} while (!done);
}
return 0;
}
uint32_t ddr_movinv32(int iter, uint32_t p1, uint32_t lb, uint32_t hb, int sval, int off)
{
int k=0, n=0, done;
uint32_t *p, *pe, *start, *end, pat = 0, p3;
p3 = sval << 31;
/* Initialize memory with the initial pattern. */
start = (uint32_t *)MEM_BASE;
end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4);
pe = end;
p = start;
done = 0;
k = off;
pat = p1;
do{
while (p <= pe)
{
*p = pat;
if (++k >= 32)
{
pat = lb;
k = 0;
}
else
{
pat = pat << 1;
pat |= sval;
}
p++;
}
if (p > end)
{
done++;
}
} while (!done);
/* Do moving inversions test. Check for initial pattern and then
* write the complement for each memory location. Test from bottom
* up and then from the top down. */
p = start;
pe = end;
done = 0;
k = off;
pat = p1;
do
{
while (1)
{
if (*p != pat)
{
return 1;
}
*p = ~pat;
if (++k >= 32)
{
pat = lb;
k = 0;
}
else
{
pat = pat << 1;
pat |= sval;
}
if (p >= pe)
break;
p++;
}
if (p >= end)
{
done++;
}
} while (!done);
if (--k < 0)
{
k = 31;
}
for (pat = lb, n = 0; n < k; n++)
{
pat = pat << 1;
pat |= sval;
}
k++;
p = end;
pe = start;
done = 0;
do{
while(1)
{
if ((*p) != ~pat)
{
return 1;
}
*p = pat;
if (--k <= 0)
{
pat = hb;
k = 32;
}
else
{
pat = pat >> 1;
pat |= p3;
}
if (p <= pe)
break;
p--;
};
if (p <= end)
{
done++;
}
} while (!done);
return 0;
}
/*
* Test all of memory using modulo X access pattern.
*/
uint32_t ddr_modtst(uint32_t offset, uint32_t iter, uint32_t p1, uint32_t p2)
{
uint32_t k, l, done;
uint32_t *p;
uint32_t *pe;
uint32_t *start, *end;
/* Write every nth location with pattern */
start = (uint32_t *)MEM_BASE;
end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4);
end -= MOD_SZ; /* adjust the ending address */
pe = end;
p = start+offset;
done = 0;
do{
/* Check for overflow */
for (; p <= pe; p += MOD_SZ)
{
*p = p1;
}
if(p>=pe)
{
done++;
}
} while (!done);
/* Write the rest of memory "iter" times with the pattern complement */
for (l=0; l<iter; l++)
{
pe = end;
p = start;
done = 0;
k = 0;
do{
for (; p <= pe; p++)
{
if (k != offset)
{
*p = p2;
}
if (++k > MOD_SZ-1)
{
k = 0;
}
}
if (p >= pe)
{
done++;
}
} while (!done);
}
/* Now check every nth location */
pe = end;
p = start+offset;
done = 0;
end -= MOD_SZ;/* adjust the ending address */
do{
for (; p <= pe; p += MOD_SZ)
{
if ((*p) != p1)
{
return 1;
}
}
if (p >= pe)
{
done++;
}
} while (!done);
return 0;
}
/*
* Test memory for bit fade, fill memory with pattern.
*/
void ddr_bit_fade_fill(uint32_t p1)
{
int done;
uint32_t *p, *pe;
uint32_t *start,*end;
/* Initialize memory with the initial pattern. */
{
start = (uint32_t *)MEM_BASE;
end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4);
pe = end;
p = start;
done = 0;
do
{
for (; p < pe;)
{
*p = p1;
p++;
}
if (pe >= end)
{
pe = end;
done++;
}
} while (!done);
}
}
uint32_t ddr_bit_fade_chk(uint32_t p1)
{
uint32_t done;
uint32_t *p, *pe;
uint32_t *start,*end;
/* Make sure that nothing changed while sleeping */
start = (uint32_t *)MEM_BASE;
end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4);
pe = end;
p = start;
done = 0;
do{
for (; p < pe;)
{
if ((*p) != p1)
{
return 1;
}
p++;
}
if (pe >= end)
{
pe = end;
done++;
}
} while (!done);
return 0;
}
/* Sleep for ms */
void ddr_sleep(uint32_t ms)
{
kdrv_clock_disable(CLK_NPU);
kdrv_clock_disable(CLK_NCPU);
kdrv_ddr_self_refresh_enter();
kdrv_pwmtimer_delay_ms(ms);
kdrv_ddr_self_refresh_exit();
kdrv_clock_enable(CLK_NCPU);
kdrv_clock_enable(CLK_NPU);
}
uint32_t ddr_memtest()
{
uint32_t ret;
uint32_t i, iter, p1, p2, p0;
uint32_t j;
uint32_t rc = 1;
int32_t cmd_size = ARRAY_SIZE(ddr_cmd_array);
char buf[256];
iter = ITER_CNT;
uint32_t random_number;
uint32_t perftime,time;
kdrv_timer_perf_open(&pftimerid);
kdrv_timer_perf_reset(&pftimerid);
kdrv_timer_perf_set(&pftimerid);
while(1)
{
int32_t id = 0;
srand(kdrv_timer_perf_get_instant(&pftimerid, &perftime, &time));
random_number = rand();
DSG_NOLF("\n === DDR Example Test Kit (%u) === \n", cmd_size);
for (i = 0; i < cmd_size; ++i)
{
sprintf(buf, "(%2d) %s", i + 1, ddr_cmd_array[i].desc);
DSG_NOLF("%s\n", buf);
}
DSG_NOLF("Set_memtest_item >> ");
rc = kmdw_console_echo_gets(buf, sizeof(buf));
if (!rc)
{
continue;
}
id = atoi(strtok(buf, " \r\n\t"));
DSG_NOLF("========================================================================== \n");
sprintf(buf, "Do memtest case %s", ddr_cmd_array[id-1].desc);
DSG_NOLF("%s\n", buf);
DSG_NOLF("========================================================================== \n");
switch(id)
{
case MEMTEST86_ID_1:
/* Address test, walking ones (test #0) */
ret = ddr_addr_tst1();
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
break;
case MEMTEST86_ID_2:
/* Address test, own address (test #1, 2) */
ret = ddr_addr_tst2();
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
break;
case MEMTEST86_ID_3:
/* Moving inversions, all ones and zeros (tests #3, 4) */
p1 = 0;
p2 = ~p1;
ret = ddr_movinv1(iter, p1, p2);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
ret = ddr_movinv1(iter, p2, p1);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
break;
case MEMTEST86_ID_4:
/* Moving inversions, 8 bit walking ones and zeros (test #5) */
p0 = 0x80;
for (i=0; i<8; i++, p0=p0>>1)
{
p1 = p0 | (p0<<8) | (p0<<16) | (p0<<24);
p2 = ~p1;
ret = ddr_movinv1(iter,p1,p2);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
/* Switch patterns */
ret = ddr_movinv1(iter,p2,p1);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
}
break;
case MEMTEST86_ID_5:
/* Moving inversions, 32 bit shifting pattern (test #8) */
for (i=0, p1=1; p1; p1=p1<<1, i++)
{
ret = ddr_movinv32(iter,p1, 1, 0x80000000, 0, i);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
ret = ddr_movinv32(iter,~p1, 0xfffffffe,0x7fffffff, 1, i);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
}
break;
case MEMTEST86_ID_6:
/* Random Data (test #6) */
for (i=0; i < iter; i++)
{
srand(kdrv_timer_perf_get_instant(&pftimerid, &perftime, &time));
random_number = rand();
p1 = random_number;
p2 = ~p1;
ddr_movinv1(2,p1,p2);
}
break;
case MEMTEST86_ID_7:
/* Random Data Sequence (test #9) */
for (i=0; i < iter; i++) {
ret = ddr_movinvr();
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
}
break;
case MEMTEST86_ID_8:
/* Bit fade test, fill (test #11) */
p1 = 0;
ddr_bit_fade_fill(p1);
ddr_sleep(1000);
ret = ddr_bit_fade_chk(p1);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
p1 = ~p1;
ddr_bit_fade_fill(p1);
ddr_sleep(1000);
ret = ddr_bit_fade_chk(p1);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
break;
case MEMTEST86_ID_9:
/* Modulo 20 check, Random pattern (test #10) */
for (j=0; j<iter; j++)
{
p1 = random_number;
for (i=0; i<MOD_SZ; i++) {
p2 = ~p1;
ret = ddr_modtst(i, 2, p1, p2);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
/* Switch patterns */
ret = ddr_modtst(i, 2, p2, p1);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
}
}
break;
case MEMTEST86_ID_10:
/* Modulo 20 check, all ones and zeros*/
p1 = 0;
for (i=0; i<MOD_SZ; i++) {
p2 = ~p1;
ret = ddr_modtst(i, 2, p1, p2);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
/* Switch patterns */
ret = ddr_modtst(i, 2, p2, p1);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
}
break;
case MEMTEST86_ID_11:
/* Modulo 20 check, 8 bit pattern*/
p0 = 0x80;
for (j=0; j<8; j++, p0=p0>>1) {
p1 = p0 | (p0<<8) | (p0<<16) | (p0<<24);
for (i=0; i<MOD_SZ; i++) {
p2 = ~p1;
ret = ddr_modtst(i, 2, p1, p2);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
/* Switch patterns */
ret = ddr_modtst(i, 2, p2, p1);
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
}
}
break;
case FARADAY_MEMTEST:
ret = ddr_sram_rw_verify();
if (ret != 0)
{
DSG_NOLF("Fail test case <%d> \n", id);
return ret;
}
break;
default:
break;
}
if(id > 0 && id < MEMTEST_ID_MAX)
DSG_NOLF("Pass test case <%d> \n", id);
}
}
/**
* @brief main, main dispatch function
*/
int main(void)
{
uint32_t ret;
SystemCoreClockUpdate(); // System Initialization
osKernelInitialize(); // Initialize CMSIS-RTOS
/* below is some primiary system init settings */
kdrv_system_init(); // primary system init
kdrv_system_init_ncpu(); // this is a must for ddr
kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr
/* below is some middleware init settings */
kdrv_uart_initialize(); // for log printing
kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing
ret = ddr_memtest();
if(ret)
{
DSG_NOLF("============================== \n");
DSG_NOLF("========= DDR TEST FAIL =========== \n");
DSG_NOLF("============================== \n");
}
while(1) {
}
}

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/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*=============================================================================
mdw setting
=============================================================================*/
/* scpu/ncpu image size */
#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

544
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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
// #include "ARMCM4.h"
#include "kdrv_cmsis_core.h"
#elif defined (ARMCM4_FP)
// #include "ARMCM4_FP.h"
#include "kdrv_cmsis_core.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifdef KL520
#define XTAL (200000000UL) /* Oscillator frequency */
#else
#define XTAL (50000000UL) /* Oscillator frequency */
#endif
#define SYSTEM_CLOCK XTAL
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

55
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#!armcc -E
#define IRAM_START 0x10102000
#define IRAM_SIZE 0x00016000
#define DRAM_START 0x10200000
#define DRAM_SIZE 0x00016000
LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region
ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;ENTRANCE_SECTION0_TEXT +0 {
; .ANY (entr_section0)
;}
ENTRANCE_SECTION1_TEXT +0 {
.ANY (entr_section1)
}
ENTRANCE_SECTION2_TEXT +0 {
.ANY (entr_section2)
}
ENTRANCE_SECTION3_TEXT +0 {
.ANY (entr_section3)
}
ENTRANCE_SECTION4_TEXT +0 {
.ANY (entr_section4)
}
ENTRANCE_SECTION5_TEXT +0 {
.ANY (entr_section5)
}
ENTRANCE_SECTION6_TEXT +0 {
.ANY (entr_section6)
}
EXIT_SECTION_TEXT +0 {
.ANY (exit_section)
}
INIT_TEXT +0 {
.ANY (init_text)
}
FINI_TEXT +0 {
.ANY (fini_text)
}
INIT_DATA +0 {
.ANY (init_data)
}
RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 AlignExpr(+0,8) {
.ANY (misc_data)
}
}

337
build/example_kdrv/ddr/sn52096/scpu_keil/scpu.uvoptx Normal file
View File

@ -0,0 +1,337 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<ScvdPack>
<Filename>C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd</Filename>
<Type>ARM.CMSIS.5.6.0</Type>
<SubType>1</SubType>
</ScvdPack>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>main</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\main_scpu\ex_ddr_main.c</PathWithFileName>
<FilenameWithoutPath>ex_ddr_main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\project.h</PathWithFileName>
<FilenameWithoutPath>project.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>mdw</GroupName>
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<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
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<File>
<GroupNumber>2</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\mdw\console\kmdw_console.c</PathWithFileName>
<FilenameWithoutPath>kmdw_console.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>driver</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c</PathWithFileName>
<FilenameWithoutPath>kdrv_ddr.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</PathWithFileName>
<FilenameWithoutPath>kdrv_clock.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</PathWithFileName>
<FilenameWithoutPath>kdrv_system.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</PathWithFileName>
<FilenameWithoutPath>kdrv_power.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
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</File>
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<FilenameWithoutPath>kdrv_pwm.c</FilenameWithoutPath>
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<bShared>0</bShared>
</File>
<File>
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<FileNumber>10</FileNumber>
<FileType>1</FileType>
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<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_timer.c</PathWithFileName>
<FilenameWithoutPath>kdrv_timer.c</FilenameWithoutPath>
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<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
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<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

633
build/example_kdrv/ddr/sn52096/scpu_keil/scpu.uvprojx Normal file
View File

@ -0,0 +1,633 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM4_FP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.6.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
<bCustSvd>0</bCustSvd>
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<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>companion</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin"</UserProg1Name>
<UserProg2Name>post_build.bat</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>1</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4099</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>0</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
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<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>1</EndSel>
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<OnChipMemories>
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<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
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</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10200000</StartAddress>
<Size>0x16000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--gnu</MiscControls>
<Define>ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10100000</TextAddressRange>
<DataAddressRange>0x10200000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\mozart_96.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>main</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>2</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\scpu\lib\kapp\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>ex_ddr_main.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\ex_ddr_main.c</FilePath>
</File>
<File>
<FileName>project.h</FileName>
<FileType>5</FileType>
<FilePath>..\project.h</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>mdw</GroupName>
<Files>
<File>
<FileName>kmdw_console.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\mdw\console\kmdw_console.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<File>
<FileName>kdrv_ddr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c</FilePath>
</File>
<File>
<FileName>kdrv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</FilePath>
</File>
<File>
<FileName>kdrv_system.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</FilePath>
</File>
<File>
<FileName>kdrv_power.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</FilePath>
</File>
<File>
<FileName>kdrv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</FilePath>
</File>
<File>
<FileName>kdrv_pwm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c</FilePath>
</File>
<File>
<FileName>kdrv_timer.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_timer.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</api>
</apis>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.1"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config_USB.h" version="6.2.0">
<instance index="0" removed="1">RTE\File_System\FS_Config_USB_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="USB" Cvendor="Keil" Cversion="6.12.0" condition="File System and USB Host MSC" maxInstances="2"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config.c" version="5.2.1">
<instance index="0" removed="1">RTE\USB\USBH_Config_0.c</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_CustomClass.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_CustomClass.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="Custom Class" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_MSC.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_MSC.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="MSC" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance, Host Driver and File System USB Drive"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

6
build/example_kdrv/ddr/sn52096/scpu_keil/vtor.ini Normal file
View File

@ -0,0 +1,6 @@
MEMSET(0x10200000, 0x10000, 0)
MEMSET(0x10210000, 0x08000, 0)
_WDWORD(0xE000ED08, 0x10102000);
SP=_RDWORD(0x10102000) // Set Stack Pointer
PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler
BS main

397
build/example_kdrv/gdma/main_scpu/ex_gdma_main.c Normal file
View File

@ -0,0 +1,397 @@
/* --------------------------------------------------------------------------
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Name: main.c
* Purpose: RTX for Kneron
*
*---------------------------------------------------------------------------*/
#include <stdio.h>
#include <string.h>
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
#include "project.h"
#include "kdrv_ddr.h"
#include "kdrv_system.h"
#include "kdrv_uart.h"
#include "kmdw_memory.h" //for ddr_malloc
#include "kmdw_console.h"
#include "kdrv_cmsis_core.h"
#include <stdlib.h>
#include "kdrv_gdma.h"
#include "kdrv_pwm.h"
typedef enum
{
TEST_GDMA_KDP_MEMCPY,
TEST_GDMA_KDP_MEMCPY_ASYNC,
TEST_GDMA_KDP_TRANSFER,
TEST_GDMA_KDP_TRANSFER_ASYNC,
TEST_SPECIFIED_DMA_CHANNEL,
} GDMA_TEST_ITEM;
volatile static int dma_waiting = 1;
void dma_cb(kdrv_status_t status, void *arg)
{
if (status != KDRV_STATUS_OK)
kmdw_printf("kdrv_gdma_memcpy_async() failed\n");
dma_waiting = 0;
}
static int one_dma_memcpy_test(uint32_t dstAddr, uint32_t srcAddr, uint32_t size,
uint32_t loop, uint32_t test_item, int ch)
{
kdrv_pwmtimer_initialize(PWMTIMER1, PWMTMR_1MSEC_PERIOD);
memset((void *)srcAddr, 0, size);
memset((void *)dstAddr, 0, size);
for (int i = 0; i < size; i++)
{
*(uint8_t *)(srcAddr + i) = (rand() % 0XFF);
}
uint32_t tick_start, tick_end;
if (test_item == TEST_GDMA_KDP_MEMCPY)
{
tick_start = kdrv_current_t1_tick();
for (uint32_t i = 0; i < loop; i++)
{
kdrv_status_t dma_sts = kdrv_gdma_memcpy(dstAddr, srcAddr, size);
//kdrv_status_t dma_sts = kdrv_gdma_transfer(3, dstAddr, srcAddr, size);
if (dma_sts != KDRV_STATUS_OK)
kmdw_printf("kdrv_gdma_memcpy() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop);
//memcpy((void *)dstAddr, (void *)srcAddr, size);
}
tick_end = kdrv_current_t1_tick();
}
else if (test_item == TEST_GDMA_KDP_MEMCPY_ASYNC)
{
tick_start = kdrv_current_t1_tick();
for (uint32_t i = 0; i < loop; i++)
{
dma_waiting = 1;
kdrv_status_t dma_sts = kdrv_gdma_memcpy_async(dstAddr, srcAddr, size, dma_cb, NULL);
if (dma_sts != KDRV_STATUS_OK)
kmdw_printf("kdrv_gdma_memcpy_async() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop);
while (dma_waiting)
;
}
tick_end = kdrv_current_t1_tick();
}
else if (test_item == TEST_GDMA_KDP_TRANSFER)
{
kdrv_gdma_handle_t dma_handle;
kdrv_status_t sts = kdrv_gdma_acquire_handle(&dma_handle);
if(sts != KDRV_STATUS_OK)
{
kmdw_printf("acquire GDMA handle failed\n");
return -1;
}
gdma_setting_t dma_setting;
dma_setting.dst_width = GDMA_TXFER_WIDTH_32_BITS;
dma_setting.src_width = GDMA_TXFER_WIDTH_32_BITS;
dma_setting.burst_size = GDMA_BURST_SIZE_16;
dma_setting.dst_addr_ctrl = GDMA_INCREMENT_ADDRESS;
dma_setting.src_addr_ctrl = GDMA_INCREMENT_ADDRESS;
dma_setting.dma_mode = GDMA_NORMAL_MODE;
dma_setting.dma_dst_req = 0;
dma_setting.dma_src_req = 0;
kdrv_gdma_configure_setting(dma_handle, &dma_setting);
tick_start = kdrv_current_t1_tick();
for (uint32_t i = 0; i < loop; i++)
{
kdrv_status_t dma_sts = kdrv_gdma_transfer(dma_handle, dstAddr, srcAddr, size);
if (dma_sts != KDRV_STATUS_OK)
kmdw_printf("kdrv_gdma_transfer() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop);
}
tick_end = kdrv_current_t1_tick();
kdrv_gdma_release_handle(dma_handle);
}
else if (test_item == TEST_GDMA_KDP_TRANSFER_ASYNC)
{
kdrv_gdma_handle_t dma_handle;
kdrv_status_t sts = kdrv_gdma_acquire_handle(&dma_handle);
if(sts != KDRV_STATUS_OK)
{
kmdw_printf("acquire GDMA handle failed\n");
return -1;
}
gdma_setting_t dma_setting;
dma_setting.dst_width = GDMA_TXFER_WIDTH_32_BITS;
dma_setting.src_width = GDMA_TXFER_WIDTH_32_BITS;
dma_setting.burst_size = GDMA_BURST_SIZE_16;
dma_setting.dst_addr_ctrl = GDMA_INCREMENT_ADDRESS;
dma_setting.src_addr_ctrl = GDMA_INCREMENT_ADDRESS;
dma_setting.dma_mode = GDMA_NORMAL_MODE;
dma_setting.dma_dst_req = 0;
dma_setting.dma_src_req = 0;
kdrv_gdma_configure_setting(dma_handle, &dma_setting);
tick_start = kdrv_current_t1_tick();
for (uint32_t i = 0; i < loop; i++)
{
dma_waiting = 1;
kdrv_status_t dma_sts = kdrv_gdma_transfer_async(dma_handle, dstAddr, srcAddr, size, dma_cb, NULL);
if (dma_sts != KDRV_STATUS_OK)
kmdw_printf("kdrv_gdma_memcpy_async() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop);
while (dma_waiting)
;
}
tick_end = kdrv_current_t1_tick();
kdrv_gdma_release_handle(dma_handle);
}
else if (test_item == TEST_SPECIFIED_DMA_CHANNEL)
{
kdrv_gdma_handle_t dma_handle = ch;
gdma_setting_t dma_setting;
dma_setting.dst_width = GDMA_TXFER_WIDTH_32_BITS;
dma_setting.src_width = GDMA_TXFER_WIDTH_32_BITS;
dma_setting.burst_size = GDMA_BURST_SIZE_16;
dma_setting.dst_addr_ctrl = GDMA_INCREMENT_ADDRESS;
dma_setting.src_addr_ctrl = GDMA_INCREMENT_ADDRESS;
dma_setting.dma_mode = GDMA_NORMAL_MODE;
dma_setting.dma_dst_req = 0;
dma_setting.dma_src_req = 0;
kdrv_gdma_configure_setting(dma_handle, &dma_setting);
tick_start = kdrv_current_t1_tick();
for (uint32_t i = 0; i < loop; i++)
{
kdrv_status_t dma_sts = kdrv_gdma_transfer(dma_handle, dstAddr, srcAddr, size);
if (dma_sts != KDRV_STATUS_OK)
kmdw_printf("kdrv_gdma_transfer() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop);
}
tick_end = kdrv_current_t1_tick();
}
int cmp_sts = memcmp((const void *)srcAddr, (const void *)dstAddr, size);
float speed = (float)((size * loop) >> 10) / (tick_end - tick_start);
kdrv_pwmtimer_close(PWMTIMER1);
kmdw_printf("[memcpy] tid 0x%x copy 0x%x to 0x%x %d bytes x %d, spent %u ms speed: %1.f MB/s ... %s\n",
osThreadGetId(), srcAddr, dstAddr, size, loop, (tick_end - tick_start), speed, (cmp_sts == 0) ? "PASSED" : "FAILED");
return (cmp_sts == 0);
}
static void test_dma_functions()
{
kmdw_printf("\n================= [%s context] =================\n\n", osThreadGetId() == 0 ? "Non-OS" : "OS");
const uint32_t size_begin = 512;
const uint32_t count_begin = 32768 / 2;
{
kmdw_printf("[ kdrv_gdma_memcpy() tests ]\n");
uint32_t dstAddr = 0x62000000;
uint32_t srcAddr = 0x62800000;
int pass_count = 0;
kmdw_printf("\nAaddress and transfer size are not divisiable by 4:\n");
for (int i = 0; i < 4; i++)
pass_count += one_dma_memcpy_test(dstAddr + i, srcAddr + i, (8 * 1024) + i, 1000, TEST_GDMA_KDP_MEMCPY, 0);
kmdw_printf("\nDifferent transfer size:\n");
uint32_t size = size_begin;
uint32_t count = count_begin;
for (int i = 0; i < 15; i++)
{
pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_GDMA_KDP_MEMCPY, 0);
size *= 2;
count /= 2;
}
kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 19 - pass_count);
}
{
uint32_t dstAddr = 0x62000000;
uint32_t srcAddr = 0x62800000;
int pass_count = 0;
kmdw_printf("\n");
kmdw_printf("[ kdrv_gdma_memcpy_async() tests ]\n");
kmdw_printf("\nDifferent transfer size:\n");
uint32_t size = size_begin;
uint32_t count = count_begin;
for (int i = 0; i < 15; i++)
{
pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_GDMA_KDP_MEMCPY_ASYNC, 0);
size *= 2;
count /= 2;
}
kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 15 - pass_count);
}
{
uint32_t dstAddr = 0x62000000;
uint32_t srcAddr = 0x62800000;
int pass_count = 0;
kmdw_printf("\n");
kmdw_printf("[ kdrv_gdma_transfer() tests ]\n");
kmdw_printf("\nDifferent transfer size:\n");
uint32_t size = size_begin;
uint32_t count = count_begin;
for (int i = 0; i < 15; i++)
{
pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_GDMA_KDP_TRANSFER, 0);
size *= 2;
count /= 2;
}
kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 15 - pass_count);
}
{
uint32_t dstAddr = 0x62000000;
uint32_t srcAddr = 0x62800000;
int pass_count = 0;
kmdw_printf("\n");
kmdw_printf("[ kdrv_gdma_transfer_async() tests ]\n");
kmdw_printf("\nDifferent transfer size:\n");
uint32_t size = size_begin;
uint32_t count = count_begin;
for (int i = 0; i < 15; i++)
{
pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_GDMA_KDP_TRANSFER_ASYNC, 0);
size *= 2;
count /= 2;
}
kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 15 - pass_count);
}
{
uint32_t dstAddr = 0x62000000;
uint32_t srcAddr = 0x62800000;
int pass_count = 0;
kmdw_printf("\n");
kmdw_printf("[ kdrv_gdma_transfer() test all 8 DMA channels ]\n");
uint32_t size = 131072;
uint32_t count = 4000;
for (int i = 0; i < 8; i++)
{
kmdw_printf("Testing DMA CH %d:\n", i);
pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_SPECIFIED_DMA_CHANNEL, i);
}
kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 8 - pass_count);
}
kmdw_printf("All GDMA tests are done !!\n");
}
static void test_gdma_thread(void *arg)
{
test_dma_functions();
}
/**
* @brief main, main dispatch function
*/
int main(void)
{
SystemCoreClockUpdate(); // System Initialization
osKernelInitialize(); // Initialize CMSIS-RTOS
/* below is some primiary system init settings */
kdrv_system_init(); // primary system init
kdrv_system_init_ncpu(); // this is a must for ddr
kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr
/* below is some middleware init settings */
kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); // for memory alloc from ddr
kdrv_uart_initialize(); // for log printing
kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing
// init GDMA resources
kdrv_gdma_initialize();
// test GDMA functions in non-OS context
test_dma_functions();
// create a thread to test GDMA functions in OS context
osThreadNew(test_gdma_thread, NULL, NULL);
//application is triggered in host_com.c
if (osKernelGetState() == osKernelReady)
{
osKernelStart();
}
while (1)
{
}
}

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/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*=============================================================================
mdw setting
=============================================================================*/
/* scpu/ncpu image size */
#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

162
build/example_kdrv/gdma/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s Normal file
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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

89
build/example_kdrv/gdma/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c Normal file
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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
// #include "ARMCM4.h"
#include "kdrv_cmsis_core.h"
#elif defined (ARMCM4_FP)
// #include "ARMCM4_FP.h"
#include "kdrv_cmsis_core.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifdef KL520
#define XTAL (200000000UL) /* Oscillator frequency */
#else
#define XTAL (50000000UL) /* Oscillator frequency */
#endif
#define SYSTEM_CLOCK XTAL
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

55
build/example_kdrv/gdma/sn52096/scpu_keil/mozart_96.sct Normal file
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#!armcc -E
#define IRAM_START 0x10102000
#define IRAM_SIZE 0x00016000
#define DRAM_START 0x10200000
#define DRAM_SIZE 0x00016000
LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region
ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;ENTRANCE_SECTION0_TEXT +0 {
; .ANY (entr_section0)
;}
ENTRANCE_SECTION1_TEXT +0 {
.ANY (entr_section1)
}
ENTRANCE_SECTION2_TEXT +0 {
.ANY (entr_section2)
}
ENTRANCE_SECTION3_TEXT +0 {
.ANY (entr_section3)
}
ENTRANCE_SECTION4_TEXT +0 {
.ANY (entr_section4)
}
ENTRANCE_SECTION5_TEXT +0 {
.ANY (entr_section5)
}
ENTRANCE_SECTION6_TEXT +0 {
.ANY (entr_section6)
}
EXIT_SECTION_TEXT +0 {
.ANY (exit_section)
}
INIT_TEXT +0 {
.ANY (init_text)
}
FINI_TEXT +0 {
.ANY (fini_text)
}
INIT_DATA +0 {
.ANY (init_data)
}
RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 AlignExpr(+0,8) {
.ANY (misc_data)
}
}

349
build/example_kdrv/gdma/sn52096/scpu_keil/scpu.uvoptx Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<ScvdPack>
<Filename>C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd</Filename>
<Type>ARM.CMSIS.5.6.0</Type>
<SubType>1</SubType>
</ScvdPack>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>main</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\main_scpu\ex_gdma_main.c</PathWithFileName>
<FilenameWithoutPath>ex_gdma_main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
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<FileName>kdrv_gdma.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c</FilePath>
</File>
<File>
<FileName>kdrv_pwm.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</api>
</apis>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.1"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config_USB.h" version="6.2.0">
<instance index="0" removed="1">RTE\File_System\FS_Config_USB_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="USB" Cvendor="Keil" Cversion="6.12.0" condition="File System and USB Host MSC" maxInstances="2"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config.c" version="5.2.1">
<instance index="0" removed="1">RTE\USB\USBH_Config_0.c</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_CustomClass.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_CustomClass.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="Custom Class" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_MSC.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_MSC.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="MSC" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance, Host Driver and File System USB Drive"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

6
build/example_kdrv/gdma/sn52096/scpu_keil/vtor.ini Normal file
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MEMSET(0x10200000, 0x10000, 0)
MEMSET(0x10210000, 0x08000, 0)
_WDWORD(0xE000ED08, 0x10102000);
SP=_RDWORD(0x10102000) // Set Stack Pointer
PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler
BS main

64
build/example_kdrv/gpio/main_scpu/ex_gpio_main.c Normal file
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/* --------------------------------------------------------------------------
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Name: main.c
* Purpose: RTX for Kneron
*
*---------------------------------------------------------------------------*/
#include <stdio.h>
#include <string.h>
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
#include "project.h"
#include "kdrv_ddr.h"
#include "kdrv_system.h"
#include "kdrv_uart.h"
#include "kmdw_console.h"
#include "kdrv_cmsis_core.h"
extern void gpio_example_init(void);
/**
* @brief main, main dispatch function
*/
int main(void)
{
SystemCoreClockUpdate(); // System Initialization
osKernelInitialize(); // Initialize CMSIS-RTOS
/* below is some primiary system init settings */
kdrv_system_init(); // primary system init
/* below is some middleware init settings */
kdrv_uart_initialize(); // for log printing
kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing
// init some GPIO pins as input or output
gpio_example_init();
//application is triggered in host_com.c
if (osKernelGetState() == osKernelReady)
{
osKernelStart();
}
while (1)
{
}
}

128
build/example_kdrv/gpio/main_scpu/gpio_example.c Normal file
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/*
* Kneron peripheral driver test code for GPIO
*
* Copyright (C) 2019 Kneron, Inc. All rights reserved.
*
*/
#include "cmsis_os2.h"
#include "kdrv_pinmux.h"
#include "kdrv_gpio.h"
#include "kmdw_console.h"
static void gpio_test_thread(void *argument);
static void gpio_callback(kdrv_gpio_pin_t pin, void *arg);
void gpio_example_init(void)
{
DSG("Creating a user thread for interrupt notification\n");
// create a thread to wait for interrupt notifications
osThreadNew(&gpio_test_thread, NULL, NULL);
DSG("Configuring pins to GPIO function, GPIO22(SD_CLK), GPIO23(SD_CMD), GPIO24(SD_DAT0), GPIO25(SD_DAT1)\n");
/*
configure selected pins as GPIO function (pinmux)
users must check pinmux table to configure specified pins
as desired peripheral functions properly
*/
kdrv_pinmux_config(KDRV_PIN_SD_CLK, PIN_MODE_3, PIN_PULL_NONE, PIN_DRIVING_8MA); // as GPIO 22
kdrv_pinmux_config(KDRV_PIN_SD_CMD, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); // as GPIO 23
kdrv_pinmux_config(KDRV_PIN_SD_DAT_0, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); // as GPIO 24
kdrv_pinmux_config(KDRV_PIN_SD_DAT_1, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); // as GPIO 25
DSG("init gpio controller\n");
// init GPIO controller
kdrv_gpio_initialize();
DSG("setting GPIO22 : Output Low\n");
// set GPIO 22 as output low in the beginning
kdrv_gpio_set_attribute(GPIO_PIN_22, GPIO_DIR_OUTPUT);
kdrv_gpio_write_pin(GPIO_PIN_22, false);
DSG("setting GPIO23 : Input with pull-high\n");
// set GPIO 23 as digital input
kdrv_gpio_set_attribute(GPIO_PIN_23, GPIO_DIR_INPUT);
DSG("setting GPIO24 : Interrupt source, pull-high, debounce\n");
/* set GPIO 24 as interrupt input, pull-high, debounce */
{
// first disable interrupt in case of wrong condition
kdrv_gpio_set_interrupt(GPIO_PIN_24, false);
// set pin attributes as desired
kdrv_gpio_set_attribute(GPIO_PIN_24, (GPIO_DIR_INPUT | GPIO_INT_EDGE_FALLING));
// enable internal hardware debounce with clock rate
kdrv_gpio_set_debounce(GPIO_PIN_24, true /* 1 for enable */, 1000);
// at last enable interrupt after all settings done
kdrv_gpio_set_interrupt(GPIO_PIN_24, true);
}
DSG("setting GPIO25 : Interrupt source, pull-high, debounce\n");
/* set GPIO 25 as interrupt input, pull-high, debounce */
{
// first disable interrupt in case of wrong condition
kdrv_gpio_set_interrupt(GPIO_PIN_25, false);
// set pin attributes as desired
kdrv_gpio_set_attribute(GPIO_PIN_25, (GPIO_DIR_INPUT | GPIO_INT_EDGE_FALLING));
// enable internal hardware debounce with clock rate
kdrv_gpio_set_debounce(GPIO_PIN_25, true /* 1 for enable */, 1000);
// at last enable interrupt after all settings done
kdrv_gpio_set_interrupt(GPIO_PIN_25, true);
}
// set interrupt callback for GPIO interrupt
kdrv_gpio_register_callback(gpio_callback, NULL);
/* exit here then let kernel get started */
}
static void gpio_callback(kdrv_gpio_pin_t pin, void *arg)
{
if (pin == GPIO_PIN_24)
{
static bool toogle = false;
/* print something */
DSG("GPIO24(SD_DAT0) btn is clicked, now inverse GPIO22(SD_CLK)\n");
toogle = toogle ? false : true;
kdrv_gpio_write_pin(GPIO_PIN_22, toogle);
}
else if (pin == GPIO_PIN_25)
{
/* print something */
DSG("GPIO25(SD_DAT1) btn clicked\n");
}
}
static void gpio_test_thread(void *argument)
{
for (;;)
{
uint32_t flags = osThreadFlagsWait(0x1, osFlagsWaitAny, 2000); // 2 secs timeout
if (flags == osFlagsErrorTimeout)
{
// do following per 2 secs timeout
// read GPIO 23
bool value;
kdrv_gpio_read_pin(GPIO_PIN_23, &value);
/* print GPIO 23 value */
DSG("GPIO23(SD_CMD) input : %s\n", value ? "High" : "Low");
}
}
}

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build/example_kdrv/gpio/sn52096/project.h Normal file
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/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*=============================================================================
mdw setting
=============================================================================*/
/* scpu/ncpu image size */
#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
// #include "ARMCM4.h"
#include "kdrv_cmsis_core.h"
#elif defined (ARMCM4_FP)
// #include "ARMCM4_FP.h"
#include "kdrv_cmsis_core.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifdef KL520
#define XTAL (200000000UL) /* Oscillator frequency */
#else
#define XTAL (50000000UL) /* Oscillator frequency */
#endif
#define SYSTEM_CLOCK XTAL
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

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build/example_kdrv/gpio/sn52096/scpu_keil/mozart_96.sct Normal file
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#!armcc -E
#define IRAM_START 0x10102000
#define IRAM_SIZE 0x00016000
#define DRAM_START 0x10200000
#define DRAM_SIZE 0x00016000
LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region
ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;ENTRANCE_SECTION0_TEXT +0 {
; .ANY (entr_section0)
;}
ENTRANCE_SECTION1_TEXT +0 {
.ANY (entr_section1)
}
ENTRANCE_SECTION2_TEXT +0 {
.ANY (entr_section2)
}
ENTRANCE_SECTION3_TEXT +0 {
.ANY (entr_section3)
}
ENTRANCE_SECTION4_TEXT +0 {
.ANY (entr_section4)
}
ENTRANCE_SECTION5_TEXT +0 {
.ANY (entr_section5)
}
ENTRANCE_SECTION6_TEXT +0 {
.ANY (entr_section6)
}
EXIT_SECTION_TEXT +0 {
.ANY (exit_section)
}
INIT_TEXT +0 {
.ANY (init_text)
}
FINI_TEXT +0 {
.ANY (fini_text)
}
INIT_DATA +0 {
.ANY (init_data)
}
RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 AlignExpr(+0,8) {
.ANY (misc_data)
}
}

337
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>0</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\UL2CM3.DLL</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<ScvdPack>
<Filename>C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd</Filename>
<Type>ARM.CMSIS.5.6.0</Type>
<SubType>1</SubType>
</ScvdPack>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>0</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>0</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>main</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\main_scpu\ex_gpio_main.c</PathWithFileName>
<FilenameWithoutPath>ex_gpio_main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\project.h</PathWithFileName>
<FilenameWithoutPath>project.h</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\main_scpu\gpio_example.c</PathWithFileName>
<FilenameWithoutPath>gpio_example.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>mdw</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\mdw\console\kmdw_console.c</PathWithFileName>
<FilenameWithoutPath>kmdw_console.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>driver</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</PathWithFileName>
<FilenameWithoutPath>kdrv_clock.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</PathWithFileName>
<FilenameWithoutPath>kdrv_system.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>7</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</PathWithFileName>
<FilenameWithoutPath>kdrv_power.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>8</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</PathWithFileName>
<FilenameWithoutPath>kdrv_uart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>9</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c</PathWithFileName>
<FilenameWithoutPath>kdrv_gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>10</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c</PathWithFileName>
<FilenameWithoutPath>kdrv_pinmux.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
<Group>
<GroupName>::Device</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>1</RteFlg>
</Group>
</ProjectOpt>

633
build/example_kdrv/gpio/sn52096/scpu_keil/scpu.uvprojx Normal file
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@ -0,0 +1,633 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>ARMCM4_FP</Device>
<Vendor>ARM</Vendor>
<PackID>ARM.CMSIS.5.6.0</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>companion</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name>fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin"</UserProg1Name>
<UserProg2Name>post_build.bat</UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>1</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -MPU</SimDllArguments>
<SimDlgDll>DCM.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM4</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> -MPU</TargetDllArguments>
<TargetDlgDll>TCM.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM4</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>4100</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3>"" ()</Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>0</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M4"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>2</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>1</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x20000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x10102000</StartAddress>
<Size>0x16000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x10200000</StartAddress>
<Size>0x16000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>4</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls>--gnu</MiscControls>
<Define>ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW</Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>0</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>0</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x10100000</TextAddressRange>
<DataAddressRange>0x10200000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile>.\mozart_96.sct</ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>main</GroupName>
<GroupOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>2</IncludeInBuild>
<AlwaysBuild>2</AlwaysBuild>
<GenerateAssemblyFile>2</GenerateAssemblyFile>
<AssembleAssemblyFile>2</AssembleAssemblyFile>
<PublicsOnly>2</PublicsOnly>
<StopOnExitCode>11</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<GroupArmAds>
<Cads>
<interw>2</interw>
<Optim>0</Optim>
<oTime>2</oTime>
<SplitLS>2</SplitLS>
<OneElfS>2</OneElfS>
<Strict>2</Strict>
<EnumInt>2</EnumInt>
<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\scpu\\lib\kapp\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>ex_gpio_main.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\ex_gpio_main.c</FilePath>
</File>
<File>
<FileName>project.h</FileName>
<FileType>5</FileType>
<FilePath>..\project.h</FilePath>
</File>
<File>
<FileName>gpio_example.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\gpio_example.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>mdw</GroupName>
<Files>
<File>
<FileName>kmdw_console.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\mdw\console\kmdw_console.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<File>
<FileName>kdrv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</FilePath>
</File>
<File>
<FileName>kdrv_system.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</FilePath>
</File>
<File>
<FileName>kdrv_power.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</FilePath>
</File>
<File>
<FileName>kdrv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</FilePath>
</File>
<File>
<FileName>kdrv_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c</FilePath>
</File>
<File>
<FileName>kdrv_pinmux.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</api>
</apis>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.1"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config_USB.h" version="6.2.0">
<instance index="0" removed="1">RTE\File_System\FS_Config_USB_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="USB" Cvendor="Keil" Cversion="6.12.0" condition="File System and USB Host MSC" maxInstances="2"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config.c" version="5.2.1">
<instance index="0" removed="1">RTE\USB\USBH_Config_0.c</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_CustomClass.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_CustomClass.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="Custom Class" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_MSC.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_MSC.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="MSC" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance, Host Driver and File System USB Drive"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

6
build/example_kdrv/gpio/sn52096/scpu_keil/vtor.ini Normal file
View File

@ -0,0 +1,6 @@
MEMSET(0x10200000, 0x10000, 0)
MEMSET(0x10210000, 0x08000, 0)
_WDWORD(0xE000ED08, 0x10102000);
SP=_RDWORD(0x10102000) // Set Stack Pointer
PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler
BS main

83
build/example_kdrv/heap_4/main_scpu/ex_heap4_main.c Normal file
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@ -0,0 +1,83 @@
/* --------------------------------------------------------------------------
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Name: main.c
* Purpose: RTX for Kneron
*
*---------------------------------------------------------------------------*/
#include <stdio.h>
#include <string.h>
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
#include "project.h"
#include "kdrv_ddr.h"
#include "kdrv_system.h"
#include "kdrv_uart.h"
#include "kmdw_memory.h" //for ddr_malloc
#include "kmdw_console.h"
#include "kdrv_cmsis_core.h"
#include "heap_4.h"
void heap_example()
{
uint8_t *buffer[10] = {0};
uint32_t size[10] = {128, 255, 322, 1028, 2000, 4000, 10200, 20000, 30000, 45678};
for (int i = 0; i < 10; i++)
{
buffer[i] = pvPortMalloc(size[i]);
DSG("Allocating memory for buffer[%d] at addr 0x%p, size %u", i, buffer[i], size[i]);
}
for (int i = 0; i < 10; i++)
{
vPortFree(buffer[i]);
DSG("Freeing memory of buffer[%d] at addr 0x%p", i, buffer[i]);
}
}
/**
* @brief main, main dispatch function
*/
int main(void)
{
SystemCoreClockUpdate(); // System Initialization
osKernelInitialize(); // Initialize CMSIS-RTOS
/* below is some primiary system init settings */
kdrv_system_init(); // primary system init
kdrv_system_init_ncpu(); // this is a must for ddr
kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr
/* below is some middleware init settings */
kdrv_uart_initialize(); // for log printing
kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing
heap_example();
//application is triggered in host_com.c
if (osKernelGetState() == osKernelReady)
{
osKernelStart();
}
while (1)
{
}
}

390
build/example_kdrv/heap_4/main_scpu/heap_4.c Normal file
View File

@ -0,0 +1,390 @@
/*
FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
All rights reserved
VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
***************************************************************************
>>! NOTE: The modification to the GPL is included to allow you to !<<
>>! distribute a combined work that includes FreeRTOS without being !<<
>>! obliged to provide the source code for proprietary components !<<
>>! outside of the FreeRTOS kernel. !<<
***************************************************************************
FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
FOR A PARTICULAR PURPOSE. Full license text is available on the following
link: http://www.freertos.org/a00114.html
***************************************************************************
* *
* FreeRTOS provides completely free yet professionally developed, *
* robust, strictly quality controlled, supported, and cross *
* platform software that is more than just the market leader, it *
* is the industry's de facto standard. *
* *
* Help yourself get started quickly while simultaneously helping *
* to support the FreeRTOS project by purchasing a FreeRTOS *
* tutorial book, reference manual, or both: *
* http://www.FreeRTOS.org/Documentation *
* *
***************************************************************************
http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
the FAQ page "My application does not run, what could be wrong?". Have you
defined //configASSERT()?
http://www.FreeRTOS.org/support - In return for receiving this top quality
embedded software for free we request you assist our global community by
participating in the support forum.
http://www.FreeRTOS.org/training - Investing in training allows your team to
be as productive as possible as early as possible. Now you can receive
FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
Ltd, and the world's leading authority on the world's leading RTOS.
http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
including FreeRTOS+Trace - an indispensable productivity tool, a DOS
compatible FAT file system, and our tiny thread aware UDP/IP stack.
http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
licenses offer ticketed support, indemnification and commercial middleware.
http://www.SafeRTOS.com - High Integrity Systems also provide a safety
engineered and independently SIL3 certified version for use in safety and
mission critical applications that require provable dependability.
1 tab == 4 spaces!
*/
/*
* A sample implementation of pvPortMalloc() and vPortFree() that combines
* (coalescences) adjacent memory blocks as they are freed, and in so doing
* limits memory fragmentation.
*
* See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
* memory management pages of http://www.FreeRTOS.org for more information.
*/
#include <cmsis_os2.h>
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
all the API functions to use the MPU wrappers. That should only be done when
task.h is included from an application file. */
#define config_HEAP_START 0x62000000
#define configTOTAL_HEAP_SIZE 16*1024*1024
#define portBYTE_ALIGNMENT 16
#define portBYTE_ALIGNMENT_MASK (portBYTE_ALIGNMENT-1)
/* Block sizes must not get too small. */
#define heapMINIMUM_BLOCK_SIZE ((size_t)(xHeapStructSize << 1))
/* Assumes 8bit bytes! */
#define heapBITS_PER_BYTE ((size_t)8)
/* Allocate the memory for the heap. */
static uint8_t ucHeap[configTOTAL_HEAP_SIZE];
/* Define the linked list structure. This is used to link free blocks in order
of their memory address. */
typedef struct A_BLOCK_LINK
{
struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */
size_t xBlockSize; /*<< The size of the free block. */
} BlockLink_t;
/*-----------------------------------------------------------*/
/*
* Inserts a block of memory that is being freed into the correct position in
* the list of free memory blocks. The block being freed will be merged with
* the block in front it and/or the block behind it if the memory blocks are
* adjacent to each other.
*/
static void prvInsertBlockIntoFreeList(BlockLink_t *pxBlockToInsert);
/*
* Called automatically to setup the required heap structures the first time
* pvPortMalloc() is called.
*/
static void prvHeapInit(void);
/*-----------------------------------------------------------*/
/* The size of the structure placed at the beginning of each allocated memory
block must by correctly byte aligned. */
static const size_t xHeapStructSize = (sizeof(BlockLink_t) + ((size_t)(portBYTE_ALIGNMENT - 1))) & ~((size_t)portBYTE_ALIGNMENT_MASK);
/* Create a couple of list links to mark the start and end of the list. */
static BlockLink_t xStart, *pxEnd = NULL;
/* Keeps track of the number of free bytes remaining, but says nothing about
fragmentation. */
static size_t xFreeBytesRemaining = 0U;
static size_t xMinimumEverFreeBytesRemaining = 0U;
/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize
member of an BlockLink_t structure is set then the block belongs to the
application. When the bit is free the block is still part of the free heap
space. */
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc(size_t xWantedSize)
{
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if (pxEnd == NULL)
{
prvHeapInit();
}
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if ((xWantedSize & xBlockAllocatedBit) == 0)
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if (xWantedSize > 0)
{
xWantedSize += xHeapStructSize;
/* Ensure that blocks are always aligned to the required number
of bytes. */
if ((xWantedSize & portBYTE_ALIGNMENT_MASK) != 0x00)
{
/* Byte alignment required. */
xWantedSize += (portBYTE_ALIGNMENT - (xWantedSize & portBYTE_ALIGNMENT_MASK));
}
}
if ((xWantedSize > 0) && (xWantedSize <= xFreeBytesRemaining))
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
pxBlock = xStart.pxNextFreeBlock;
while ((pxBlock->xBlockSize < xWantedSize) && (pxBlock->pxNextFreeBlock != NULL))
{
pxPreviousBlock = pxBlock;
pxBlock = pxBlock->pxNextFreeBlock;
}
/* If the end marker was reached then a block of adequate size
was not found. */
if (pxBlock != pxEnd)
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = (void *)(((uint8_t *)pxPreviousBlock->pxNextFreeBlock) + xHeapStructSize);
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
/* If the block is larger than required it can be split into
two. */
if ((pxBlock->xBlockSize - xWantedSize) > heapMINIMUM_BLOCK_SIZE)
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = (void *)(((uint8_t *)pxBlock) + xWantedSize);
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
pxBlock->xBlockSize = xWantedSize;
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList(pxNewBlockLink);
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
if (xFreeBytesRemaining < xMinimumEverFreeBytesRemaining)
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
pxBlock->pxNextFreeBlock = NULL;
}
}
}
return pvReturn;
}
/*-----------------------------------------------------------*/
void vPortFree(void *pv)
{
uint8_t *puc = (uint8_t *)pv;
BlockLink_t *pxLink;
if (pv != NULL)
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
/* This casting is to keep the compiler from issuing warnings. */
pxLink = (void *)puc;
if ((pxLink->xBlockSize & xBlockAllocatedBit) != 0)
{
if (pxLink->pxNextFreeBlock == NULL)
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
//vTaskSuspendAll();
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
prvInsertBlockIntoFreeList(((BlockLink_t *)pxLink));
}
}
}
}
}
/*-----------------------------------------------------------*/
size_t xPortGetFreeHeapSize(void)
{
return xFreeBytesRemaining;
}
/*-----------------------------------------------------------*/
size_t xPortGetMinimumEverFreeHeapSize(void)
{
return xMinimumEverFreeBytesRemaining;
}
/*-----------------------------------------------------------*/
void vPortInitialiseBlocks(void)
{
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit(void)
{
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = (size_t)config_HEAP_START;
if ((uxAddress & portBYTE_ALIGNMENT_MASK) != 0)
{
uxAddress += (portBYTE_ALIGNMENT - 1);
uxAddress &= ~((size_t)portBYTE_ALIGNMENT_MASK);
xTotalHeapSize -= uxAddress - (size_t)ucHeap;
}
pucAlignedHeap = (uint8_t *)uxAddress;
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = (void *)pucAlignedHeap;
xStart.xBlockSize = (size_t)0;
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ((size_t)pucAlignedHeap) + xTotalHeapSize;
uxAddress -= xHeapStructSize;
uxAddress &= ~((size_t)portBYTE_ALIGNMENT_MASK);
pxEnd = (void *)uxAddress;
pxEnd->xBlockSize = 0;
pxEnd->pxNextFreeBlock = NULL;
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = (void *)pucAlignedHeap;
pxFirstFreeBlock->xBlockSize = uxAddress - (size_t)pxFirstFreeBlock;
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ((size_t)1) << ((sizeof(size_t) * heapBITS_PER_BYTE) - 1);
}
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList(BlockLink_t *pxBlockToInsert)
{
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for (pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock)
{
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = (uint8_t *)pxIterator;
if ((puc + pxIterator->xBlockSize) == (uint8_t *)pxBlockToInsert)
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
pxBlockToInsert = pxIterator;
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = (uint8_t *)pxBlockToInsert;
if ((puc + pxBlockToInsert->xBlockSize) == (uint8_t *)pxIterator->pxNextFreeBlock)
{
if (pxIterator->pxNextFreeBlock != pxEnd)
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
}
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if (pxIterator != pxBlockToInsert)
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
}
}

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#ifndef __HEAP_4_H_
#define __HEAP_4_H_
#include <stdlib.h>
extern void *pvPortMalloc(size_t xWantedSize);
extern void vPortFree(void *pv);
#endif

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/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*=============================================================================
mdw setting
=============================================================================*/
/* scpu/ncpu image size */
#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

544
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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

89
build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c Normal file
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/**************************************************************************//**
* @file system_ARMCM4.c
* @brief CMSIS Device System Source File for
* ARMCM4 Device
* @version V5.3.1
* @date 09. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined (ARMCM4)
// #include "ARMCM4.h"
#include "kdrv_cmsis_core.h"
#elif defined (ARMCM4_FP)
// #include "ARMCM4_FP.h"
#include "kdrv_cmsis_core.h"
#else
#error device not specified!
#endif
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#ifdef KL520
#define XTAL (200000000UL) /* Oscillator frequency */
#else
#define XTAL (50000000UL) /* Oscillator frequency */
#endif
#define SYSTEM_CLOCK XTAL
/*----------------------------------------------------------------------------
Externals
*----------------------------------------------------------------------------*/
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
extern uint32_t __Vectors;
#endif
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = SYSTEM_CLOCK;
}
/*----------------------------------------------------------------------------
System initialization function
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
SCB->VTOR = (uint32_t) &__Vectors;
#endif
#if defined (__FPU_USED) && (__FPU_USED == 1U)
SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */
(3U << 11U*2U) ); /* enable CP11 Full Access */
#endif
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = SYSTEM_CLOCK;
}

55
build/example_kdrv/heap_4/sn52096/scpu_keil/mozart_96.sct Normal file
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#!armcc -E
#define IRAM_START 0x10102000
#define IRAM_SIZE 0x00016000
#define DRAM_START 0x10200000
#define DRAM_SIZE 0x00016000
LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region
ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
;ENTRANCE_SECTION0_TEXT +0 {
; .ANY (entr_section0)
;}
ENTRANCE_SECTION1_TEXT +0 {
.ANY (entr_section1)
}
ENTRANCE_SECTION2_TEXT +0 {
.ANY (entr_section2)
}
ENTRANCE_SECTION3_TEXT +0 {
.ANY (entr_section3)
}
ENTRANCE_SECTION4_TEXT +0 {
.ANY (entr_section4)
}
ENTRANCE_SECTION5_TEXT +0 {
.ANY (entr_section5)
}
ENTRANCE_SECTION6_TEXT +0 {
.ANY (entr_section6)
}
EXIT_SECTION_TEXT +0 {
.ANY (exit_section)
}
INIT_TEXT +0 {
.ANY (init_text)
}
FINI_TEXT +0 {
.ANY (fini_text)
}
INIT_DATA +0 {
.ANY (init_data)
}
RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data
.ANY (+RW +ZI)
}
RW_IRAM2 AlignExpr(+0,8) {
.ANY (misc_data)
}
}

325
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>scpu</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>0</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>7</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
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<PlainCh>2</PlainCh>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<wLevel>0</wLevel>
<uThumb>2</uThumb>
<uSurpInc>2</uSurpInc>
<uC99>2</uC99>
<uGnu>2</uGnu>
<useXO>2</useXO>
<v6Lang>0</v6Lang>
<v6LangP>0</v6LangP>
<vShortEn>2</vShortEn>
<vShortWch>2</vShortWch>
<v6Lto>2</v6Lto>
<v6WtE>2</v6WtE>
<v6Rtti>2</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath>..\..\..\..\scpu\\lib\kapp\include</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>2</interw>
<Ropi>2</Ropi>
<Rwpi>2</Rwpi>
<thumb>2</thumb>
<SplitLS>2</SplitLS>
<SwStkChk>2</SwStkChk>
<NoWarn>2</NoWarn>
<uSurpInc>2</uSurpInc>
<useXO>2</useXO>
<uClangAs>2</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
</GroupArmAds>
</GroupOption>
<Files>
<File>
<FileName>heap_4.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\heap_4.c</FilePath>
</File>
<File>
<FileName>project.h</FileName>
<FileType>5</FileType>
<FilePath>..\project.h</FilePath>
</File>
<File>
<FileName>ex_heap4_main.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\main_scpu\ex_heap4_main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>mdw</GroupName>
<Files>
<File>
<FileName>kmdw_console.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\mdw\console\kmdw_console.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>driver</GroupName>
<Files>
<File>
<FileName>kdrv_clock.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c</FilePath>
</File>
<File>
<FileName>kdrv_system.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c</FilePath>
</File>
<File>
<FileName>kdrv_power.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c</FilePath>
</File>
<File>
<FileName>kdrv_ddr.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c</FilePath>
</File>
<File>
<FileName>kdrv_uart.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>::CMSIS</GroupName>
</Group>
<Group>
<GroupName>::Device</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis>
<api Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" exclusive="1">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</api>
</apis>
<components>
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.3.0" condition="ARMv6_7_8-M Device">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS">
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</component>
</components>
<files>
<file attr="config" category="source" name="CMSIS\RTOS2\RTX\Config\RTX_Config.c" version="5.1.0">
<instance index="0">RTE\CMSIS\RTX_Config.c</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="CMSIS\RTOS2\RTX\Config\RTX_Config.h" version="5.5.0">
<instance index="0">RTE\CMSIS\RTX_Config.h</instance>
<component Capiversion="2.1.3" Cclass="CMSIS" Cgroup="RTOS2" Csub="Keil RTX5" Cvariant="Library" Cvendor="ARM" Cversion="5.5.1" condition="RTOS2 RTX5 Lib"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="header" name="Config\EventRecorderConf.h" version="1.1.0">
<instance index="0" removed="1">RTE\Compiler\EventRecorderConf.h</instance>
<component Cbundle="ARM Compiler" Cclass="Compiler" Cgroup="Event Recorder" Cvariant="DAP" Cvendor="Keil" Cversion="1.4.0" condition="Cortex-M Device"/>
<package name="ARM_Compiler" schemaVersion="1.4.9" url="http://www.keil.com/pack/" vendor="Keil" version="1.6.1"/>
<targetInfos/>
</file>
<file attr="config" category="sourceAsm" condition="ARMCC" name="Device\ARM\ARMCM4\Source\ARM\startup_ARMCM4.s" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\startup_ARMCM4.s</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="sourceC" name="Device\ARM\ARMCM4\Source\system_ARMCM4.c" version="1.0.0">
<instance index="0">RTE\Device\ARMCM4_FP\system_ARMCM4.c</instance>
<component Cclass="Device" Cgroup="Startup" Cvendor="ARM" Cversion="1.2.0" condition="ARMCM4 CMSIS"/>
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.6.0"/>
<targetInfos>
<targetInfo name="scpu"/>
</targetInfos>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config.c" version="6.3.0">
<instance index="0" removed="1">RTE\File_System\FS_Config.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Config_USB.h" version="6.2.0">
<instance index="0" removed="1">RTE\File_System\FS_Config_USB_0.h</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="Drive" Csub="USB" Cvendor="Keil" Cversion="6.12.0" condition="File System and USB Host MSC" maxInstances="2"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="FileSystem\Config\FS_Debug.c" version="1.0.0">
<instance index="0" removed="1">RTE\File_System\FS_Debug.c</instance>
<component Cbundle="MDK-Plus" Cclass="File System" Cgroup="CORE" Cvariant="LFN Debug" Cvendor="Keil" Cversion="6.12.0" condition="CMSIS Core with RTOS and File System I/O and Event Recorder"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config.c" version="5.2.1">
<instance index="0" removed="1">RTE\USB\USBH_Config_0.c</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver" maxInstances="4"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_CustomClass.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_CustomClass.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="Custom Class" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance and Host Driver"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
<file attr="config" category="source" name="USB\Config\USBH_Config_MSC.h" version="5.0.0">
<instance index="0" removed="1">RTE\USB\USBH_Config_MSC.h</instance>
<component Cbundle="MDK-Pro" Cclass="USB" Cgroup="Host" Csub="MSC" Cvendor="Keil" Cversion="6.13.6" condition="USB Core, Host Instance, Host Driver and File System USB Drive"/>
<package name="MDK-Middleware" schemaVersion="1.4" url="http://www.keil.com/pack/" vendor="Keil" version="7.9.0"/>
<targetInfos/>
</file>
</files>
</RTE>
</Project>

6
build/example_kdrv/heap_4/sn52096/scpu_keil/vtor.ini Normal file
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MEMSET(0x10200000, 0x10000, 0)
MEMSET(0x10210000, 0x08000, 0)
_WDWORD(0xE000ED08, 0x10102000);
SP=_RDWORD(0x10102000) // Set Stack Pointer
PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler
BS main

64
build/example_kdrv/i2c_master/main_scpu/ex_i2cm_main.c Normal file
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/* --------------------------------------------------------------------------
* Copyright (c) 2013-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* Name: main.c
* Purpose: RTX for Kneron
*
*---------------------------------------------------------------------------*/
#include <stdio.h>
#include <string.h>
#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5
#include "project.h"
#include "kdrv_ddr.h"
#include "kdrv_system.h"
#include "kdrv_uart.h"
#include "kmdw_memory.h" //for ddr_malloc
#include "kmdw_console.h"
#include "kdrv_cmsis_core.h"
extern void i2c_master_example(void);
/**
* @brief main, main dispatch function
*/
int main(void)
{
SystemCoreClockUpdate(); // System Initialization
osKernelInitialize(); // Initialize CMSIS-RTOS
/* below is some primiary system init settings */
kdrv_system_init(); // primary system init
/* below is some middleware init settings */
kdrv_uart_initialize(); // for log printing
kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing
i2c_master_example();
//application is triggered in host_com.c
if (osKernelGetState() == osKernelReady)
{
osKernelStart();
}
while (1)
{
}
}

70
build/example_kdrv/i2c_master/main_scpu/i2c_master_example.c Normal file
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/*
* Kneron I2C driver API testing code
*
* Copyright (C) 2019 Kneron, Inc. All rights reserved.
*
*/
#include "cmsis_os2.h"
#include "kdrv_i2c.h"
#include "kdrv_pinmux.h"
#include "kmdw_console.h"
static void i2c_sht20_thread(void *argument)
{
uint16_t dev_addr = 0x40;
uint8_t cmd = 0xF3;
uint8_t data[3];
kdrv_status_t status;
while(1)
{
status = kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 1, 1, 1, &cmd);
if(status != KDRV_STATUS_OK){
DSG("kdrv_i2c_write_register() failed, status = %d\n", status);
break;
}
while(1)
{
osDelay(10);
status = kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 3, 3, 3, data);
if(status != KDRV_STATUS_OK){
continue;
}
else
{
DSG("read data = 0x%x 0x%x 0x%x\n", data[0], data[1], data[2]);
osDelay(5000);
break;
}
}
}
}
void i2c_master_example()
{
DSG("Configuring pins for I2C device, enable KDRV_PIN_I2C0_SCL and KDRV_PIN_I2C0_SCL\n");
/*
configure selected pins as GPIO function (pinmux)
users must check pinmux table to configure specified pins
as desired peripheral functions properly
*/
kdrv_pinmux_config(KDRV_PIN_I2C0_SCL, PIN_MODE_0, PIN_PULL_NONE, PIN_DRIVING_8MA);
kdrv_pinmux_config(KDRV_PIN_I2C0_SDA, PIN_MODE_0, PIN_PULL_NONE, PIN_DRIVING_8MA);
DSG("init I2C0\n");
// init GPIO controller
kdrv_status_t status;
if( KDRV_STATUS_OK == (status = kdrv_i2c_initialize(KDRV_I2C_CTRL_0, KDRV_I2C_SPEED_400K)))
osThreadNew(i2c_sht20_thread, NULL, NULL);
else{
DSG("kdrv_i2c_initialize() failed, status = \n", status);
}
}

164
build/example_kdrv/i2c_master/sn52096/project.h Normal file
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/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
*
* The information contained herein is property of Kneron, Inc.
* Terms and conditions of usage are described in detail in Kneron
* STANDARD SOFTWARE LICENSE AGREEMENT.
*
* Licensees are granted free, non-transferable use of the information.
* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
* from the file.
*/
/******************************************************************************
* Filename:
* ---------
* project.h
*
* Description:
* ------------
*
*
******************************************************************************/
#ifndef _PROJECT_H_
#define _PROJECT_H_
/*=============================================================================
asic setting
=============================================================================*/
#include "membase.h"
/*=============================================================================
board setting
=============================================================================*/
#include "board.h"
#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
#define FLASH_SIZE FLASH_SIZE_256MBIT
#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
#define FLASH_DRV FLASH_DRV_NORMAL_MODE
/*=============================================================================
COMM setting
=============================================================================*/
#define UART_NUM 1
#define MSG_PORT COMM_PORT_ID_0
#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
/*=============================================================================
Pinmux setting
=============================================================================*/
#define PIN_NUM 38
#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
/*=============================================================================
fw setting
=============================================================================*/
#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
/*=============================================================================
DDR configuration
=============================================================================*/
/* DDR table */
#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
/** Reserve for all_models.bin */
//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
/** Resseve for DDR heap. Allocation direction from END to BEGIN */
//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
/** Reserve for system information, 188KB */
//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */
//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */
/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
/*=============================================================================
Flash configuration
=============================================================================*/
/* Flash table */
//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
/*=============================================================================
mdw setting
=============================================================================*/
/* scpu/ncpu image size */
#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-->critical setting<--
Below setting is for RD tuning or testing.
**Don't touch anything if you don't know what you are doing**
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
#endif //_PROJECT_H_

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
#include "kmdw_power_manager.h"
#include "kmdw_console.h"
__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void)
{
while(1);
}
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
kmdw_power_manager_cpu_idle();
}
__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id)
{
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
#if 0
err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id);
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
// Reserved
break;
}
for (;;) {}
//return 0U;
#else
kmdw_power_manager_error_notify(code, object_id);
return 0;
#endif
}

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/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.4.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 4096
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 16
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 1
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 10
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 10
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 256
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 256
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 256
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 256
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 256
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial event filter settings applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Event filter settings for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <e.7>Memory Management
// <i> Filter enable settings for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMORY_FILTER
#define OS_EVR_MEMORY_FILTER 0x81U
#endif
// <e.7>Kernel
// <i> Filter enable settings for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_KERNEL_FILTER
#define OS_EVR_KERNEL_FILTER 0x81U
#endif
// <e.7>Thread
// <i> Filter enable settings for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_THREAD_FILTER
#define OS_EVR_THREAD_FILTER 0x85U
#endif
// <e.7>Timer
// <i> Filter enable settings for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_TIMER_FILTER
#define OS_EVR_TIMER_FILTER 0x81U
#endif
// <e.7>Event Flags
// <i> Filter enable settings for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_EVFLAGS_FILTER
#define OS_EVR_EVFLAGS_FILTER 0x81U
#endif
// <e.7>Mutex
// <i> Filter enable settings for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MUTEX_FILTER
#define OS_EVR_MUTEX_FILTER 0x81U
#endif
// <e.7>Semaphore
// <i> Filter enable settings for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_SEMAPHORE_FILTER
#define OS_EVR_SEMAPHORE_FILTER 0x81U
#endif
// <e.7>Memory Pool
// <i> Filter enable settings for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MEMPOOL_FILTER
#define OS_EVR_MEMPOOL_FILTER 0x81U
#endif
// <e.7>Message Queue
// <i> Filter enable settings for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </e>
#ifndef OS_EVR_MSGQUEUE_FILTER
#define OS_EVR_MSGQUEUE_FILTER 0x81U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#define OS_THREAD_LIBSPACE_NUM 4
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

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;/**************************************************************************//**
; * @file startup_ARMCM4.s
; * @brief CMSIS Core Device Startup File for
; * ARMCM4 Device
; * @version V5.3.1
; * @date 09. July 2018
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;<h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
__stack_limit
Stack_Mem SPACE Stack_Size
__initial_sp
;<h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
;</h>
Heap_Size EQU 0x00002000
IF Heap_Size != 0 ; Heap is provided
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
ENDIF
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; -14 NMI Handler
DCD HardFault_Handler ; -13 Hard Fault Handler
DCD MemManage_Handler ; -12 MPU Fault Handler
DCD BusFault_Handler ; -11 Bus Fault Handler
DCD UsageFault_Handler ; -10 Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; -5 SVCall Handler
DCD DebugMon_Handler ; -4 Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; -2 PendSV Handler
DCD SysTick_Handler ; -1 SysTick Handler
; Interrupts
DCD Interrupt0_Handler ; 0 Interrupt 0
DCD Interrupt1_Handler ; 1 Interrupt 1
DCD Interrupt2_Handler ; 2 Interrupt 2
DCD AHB_DMA_IRQHandler ; 3 Interrupt 3
DCD Interrupt4_Handler ; 4 Interrupt 4
DCD Interrupt5_Handler ; 5 Interrupt 5
DCD Interrupt6_Handler ; 6 Interrupt 6
DCD Interrupt7_Handler ; 7 Interrupt 7
DCD Interrupt8_Handler ; 8 Interrupt 8
DCD Interrupt9_Handler ; 9 Interrupt 9
SPACE (214 * 4) ; Interrupts 10 .. 224 are left out
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
MACRO
Set_Default_Handler $Handler_Name
$Handler_Name PROC
EXPORT $Handler_Name [WEAK]
B .
ENDP
MEND
; Default exception/interrupt handler
Set_Default_Handler NMI_Handler
Set_Default_Handler HardFault_Handler
Set_Default_Handler MemManage_Handler
Set_Default_Handler BusFault_Handler
Set_Default_Handler UsageFault_Handler
Set_Default_Handler SVC_Handler
Set_Default_Handler DebugMon_Handler
Set_Default_Handler PendSV_Handler
Set_Default_Handler SysTick_Handler
Set_Default_Handler Interrupt0_Handler
Set_Default_Handler Interrupt1_Handler
Set_Default_Handler Interrupt2_Handler
Set_Default_Handler AHB_DMA_IRQHandler
Set_Default_Handler Interrupt4_Handler
Set_Default_Handler Interrupt5_Handler
Set_Default_Handler Interrupt6_Handler
Set_Default_Handler Interrupt7_Handler
Set_Default_Handler Interrupt8_Handler
Set_Default_Handler Interrupt9_Handler
ALIGN
; User setup Stack & Heap
EXPORT __stack_limit
EXPORT __initial_sp
IF Heap_Size != 0 ; Heap is provided
EXPORT __heap_base
EXPORT __heap_limit
ENDIF
END

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