commit f503ec9b05973fb2d297b0586f82aef4fc7ffd30 Author: Dereck Hao Date: Wed Dec 17 15:55:25 2025 +0800 Initial upload of KL520 SDK 2.2 diff --git a/app/demo_customize_inf_multiple_models.c b/app/demo_customize_inf_multiple_models.c new file mode 100644 index 0000000..51262a3 --- /dev/null +++ b/app/demo_customize_inf_multiple_models.c @@ -0,0 +1,185 @@ +/* + * Kneron Application general functions + * + * Copyright (C) 2021 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include + +#include "model_type.h" +#include "model_res.h" +#include "kmdw_console.h" + +#include "kmdw_inference_app.h" +#include "kmdw_fifoq_manager.h" +#include "demo_customize_inf_multiple_models.h" + +#define TY_MAX_BOX_NUM (50) +#define FACE_SCORE_THRESHOLD 0.8f + +// for face detection result, should be in DDR +static struct yolo_result_s *fd_result = NULL; + +static int inference_face_detection(demo_customize_inf_multiple_models_header_t *input_header, + struct yolo_result_s *fd_result /* output */) +{ + // config image preprocessing and model settings + kmdw_inference_app_config_t inf_config; + memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false' + + // image buffer address should be just after the header + inf_config.num_image = 1; + inf_config.image_list[0].image_buf = (void *)((uint32_t)input_header + sizeof(demo_customize_inf_multiple_models_header_t)); + inf_config.image_list[0].image_width = input_header->width; + inf_config.image_list[0].image_height = input_header->height; + inf_config.image_list[0].image_channel = 3; // assume RGB565 + inf_config.image_list[0].image_format = KP_IMAGE_FORMAT_RGB565; // assume RGB565 + inf_config.image_list[0].image_resize = KP_RESIZE_ENABLE; // enable resize + inf_config.image_list[0].image_padding = KP_PADDING_CORNER; // enable padding on corner + inf_config.image_list[0].image_norm = KP_NORMALIZE_KNERON; // this depends on model + inf_config.model_id = KNERON_FD_MASK_MBSSD_200_200_3; // this depends on model + + // set up fd result output buffer for ncpu/npu + inf_config.ncpu_result_buf = (void *)fd_result; + + return kmdw_inference_app_execute(&inf_config); +} + +static int inference_face_landmarks(demo_customize_inf_multiple_models_header_t *input_header, + struct bounding_box_s *face_box, + kp_landmark_result_t *lm_result /* output */) +{ + // config image preprocessing and model settings + kmdw_inference_app_config_t inf_config; + memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false' + + int32_t left = (int32_t)(face_box->x1); + int32_t top = (int32_t)(face_box->y1); + int32_t right = (int32_t)(face_box->x2); + int32_t bottom = (int32_t)(face_box->y2); + + // image buffer address should be just after the header + inf_config.model_id = KNERON_LM_5PTS_ONET_56_56_3; // this depends on model + inf_config.num_image = 1; + inf_config.image_list[0].image_buf = (void *)((uint32_t)input_header + sizeof(demo_customize_inf_multiple_models_header_t)); + inf_config.image_list[0].image_width = input_header->width; + inf_config.image_list[0].image_height = input_header->height; + inf_config.image_list[0].image_channel = 3; // assume RGB565 + inf_config.image_list[0].image_format = KP_IMAGE_FORMAT_RGB565; // assume RGB565 + inf_config.image_list[0].image_norm = KP_NORMALIZE_KNERON; // this depends on model + inf_config.image_list[0].image_resize = KP_RESIZE_ENABLE; // enable resize + inf_config.image_list[0].image_padding = KP_PADDING_CORNER; // enable padding on corner + inf_config.image_list[0].enable_crop = true; // enable crop image in ncpu/npu + + // set crop box + inf_config.image_list[0].crop_area.crop_number = 0; + inf_config.image_list[0].crop_area.x1 = left; + inf_config.image_list[0].crop_area.y1 = top; + inf_config.image_list[0].crop_area.width = right - left; + inf_config.image_list[0].crop_area.height = bottom - top; + + // set up landmark result output buffer for ncpu/npu + inf_config.ncpu_result_buf = (void *)lm_result; + + return kmdw_inference_app_execute(&inf_config); +} + +static bool init_temp_buffer() +{ + // allocate DDR memory for ncpu/npu output restult + fd_result = (struct yolo_result_s *)kmdw_ddr_reserve(sizeof(struct yolo_result_s) + TY_MAX_BOX_NUM * sizeof(struct bounding_box_s)); + + if (fd_result == NULL) { + return false; + } + + return true; +} + +void demo_customize_inf_multiple_models(uint32_t job_id, int num_input_buf, void **inf_input_buf_list) +{ + if (1 != num_input_buf) { + kmdw_inference_app_send_status_code(job_id, KP_FW_WRONG_INPUT_BUFFER_COUNT_110); + return; + } + + // 'inf_input_buf' and 'inf_result_buf' are provided by kdp2 middleware + // the content of 'inf_input_buf' is transmitted from host SW = header + image + // 'inf_result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu) + + // now get an available free result buffer + // normally the begin part of result buffer should contain app-defined result header + // and the rest is for ncpu/npu inference output data + int inf_status; + int result_buf_size; + void *inf_result_buf = kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size); + + demo_customize_inf_multiple_models_header_t *input_header = (demo_customize_inf_multiple_models_header_t *)inf_input_buf_list[0]; + demo_customize_inf_multiple_models_result_t *output_result = (demo_customize_inf_multiple_models_result_t *)inf_result_buf; + + // pre set up result header stuff + // header_stamp is a must to correctly transfer result data back to host SW + output_result->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + output_result->header_stamp.total_size = sizeof(demo_customize_inf_multiple_models_result_t); + output_result->header_stamp.job_id = job_id; + + // this app needs extra DDR buffers for ncpu result + static bool is_init = false; + + if (!is_init) { + int status = init_temp_buffer(); + if (!status) { + // notify host error ! + output_result->header_stamp.status_code = KP_FW_DDR_MALLOC_FAILED_102; + kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false); + return; + } + + is_init = true; + } + + // do face detection + inf_status = inference_face_detection(input_header, fd_result); + if (inf_status != KP_SUCCESS) { + // notify host error ! + output_result->header_stamp.status_code = inf_status; + kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false); + return; + } + + int face_cnt = 0; + int max_face = (fd_result->box_count > FD_MAX) ? FD_MAX : fd_result->box_count; + + for (int i = 0; i < max_face; i++) { + struct bounding_box_s *face_box = &fd_result->boxes[i]; + kp_landmark_result_t *face_lm_result = &output_result->faces[face_cnt].lm; + + if (FACE_SCORE_THRESHOLD < face_box->score) { + // do face landmark for each faces + inf_status = inference_face_landmarks(input_header, face_box, face_lm_result); + + if (KP_SUCCESS != inf_status) { + // notify host error ! + output_result->header_stamp.status_code = inf_status; + kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false); + return; + } + + // skip it if face lm is not good + if (0.99f > face_lm_result->score) { + continue; + } + + memcpy(&output_result->faces[face_cnt].fd, face_box, sizeof(kp_bounding_box_t)); + face_cnt++; + } + } + + output_result->face_count = face_cnt; + output_result->header_stamp.status_code = KP_SUCCESS; + + kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false); +} diff --git a/app/demo_customize_inf_multiple_models.h b/app/demo_customize_inf_multiple_models.h new file mode 100644 index 0000000..0737b4a --- /dev/null +++ b/app/demo_customize_inf_multiple_models.h @@ -0,0 +1,29 @@ +#pragma once + +#define DEMO_KL520_CUSTOMIZE_INF_MULTIPLE_MODEL_JOB_ID 1001 +#define FD_MAX 10 + +typedef struct +{ + kp_bounding_box_t fd; /**< fd result */ + kp_landmark_result_t lm; /**< lm result */ +} __attribute__((aligned(4))) one_person_face_data_t; + +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t width; + uint32_t height; +} __attribute__((aligned(4))) demo_customize_inf_multiple_models_header_t; + +// result (header + data) for 'Kneron APP Yolo Inference' +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t face_count; + one_person_face_data_t faces[FD_MAX]; +} __attribute__((aligned(4))) demo_customize_inf_multiple_models_result_t; + +void demo_customize_inf_multiple_models(uint32_t job_id, int num_input_buf, void **inf_input_buf_list); diff --git a/app/demo_customize_inf_single_model.c b/app/demo_customize_inf_single_model.c new file mode 100644 index 0000000..face802 --- /dev/null +++ b/app/demo_customize_inf_single_model.c @@ -0,0 +1,103 @@ +/* + * Kneron Application general functions + * + * Copyright (C) 2021 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include + +#include "model_type.h" +#include "kmdw_console.h" + +#include "kmdw_inference_app.h" +#include "kmdw_fifoq_manager.h" +#include "demo_customize_inf_single_model.h" + +/** + * @brief describe a yolo post-process configurations for yolo v5 series + */ +typedef struct +{ + float prob_thresh; + float nms_thresh; + uint32_t max_detection_per_class; + uint16_t anchor_row; + uint16_t anchor_col; + uint16_t stride_size; + uint16_t reserved_size; + uint32_t data[40]; +} __attribute__((aligned(4))) kp_app_yolo_post_proc_config_t; + +static kp_app_yolo_post_proc_config_t post_proc_params_v3 = { + .prob_thresh = 0.2, + .nms_thresh = 0.45, + .max_detection_per_class = YOLO_GOOD_BOX_MAX, + .anchor_row = 3, + .anchor_col = 6, + .stride_size = 3, + .reserved_size = 0, + .data = { + // anchors[3][6] + 81, 82, 135, 169, 344, 319, + 23, 27, 37, 58, 81, 82, + 0, 0, 0, 0, 0, 0, // -> not used in tiny yolo v3 post-proc + // strides[3] -> not used in tiny yolo v3 post-proc + 8, 16, 32, + }, +}; + +void demo_customize_inf_single_model(uint32_t job_id, int num_input_buf, void **inf_input_buf_list) +{ + if (1 != num_input_buf) { + kmdw_inference_app_send_status_code(job_id, KP_FW_WRONG_INPUT_BUFFER_COUNT_110); + return; + } + + // 'inf_input_buf' and 'inf_result_buf' are provided by kdp2 middleware + // the content of 'inf_input_buf' is transmitted from host SW = header + image + // 'inf_result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu) + + // now get an available free result buffer + // normally the begin part of result buffer should contain app-defined result header + // and the rest is for ncpu/npu inference output data + int result_buf_size; + void *inf_result_buf = kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size); + + demo_customize_inf_single_model_header_t *input_header = (demo_customize_inf_single_model_header_t *)inf_input_buf_list[0]; + demo_customize_inf_single_model_result_t *output_result = (demo_customize_inf_single_model_result_t *)inf_result_buf; + + // config image preprocessing and model settings + kmdw_inference_app_config_t inf_config; + memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false' + + // image buffer address should be just after the header + inf_config.num_image = 1; + inf_config.image_list[0].image_buf = (void *)((uint32_t)input_header + sizeof(demo_customize_inf_single_model_header_t)); + inf_config.image_list[0].image_width = input_header->width; + inf_config.image_list[0].image_height = input_header->height; + inf_config.image_list[0].image_channel = 3; // assume RGB565 + inf_config.image_list[0].image_format = KP_IMAGE_FORMAT_RGB565; // assume RGB565 + inf_config.image_list[0].image_norm = KP_NORMALIZE_KNERON; // this depends on model + inf_config.image_list[0].image_resize = KP_RESIZE_ENABLE; // enable resize + inf_config.image_list[0].image_padding = KP_PADDING_CORNER; // enable padding on corner + inf_config.model_id = TINY_YOLO_V3_224_224_3; // this depends on model + inf_config.ncpu_result_buf = (void *)&(output_result->yolo_result); // give result buffer for ncpu/npu, callback will carry it + inf_config.user_define_data = (void *)&post_proc_params_v3; // yolo post-process configurations for yolo v3 series + + // run preprocessing and inference, trigger ncpu/npu to do the work + // if enable_parallel=true (works only for single model), result callback is needed + // however if inference error then no callback will be invoked + int inf_status = kmdw_inference_app_execute(&inf_config); + + // header_stamp is a must to correctly transfer result data back to host SW + output_result->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + output_result->header_stamp.total_size = sizeof(demo_customize_inf_single_model_result_t); + output_result->header_stamp.job_id = job_id; + output_result->header_stamp.status_code = inf_status; + + // send output result buffer back to host SW + kmdw_fifoq_manager_result_enqueue((void *)output_result, result_buf_size, false); +} diff --git a/app/demo_customize_inf_single_model.h b/app/demo_customize_inf_single_model.h new file mode 100644 index 0000000..238a2f2 --- /dev/null +++ b/app/demo_customize_inf_single_model.h @@ -0,0 +1,32 @@ +#pragma once + +#define DEMO_KL520_CUSTOMIZE_INF_SINGLE_MODEL_JOB_ID 1000 +#define YOLO_BOX_MAX 100 /**< maximum number of bounding boxes for Yolo models */ + +/** + * @brief describe a yolo output result after post-processing + */ +typedef struct +{ + uint32_t class_count; /**< total class count */ + uint32_t box_count; /**< boxes of all classes */ + kp_bounding_box_t boxes[YOLO_BOX_MAX]; /**< box information */ +} __attribute__((aligned(4))) kp_custom_yolo_result_t; + +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t width; + uint32_t height; +} __attribute__((aligned(4))) demo_customize_inf_single_model_header_t; + +// result (header + data) for 'Kneron APP Yolo Inference' +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + kp_custom_yolo_result_t yolo_result; +} __attribute__((aligned(4))) demo_customize_inf_single_model_result_t; + +void demo_customize_inf_single_model(uint32_t job_id, int num_input_buf, void **inf_input_buf_list); diff --git a/app/kdp2_inf_app_yolo.c b/app/kdp2_inf_app_yolo.c new file mode 100644 index 0000000..f59b720 --- /dev/null +++ b/app/kdp2_inf_app_yolo.c @@ -0,0 +1,317 @@ +/* + * Kneron Application general functions + * + * Copyright (C) 2021 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include + +#include "kmdw_console.h" + +#include "kmdw_inference_app.h" +#include "kmdw_fifoq_manager.h" +#include "kdp2_inf_app_yolo.h" + +#include "model_type.h" + +static kp_app_yolo_post_proc_config_t post_proc_params_v5s = { + .prob_thresh = 0.15, + .nms_thresh = 0.5, + .max_detection_per_class = YOLO_GOOD_BOX_MAX, + .anchor_row = 3, + .anchor_col = 6, + .stride_size = 3, + .reserved_size = 0, + .data = { + // anchors[3][6] + 10, 13, 16, 30, 33, 23, + 30, 61, 62, 45, 59, 119, + 116, 90, 156, 198, 373, 326, + // strides[3] + 8, 16, 32, + }, +}; + +static kp_app_yolo_post_proc_config_t post_proc_params_v5s6_480_256_3 = { + .prob_thresh = 0.3, + .nms_thresh = 0.65, + .max_detection_per_class = YOLO_GOOD_BOX_MAX, + .anchor_row = 3, + .anchor_col = 6, + .stride_size = 3, + .reserved_size = 0, + .data = { + // anchors[3][6] + 7, 7, 13, 9, 9, 20, + 19, 15, 30, 24, 18, 45, + 48, 34, 90, 61, 156, 131, + // strides[3] + 8, 16, 32, + }, +}; + +static kp_app_yolo_post_proc_config_t post_proc_params_v5m = { + .prob_thresh = 0.3, + .nms_thresh = 0.45, + .max_detection_per_class = YOLO_GOOD_BOX_MAX, + .anchor_row = 3, + .anchor_col = 6, + .stride_size = 3, + .reserved_size = 0, + .data = { + // anchors[3][6] + 10, 13, 16, 30, 33, 23, + 30, 61, 62, 45, 59, 119, + 116, 90, 156, 198, 373, 326, + // strides[3] + 8, 16, 32, + }, +}; + +static kp_app_yolo_post_proc_config_t post_proc_params_v3 = { + .prob_thresh = 0.2, + .nms_thresh = 0.45, + .max_detection_per_class = YOLO_GOOD_BOX_MAX, + .anchor_row = 3, + .anchor_col = 6, + .stride_size = 3, + .reserved_size = 0, + .data = { + // anchors[3][6] + 81, 82, 135, 169, 344, 319, + 23, 27, 37, 58, 81, 82, + 4, 9, 13, 24, 24, 50, // -> not used in tiny yolo v3 post-proc + // strides[3] -> not used in tiny yolo v3 post-proc + 8, 16, 32, + }, +}; + +typedef struct +{ + int model_id; + int param_size; + void *post_proc_params; +} map_model_post_proc_t; + +#define MAX_MODEL_PAIRS 4 +static map_model_post_proc_t model_pp[MAX_MODEL_PAIRS] = {0}; // 4 pairs of modle-post_proc enough ? + +static map_model_post_proc_t get_model_post_proc_param(int model_id) +{ + map_model_post_proc_t mapping = {0}; + + // looking for model's post-proc params, if none apply some defaults + for (int i = 0; i < MAX_MODEL_PAIRS; i++) + { + if (model_pp[i].model_id == model_id) + { + // found matched model id with post-proc params + mapping = model_pp[i]; + break; + } + else if (model_pp[i].model_id == 0) + { + // register some default settings + model_pp[i].model_id = model_id; + switch (model_id) + { + case KNERON_YOLOV5S_COCO80_640_640_3: + case KNERON_YOLOV5S_PersonBottleChairPottedplant4_640_288_3: + model_pp[i].param_size = sizeof(post_proc_params_v5s); + model_pp[i].post_proc_params = (void *)&post_proc_params_v5s; + break; + case KNERON_YOLOV5S_PersonBicycleCarMotorcycleBusTruck6_480_256_3: + model_pp[i].param_size = sizeof(post_proc_params_v5s6_480_256_3); + model_pp[i].post_proc_params = (void *)&post_proc_params_v5s6_480_256_3; + break; + case KNERON_YOLOV5m_COCO80_640_640_3: + case KNERON_PERSONDETECTION_YOLOV5s_480_256_3: + case KNERON_PERSONDETECTION_YOLOV5sParklot_480_256_3: + model_pp[i].param_size = sizeof(post_proc_params_v5m); + model_pp[i].post_proc_params = (void *)&post_proc_params_v5m; + break; + case TINY_YOLO_V3_224_224_3: + case TINY_YOLO_V3_416_416_3: + case TINY_YOLO_V3_608_608_3: + model_pp[i].param_size = sizeof(post_proc_params_v3); + model_pp[i].post_proc_params = (void *)&post_proc_params_v3; + break; + default: + // cannot find matched post-proc config + break; + } + + mapping = model_pp[i]; + break; + } + } + + return mapping; +} + +void kdp2_app_yolo_config_post_process_parameters(uint32_t job_id, int num_input_buf, void **inf_input_buf_list) +{ + if (1 != num_input_buf) { + kmdw_inference_app_send_status_code(job_id, KP_FW_WRONG_INPUT_BUFFER_COUNT_110); + return; + } + + kdp2_ipc_app_yolo_post_proc_config_t *yolo_pp_config = (kdp2_ipc_app_yolo_post_proc_config_t *)inf_input_buf_list[0]; + + if (yolo_pp_config->set_or_get == 1) + { + // setting post-proc configs with specified model_id + for (int i = 0; i < MAX_MODEL_PAIRS; i++) + { + if (model_pp[i].model_id == yolo_pp_config->model_id || model_pp[i].model_id == 0) + { + model_pp[i].model_id = yolo_pp_config->model_id; // for model_pp[i].model_id == 0 + if (model_pp[i].post_proc_params == NULL || yolo_pp_config->param_size > model_pp[i].param_size) + { + model_pp[i].post_proc_params = malloc(yolo_pp_config->param_size); + if (model_pp[i].post_proc_params == NULL) + { + kmdw_printf("[app_yolo]: error ! no memory for malloc post-proc parameters\n"); + kmdw_inference_app_send_status_code(job_id, KP_FW_CONFIG_POST_PROC_ERROR_MALLOC_FAILED_105); + return; // failed return + } + + model_pp[i].param_size = yolo_pp_config->param_size; + } + + memcpy(model_pp[i].post_proc_params, (void *)yolo_pp_config->param_data, yolo_pp_config->param_size); + kmdw_inference_app_send_status_code(job_id, KP_SUCCESS); + return; // sucessful return + } + } + + kmdw_inference_app_send_status_code(job_id, KP_FW_CONFIG_POST_PROC_ERROR_NO_SPACE_106); + return; // failed return + } + else + { + // getting post-proc configs with specified model_id + // get a result buffer to save pp parameters + int result_buf_size; + kdp2_ipc_app_yolo_post_proc_config_t *return_pp_config = (kdp2_ipc_app_yolo_post_proc_config_t *)kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size); + + map_model_post_proc_t mapping = get_model_post_proc_param(yolo_pp_config->model_id); + + return_pp_config->header_stamp = yolo_pp_config->header_stamp; + return_pp_config->header_stamp.status_code = KP_SUCCESS; + return_pp_config->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_post_proc_config_t); + return_pp_config->set_or_get = 0; + return_pp_config->model_id = yolo_pp_config->model_id; + return_pp_config->param_size = mapping.param_size; + if (mapping.param_size > 0) + memcpy((void *)return_pp_config->param_data, mapping.post_proc_params, mapping.param_size); + + // send pp params back to host SW + kmdw_fifoq_manager_result_enqueue((void *)return_pp_config, result_buf_size, false); + } +} + +void kdp2_app_yolo_result_callback(int status, void *inf_result_buf, int inf_result_buf_size, void *ncpu_result_buf) +{ + // when ncpu has done post-process then it comes to here with inference result buffer filled + // 'inf_result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu) + // 'ncpu_result_buf' is post-processing result buffer done by ncpu + // normally 'inf_result_buf' contains 'ncpu_result_buf', and user should send 'inf_result_buf' to host SW + + kdp2_ipc_app_yolo_result_t *app_yolo_result = (kdp2_ipc_app_yolo_result_t *)inf_result_buf; + kp_app_yolo_result_t *yolo_data = (kp_app_yolo_result_t *)ncpu_result_buf; + + if (status != KP_SUCCESS) + { + app_yolo_result->header_stamp.status_code = status; + app_yolo_result->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_result_t) - sizeof(kp_app_yolo_result_t); + // send error status result back to host + kmdw_fifoq_manager_result_enqueue((void *)inf_result_buf, inf_result_buf_size, false); + return; + } + + if (yolo_data->box_count > YOLO_GOOD_BOX_MAX) + { + kmdw_printf("[app_yolo]: error ! too many bounding boxes = %d!!!\n", yolo_data->box_count); + yolo_data->box_count = YOLO_GOOD_BOX_MAX; + } + + app_yolo_result->header_stamp.status_code = KP_SUCCESS; + app_yolo_result->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_result_t) - sizeof(kp_app_yolo_result_t) + + sizeof(yolo_data->class_count) + sizeof(yolo_data->box_count) + yolo_data->box_count * sizeof(kp_bounding_box_t); + + // send output result buffer back to host SW + kmdw_fifoq_manager_result_enqueue((void *)inf_result_buf, inf_result_buf_size, false); +} + +void kdp2_app_yolo_inference(uint32_t job_id, int num_input_buf, void **inf_input_buf_list) +{ + if (1 != num_input_buf) { + kmdw_inference_app_send_status_code(job_id, KP_FW_WRONG_INPUT_BUFFER_COUNT_110); + return; + } + + // 'inf_input_buf' and 'inf_result_buf' are provided by kdp2 middleware + // the content of 'inf_input_buf' is transmitted from host SW = header + image + // 'inf_result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu) + + // now get an available free result buffer + // normally the begin part of result buffer should contain app-defined result header + // and the rest is for ncpu/npu inference output data + int result_buf_size; + void *inf_result_buf = kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size); + + kdp2_ipc_app_yolo_inf_header_t *app_yolo_header = (kdp2_ipc_app_yolo_inf_header_t *)inf_input_buf_list[0]; + kdp2_ipc_app_yolo_result_t *app_yolo_result = (kdp2_ipc_app_yolo_result_t *)inf_result_buf; + + // config image preprocessing and model settings + kmdw_inference_app_config_t inf_config; + memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false' + + // image buffer address should be just after the header + inf_config.num_image = 1; + inf_config.image_list[0].image_buf = (void *)((uint32_t)app_yolo_header + sizeof(kdp2_ipc_app_yolo_inf_header_t)); + inf_config.image_list[0].image_width = app_yolo_header->width; + inf_config.image_list[0].image_height = app_yolo_header->height; + inf_config.image_list[0].image_channel = app_yolo_header->channel; + inf_config.image_list[0].image_format = app_yolo_header->image_format; + inf_config.image_list[0].image_norm = app_yolo_header->model_normalize; + inf_config.image_list[0].image_resize = KP_RESIZE_ENABLE; // enable resize + inf_config.image_list[0].image_padding = KP_PADDING_CORNER; // enable padding on corner + inf_config.image_list[0].pad_value = NULL; + + inf_config.model_id = app_yolo_header->model_id; + inf_config.enable_parallel = true; // only works for single model and post-process in ncpu + inf_config.inf_result_buf = inf_result_buf; // for callback + inf_config.inf_result_buf_size = result_buf_size; // + inf_config.ncpu_result_buf = (void *)&(app_yolo_result->yolo_data); // give result buffer for ncpu/npu, callback will carry it + + inf_config.result_callback = kdp2_app_yolo_result_callback; + + map_model_post_proc_t mapping = get_model_post_proc_param(inf_config.model_id); + inf_config.user_define_data = mapping.post_proc_params; // FIXME: if NULL what happen ? + + // pre-set something for result output + // header_stamp is a must to correctly transfer result data back to host SW + app_yolo_result->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + app_yolo_result->header_stamp.total_size = 0; + app_yolo_result->header_stamp.job_id = job_id; + app_yolo_result->inf_number = app_yolo_header->inf_number; // sync the inference number + + // run preprocessing and inference, trigger ncpu/npu to do the work + // if enable_parallel=true (works only for single model), result callback is needed + // however if inference error then no callback will be invoked + int ret = kmdw_inference_app_execute(&inf_config); + if (ret != KP_SUCCESS) + { + // some sort of inference error + app_yolo_result->header_stamp.status_code = ret; + app_yolo_result->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_result_t) - sizeof(kp_app_yolo_result_t); + + // send error status result back to host + kmdw_fifoq_manager_result_enqueue((void *)inf_result_buf, result_buf_size, false); + } +} diff --git a/app/kdp2_inf_app_yolo.h b/app/kdp2_inf_app_yolo.h new file mode 100644 index 0000000..707b080 --- /dev/null +++ b/app/kdp2_inf_app_yolo.h @@ -0,0 +1,80 @@ +#pragma once + +#define KDP2_INF_ID_APP_YOLO 11 +#define KDP2_JOB_ID_APP_YOLO_CONFIG_POST_PROC 100 // handle set or get + +typedef struct +{ + uint32_t model_id; // specify model id + kp_normalize_mode_t model_norm; // specify model normalization +} __attribute__((aligned(4))) kp_app_yolo_config_t; + +/** + * @brief describe a yolo post-process configurations for yolo v5 series + */ +typedef struct +{ + float prob_thresh; + float nms_thresh; + uint32_t max_detection_per_class; + uint16_t anchor_row; + uint16_t anchor_col; + uint16_t stride_size; + uint16_t reserved_size; + uint32_t data[40]; +} __attribute__((aligned(4))) kp_app_yolo_post_proc_config_t; + +#define YOLO_GOOD_BOX_MAX 100 /**< maximum number of bounding boxes for Yolo models */ + +/** + * @brief describe a yolo output result after post-processing + */ +typedef struct +{ + uint32_t class_count; /**< total class count */ + uint32_t box_count; /**< boxes of all classes */ + kp_bounding_box_t boxes[YOLO_GOOD_BOX_MAX]; /**< box information */ +} __attribute__((aligned(4))) kp_app_yolo_result_t; + +/********** KDP2_INF_ID_APP_YOLO **********/ + +// post-proc config data struct shared for setting or getting +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t set_or_get; // get = 0, set = 1 + uint32_t model_id; + uint32_t param_size; + uint8_t param_data[200]; // contains kp_app_yolo_post_proc_config_*** body + +} __attribute__((aligned(4))) kdp2_ipc_app_yolo_post_proc_config_t; + +// input header for 'Kneron APP Yolo Inference' +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + + uint32_t inf_number; + uint32_t width; + uint32_t height; + uint32_t channel; + uint32_t model_id; + uint32_t image_format; // kp_image_format_t + uint32_t model_normalize; // kp_normalize_mode_t + +} __attribute__((aligned(4))) kdp2_ipc_app_yolo_inf_header_t; + +// result (header + data) for 'Kneron APP Yolo Inference' +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t inf_number; + kp_app_yolo_result_t yolo_data; + +} __attribute__((aligned(4))) kdp2_ipc_app_yolo_result_t; + +void kdp2_app_yolo_config_post_process_parameters(uint32_t job_id, int num_input_buf, void **inf_input_buf_list); +void kdp2_app_yolo_inference(uint32_t job_id, int num_input_buf, void **inf_input_buf_list); diff --git a/build/example_kdrv/adc/main_scpu/ex_adc_main.c b/build/example_kdrv/adc/main_scpu/ex_adc_main.c new file mode 100644 index 0000000..cfa8f6e --- /dev/null +++ b/build/example_kdrv/adc/main_scpu/ex_adc_main.c @@ -0,0 +1,54 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "kdrv_cmsis_core.h" +#include "kdrv_system.h" +#include "kdrv_uart.h" +#include "kdrv_adc.h" + +void myADCtest(void) +{ + kdrv_adc_initialize(); +} + + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + kdrv_system_init(); + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // for log + + SystemCoreClockUpdate(); // System Initialization + + myADCtest(); + + while(1); +} + + diff --git a/build/example_kdrv/adc/sn52096/project.h b/build/example_kdrv/adc/sn52096/project.h new file mode 100644 index 0000000..f86d881 --- /dev/null +++ b/build/example_kdrv/adc/sn52096/project.h @@ -0,0 +1,162 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/adc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/adc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/adc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/adc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/adc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/adc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/adc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/adc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/adc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/adc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/adc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/adc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/adc/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/adc/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/adc/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/adc/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/adc/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..701d807 --- /dev/null +++ b/build/example_kdrv/adc/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,370 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\vtor.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + d + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 1 + 0 + 0x62ec1762 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_adc_main.c + ex_adc_main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_adc.c + kdrv_adc.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/adc/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/adc/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..c43d5a8 --- /dev/null +++ b/build/example_kdrv/adc/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,624 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + project.h + 5 + ..\project.h + + + ex_adc_main.c + 1 + ..\..\main_scpu\ex_adc_main.c + + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_adc.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_adc.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/adc/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/adc/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/adc/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/basic/main_scpu/ex_basic_main.c b/build/example_kdrv/basic/main_scpu/ex_basic_main.c new file mode 100644 index 0000000..de0e3ed --- /dev/null +++ b/build/example_kdrv/basic/main_scpu/ex_basic_main.c @@ -0,0 +1,57 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" +#include "kdrv_system.h" +#include "kmdw_console.h" +#include "kdrv_cmsis_core.h" + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + + /* below is some middleware init settings */ + kdrv_uart_initialize(); // for log printing + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); + DSG("\nStart..."); + DSG("Kneron"); + DSG("examples"); + + if (osKernelGetState() == osKernelReady) { + osKernelStart(); + } + + while(1) { + } +} + + diff --git a/build/example_kdrv/basic/sn52096/project.h b/build/example_kdrv/basic/sn52096/project.h new file mode 100644 index 0000000..9411d09 --- /dev/null +++ b/build/example_kdrv/basic/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/basic/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/basic/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/basic/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/basic/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/basic/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/basic/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/basic/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/basic/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/basic/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/basic/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/basic/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/basic/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/basic/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/basic/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/basic/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/basic/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/basic/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..ca0087f --- /dev/null +++ b/build/example_kdrv/basic/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,370 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\vtor.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + d + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 1 + 0 + 0x62ec1762 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_basic_main.c + ex_basic_main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/basic/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/basic/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..7406cce --- /dev/null +++ b/build/example_kdrv/basic/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,623 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ex_basic_main.c + 1 + ..\..\main_scpu\ex_basic_main.c + + + project.h + 5 + ..\project.h + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/basic/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/basic/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/basic/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/camera/dvp/main_scpu/board_kl520_dvp_example.h b/build/example_kdrv/camera/dvp/main_scpu/board_kl520_dvp_example.h new file mode 100644 index 0000000..d09eb7f --- /dev/null +++ b/build/example_kdrv/camera/dvp/main_scpu/board_kl520_dvp_example.h @@ -0,0 +1,104 @@ +#ifndef __BOARD_KDP520_DVP_H__ +#define __BOARD_KDP520_DVP_H__ + +#define IMGSRC_IN_0 YES +#define IMGSRC_IN_1 NO + +#if (IMGSRC_IN_0 == YES) +#define IMGSRC_IN_0_PORT IMGSRC_IN_PORT_DPI +#define IMGSRC_0_SENSORID SENSOR_ID_EXTERN +#define IMGSRC_0_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 +#else +#define IMGSRC_IN_0_PORT IMGSRC_IN_PORT_NONE +#define IMGSRC_0_SENSORID SENSOR_ID_NONE +#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 +#endif + +#if (IMGSRC_IN_1 == YES) +#define IMGSRC_IN_1_PORT IMGSRC_IN_PORT_MIPI +#define IMGSRC_1_SENSORID SENSOR_ID_SC132GS +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 +#else +#define IMGSRC_IN_1_PORT IMGSRC_IN_PORT_NONE +#define IMGSRC_1_SENSORID SENSOR_ID_NONE +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 +#endif + +#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_MIPI || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_MIPI) +#define IMGSRC_IN_HAS_MIPI +#define MIPI_LANE_RGB 2 +#define MIPI_LANE_NIR 2 +#endif + +#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_DPI || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_DPI) +#define IMGSRC_IN_HAS_DPI +#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_DPI) +#define IMAGE_DVP_PORT_NO 0 +#else +#define IMAGE_DVP_PORT_NO 1 +#endif +#endif + +#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_UVC || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_UVC) +#define IMGSRC_IN_HAS_UVC +#endif + +#if (IMGSRC_IN_0 && IMGSRC_IN_1 && IMGSRC_IN_2) +#define CAM_ID_MAX 3 +#elif (IMGSRC_IN_0 && IMGSRC_IN_1) +#define CAM_ID_MAX 2 +#elif (IMGSRC_IN_0 || IMGSRC_IN_1) +#define CAM_ID_MAX 1 +#else +#define CAM_ID_MAX 0 +#endif + +#define IMGSRC_NUM CAM_ID_MAX +#define MIPI_CAM_RGB 0 +#define MIPI_CAM_NIR 1 + +#define LCDC_WIDTH 640 +#define LCDC_HEIGHT 480 + +#define RGB_IMG_SOURCE_W IMGSRC_0_WIDTH +#define RGB_IMG_SOURCE_H IMGSRC_0_HEIGHT +#define NIR_IMG_SOURCE_W IMGSRC_1_WIDTH +#define NIR_IMG_SOURCE_H IMGSRC_1_HEIGHT + +#define PANEL_TYPE PANEL_MZT_480X272 +#define DISPLAY_DEVICE DISPLAY_DEVICE_LCDC + +#define CAM_CLK_MS 2 +#define CAM_CLK_NS 242 +#define CAM_CLK_PS 2 +#define CSI0_TXESC 4 +#define CSI0_CSI 11 +#define CSI0_VC0 5 +#define CSI1_TXESC 4 +#define CSI1_CSI 7 +#define CSI1_VC0 1 +#endif // __BOARD_KDP520_DVP_H__ diff --git a/build/example_kdrv/camera/dvp/main_scpu/ex_camera_main.c b/build/example_kdrv/camera/dvp/main_scpu/ex_camera_main.c new file mode 100644 index 0000000..215684a --- /dev/null +++ b/build/example_kdrv/camera/dvp/main_scpu/ex_camera_main.c @@ -0,0 +1,161 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include "project.h" + +#include "kdrv_cmsis_core.h" +#include "kdrv_pinmux.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kdrv_uart.h" +#include "kdrv_i2c.h" + +#include "kmdw_memory.h" +#include "kmdw_console.h" +#include "kmdw_camera.h" + + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; + +typedef struct myCamera_ctx { + bool init; + enum camera_state state; + uint32_t width; + uint32_t height; + uint32_t pixelformat; +} myCamera_exp_ctx; + +myCamera_exp_ctx m_kdp_cam_exp_ctx[IMGSRC_NUM + 2] = { + {false, CAMERA_STATE_IDLE, 0, 0, 0}, + {false, CAMERA_STATE_IDLE, 0, 0, 0}, +}; +static uint32_t myCamera_example_open(uint8_t cam_idx) +{ + uint32_t ret; + + struct cam_capability cap; + struct cam_format fmt; + + char fmtstr[8]; + memset(&cap, 0, sizeof(cap)); + memset(&fmt, 0, sizeof(fmt)); + + if (0 != (ret = kmdw_camera_open(cam_idx))) + return ret; + + if (0 != (ret = kmdw_camera_get_device_info(cam_idx, &cap))) + return ret; + + fmt.width = m_kdp_cam_exp_ctx[cam_idx].width; + fmt.height = m_kdp_cam_exp_ctx[cam_idx].height; + fmt.pixelformat = m_kdp_cam_exp_ctx[cam_idx].pixelformat; + kmdw_printf("[%s] cam_idx:%d, width:%d, height:%d, pixelformat: %d\n", __func__, cam_idx, fmt.width, fmt.height, fmt.pixelformat); + if (0 != (ret = kmdw_camera_set_frame_format(cam_idx, (struct cam_format *)&fmt))) + return ret; + + if (0 != (ret = kmdw_camera_get_frame_format(cam_idx, &fmt))) + return ret; + + memset(fmtstr, 0, 8); + memcpy(fmtstr, &fmt.pixelformat, 4); + + // two buffers for MIPI camera + uint32_t buffer_addr[2] = {0}; + buffer_addr[0] = kmdw_ddr_reserve(1024*1024); + buffer_addr[1] = kmdw_ddr_reserve(1024*1024); + + if (0 != (ret = kmdw_camera_buffer_init(cam_idx, buffer_addr[0], buffer_addr[1]))) + return ret; + + m_kdp_cam_exp_ctx[cam_idx].state = CAMERA_STATE_INITED; + return 0; +} + +static uint32_t myCamera_example_setting(uint8_t cam_idx, unsigned int width, unsigned int height, unsigned int pixelformat) +{ + if(true == m_kdp_cam_exp_ctx[cam_idx].init) { + kmdw_printf("[%s] camera index %d is already initialized\n", __func__, cam_idx); + return 1; + } + m_kdp_cam_exp_ctx[cam_idx].init = true; + m_kdp_cam_exp_ctx[cam_idx].width = width; + m_kdp_cam_exp_ctx[cam_idx].height = height; + m_kdp_cam_exp_ctx[cam_idx].pixelformat = pixelformat; + return 0; +} + +static uint32_t myCamera_example_start(uint32_t cam_idx) +{ + uint32_t ret; + + if (0 != (ret = kmdw_camera_start(cam_idx, NULL))) { + return ret; + } + + m_kdp_cam_exp_ctx[cam_idx].state = CAMERA_STATE_RUNNING; + return 0; +} +void myCameratest() +{ +#if (IMGSRC_IN_0) + myCamera_example_setting(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT); + myCamera_example_open(0); + myCamera_example_start(0); +#endif + kmdw_printf("============================================================================================\n"); + kmdw_printf("Camera dvp example :\n"); + kmdw_printf("Use customer's evb board to transfer color bar Raw8 yuv image to Kneron's evb board.\n"); + kmdw_printf("Please use keil command window to input save image cmd to store image from rgb/nir sensor.\n"); + kmdw_printf(" ex: save rgb.hex 0x62f42800, 0x62f42800+(640*480*2)\n"); + kmdw_printf("Then use thirdparty's tool to verify image.\n"); + kmdw_printf("rgb sensor : size 640*480*2, with color bar image \n"); + kmdw_printf("============================================================================================\n"); +} + +int main(void) +{ + SystemCoreClockUpdate(); + osKernelInitialize(); + + kdrv_system_init(); + kdrv_system_init_ncpu(); + kdrv_ddr_system_init(DDR_INIT_ALL); + kdrv_pinmux_initialize(PIN_NUM, pinmux_array); + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kdrv_uart_initialize(); + + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); + kmdw_console_set_log_level_scpu(LOG_PROFILE); + + kmdw_camera_init(); + myCameratest(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/camera/dvp/sn520ev/project.h b/build/example_kdrv/camera/dvp/sn520ev/project.h new file mode 100644 index 0000000..e6e3f7f --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/project.h @@ -0,0 +1,157 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_5 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000085 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +#//define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..6838d9f --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/_Target-SCPU/RTE_Components.h b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/_Target-SCPU/RTE_Components.h new file mode 100644 index 0000000..e999392 --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/_Target-SCPU/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'Target-SCPU' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..bffe29f --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/mozart_96.sct b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/scpu.uvoptx b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..850e2de --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/scpu.uvoptx @@ -0,0 +1,534 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\vtor.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U63680012 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 126 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + D:\_git_home\workspace\mozart_sw_dev\firmware\build\example_kdrv\camera\dvp\sn520ev\scpu_keil\main\ex_camera_main.c + + + + + + + 0 + 1 + fbp + + + + + 1 + 0 + 0x62f42800 + 0 + + + + + 2 + 2 + 0xC3900000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_camera_main.c + ex_camera_main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 3 + 5 + 0 + 0 + 0 + ..\..\main_scpu\board_kl520_dvp_example.h + board_kl520_dvp_example.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\camera\kmdw_camera.c + kmdw_camera.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\camera\kmdw_camera_kl520.c + kmdw_camera_kl520.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\camera\kmdw_sensor.c + kmdw_sensor.c + 0 + 0 + + + 2 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + kdrv_pinmux.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c + kdrv_dpi2ahb.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c + kdrv_mipicsirx.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + kdrv_i2c.c + 0 + 0 + + + + + dev + 0 + 0 + 0 + 0 + + 4 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c + kdev_sensor_gc2145.c + 0 + 0 + + + 4 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c + kdev_sensor_sc132gs.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/scpu.uvprojx b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..1dbdba8 --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/scpu.uvprojx @@ -0,0 +1,683 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE,BOARD_DVP_EXAMPLE + + ..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\dev\include;..\..\..\..\..\..\mdw\include;..\..\..\..\..\..\include;..\;..\..\main_scpu + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ex_camera_main.c + 1 + ..\..\main_scpu\ex_camera_main.c + + + project.h + 5 + ..\project.h + + + board_kl520_dvp_example.h + 5 + ..\..\main_scpu\board_kl520_dvp_example.h + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_camera.c + 1 + ..\..\..\..\..\..\mdw\camera\kmdw_camera.c + + + kmdw_camera_kl520.c + 1 + ..\..\..\..\..\..\mdw\camera\kmdw_camera_kl520.c + + + kmdw_sensor.c + 1 + ..\..\..\..\..\..\mdw\camera\kmdw_sensor.c + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + + + driver + + + kdrv_pinmux.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_dpi2ahb.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c + + + kdrv_mipicsirx.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c + + + kdrv_i2c.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + + + + + dev + + + kdev_sensor_gc2145.c + 1 + ..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c + + + kdev_sensor_sc132gs.c + 1 + ..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/vtor.ini b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/camera/dvp/sn520ev/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/camera/mipi/main_scpu/ex_camera_main.c b/build/example_kdrv/camera/mipi/main_scpu/ex_camera_main.c new file mode 100644 index 0000000..5d13637 --- /dev/null +++ b/build/example_kdrv/camera/mipi/main_scpu/ex_camera_main.c @@ -0,0 +1,164 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include "kdrv_cmsis_core.h" +#include "project.h" + +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kdrv_uart.h" +#include "kdrv_i2c.h" + +#include "kmdw_memory.h" +#include "kmdw_console.h" +#include "kmdw_camera.h" + + +typedef struct myCamera_ctx { + bool init; + enum camera_state state; + uint32_t width; + uint32_t height; + uint32_t pixelformat; +} myCamera_exp_ctx; + +myCamera_exp_ctx m_kdp_cam_exp_ctx[IMGSRC_NUM + 2] = { + {false, CAMERA_STATE_IDLE, 0, 0, 0}, + {false, CAMERA_STATE_IDLE, 0, 0, 0}, +}; +static uint32_t myCamera_example_open(uint8_t cam_idx) +{ + uint32_t ret; + + struct cam_capability cap; + struct cam_format fmt; + + char fmtstr[8]; + memset(&cap, 0, sizeof(cap)); + memset(&fmt, 0, sizeof(fmt)); + + if (0 != (ret = kmdw_camera_open(cam_idx))) + return ret; + + if (0 != (ret = kmdw_camera_get_device_info(cam_idx, &cap))) + return ret; + + fmt.width = m_kdp_cam_exp_ctx[cam_idx].width; + fmt.height = m_kdp_cam_exp_ctx[cam_idx].height; + fmt.pixelformat = m_kdp_cam_exp_ctx[cam_idx].pixelformat; + kmdw_printf("[%s] cam_idx:%d, width:%d, height:%d, pixelformat: %d\n", __func__, cam_idx, fmt.width, fmt.height, fmt.pixelformat); + if (0 != (ret = kmdw_camera_set_frame_format(cam_idx, (struct cam_format *)&fmt))) + return ret; + + if (0 != (ret = kmdw_camera_get_frame_format(cam_idx, &fmt))) + return ret; + + memset(fmtstr, 0, 8); + memcpy(fmtstr, &fmt.pixelformat, 4); + + // two buffers for MIPI camera + uint32_t buffer_addr[2] = {0}; + buffer_addr[0] = kmdw_ddr_reserve(1024*1024); + buffer_addr[1] = kmdw_ddr_reserve(1024*1024); + + if (0 != (ret = kmdw_camera_buffer_init(cam_idx, buffer_addr[0], buffer_addr[1]))) + return ret; + + m_kdp_cam_exp_ctx[cam_idx].state = CAMERA_STATE_INITED; + return 0; +} + +static uint32_t myCamera_example_setting(uint8_t cam_idx, unsigned int width, unsigned int height, unsigned int pixelformat) +{ + if(true == m_kdp_cam_exp_ctx[cam_idx].init) { + kmdw_printf("[%s] camera index %d is already initialized\n", __func__, cam_idx); + return 1; + } + m_kdp_cam_exp_ctx[cam_idx].init = true; + m_kdp_cam_exp_ctx[cam_idx].width = width; + m_kdp_cam_exp_ctx[cam_idx].height = height; + m_kdp_cam_exp_ctx[cam_idx].pixelformat = pixelformat; + return 0; +} + +static uint32_t myCamera_example_start(uint32_t cam_idx) +{ + uint32_t ret; + + if (0 != (ret = kmdw_camera_start(cam_idx, NULL))) { + return ret; + } + + m_kdp_cam_exp_ctx[cam_idx].state = CAMERA_STATE_RUNNING; + return 0; +} +void myCameratest() +{ +#if (IMGSRC_IN_0) + myCamera_example_setting(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT); + myCamera_example_open(0); + myCamera_example_start(0); +#endif +#if (IMGSRC_IN_1) + myCamera_example_setting(1, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, IMGSRC_1_FORMAT); + myCamera_example_open(1); + myCamera_example_start(1); +#endif + kmdw_printf("============================================================================================\n"); + kmdw_printf("Camera example :\n"); + kmdw_printf("Please use keil command window to input save image cmd to store image from rgb/nir sensor.\n"); + kmdw_printf(" ex: save rgb.hex 0x62f42800, 0x62f42800+(640*480*2)\n"); + kmdw_printf(" save nir.hex 0x62979250, 0x62979250+(640*480)\n"); + kmdw_printf("Then use thirdparty's tool to verify image.\n"); + kmdw_printf("rgb sensor : size 640*480*2, with color bar image \n"); + kmdw_printf("nir sensor : size 480*640, with gray bar image\n"); + kmdw_printf("============================================================================================\n"); +} + +int main(void) +{ + SystemCoreClockUpdate(); + osKernelInitialize(); + + kdrv_system_init(); + kdrv_system_init_ncpu(); + kdrv_ddr_system_init(DDR_INIT_ALL); + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kdrv_uart_initialize(); + //kmdw_console_init(UART0_DEV); + kdrv_uart_console_init(COMM_PORT_ID_0, COMM_UART_BAUDRATE_115200, NULL); + kmdw_console_set_log_level_scpu(LOG_PROFILE); + kdrv_i2c_initialize(KDRV_I2C_CTRL_0, KDRV_I2C_SPEED_400K); + + kmdw_camera_init(); + myCameratest(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/camera/mipi/sn52096/project.h b/build/example_kdrv/camera/mipi/sn52096/project.h new file mode 100644 index 0000000..3019206 --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/project.h @@ -0,0 +1,184 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +CAM setting +=============================================================================*/ +//project.h +#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 + +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +#//define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..6838d9f --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h new file mode 100644 index 0000000..e999392 --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'Target-SCPU' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..bffe29f --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..f0ae2f5 --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,481 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\vtor.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + d + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U63680012 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 0 + 1 + fbp + + + + + 1 + 0 + 0x62f42800 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_camera_main.c + ex_camera_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\camera\kmdw_camera.c + kmdw_camera.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\camera\kmdw_camera_kl520.c + kmdw_camera_kl520.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\camera\kmdw_sensor.c + kmdw_sensor.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c + kdrv_dpi2ahb.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c + kdrv_mipicsirx.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + kdrv_i2c.c + 0 + 0 + + + + + dev + 0 + 0 + 0 + 0 + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c + kdev_sensor_sc132gs.c + 0 + 0 + + + 4 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c + kdev_sensor_gc2145.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..2b8e6a8 --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,668 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW,BOARD_96,MIPI_EXAMPLE + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\dev\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ex_camera_main.c + 1 + ..\..\main_scpu\ex_camera_main.c + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_camera.c + 1 + ..\..\..\..\..\..\mdw\camera\kmdw_camera.c + + + kmdw_camera_kl520.c + 1 + ..\..\..\..\..\..\mdw\camera\kmdw_camera_kl520.c + + + kmdw_sensor.c + 1 + ..\..\..\..\..\..\mdw\camera\kmdw_sensor.c + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_dpi2ahb.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c + + + kdrv_mipicsirx.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c + + + kdrv_i2c.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + + + + + dev + + + kdev_sensor_sc132gs.c + 1 + ..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c + + + kdev_sensor_gc2145.c + 1 + ..\..\..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/camera/mipi/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/camera/mipi/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/ddr/main_scpu/ex_ddr_main.c b/build/example_kdrv/ddr/main_scpu/ex_ddr_main.c new file mode 100644 index 0000000..454b5c4 --- /dev/null +++ b/build/example_kdrv/ddr/main_scpu/ex_ddr_main.c @@ -0,0 +1,994 @@ +#include +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kmdw_console.h" +#include "io.h" +#include "kdrv_uart.h" +#include "kdrv_pwm.h" +#include "kdrv_timer.h" +#include "kdrv_clock.h" +#include "kdrv_cmsis_core.h" + +extern void kdrv_system_init(void); + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define MEM_BASE (DDR_MEM_BASE) +#define MEM_SIZE (0x4000000)//(0x80000)// +#define MEM_BASE4NPU (MEM_BASE) +#define PATTERN_LENGTH (17*16) +#define PATTERN1(i) ((i^0x55aa)+((i^0xaa55)<<16)) + +#define MOD_SZ 20 +#define ITER_CNT 2// + +typedef enum { + MEMTEST86_ID_1 = 1, + MEMTEST86_ID_2, + MEMTEST86_ID_3, + MEMTEST86_ID_4, + MEMTEST86_ID_5, + MEMTEST86_ID_6, + MEMTEST86_ID_7, + MEMTEST86_ID_8, + MEMTEST86_ID_9, + MEMTEST86_ID_10, + MEMTEST86_ID_11, + FARADAY_MEMTEST, + MEMTEST_ID_MAX, + +}MEMTEST_ID; + +typedef int (*ddr_cmd_func)(void); +struct ddr_cmd_info +{ + char *desc; +}; +struct ddr_cmd_info ddr_cmd_array[MEMTEST_ID_MAX-1] = { + {"MEMTEST86_ID_1 : Address test, walking ones"}, + {"MEMTEST86_ID_2 : Address test, own address"}, + {"MEMTEST86_ID_3 : Moving inversions, all ones and zeros"}, + {"MEMTEST86_ID_4 : Moving inversions, 8 bit walking ones and zeros"}, + {"MEMTEST86_ID_5 : Moving inversions, 32 bit shifting pattern"}, + {"MEMTEST86_ID_6 : Random Data"}, + {"MEMTEST86_ID_7 : Random Data Sequence"}, + {"MEMTEST86_ID_8 : Bit fade test"}, + {"MEMTEST86_ID_9 : Modulo 20 check, Random pattern"}, + {"MEMTEST86_ID_10 : Modulo 20 check, all ones and zeros"}, + {"MEMTEST86_ID_11 : Modulo 20 check, 8 bit pattern"}, + {"FARADAY_MEMTEST : Faraday's ddr memory test"}, +}; + +uint32_t pftimerid; + +uint32_t static ddr_sram_rw_verify(void) +{ + int i, j, k, len, test_loop; + k=0; + int test1_err_cnt = 0; + int test2_err_cnt = 0; + int test3_err_cnt = 0; + test_loop = 50; + DSG("Test mem 1\n"); + for (k = 0; k < test_loop; k++) + { + for (i = 0; i < MEM_SIZE / 4; i++) + { + outw(MEM_BASE+4 * i, PATTERN1(i)); + } + len = 0; + for (i=0; i < MEM_SIZE / 4; i++) + { + j = inw(MEM_BASE+4*i); + if (j != PATTERN1(i)) + { + test1_err_cnt++; + DSG("%d> Test mem 1 failed ev=%08x, av=%08x\n", i, PATTERN1(i), j); + len++; + if(len > 10) + { + DSG("%d> exit\n"); + return (1); + } + } + } + DSG("Test loop %d/%d\n", k, test_loop); + } + + DSG("Test mem 2\n"); + for (k = 0; k < test_loop; k++) + { + for (i = 0; i < MEM_SIZE / 4; i++) + { + outw(MEM_BASE + 4 * i, (i << 16) + ((i^0xffff))); + } + len = 0; + for(i = 0; i < MEM_SIZE / 4; i++) + { + j = inw(MEM_BASE + 4 * i); + if ( j != ((i << 16) + (i^0xffff))) + { + test2_err_cnt++; + DSG("Test mem 2 failed ev=%08x, av=%08x\n", (i<<16)+((i^0xffff)), j); + len++; + if(len>10) + { + DSG("%d> exit\n"); + return (1); + } + } + } + DSG("Test loop %d/%d\n", k, test_loop); + } + + DSG("Test mem 3\n"); + for(k = 0; k < test_loop; k++) + { + for(i = 0; i < MEM_SIZE / 4; i++) + { + outw(MEM_BASE + 4 * i, 0); + } + len=0; + for(i = 0; i < MEM_SIZE / 4; i++) + { + j = inw(MEM_BASE + 4 * i); + if ( j != (0)) + { + test3_err_cnt++; + DSG("Test mem 3 failed ev=%08x, av=%08x\n", 0, j); + len++; + if (len > 10) + { + DSG("%d> exit\n"); + return (1); + } + } + } + DSG("Test loop %d/%d\n", k, test_loop); + } + DSG("End of test\n"); + DSG("Test result mem1_test %d/%d, mem2_test=%d/%d, mem3_test=%d/%d\n", + test_loop - test1_err_cnt, test_loop, + test_loop - test2_err_cnt, test_loop, + test_loop - test3_err_cnt, test_loop); + return 0; +} + +uint32_t roundup(uint32_t value, uint32_t mask) +{ + return (value + mask) & ~mask; +} + +/* + * Memory address test, walking ones + */ +uint32_t ddr_addr_tst1() +{ + int32_t i, j, k; + volatile uint32_t *p, *pt, *end, *start; + uint32_t mask, bank, p1; + + /* Test the global address bits */ + for (p1=0, j=0; j<2; j++) + { + /* Set pattern in our lowest multiple of 0x20000 */ + start = (uint32_t *)MEM_BASE; + end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4); + p = (uint32_t *)roundup((uint32_t)start, 0x1ffff); + + *p = p1; + p1 = ~p1; + for (i=0; i<100; i++) + { + mask = 4; + do{ + pt = (uint32_t *)((uint32_t)p | mask); + if (pt == p) + { + mask = mask << 1; + continue; + } + if (pt >= end) + { + break; + } + *pt = p1; + if ((*p) != ~p1) + { + return 1; + } + mask = mask << 1; + } while(mask); + } + } + + /* Now check the address bits in each bank */ + /* If we have more than 8mb of memory then the bank size must be */ + /* bigger than 256k. If so use 1mb for the bank size. */ + if ((uint32_t)end > (0x800000 >> 12)) + { + bank = 0x100000; + } + else + { + bank = 0x40000; + } + for (p1=0, k=0; k<2; k++) + { + p = start; + /* Force start address to be a multiple of 256k */ + p = (uint32_t *)roundup((uint32_t)p, bank - 1); + + /* Redundant checks for overflow */ + while (p < end && p >= start && p != 0) + { + *p = p1; + p1 = ~p1; + for (i=0; i<50; i++) + { + mask = 4; + do{ + pt = (uint32_t *)((uint32_t)p | mask); + if (pt == p) + { + mask = mask << 1; + continue; + } + if (pt >= end) + { + break; + } + *pt = p1; + if ((*p) != ~p1) + { + return 1; + } + mask = mask << 1; + } while(mask); + } + if (p + bank > p) + { + p += bank; + } + else + { + p = end; + } + p1 = ~p1; + } + p1 = ~p1; + } + return 0; +} + +/* + * Memory address test, own address + */ +uint32_t ddr_addr_tst2() +{ + int32_t done; + uint32_t *p, *pe, *end, *start; + + /* Write each address with it's own address */ + start = (uint32_t *)MEM_BASE; + end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4); + pe = (uint32_t *)end; + p = start; + done = 0; + do{ + for (; p <= pe; p++) + { + *p = (uint32_t)p; + } + if (p >= pe) + { + done++; + } + } while (!done); + + /* Each address should have its own address */ + pe = end; + p = start; + done = 0; + do{ + for (; p <= pe; p++) + { + if((*p) != (uint32_t)p) + { + return 1; + } + } + if (p >= pe) + { + done++; + } + } while (!done); + return 0; +} + +/* + * Test all of memory using a "half moving inversions" algorithm using random + * numbers and their complment as the data pattern. Since we are not able to + * produce random numbers in reverse order testing is only done in the forward + * direction. + */ +uint32_t ddr_movinvr() +{ + int32_t i, done; + uint32_t *p; + uint32_t *pe; + uint32_t *start,*end; + uint32_t num; + uint32_t random_number; + uint32_t perftime, time; + /* Initialize memory with initial sequence of random numbers. */ + start = (uint32_t *)MEM_BASE; + end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4); + + srand(kdrv_timer_perf_get_instant(&pftimerid, &perftime, &time)); + random_number = rand(); + + pe = end; + p = start; + done = 0; + do { + for (; p <= pe; p++) + { + *p = random_number; + } + if (p >= end) + { + done++; + } + } while (!done); + + /* Do moving inversions test. Check for initial pattern and then + * write the complement for each memory location. + */ + for (i=0; i<2; i++) { + pe = end; + p = start; + done = 0; + do { + for (; p <= pe; p++) + { + num = random_number; + if (i) + { + num = ~num; + } + if ((*p) != num) + { + return 1; + } + *p = ~num; + } + if (p >= end) + { + done++; + } + } while (!done); + } + return 0; +} + +/* + * Test all of memory using a "moving inversions" algorithm using the + * pattern in p1 and it's complement in p2. + */ +uint32_t ddr_movinv1 (uint32_t iter, uint32_t p1, uint32_t p2) +{ + int32_t i, done; + uint32_t *p, *pe, *start, *end; + + start = (uint32_t *)MEM_BASE; + end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4); + + /* Initialize memory with the initial pattern. */ + pe = end; + p = start; + done = 0; + do{ + for (; p <= pe; p++) + { + *p = p1; + } + if (p >= pe) + { + done++; + } + } while (!done); + + /* Do moving inversions test. Check for initial pattern and then + * write the complement for each memory location. Test from bottom + * up and then from the top down. */ + for (i=0; i= end) + { + done++; + } + } while (!done); + + pe = start; + p = end; + done = 0; + do + { + do + { + if ((*p) != p2) + { + return 1; + } + *p = p1; + } while (--p >= pe); + + if (p <= end) + { + done++; + } + } while (!done); + } + return 0; +} + +uint32_t ddr_movinv32(int iter, uint32_t p1, uint32_t lb, uint32_t hb, int sval, int off) +{ + int k=0, n=0, done; + uint32_t *p, *pe, *start, *end, pat = 0, p3; + + p3 = sval << 31; + + /* Initialize memory with the initial pattern. */ + start = (uint32_t *)MEM_BASE; + end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4); + pe = end; + p = start; + done = 0; + k = off; + pat = p1; + do{ + while (p <= pe) + { + *p = pat; + if (++k >= 32) + { + pat = lb; + k = 0; + } + else + { + pat = pat << 1; + pat |= sval; + } + p++; + } + if (p > end) + { + done++; + } + } while (!done); + + /* Do moving inversions test. Check for initial pattern and then + * write the complement for each memory location. Test from bottom + * up and then from the top down. */ + p = start; + pe = end; + done = 0; + k = off; + pat = p1; + do + { + while (1) + { + if (*p != pat) + { + return 1; + } + *p = ~pat; + + if (++k >= 32) + { + pat = lb; + k = 0; + } + else + { + pat = pat << 1; + pat |= sval; + } + if (p >= pe) + break; + p++; + } + if (p >= end) + { + done++; + } + } while (!done); + + if (--k < 0) + { + k = 31; + } + for (pat = lb, n = 0; n < k; n++) + { + pat = pat << 1; + pat |= sval; + } + + k++; + p = end; + pe = start; + done = 0; + do{ + while(1) + { + if ((*p) != ~pat) + { + return 1; + } + *p = pat; + if (--k <= 0) + { + pat = hb; + k = 32; + } + else + { + pat = pat >> 1; + pat |= p3; + } + if (p <= pe) + break; + p--; + }; + if (p <= end) + { + done++; + } + } while (!done); + return 0; +} + +/* + * Test all of memory using modulo X access pattern. + */ +uint32_t ddr_modtst(uint32_t offset, uint32_t iter, uint32_t p1, uint32_t p2) +{ + uint32_t k, l, done; + uint32_t *p; + uint32_t *pe; + uint32_t *start, *end; + + /* Write every nth location with pattern */ + start = (uint32_t *)MEM_BASE; + end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4); + end -= MOD_SZ; /* adjust the ending address */ + pe = end; + p = start+offset; + done = 0; + do{ + /* Check for overflow */ + for (; p <= pe; p += MOD_SZ) + { + *p = p1; + } + if(p>=pe) + { + done++; + } + } while (!done); + + /* Write the rest of memory "iter" times with the pattern complement */ + for (l=0; l MOD_SZ-1) + { + k = 0; + } + } + + if (p >= pe) + { + done++; + } + } while (!done); + } + + /* Now check every nth location */ + pe = end; + p = start+offset; + done = 0; + end -= MOD_SZ;/* adjust the ending address */ + do{ + for (; p <= pe; p += MOD_SZ) + { + if ((*p) != p1) + { + return 1; + } + } + if (p >= pe) + { + done++; + } + } while (!done); + return 0; +} + + +/* + * Test memory for bit fade, fill memory with pattern. + */ +void ddr_bit_fade_fill(uint32_t p1) +{ + int done; + uint32_t *p, *pe; + uint32_t *start,*end; + + /* Initialize memory with the initial pattern. */ + { + start = (uint32_t *)MEM_BASE; + end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4); + + pe = end; + p = start; + done = 0; + do + { + for (; p < pe;) + { + *p = p1; + p++; + } + if (pe >= end) + { + pe = end; + done++; + } + } while (!done); + } +} + +uint32_t ddr_bit_fade_chk(uint32_t p1) +{ + uint32_t done; + uint32_t *p, *pe; + uint32_t *start,*end; + + /* Make sure that nothing changed while sleeping */ + start = (uint32_t *)MEM_BASE; + end = (uint32_t *)(MEM_BASE + MEM_SIZE - 4); + pe = end; + p = start; + done = 0; + do{ + for (; p < pe;) + { + if ((*p) != p1) + { + return 1; + } + p++; + } + if (pe >= end) + { + pe = end; + done++; + } + } while (!done); + return 0; +} + +/* Sleep for ms */ +void ddr_sleep(uint32_t ms) +{ + kdrv_clock_disable(CLK_NPU); + kdrv_clock_disable(CLK_NCPU); + kdrv_ddr_self_refresh_enter(); + kdrv_pwmtimer_delay_ms(ms); + kdrv_ddr_self_refresh_exit(); + kdrv_clock_enable(CLK_NCPU); + kdrv_clock_enable(CLK_NPU); +} + +uint32_t ddr_memtest() +{ + uint32_t ret; + uint32_t i, iter, p1, p2, p0; + uint32_t j; + uint32_t rc = 1; + int32_t cmd_size = ARRAY_SIZE(ddr_cmd_array); + char buf[256]; + iter = ITER_CNT; + uint32_t random_number; + uint32_t perftime,time; + kdrv_timer_perf_open(&pftimerid); + kdrv_timer_perf_reset(&pftimerid); + kdrv_timer_perf_set(&pftimerid); + while(1) + { + int32_t id = 0; + srand(kdrv_timer_perf_get_instant(&pftimerid, &perftime, &time)); + random_number = rand(); + DSG_NOLF("\n === DDR Example Test Kit (%u) === \n", cmd_size); + for (i = 0; i < cmd_size; ++i) + { + sprintf(buf, "(%2d) %s", i + 1, ddr_cmd_array[i].desc); + DSG_NOLF("%s\n", buf); + } + DSG_NOLF("Set_memtest_item >> "); + rc = kmdw_console_echo_gets(buf, sizeof(buf)); + if (!rc) + { + continue; + } + id = atoi(strtok(buf, " \r\n\t")); + DSG_NOLF("========================================================================== \n"); + sprintf(buf, "Do memtest case %s", ddr_cmd_array[id-1].desc); + DSG_NOLF("%s\n", buf); + DSG_NOLF("========================================================================== \n"); + switch(id) + { + case MEMTEST86_ID_1: + /* Address test, walking ones (test #0) */ + ret = ddr_addr_tst1(); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + break; + case MEMTEST86_ID_2: + /* Address test, own address (test #1, 2) */ + ret = ddr_addr_tst2(); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + break; + case MEMTEST86_ID_3: + /* Moving inversions, all ones and zeros (tests #3, 4) */ + p1 = 0; + p2 = ~p1; + ret = ddr_movinv1(iter, p1, p2); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + ret = ddr_movinv1(iter, p2, p1); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + break; + case MEMTEST86_ID_4: + /* Moving inversions, 8 bit walking ones and zeros (test #5) */ + p0 = 0x80; + for (i=0; i<8; i++, p0=p0>>1) + { + p1 = p0 | (p0<<8) | (p0<<16) | (p0<<24); + p2 = ~p1; + ret = ddr_movinv1(iter,p1,p2); + + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + + /* Switch patterns */ + ret = ddr_movinv1(iter,p2,p1); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + } + break; + case MEMTEST86_ID_5: + /* Moving inversions, 32 bit shifting pattern (test #8) */ + for (i=0, p1=1; p1; p1=p1<<1, i++) + { + ret = ddr_movinv32(iter,p1, 1, 0x80000000, 0, i); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + ret = ddr_movinv32(iter,~p1, 0xfffffffe,0x7fffffff, 1, i); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + } + break; + case MEMTEST86_ID_6: + /* Random Data (test #6) */ + for (i=0; i < iter; i++) + { + srand(kdrv_timer_perf_get_instant(&pftimerid, &perftime, &time)); + random_number = rand(); + p1 = random_number; + p2 = ~p1; + ddr_movinv1(2,p1,p2); + } + break; + case MEMTEST86_ID_7: + /* Random Data Sequence (test #9) */ + for (i=0; i < iter; i++) { + ret = ddr_movinvr(); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + } + break; + case MEMTEST86_ID_8: + /* Bit fade test, fill (test #11) */ + p1 = 0; + ddr_bit_fade_fill(p1); + ddr_sleep(1000); + ret = ddr_bit_fade_chk(p1); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + p1 = ~p1; + ddr_bit_fade_fill(p1); + ddr_sleep(1000); + ret = ddr_bit_fade_chk(p1); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + break; + case MEMTEST86_ID_9: + /* Modulo 20 check, Random pattern (test #10) */ + for (j=0; j \n", id); + return ret; + } + + /* Switch patterns */ + ret = ddr_modtst(i, 2, p2, p1); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + } + } + break; + case MEMTEST86_ID_10: + /* Modulo 20 check, all ones and zeros*/ + p1 = 0; + for (i=0; i \n", id); + return ret; + } + + /* Switch patterns */ + ret = ddr_modtst(i, 2, p2, p1); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + } + break; + case MEMTEST86_ID_11: + /* Modulo 20 check, 8 bit pattern*/ + p0 = 0x80; + for (j=0; j<8; j++, p0=p0>>1) { + p1 = p0 | (p0<<8) | (p0<<16) | (p0<<24); + for (i=0; i \n", id); + return ret; + } + + /* Switch patterns */ + ret = ddr_modtst(i, 2, p2, p1); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + } + } + break; + case FARADAY_MEMTEST: + ret = ddr_sram_rw_verify(); + if (ret != 0) + { + DSG_NOLF("Fail test case <%d> \n", id); + return ret; + } + break; + default: + break; + } + if(id > 0 && id < MEMTEST_ID_MAX) + DSG_NOLF("Pass test case <%d> \n", id); + } +} +/** + * @brief main, main dispatch function + */ +int main(void) +{ + uint32_t ret; + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kdrv_uart_initialize(); // for log printing + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing + + ret = ddr_memtest(); + if(ret) + { + DSG_NOLF("============================== \n"); + DSG_NOLF("========= DDR TEST FAIL =========== \n"); + DSG_NOLF("============================== \n"); + } + + while(1) { + } +} diff --git a/build/example_kdrv/ddr/sn52096/project.h b/build/example_kdrv/ddr/sn52096/project.h new file mode 100644 index 0000000..9713321 --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/ddr/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/ddr/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/ddr/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/ddr/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..6f51a96 --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,337 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_ddr_main.c + ex_ddr_main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_timer.c + kdrv_timer.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/ddr/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/ddr/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..cff439c --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,633 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ex_ddr_main.c + 1 + ..\..\main_scpu\ex_ddr_main.c + + + project.h + 5 + ..\project.h + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + kdrv_timer.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_timer.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/ddr/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/ddr/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/ddr/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/gdma/main_scpu/ex_gdma_main.c b/build/example_kdrv/gdma/main_scpu/ex_gdma_main.c new file mode 100644 index 0000000..397f7d0 --- /dev/null +++ b/build/example_kdrv/gdma/main_scpu/ex_gdma_main.c @@ -0,0 +1,397 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kdrv_uart.h" +#include "kmdw_memory.h" //for ddr_malloc +#include "kmdw_console.h" +#include "kdrv_cmsis_core.h" + +#include +#include "kdrv_gdma.h" +#include "kdrv_pwm.h" + +typedef enum +{ + TEST_GDMA_KDP_MEMCPY, + TEST_GDMA_KDP_MEMCPY_ASYNC, + TEST_GDMA_KDP_TRANSFER, + TEST_GDMA_KDP_TRANSFER_ASYNC, + TEST_SPECIFIED_DMA_CHANNEL, +} GDMA_TEST_ITEM; + +volatile static int dma_waiting = 1; + +void dma_cb(kdrv_status_t status, void *arg) +{ + if (status != KDRV_STATUS_OK) + kmdw_printf("kdrv_gdma_memcpy_async() failed\n"); + + dma_waiting = 0; +} + +static int one_dma_memcpy_test(uint32_t dstAddr, uint32_t srcAddr, uint32_t size, + uint32_t loop, uint32_t test_item, int ch) +{ + + kdrv_pwmtimer_initialize(PWMTIMER1, PWMTMR_1MSEC_PERIOD); + + memset((void *)srcAddr, 0, size); + memset((void *)dstAddr, 0, size); + + for (int i = 0; i < size; i++) + { + *(uint8_t *)(srcAddr + i) = (rand() % 0XFF); + } + + uint32_t tick_start, tick_end; + + if (test_item == TEST_GDMA_KDP_MEMCPY) + { + tick_start = kdrv_current_t1_tick(); + + for (uint32_t i = 0; i < loop; i++) + { + kdrv_status_t dma_sts = kdrv_gdma_memcpy(dstAddr, srcAddr, size); + //kdrv_status_t dma_sts = kdrv_gdma_transfer(3, dstAddr, srcAddr, size); + if (dma_sts != KDRV_STATUS_OK) + kmdw_printf("kdrv_gdma_memcpy() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop); + //memcpy((void *)dstAddr, (void *)srcAddr, size); + } + + tick_end = kdrv_current_t1_tick(); + } + else if (test_item == TEST_GDMA_KDP_MEMCPY_ASYNC) + { + tick_start = kdrv_current_t1_tick(); + + for (uint32_t i = 0; i < loop; i++) + { + dma_waiting = 1; + kdrv_status_t dma_sts = kdrv_gdma_memcpy_async(dstAddr, srcAddr, size, dma_cb, NULL); + if (dma_sts != KDRV_STATUS_OK) + kmdw_printf("kdrv_gdma_memcpy_async() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop); + while (dma_waiting) + ; + } + + tick_end = kdrv_current_t1_tick(); + } + else if (test_item == TEST_GDMA_KDP_TRANSFER) + { + kdrv_gdma_handle_t dma_handle; + kdrv_status_t sts = kdrv_gdma_acquire_handle(&dma_handle); + + if(sts != KDRV_STATUS_OK) + { + kmdw_printf("acquire GDMA handle failed\n"); + return -1; + } + + gdma_setting_t dma_setting; + + dma_setting.dst_width = GDMA_TXFER_WIDTH_32_BITS; + dma_setting.src_width = GDMA_TXFER_WIDTH_32_BITS; + dma_setting.burst_size = GDMA_BURST_SIZE_16; + dma_setting.dst_addr_ctrl = GDMA_INCREMENT_ADDRESS; + dma_setting.src_addr_ctrl = GDMA_INCREMENT_ADDRESS; + dma_setting.dma_mode = GDMA_NORMAL_MODE; + dma_setting.dma_dst_req = 0; + dma_setting.dma_src_req = 0; + + kdrv_gdma_configure_setting(dma_handle, &dma_setting); + + tick_start = kdrv_current_t1_tick(); + + for (uint32_t i = 0; i < loop; i++) + { + kdrv_status_t dma_sts = kdrv_gdma_transfer(dma_handle, dstAddr, srcAddr, size); + if (dma_sts != KDRV_STATUS_OK) + kmdw_printf("kdrv_gdma_transfer() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop); + } + + tick_end = kdrv_current_t1_tick(); + + kdrv_gdma_release_handle(dma_handle); + } + else if (test_item == TEST_GDMA_KDP_TRANSFER_ASYNC) + { + kdrv_gdma_handle_t dma_handle; + kdrv_status_t sts = kdrv_gdma_acquire_handle(&dma_handle); + + if(sts != KDRV_STATUS_OK) + { + kmdw_printf("acquire GDMA handle failed\n"); + return -1; + } + + gdma_setting_t dma_setting; + + dma_setting.dst_width = GDMA_TXFER_WIDTH_32_BITS; + dma_setting.src_width = GDMA_TXFER_WIDTH_32_BITS; + dma_setting.burst_size = GDMA_BURST_SIZE_16; + dma_setting.dst_addr_ctrl = GDMA_INCREMENT_ADDRESS; + dma_setting.src_addr_ctrl = GDMA_INCREMENT_ADDRESS; + dma_setting.dma_mode = GDMA_NORMAL_MODE; + dma_setting.dma_dst_req = 0; + dma_setting.dma_src_req = 0; + + kdrv_gdma_configure_setting(dma_handle, &dma_setting); + + tick_start = kdrv_current_t1_tick(); + + for (uint32_t i = 0; i < loop; i++) + { + dma_waiting = 1; + kdrv_status_t dma_sts = kdrv_gdma_transfer_async(dma_handle, dstAddr, srcAddr, size, dma_cb, NULL); + if (dma_sts != KDRV_STATUS_OK) + kmdw_printf("kdrv_gdma_memcpy_async() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop); + while (dma_waiting) + ; + } + + tick_end = kdrv_current_t1_tick(); + + kdrv_gdma_release_handle(dma_handle); + } + else if (test_item == TEST_SPECIFIED_DMA_CHANNEL) + { + kdrv_gdma_handle_t dma_handle = ch; + gdma_setting_t dma_setting; + + dma_setting.dst_width = GDMA_TXFER_WIDTH_32_BITS; + dma_setting.src_width = GDMA_TXFER_WIDTH_32_BITS; + dma_setting.burst_size = GDMA_BURST_SIZE_16; + dma_setting.dst_addr_ctrl = GDMA_INCREMENT_ADDRESS; + dma_setting.src_addr_ctrl = GDMA_INCREMENT_ADDRESS; + dma_setting.dma_mode = GDMA_NORMAL_MODE; + dma_setting.dma_dst_req = 0; + dma_setting.dma_src_req = 0; + + kdrv_gdma_configure_setting(dma_handle, &dma_setting); + + tick_start = kdrv_current_t1_tick(); + + for (uint32_t i = 0; i < loop; i++) + { + kdrv_status_t dma_sts = kdrv_gdma_transfer(dma_handle, dstAddr, srcAddr, size); + if (dma_sts != KDRV_STATUS_OK) + kmdw_printf("kdrv_gdma_transfer() failed at dst 0x%x src 0x%s loop %d\n", dstAddr, srcAddr, loop); + } + + tick_end = kdrv_current_t1_tick(); + } + + int cmp_sts = memcmp((const void *)srcAddr, (const void *)dstAddr, size); + + float speed = (float)((size * loop) >> 10) / (tick_end - tick_start); + + kdrv_pwmtimer_close(PWMTIMER1); + + kmdw_printf("[memcpy] tid 0x%x copy 0x%x to 0x%x %d bytes x %d, spent %u ms speed: %1.f MB/s ... %s\n", + osThreadGetId(), srcAddr, dstAddr, size, loop, (tick_end - tick_start), speed, (cmp_sts == 0) ? "PASSED" : "FAILED"); + + return (cmp_sts == 0); +} + +static void test_dma_functions() +{ + + kmdw_printf("\n================= [%s context] =================\n\n", osThreadGetId() == 0 ? "Non-OS" : "OS"); + + const uint32_t size_begin = 512; + const uint32_t count_begin = 32768 / 2; + + { + kmdw_printf("[ kdrv_gdma_memcpy() tests ]\n"); + + uint32_t dstAddr = 0x62000000; + uint32_t srcAddr = 0x62800000; + + int pass_count = 0; + + kmdw_printf("\nAaddress and transfer size are not divisiable by 4:\n"); + + for (int i = 0; i < 4; i++) + pass_count += one_dma_memcpy_test(dstAddr + i, srcAddr + i, (8 * 1024) + i, 1000, TEST_GDMA_KDP_MEMCPY, 0); + + kmdw_printf("\nDifferent transfer size:\n"); + + uint32_t size = size_begin; + uint32_t count = count_begin; + for (int i = 0; i < 15; i++) + { + pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_GDMA_KDP_MEMCPY, 0); + size *= 2; + count /= 2; + } + + kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 19 - pass_count); + } + + { + uint32_t dstAddr = 0x62000000; + uint32_t srcAddr = 0x62800000; + + int pass_count = 0; + + kmdw_printf("\n"); + kmdw_printf("[ kdrv_gdma_memcpy_async() tests ]\n"); + + kmdw_printf("\nDifferent transfer size:\n"); + + uint32_t size = size_begin; + uint32_t count = count_begin; + + for (int i = 0; i < 15; i++) + { + pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_GDMA_KDP_MEMCPY_ASYNC, 0); + size *= 2; + count /= 2; + } + + kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 15 - pass_count); + } + + { + uint32_t dstAddr = 0x62000000; + uint32_t srcAddr = 0x62800000; + + int pass_count = 0; + + kmdw_printf("\n"); + kmdw_printf("[ kdrv_gdma_transfer() tests ]\n"); + + kmdw_printf("\nDifferent transfer size:\n"); + + uint32_t size = size_begin; + uint32_t count = count_begin; + + for (int i = 0; i < 15; i++) + { + pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_GDMA_KDP_TRANSFER, 0); + size *= 2; + count /= 2; + } + + kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 15 - pass_count); + } + + { + uint32_t dstAddr = 0x62000000; + uint32_t srcAddr = 0x62800000; + + int pass_count = 0; + + kmdw_printf("\n"); + kmdw_printf("[ kdrv_gdma_transfer_async() tests ]\n"); + + kmdw_printf("\nDifferent transfer size:\n"); + + uint32_t size = size_begin; + uint32_t count = count_begin; + + for (int i = 0; i < 15; i++) + { + pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_GDMA_KDP_TRANSFER_ASYNC, 0); + size *= 2; + count /= 2; + } + + kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 15 - pass_count); + } + + { + uint32_t dstAddr = 0x62000000; + uint32_t srcAddr = 0x62800000; + + int pass_count = 0; + + kmdw_printf("\n"); + kmdw_printf("[ kdrv_gdma_transfer() test all 8 DMA channels ]\n"); + + uint32_t size = 131072; + uint32_t count = 4000; + + for (int i = 0; i < 8; i++) + { + kmdw_printf("Testing DMA CH %d:\n", i); + pass_count += one_dma_memcpy_test(dstAddr, srcAddr, size, count, TEST_SPECIFIED_DMA_CHANNEL, i); + } + + kmdw_printf("Passed: %d, Failed: %d\n", pass_count, 8 - pass_count); + } + + kmdw_printf("All GDMA tests are done !!\n"); +} + +static void test_gdma_thread(void *arg) +{ + test_dma_functions(); +} + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); // for memory alloc from ddr + kdrv_uart_initialize(); // for log printing + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing + + + // init GDMA resources + kdrv_gdma_initialize(); + + // test GDMA functions in non-OS context + test_dma_functions(); + + // create a thread to test GDMA functions in OS context + osThreadNew(test_gdma_thread, NULL, NULL); + + //application is triggered in host_com.c + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/gdma/sn52096/project.h b/build/example_kdrv/gdma/sn52096/project.h new file mode 100644 index 0000000..f469262 --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/gdma/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/gdma/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/gdma/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/gdma/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..24a8ecf --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,349 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_gdma_main.c + ex_gdma_main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + kdrv_gdma.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/gdma/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/gdma/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..631994d --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,638 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ex_gdma_main.c + 1 + ..\..\main_scpu\ex_gdma_main.c + + + project.h + 5 + ..\project.h + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_memory.c + 1 + ..\..\..\..\..\mdw\memory\kmdw_memory.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_ddr.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_gdma.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/gdma/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/gdma/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/gdma/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/gpio/main_scpu/ex_gpio_main.c b/build/example_kdrv/gpio/main_scpu/ex_gpio_main.c new file mode 100644 index 0000000..d72349e --- /dev/null +++ b/build/example_kdrv/gpio/main_scpu/ex_gpio_main.c @@ -0,0 +1,64 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kdrv_uart.h" +#include "kmdw_console.h" +#include "kdrv_cmsis_core.h" + +extern void gpio_example_init(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + + /* below is some middleware init settings */ + kdrv_uart_initialize(); // for log printing + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing + + // init some GPIO pins as input or output + gpio_example_init(); + + //application is triggered in host_com.c + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/gpio/main_scpu/gpio_example.c b/build/example_kdrv/gpio/main_scpu/gpio_example.c new file mode 100644 index 0000000..d50ff96 --- /dev/null +++ b/build/example_kdrv/gpio/main_scpu/gpio_example.c @@ -0,0 +1,128 @@ +/* + * Kneron peripheral driver test code for GPIO + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include "cmsis_os2.h" + +#include "kdrv_pinmux.h" +#include "kdrv_gpio.h" +#include "kmdw_console.h" + +static void gpio_test_thread(void *argument); +static void gpio_callback(kdrv_gpio_pin_t pin, void *arg); + +void gpio_example_init(void) +{ + DSG("Creating a user thread for interrupt notification\n"); + + // create a thread to wait for interrupt notifications + osThreadNew(&gpio_test_thread, NULL, NULL); + + DSG("Configuring pins to GPIO function, GPIO22(SD_CLK), GPIO23(SD_CMD), GPIO24(SD_DAT0), GPIO25(SD_DAT1)\n"); + + /* + configure selected pins as GPIO function (pinmux) + users must check pinmux table to configure specified pins + as desired peripheral functions properly + */ + kdrv_pinmux_config(KDRV_PIN_SD_CLK, PIN_MODE_3, PIN_PULL_NONE, PIN_DRIVING_8MA); // as GPIO 22 + kdrv_pinmux_config(KDRV_PIN_SD_CMD, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); // as GPIO 23 + kdrv_pinmux_config(KDRV_PIN_SD_DAT_0, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); // as GPIO 24 + kdrv_pinmux_config(KDRV_PIN_SD_DAT_1, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); // as GPIO 25 + + DSG("init gpio controller\n"); + + // init GPIO controller + kdrv_gpio_initialize(); + + DSG("setting GPIO22 : Output Low\n"); + + // set GPIO 22 as output low in the beginning + kdrv_gpio_set_attribute(GPIO_PIN_22, GPIO_DIR_OUTPUT); + kdrv_gpio_write_pin(GPIO_PIN_22, false); + + DSG("setting GPIO23 : Input with pull-high\n"); + + // set GPIO 23 as digital input + kdrv_gpio_set_attribute(GPIO_PIN_23, GPIO_DIR_INPUT); + + DSG("setting GPIO24 : Interrupt source, pull-high, debounce\n"); + + /* set GPIO 24 as interrupt input, pull-high, debounce */ + { + // first disable interrupt in case of wrong condition + kdrv_gpio_set_interrupt(GPIO_PIN_24, false); + + // set pin attributes as desired + kdrv_gpio_set_attribute(GPIO_PIN_24, (GPIO_DIR_INPUT | GPIO_INT_EDGE_FALLING)); + + // enable internal hardware debounce with clock rate + kdrv_gpio_set_debounce(GPIO_PIN_24, true /* 1 for enable */, 1000); + + // at last enable interrupt after all settings done + kdrv_gpio_set_interrupt(GPIO_PIN_24, true); + } + + DSG("setting GPIO25 : Interrupt source, pull-high, debounce\n"); + + /* set GPIO 25 as interrupt input, pull-high, debounce */ + { + // first disable interrupt in case of wrong condition + kdrv_gpio_set_interrupt(GPIO_PIN_25, false); + + // set pin attributes as desired + kdrv_gpio_set_attribute(GPIO_PIN_25, (GPIO_DIR_INPUT | GPIO_INT_EDGE_FALLING)); + + // enable internal hardware debounce with clock rate + kdrv_gpio_set_debounce(GPIO_PIN_25, true /* 1 for enable */, 1000); + + // at last enable interrupt after all settings done + kdrv_gpio_set_interrupt(GPIO_PIN_25, true); + } + + // set interrupt callback for GPIO interrupt + kdrv_gpio_register_callback(gpio_callback, NULL); + + /* exit here then let kernel get started */ +} + +static void gpio_callback(kdrv_gpio_pin_t pin, void *arg) +{ + if (pin == GPIO_PIN_24) + { + static bool toogle = false; + /* print something */ + DSG("GPIO24(SD_DAT0) btn is clicked, now inverse GPIO22(SD_CLK)\n"); + + toogle = toogle ? false : true; + kdrv_gpio_write_pin(GPIO_PIN_22, toogle); + } + else if (pin == GPIO_PIN_25) + { + /* print something */ + DSG("GPIO25(SD_DAT1) btn clicked\n"); + } +} + +static void gpio_test_thread(void *argument) +{ + + for (;;) + { + uint32_t flags = osThreadFlagsWait(0x1, osFlagsWaitAny, 2000); // 2 secs timeout + if (flags == osFlagsErrorTimeout) + { + // do following per 2 secs timeout + + // read GPIO 23 + bool value; + kdrv_gpio_read_pin(GPIO_PIN_23, &value); + + /* print GPIO 23 value */ + DSG("GPIO23(SD_CMD) input : %s\n", value ? "High" : "Low"); + } + } +} diff --git a/build/example_kdrv/gpio/sn52096/project.h b/build/example_kdrv/gpio/sn52096/project.h new file mode 100644 index 0000000..9454e5f --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/gpio/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/gpio/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/gpio/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/gpio/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..a5c4b9d --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,337 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_gpio_main.c + ex_gpio_main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\main_scpu\gpio_example.c + gpio_example.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + kdrv_gpio.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + kdrv_pinmux.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/gpio/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/gpio/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..35e0007 --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,633 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ex_gpio_main.c + 1 + ..\..\main_scpu\ex_gpio_main.c + + + project.h + 5 + ..\project.h + + + gpio_example.c + 1 + ..\..\main_scpu\gpio_example.c + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_gpio.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + + + kdrv_pinmux.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/gpio/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/gpio/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/gpio/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/heap_4/main_scpu/ex_heap4_main.c b/build/example_kdrv/heap_4/main_scpu/ex_heap4_main.c new file mode 100644 index 0000000..8a5cc7b --- /dev/null +++ b/build/example_kdrv/heap_4/main_scpu/ex_heap4_main.c @@ -0,0 +1,83 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kdrv_uart.h" +#include "kmdw_memory.h" //for ddr_malloc +#include "kmdw_console.h" +#include "kdrv_cmsis_core.h" + +#include "heap_4.h" + +void heap_example() +{ + uint8_t *buffer[10] = {0}; + uint32_t size[10] = {128, 255, 322, 1028, 2000, 4000, 10200, 20000, 30000, 45678}; + + for (int i = 0; i < 10; i++) + { + buffer[i] = pvPortMalloc(size[i]); + DSG("Allocating memory for buffer[%d] at addr 0x%p, size %u", i, buffer[i], size[i]); + } + + for (int i = 0; i < 10; i++) + { + vPortFree(buffer[i]); + DSG("Freeing memory of buffer[%d] at addr 0x%p", i, buffer[i]); + } +} + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kdrv_uart_initialize(); // for log printing + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing + + heap_example(); + + //application is triggered in host_com.c + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/heap_4/main_scpu/heap_4.c b/build/example_kdrv/heap_4/main_scpu/heap_4.c new file mode 100644 index 0000000..f46571f --- /dev/null +++ b/build/example_kdrv/heap_4/main_scpu/heap_4.c @@ -0,0 +1,390 @@ +/* + FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined //configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * A sample implementation of pvPortMalloc() and vPortFree() that combines + * (coalescences) adjacent memory blocks as they are freed, and in so doing + * limits memory fragmentation. + * + * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the + * memory management pages of http://www.FreeRTOS.org for more information. + */ + +#include + +/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining +all the API functions to use the MPU wrappers. That should only be done when +task.h is included from an application file. */ + +#define config_HEAP_START 0x62000000 +#define configTOTAL_HEAP_SIZE 16*1024*1024 +#define portBYTE_ALIGNMENT 16 +#define portBYTE_ALIGNMENT_MASK (portBYTE_ALIGNMENT-1) + +/* Block sizes must not get too small. */ +#define heapMINIMUM_BLOCK_SIZE ((size_t)(xHeapStructSize << 1)) + +/* Assumes 8bit bytes! */ +#define heapBITS_PER_BYTE ((size_t)8) + +/* Allocate the memory for the heap. */ +static uint8_t ucHeap[configTOTAL_HEAP_SIZE]; + +/* Define the linked list structure. This is used to link free blocks in order +of their memory address. */ +typedef struct A_BLOCK_LINK +{ + struct A_BLOCK_LINK *pxNextFreeBlock; /*<< The next free block in the list. */ + size_t xBlockSize; /*<< The size of the free block. */ +} BlockLink_t; + +/*-----------------------------------------------------------*/ + +/* + * Inserts a block of memory that is being freed into the correct position in + * the list of free memory blocks. The block being freed will be merged with + * the block in front it and/or the block behind it if the memory blocks are + * adjacent to each other. + */ +static void prvInsertBlockIntoFreeList(BlockLink_t *pxBlockToInsert); + +/* + * Called automatically to setup the required heap structures the first time + * pvPortMalloc() is called. + */ +static void prvHeapInit(void); + +/*-----------------------------------------------------------*/ + +/* The size of the structure placed at the beginning of each allocated memory +block must by correctly byte aligned. */ +static const size_t xHeapStructSize = (sizeof(BlockLink_t) + ((size_t)(portBYTE_ALIGNMENT - 1))) & ~((size_t)portBYTE_ALIGNMENT_MASK); + +/* Create a couple of list links to mark the start and end of the list. */ +static BlockLink_t xStart, *pxEnd = NULL; + +/* Keeps track of the number of free bytes remaining, but says nothing about +fragmentation. */ +static size_t xFreeBytesRemaining = 0U; +static size_t xMinimumEverFreeBytesRemaining = 0U; + +/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize +member of an BlockLink_t structure is set then the block belongs to the +application. When the bit is free the block is still part of the free heap +space. */ +static size_t xBlockAllocatedBit = 0; + +/*-----------------------------------------------------------*/ + +void *pvPortMalloc(size_t xWantedSize) +{ + BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; + void *pvReturn = NULL; + + /* If this is the first call to malloc then the heap will require + initialisation to setup the list of free blocks. */ + if (pxEnd == NULL) + { + prvHeapInit(); + } + + /* Check the requested block size is not so large that the top bit is + set. The top bit of the block size member of the BlockLink_t structure + is used to determine who owns the block - the application or the + kernel, so it must be free. */ + if ((xWantedSize & xBlockAllocatedBit) == 0) + { + /* The wanted size is increased so it can contain a BlockLink_t + structure in addition to the requested amount of bytes. */ + if (xWantedSize > 0) + { + xWantedSize += xHeapStructSize; + + /* Ensure that blocks are always aligned to the required number + of bytes. */ + if ((xWantedSize & portBYTE_ALIGNMENT_MASK) != 0x00) + { + /* Byte alignment required. */ + xWantedSize += (portBYTE_ALIGNMENT - (xWantedSize & portBYTE_ALIGNMENT_MASK)); + } + } + + if ((xWantedSize > 0) && (xWantedSize <= xFreeBytesRemaining)) + { + /* Traverse the list from the start (lowest address) block until + one of adequate size is found. */ + pxPreviousBlock = &xStart; + pxBlock = xStart.pxNextFreeBlock; + while ((pxBlock->xBlockSize < xWantedSize) && (pxBlock->pxNextFreeBlock != NULL)) + { + pxPreviousBlock = pxBlock; + pxBlock = pxBlock->pxNextFreeBlock; + } + + /* If the end marker was reached then a block of adequate size + was not found. */ + if (pxBlock != pxEnd) + { + /* Return the memory space pointed to - jumping over the + BlockLink_t structure at its start. */ + pvReturn = (void *)(((uint8_t *)pxPreviousBlock->pxNextFreeBlock) + xHeapStructSize); + + /* This block is being returned for use so must be taken out + of the list of free blocks. */ + pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; + + /* If the block is larger than required it can be split into + two. */ + if ((pxBlock->xBlockSize - xWantedSize) > heapMINIMUM_BLOCK_SIZE) + { + /* This block is to be split into two. Create a new + block following the number of bytes requested. The void + cast is used to prevent byte alignment warnings from the + compiler. */ + pxNewBlockLink = (void *)(((uint8_t *)pxBlock) + xWantedSize); + + /* Calculate the sizes of two blocks split from the + single block. */ + pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; + pxBlock->xBlockSize = xWantedSize; + + /* Insert the new block into the list of free blocks. */ + prvInsertBlockIntoFreeList(pxNewBlockLink); + } + + xFreeBytesRemaining -= pxBlock->xBlockSize; + + if (xFreeBytesRemaining < xMinimumEverFreeBytesRemaining) + { + xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; + } + + /* The block is being returned - it is allocated and owned + by the application and has no "next" block. */ + pxBlock->xBlockSize |= xBlockAllocatedBit; + pxBlock->pxNextFreeBlock = NULL; + } + } + } + + return pvReturn; +} +/*-----------------------------------------------------------*/ + +void vPortFree(void *pv) +{ + uint8_t *puc = (uint8_t *)pv; + BlockLink_t *pxLink; + + if (pv != NULL) + { + /* The memory being freed will have an BlockLink_t structure immediately + before it. */ + puc -= xHeapStructSize; + + /* This casting is to keep the compiler from issuing warnings. */ + pxLink = (void *)puc; + + if ((pxLink->xBlockSize & xBlockAllocatedBit) != 0) + { + if (pxLink->pxNextFreeBlock == NULL) + { + /* The block is being returned to the heap - it is no longer + allocated. */ + pxLink->xBlockSize &= ~xBlockAllocatedBit; + + //vTaskSuspendAll(); + { + /* Add this block to the list of free blocks. */ + xFreeBytesRemaining += pxLink->xBlockSize; + prvInsertBlockIntoFreeList(((BlockLink_t *)pxLink)); + } + } + } + } +} +/*-----------------------------------------------------------*/ + +size_t xPortGetFreeHeapSize(void) +{ + return xFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +size_t xPortGetMinimumEverFreeHeapSize(void) +{ + return xMinimumEverFreeBytesRemaining; +} +/*-----------------------------------------------------------*/ + +void vPortInitialiseBlocks(void) +{ + /* This just exists to keep the linker quiet. */ +} +/*-----------------------------------------------------------*/ + +static void prvHeapInit(void) +{ + BlockLink_t *pxFirstFreeBlock; + uint8_t *pucAlignedHeap; + size_t uxAddress; + size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; + + /* Ensure the heap starts on a correctly aligned boundary. */ + uxAddress = (size_t)config_HEAP_START; + + if ((uxAddress & portBYTE_ALIGNMENT_MASK) != 0) + { + uxAddress += (portBYTE_ALIGNMENT - 1); + uxAddress &= ~((size_t)portBYTE_ALIGNMENT_MASK); + xTotalHeapSize -= uxAddress - (size_t)ucHeap; + } + + pucAlignedHeap = (uint8_t *)uxAddress; + + /* xStart is used to hold a pointer to the first item in the list of free + blocks. The void cast is used to prevent compiler warnings. */ + xStart.pxNextFreeBlock = (void *)pucAlignedHeap; + xStart.xBlockSize = (size_t)0; + + /* pxEnd is used to mark the end of the list of free blocks and is inserted + at the end of the heap space. */ + uxAddress = ((size_t)pucAlignedHeap) + xTotalHeapSize; + uxAddress -= xHeapStructSize; + uxAddress &= ~((size_t)portBYTE_ALIGNMENT_MASK); + pxEnd = (void *)uxAddress; + pxEnd->xBlockSize = 0; + pxEnd->pxNextFreeBlock = NULL; + + /* To start with there is a single free block that is sized to take up the + entire heap space, minus the space taken by pxEnd. */ + pxFirstFreeBlock = (void *)pucAlignedHeap; + pxFirstFreeBlock->xBlockSize = uxAddress - (size_t)pxFirstFreeBlock; + pxFirstFreeBlock->pxNextFreeBlock = pxEnd; + + /* Only one block exists - and it covers the entire usable heap space. */ + xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; + + /* Work out the position of the top bit in a size_t variable. */ + xBlockAllocatedBit = ((size_t)1) << ((sizeof(size_t) * heapBITS_PER_BYTE) - 1); +} +/*-----------------------------------------------------------*/ + +static void prvInsertBlockIntoFreeList(BlockLink_t *pxBlockToInsert) +{ + BlockLink_t *pxIterator; + uint8_t *puc; + + /* Iterate through the list until a block is found that has a higher address + than the block being inserted. */ + for (pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock) + { + /* Nothing to do here, just iterate to the right position. */ + } + + /* Do the block being inserted, and the block it is being inserted after + make a contiguous block of memory? */ + puc = (uint8_t *)pxIterator; + if ((puc + pxIterator->xBlockSize) == (uint8_t *)pxBlockToInsert) + { + pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; + pxBlockToInsert = pxIterator; + } + + /* Do the block being inserted, and the block it is being inserted before + make a contiguous block of memory? */ + puc = (uint8_t *)pxBlockToInsert; + if ((puc + pxBlockToInsert->xBlockSize) == (uint8_t *)pxIterator->pxNextFreeBlock) + { + if (pxIterator->pxNextFreeBlock != pxEnd) + { + /* Form one big block from the two blocks. */ + pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxEnd; + } + } + else + { + pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; + } + + /* If the block being inserted plugged a gab, so was merged with the block + before and the block after, then it's pxNextFreeBlock pointer will have + already been set, and should not be set here as that would make it point + to itself. */ + if (pxIterator != pxBlockToInsert) + { + pxIterator->pxNextFreeBlock = pxBlockToInsert; + } +} diff --git a/build/example_kdrv/heap_4/main_scpu/heap_4.h b/build/example_kdrv/heap_4/main_scpu/heap_4.h new file mode 100644 index 0000000..dfd27a7 --- /dev/null +++ b/build/example_kdrv/heap_4/main_scpu/heap_4.h @@ -0,0 +1,10 @@ +#ifndef __HEAP_4_H_ +#define __HEAP_4_H_ + +#include + +extern void *pvPortMalloc(size_t xWantedSize); +extern void vPortFree(void *pv); + +#endif + diff --git a/build/example_kdrv/heap_4/sn52096/project.h b/build/example_kdrv/heap_4/sn52096/project.h new file mode 100644 index 0000000..9454e5f --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/heap_4/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/heap_4/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/heap_4/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/heap_4/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..d75717c --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,325 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\heap_4.c + heap_4.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_heap4_main.c + ex_heap4_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/heap_4/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/heap_4/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..c79d654 --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,628 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + heap_4.c + 1 + ..\..\main_scpu\heap_4.c + + + project.h + 5 + ..\project.h + + + ex_heap4_main.c + 1 + ..\..\main_scpu\ex_heap4_main.c + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_ddr.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/heap_4/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/heap_4/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/heap_4/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/i2c_master/main_scpu/ex_i2cm_main.c b/build/example_kdrv/i2c_master/main_scpu/ex_i2cm_main.c new file mode 100644 index 0000000..8e1c534 --- /dev/null +++ b/build/example_kdrv/i2c_master/main_scpu/ex_i2cm_main.c @@ -0,0 +1,64 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kdrv_uart.h" +#include "kmdw_memory.h" //for ddr_malloc +#include "kmdw_console.h" +#include "kdrv_cmsis_core.h" + +extern void i2c_master_example(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + + /* below is some middleware init settings */ + kdrv_uart_initialize(); // for log printing + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing + + i2c_master_example(); + + //application is triggered in host_com.c + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/i2c_master/main_scpu/i2c_master_example.c b/build/example_kdrv/i2c_master/main_scpu/i2c_master_example.c new file mode 100644 index 0000000..6d55139 --- /dev/null +++ b/build/example_kdrv/i2c_master/main_scpu/i2c_master_example.c @@ -0,0 +1,70 @@ +/* + * Kneron I2C driver API testing code + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include "cmsis_os2.h" + +#include "kdrv_i2c.h" +#include "kdrv_pinmux.h" +#include "kmdw_console.h" + +static void i2c_sht20_thread(void *argument) +{ + uint16_t dev_addr = 0x40; + uint8_t cmd = 0xF3; + uint8_t data[3]; + kdrv_status_t status; + + while(1) + { + status = kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 1, 1, 1, &cmd); + if(status != KDRV_STATUS_OK){ + DSG("kdrv_i2c_write_register() failed, status = %d\n", status); + break; + } + + while(1) + { + osDelay(10); + status = kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 3, 3, 3, data); + if(status != KDRV_STATUS_OK){ + continue; + } + else + { + DSG("read data = 0x%x 0x%x 0x%x\n", data[0], data[1], data[2]); + osDelay(5000); + break; + } + } + + } +} + + +void i2c_master_example() +{ + DSG("Configuring pins for I2C device, enable KDRV_PIN_I2C0_SCL and KDRV_PIN_I2C0_SCL\n"); + + /* + configure selected pins as GPIO function (pinmux) + users must check pinmux table to configure specified pins + as desired peripheral functions properly + */ + kdrv_pinmux_config(KDRV_PIN_I2C0_SCL, PIN_MODE_0, PIN_PULL_NONE, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_I2C0_SDA, PIN_MODE_0, PIN_PULL_NONE, PIN_DRIVING_8MA); + + DSG("init I2C0\n"); + + // init GPIO controller + kdrv_status_t status; + if( KDRV_STATUS_OK == (status = kdrv_i2c_initialize(KDRV_I2C_CTRL_0, KDRV_I2C_SPEED_400K))) + osThreadNew(i2c_sht20_thread, NULL, NULL); + else{ + DSG("kdrv_i2c_initialize() failed, status = \n", status); + } +} + diff --git a/build/example_kdrv/i2c_master/sn52096/project.h b/build/example_kdrv/i2c_master/sn52096/project.h new file mode 100644 index 0000000..9454e5f --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/i2c_master/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/i2c_master/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/i2c_master/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/i2c_master/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..165fe6a --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,337 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\i2c_master_example.c + i2c_master_example.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_i2cm_main.c + ex_i2cm_main.c + 0 + 0 + + + 1 + 3 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + kdrv_i2c.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + kdrv_pinmux.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/i2c_master/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/i2c_master/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..63f265d --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,633 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + i2c_master_example.c + 1 + ..\..\main_scpu\i2c_master_example.c + + + ex_i2cm_main.c + 1 + ..\..\main_scpu\ex_i2cm_main.c + + + project.h + 5 + ..\project.h + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_i2c.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + + + kdrv_pinmux.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/i2c_master/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/i2c_master/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/i2c_master/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/panel/lcdc/main_scpu/main.c b/build/example_kdrv/panel/lcdc/main_scpu/main.c new file mode 100644 index 0000000..674e857 --- /dev/null +++ b/build/example_kdrv/panel/lcdc/main_scpu/main.c @@ -0,0 +1,98 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "cmsis_os2.h" +#include "kdrv_cmsis_core.h" + +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kdrv_pinmux.h" + +#include "kmdw_memory.h" +#include "kmdw_console.h" +#include "kmdw_display.h" + + +#define CAMERA_RGB_IDX (0) +#define CAMERA_NIR_IDX (1) + +//project.h -> board.h +//#define LCDC_WIDTH (640) +//#define LCDC_HEIGHT (480) + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; + +void example_dp_open(uint32_t width, uint32_t height, uint32_t pixelformat) +{ + struct video_input_params params; + + params.input_fmt = pixelformat; + params.input_xres = width; + params.input_yres = height; + + kmdw_video_renderer_open(¶ms); + kmdw_video_renderer_set_camera(CAMERA_RGB_IDX); + kmdw_display_set_pen_rgb565(BLACK, 4); + kmdw_video_renderer_buffer_initialize(¶ms); + kmdw_video_renderer_start(); +} + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); // for memory alloc from ddr + kdrv_uart_initialize(); // for log printing + kdrv_uart_console_init(COMM_PORT_ID_0, COMM_UART_BAUDRATE_115200, NULL); // enable console mdw for printing + + kdrv_pinmux_initialize(PIN_NUM, pinmux_array); + + /* init the display */ + kmdw_display_test_pattern_gen(TRUE); + kmdw_display_initialize(); + + /* init the application */ + example_dp_open(LCDC_WIDTH, LCDC_HEIGHT, V2K_PIX_FMT_RGB565); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/panel/lcdc/sn52096/project.h b/build/example_kdrv/panel/lcdc/sn52096/project.h new file mode 100644 index 0000000..8765932 --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/project.h @@ -0,0 +1,185 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +CAM setting +=============================================================================*/ +//project.h +#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 + +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h new file mode 100644 index 0000000..e999392 --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'Target-SCPU' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..bffe29f --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..210dd77 --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,418 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\vtor.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + d + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\main.c + main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\display\kmdw_display.c + kmdw_display.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + kdrv_pinmux.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_lcdc.c + kdrv_lcdc.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + + + device + 0 + 0 + 0 + 0 + + 4 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\dev\panel\kdev_mzt_480x272.c + kdev_mzt_480x272.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..83eaff2 --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,658 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4100 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, BOARD_96 + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\dev\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + main.c + 1 + ..\..\main_scpu\main.c + + + project.h + 5 + ..\project.h + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_display.c + 1 + ..\..\..\..\..\..\mdw\display\kmdw_display.c + + + + + driver + + + kdrv_pinmux.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_lcdc.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_lcdc.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + + + device + + + kdev_mzt_480x272.c + 1 + ..\..\..\..\..\..\platform\dev\panel\kdev_mzt_480x272.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/panel/lcdc/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/pwm/main_scpu/ex_pwm_main.c b/build/example_kdrv/pwm/main_scpu/ex_pwm_main.c new file mode 100644 index 0000000..16d0044 --- /dev/null +++ b/build/example_kdrv/pwm/main_scpu/ex_pwm_main.c @@ -0,0 +1,176 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" +#include "kdrv_system.h" +#include "kmdw_console.h" +#include "kdrv_cmsis_core.h" + +#include "kdrv_pwm.h" + +extern void delay_ms(unsigned int msec); // FIXME... + +#define PWM_Duty_Check_holdtime 1000 //1sec + +extern void delay_ms_enable(void); + +#include "rtc.h" + +struct rtc_time_s mytime; + + +void sample_pwm_test(pwmtimer pwm_channel) +{ + char buf[256]; + unsigned int period, duty, polarity; + + DSG("[PWM%d Test]",pwm_channel); + DSG("Please input the period(10ns)"); + kmdw_console_echo_gets(buf, sizeof(buf)); + period = atoi(buf); + DSG("Please input duty(10ns)"); + kmdw_console_echo_gets(buf, sizeof(buf)); + duty = atoi(buf); + DSG("Please input polarity(0:low, 1:high)"); + kmdw_console_echo_gets(buf, sizeof(buf)); + polarity = atoi(buf); + DSG("period = %d, duty = %d, polarity = %d", period, duty, polarity); + + kdrv_pwm_config((pwmtimer)pwm_channel, (pwmpolarity)polarity, duty, period, 0); + kdrv_pwm_enable((pwmtimer)pwm_channel); + DSG("setting done!"); + +} + +void sample_pwm_adjust_duty_test(pwmtimer pwm_channel, uint16_t duty) +{ + //char buf[256]; + unsigned int period, polarity; + + DSG("[PWM%d Test]",pwm_channel); + period = 1000; + polarity = 0; + DSG("period = %d, duty = %d, polarity = %d", period, duty, polarity); + + kdrv_pwm_config((pwmtimer)pwm_channel, (pwmpolarity)polarity, duty, period, 0); + kdrv_pwm_enable((pwmtimer)pwm_channel); + DSG("setting done!"); + +} + +void myPWMtest(void) +{ + char buf[256]; + uint16_t duty=0; + + //TEST 1 + DSG("************************************"); + sample_pwm_test(PWMTIMER1); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + kdrv_pwm_disable(PWMTIMER1); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + + DSG("************************************"); + sample_pwm_test(PWMTIMER2); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + kdrv_pwm_disable(PWMTIMER2); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + + DSG("************************************"); + sample_pwm_test(PWMTIMER3); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + kdrv_pwm_disable(PWMTIMER3); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + + DSG("************************************"); + sample_pwm_test(PWMTIMER4); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + kdrv_pwm_disable(PWMTIMER4); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + + DSG("************************************"); + sample_pwm_test(PWMTIMER5); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + kdrv_pwm_disable(PWMTIMER5); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + + DSG("************************************"); + sample_pwm_test(PWMTIMER6); + DSG("Enter to go next step!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + kdrv_pwm_disable(PWMTIMER6); + DSG("Enter to go to next test!"); + kmdw_console_echo_gets(buf, sizeof(buf)); + + //TEST 2 + DSG("************************************"); + DSG("PWM duty increasing test!"); + for(duty=50; duty <= 1000; duty+=50) + { + sample_pwm_adjust_duty_test(PWMTIMER6, duty); + kdrv_pwmtimer_delay_ms(PWM_Duty_Check_holdtime); + } + + //TEST 3 + DSG("************************************"); + DSG("PWM duty decreasing test!"); + for(duty=1000; duty >= 50; duty-=50) + { + sample_pwm_adjust_duty_test(PWMTIMER6, duty); + kdrv_pwmtimer_delay_ms(PWM_Duty_Check_holdtime); + } +} + + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + kdrv_system_init(); + + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // for log + + SystemCoreClockUpdate(); // System Initialization + + myPWMtest(); + + while(1); +} + + diff --git a/build/example_kdrv/pwm/sn52096/project.h b/build/example_kdrv/pwm/sn52096/project.h new file mode 100644 index 0000000..9454e5f --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/pwm/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/pwm/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/pwm/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/pwm/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..5a17461 --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,313 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_pwm_main.c + ex_pwm_main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/pwm/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/pwm/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..67f5b35 --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,623 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ex_pwm_main.c + 1 + ..\..\main_scpu\ex_pwm_main.c + + + project.h + 5 + ..\project.h + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/pwm/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/pwm/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/pwm/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/sdc/main_scpu/ex_sdc_main.c b/build/example_kdrv/sdc/main_scpu/ex_sdc_main.c new file mode 100644 index 0000000..bb0ec83 --- /dev/null +++ b/build/example_kdrv/sdc/main_scpu/ex_sdc_main.c @@ -0,0 +1,45 @@ +/*( + * Kneron Peripheral API - SDC Test function + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ +#include +#include +#include "cmsis_os2.h" +#include "project.h" +#include "kdrv_cmsis_core.h" +#include "kdrv_uart.h" +#include "kdrv_system.h" +#include "kdrv_power.h" +#include "kdrv_pwm.h" +#include "kdrv_sdc.h" +#include "base.h" +#include "io.h" +#include "kdrv_ddr.h" +#include "kmdw_console.h" +#include "kdrv_status.h" +extern void kdrv_system_init(void); +extern void sdc_test_main(void); + + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + kdrv_system_init(); // system default clock and power initialize + kdrv_uart_initialize(); // uart initialize + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // uart0 initialize for log + kdrv_system_init_ncpu(); // init ncpu/ddr power domain, this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // ddr initialize + /* pwmtimer initialize for 1ms timer */ + if(kdrv_pwmtimer_initialize(PWMTIMER1, PWMTMR_1MSEC_PERIOD) != KDRV_STATUS_OK) { + kmdw_printf("Init timer%d Fail!\n",PWMTIMER1); + } + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + sdc_test_main(); + while(1) { + } +} diff --git a/build/example_kdrv/sdc/main_scpu/kdp_sdc_main.c b/build/example_kdrv/sdc/main_scpu/kdp_sdc_main.c new file mode 100644 index 0000000..d55d606 --- /dev/null +++ b/build/example_kdrv/sdc/main_scpu/kdp_sdc_main.c @@ -0,0 +1,346 @@ +/* + * Kneron Peripheral API - SDC Test function + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ +#include +#include +#include "base.h" +#include "io.h" +#include "kdrv_sdc.h" +#include "kmdw_console.h" +#include "kdrv_power.h" +#include "kdrv_scu_ext.h" +#include "kdrv_status.h" +#include "kdrv_pwm.h" + +typedef signed long clock_t; +#define USE_DRAM +#ifdef USE_DRAM +#define TEST_LOOP 10 +#define TEST_LEN 32 * 1024 //32KB test length +static uint8_t *read_buf= (uint8_t *) 0x60300000; +static uint8_t *write_buf = (uint8_t *) 0x60400000; +#else +#define TEST_LOOP 1 +#define TEST_LEN 512 +static uint8_t read_buf[TEST_LEN]; +static uint8_t write_buf[TEST_LEN]; +#endif + +const int8_t *abort_type_table[] = { + {"Asynchronous abort"}, + {"Synchronous abort"}, + {"Undefined abort type"} +}; + +const int8_t *transfer_speed_table[] = { + "Normal Speed / SDR12", + "High Speed / SDR25", + "SDR50-100MHz", + "SDR104-208MHz", + "DDR50", + "Undefined Speed" +}; + +const int8_t *transfer_type_table[] = { + "ADMA", + "SDMA", + "PIO", + "External DMA", + "Undefined Transfer Type" +}; + +const int8_t *kdrv_status_msg[] = { + "KDRV_STATUS_OK", + "KDRV_STATUS_ERROR", + "KDRV_STATUS_INVALID_PARAM", + "KDRV_STATUS_I2C_BUS_BUSY", + "KDRV_STATUS_I2C_DEVICE_NACK", + "KDRV_STATUS_I2C_TIMEOUT", + "KDRV_STATUS_USBD_INVALID_ENDPOINT", + "KDRV_STATUS_USBD_TRANSFER_TIMEOUT", + "KDRV_STATUS_USBD_INVALID_TRANSFER", + "KDRV_STATUS_USBD_TRANSFER_IN_PROGRESS", + "KDRV_STATUS_GDMA_ERROR_NO_RESOURCE", + "KDRV_STATUS_TIMER_ID_NOT_IN_USED", + "KDRV_STATUS_TIMER_ID_IN_USED", + "KDRV_STATUS_TIMER_ID_NOT_AVAILABLE", + "KDRV_STATUS_TIMER_INVALID_TIMER_ID", + "KDRV_STATUS_UART_TX_RX_BUSY", + "KDRV_STATUS_UART_TIMEOUT", + "KDRV_STATUS_SDC_CMD_ERR", + "KDRV_STATUS_SDC_INIT_ERR", + "KDRV_STATUS_SDC_CARD_NO_EXISTED", + "KDRV_STATUS_SDC_CARD_TYPE_ERR", + "KDRV_STATUS_SDC_CSD_EXT_READ_ERR", + "KDRV_STATUS_SDC_CID_READ_ERR", + "KDRV_STATUS_SDC_MEM_ALLOC_ERR", + "KDRV_STATUS_SDC_READ_FAIL", + "KDRV_STATUS_SDC_WRITE_FAIL", + "KDRV_STATUS_SDC_TRANSFER_FAIL", + "KDRV_STATUS_SDC_TIMEOUT", + "KDRV_STATUS_SDC_CMD_NOT_SUPPORT", + "KDRV_STATUS_SDC_BUS_WIDTH_NOT_SUPPORT", + "KDRV_STATUS_SDC_BUS_WIDTH_ERR", + "KDRV_STATUS_SDC_SPEED_MOD_ERR", + "KDRV_STATUS_SDC_VOL_ERR", + "KDRV_STATUS_SDC_INHIBIT_ERR", + "KDRV_STATUS_SDC_RECOVERABLE_ERR", + "KDRV_STATUS_SDC_ABORT_ERR", + "KDRV_STATUS_SDC_SWITCH_ERR", + "KDRV_STATUS_SDC_PWR_SET_ERR", +}; + +uint8_t *kdrv_status_msg_show(kdrv_status_t id) +{ + return (uint8_t *)kdrv_status_msg[id]; +} + +uint8_t *sdc_abort_type_to_str(kdrv_sdc_abort_type_e type) +{ + if (type > ABORT_UNDEFINED) + type = ABORT_UNDEFINED; + + return (uint8_t *)abort_type_table[type]; +} + +/** + * @brief sdc_transfer_type_to_str() convert kdrv_sdc_transfer_type_e to string + */ +uint8_t *sdc_transfer_type_to_str(kdrv_sdc_transfer_type_e tType) +{ + if (tType > TRANS_UNKNOWN) + tType = TRANS_UNKNOWN; + + return (uint8_t *)transfer_type_table[tType]; +} + +/** + * @brief sdc_transfer_speed_to_str() convert transfer_speed to string + */ +uint8_t *sdc_transfer_speed_to_str(kdrv_sdc_bus_speed_e speed) +{ + if (speed > SPEED_RSRV) + speed = SPEED_RSRV; + + return (uint8_t *)transfer_speed_table[speed]; +} + + +/** + * @brief sdc_scr_display() display scr information + */ +void sdc_scr_display(kdrv_sdc_res_t *dev) +{ + volatile kdrv_sdc_sdcard_info_t *card_info = dev->card_info; + kmdw_printf("**************** scr register ****************\n"); + kmdw_printf("SCR Structure: %d\n", card_info->scr.scr_structure); + kmdw_printf("SCR Memory Card - Spec. Version: %d\n", card_info->scr.sd_spec); + kmdw_printf("Data status after erase: %d\n", card_info->scr.data_stat_after_erase); + kmdw_printf("SD Security Support: %d\n", card_info->scr.sd_security); + kmdw_printf("DAT Bus widths supported: %d\n", card_info->scr.sd_bus_widths); + kmdw_printf("CMD23 supported: %d\n", card_info->scr.cmd23_support); + kmdw_printf("CMD20 supported: %d\n", card_info->scr.cmd20_support); + kmdw_printf("**********************************************\n"); +} + + +/** + * @brief sdc_ext_cid_display() display cid information + */ +void sdc_ext_cid_display(kdrv_sdc_res_t *dev) +{ + volatile kdrv_sdc_sdcard_info_t *card = dev->card_info; + kmdw_printf("**************** CID register **************** %x\n",&card->cid_lo); + if (card->card_type == MEMORY_CARD_TYPE_SD) { + kmdw_printf("Manufacturer ID: 0x%02x\n", (unsigned long)(card->cid_hi >> 48)); + kmdw_printf("OEM / App ID: 0x%04x\n", (unsigned long)((card->cid_hi >> 32) & 0xFFFF)); + kmdw_printf("Product Name: 0x%02x\n", + (unsigned long)((((card->cid_hi) & 0xFFFFFFFF) << 8) | (card->cid_lo >> 56) & 0xFF)); + kmdw_printf("Product Revision: %d.%d\n", (card->cid_lo >> 52) & 0xF, (card->cid_lo >> 48) & 0xF); + kmdw_printf("Product Serial No.: %u\n", (card->cid_lo >> 16) & 0xFFFFFFFF); + kmdw_printf("reserved:0x%x\n", (unsigned long)((card->cid_lo & 0xF000) >> 12)); + kmdw_printf("Manufacturer Date: %d - %0.2d\n", + ((card->cid_lo & 0xFF0) >> 4) + 2000, (card->cid_lo & 0xF)); + } else { + kmdw_printf("Manufacturer ID: 0x%02x\n", (unsigned long)(card->cid_hi >> 48)); + kmdw_printf("OEM / App ID: 0x%04x\n", (unsigned long)((card->cid_hi >> 32) & 0xFFFF)); + kmdw_printf("Product Name: 0x%02x\n", + (unsigned long)((((card->cid_hi) & 0xFFFFFFFF) << 16) | (card->cid_lo >> 48) & 0xFFFF)); + kmdw_printf("Product Revision: %d.%d\n", (card->cid_lo >> 44) & 0xF, (card->cid_lo >> 40) & 0xF); + kmdw_printf("Product Serial No.: %u\n", (card->cid_lo >> 8) & 0xFFFFFFFF); + kmdw_printf("Manufacturer Date: %d - %0.2d\n", + ((card->cid_lo & 0xF) + 1997), (card->cid_lo & 0xF0) >> 4); + } +} + +/** + * @brief sdc_ext_csd_display() display csd information + */ +void sdc_ext_csd_display(kdrv_sdc_res_t *dev) +{ + volatile kdrv_sdc_sdcard_info_t *card_info = dev->card_info; + kmdw_printf("**************** Extended CSD register ****************\n"); + kmdw_printf("Ext-CSD: Max Speed %d Hz.\n", card_info->max_dtr); + // Below information is EMBEDDED_MMC + kmdw_printf(" boot_info[228]:0x%x\n", card_info->ext_csd_mmc.boot_info); + /* Some eMMC occupy byte 227 as second byte for BOOT_SIZE_MULTI */ + kmdw_printf(" boot_size_mult[226]:0x%x.\n", (card_info->ext_csd_mmc.reserved6 << 8 | + card_info->ext_csd_mmc.boot_size_mult)); + kmdw_printf(" sec_count[215-212]: 0x%08x.\n", card_info->ext_csd_mmc.sec_count); + kmdw_printf(" hs_timing[185]: 0x%x.\n", card_info->ext_csd_mmc.hs_timing); + kmdw_printf(" bus_width[183]: 0x%x.\n", card_info->ext_csd_mmc.bus_width); + kmdw_printf(" partition_conf[179]: 0x%x.\n", card_info->ext_csd_mmc.partition_conf); + kmdw_printf(" boot_config_port[178]: 0x%x.\n", card_info->ext_csd_mmc.boot_config_prot); + kmdw_printf(" boot_bus_width[177]: 0x%x.\n", card_info->ext_csd_mmc.boot_bus_width); + kmdw_printf(" boot_bus_wp[173]: 0x%x.\n", card_info->ext_csd_mmc.boot_wp); + kmdw_printf(" partition_setting_completed[155]: 0x%x.\n", + card_info->ext_csd_mmc.partition_setting_completed); + + kmdw_printf("**********************************************\n"); + + /* The block number of MMC card, which capacity is more than 2GB, shall be fetched from Ext-CSD. */ + if (card_info->ext_csd_mmc.ext_csd_rev >= 2) { + kmdw_printf(" MMC Ext CSD version %d\n", card_info->ext_csd_mmc.ext_csd_rev); + kmdw_printf(" Ext-CSD: block number %d\n", card_info->num_of_blks, card_info->max_dtr); + } else { + kmdw_printf(" MMC CSD Version 1.%d\n", card_info->csd_mmc.csd_structure); + kmdw_printf(" CSD: block number %d\n", card_info->num_of_blks, card_info->max_dtr); + } + kmdw_printf("**********************************************\n"); +} + + +/** + * @brief sdc_sd_info_display() display sd card information + */ +void sdc_sd_info_display(kdrv_sdc_res_t *dev) +{ + volatile kdrv_sdc_sdcard_info_t *card_info = dev->card_info; + + kmdw_printf("**************** SD Information ****************\n"); + kmdw_printf("* Bus width: %d.\n", card_info->bus_width); + kmdw_printf("* Transfer speed: %s.\n", sdc_transfer_speed_to_str(card_info->speed)); + kmdw_printf("* Transfer type: %s.\n", sdc_transfer_type_to_str(card_info->flow_set.use_dma)); + kmdw_printf("* Auto Command: %d.\n", card_info->flow_set.auto_cmd); + kmdw_printf("* Infinite Test Mode: %d.\n", dev->infinite_mode); + kmdw_printf("* Abort: %s.\n\n", sdc_abort_type_to_str(card_info->flow_set.sync_abort)); +} + + +/** + * @brief dump_data, dump data information + * + * @param start_addr start address for data information + * @param size size for data output + * @return N/A + */ +void dump_data(uint32_t *pp, uint32_t start_addr, uint32_t size) +{ + uint32_t i=0; + do { + if((i%4)==0) { + kmdw_printf("\n"); + kmdw_printf("[0x%08x]:",start_addr); + start_addr+=16; + } + kmdw_printf(" 0x%08x", *(pp++)); + i++; + } while((pp!=NULL)&&(icard_info->card_type == MEMORY_CARD_TYPE_SD) { + kmdw_printf("** Get SD Card **\n"); + sdc_scr_display(dev); + } else if (dev->card_info->card_type == MEMORY_CARD_TYPE_MMC) { + kmdw_printf("** Get eMMC/MMC Card **\n"); + sdc_ext_csd_display(dev); + } + } +#ifdef TEST1 + kmdw_printf("Dump read buffer before action !\n"); + dump_data((uint32_t*) read_buf, 0, 512/4); + kmdw_printf("\n\nDump read buffe !\n"); + kdrv_sdc_read(read_buf, 0, TEST_LEN); + dump_data((uint32_t*) read_buf, 0, TEST_LEN/4); +#endif +#ifdef TEST2 + for (int i = 0; i < TEST_LEN; i++) { + *(write_buf + i) = i + 0x30; + } + kdrv_sdc_write(write_buf, 0, TEST_LEN); + kdrv_sdc_read(read_buf, 0, TEST_LEN); + kmdw_printf("\n\nDump read buffe after flash write !\n"); + dump_data((uint32_t*) read_buf, 0, TEST_LEN/4); + if (memcmp(read_buf, write_buf, TEST_LEN) != 0) + kmdw_printf("SDC Read/Write compare FAIL.(%dB )!\r\n", TEST_LEN); + else + kmdw_printf("SDC Read/Write compare PASS.(%dB )!\r\n", TEST_LEN); +#endif +#ifdef TEST3 + sdc_rw_stress_test(); +#endif + return 0; +} + diff --git a/build/example_kdrv/sdc/sn52096/project.h b/build/example_kdrv/sdc/sn52096/project.h new file mode 100644 index 0000000..9454e5f --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/sdc/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/sdc/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/sdc/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/sdc/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..e21db85 --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,349 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_sdc_main.c + ex_sdc_main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\main_scpu\kdp_sdc_main.c + kdp_sdc_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_sdc.c + kdrv_sdc.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/sdc/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/sdc/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..03fac42 --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,638 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + mozart + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\mozart.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10100000 + 0x18000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, TARGET_SCPU, LOG_ENABLE, KL520 + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + project.h + 5 + ..\project.h + + + ex_sdc_main.c + 1 + ..\..\main_scpu\ex_sdc_main.c + + + kdp_sdc_main.c + 1 + ..\..\main_scpu\kdp_sdc_main.c + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + kdrv_sdc.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_sdc.c + + + kdrv_ddr.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/sdc/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/sdc/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..902d253 --- /dev/null +++ b/build/example_kdrv/sdc/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,9 @@ +//MEMSET(0x10200000, 0x10000, 0) +//MEMSET(0x10210000, 0x08000, 0) +//_WDWORD(0xE000ED08, 0x10102000); +//SP=_RDWORD(0x10102000) // Set Stack Pointer +//PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +//BS main +_WDWORD(0xE000ED08, 0x10100000); +$=0x10100000 +BS main diff --git a/build/example_kdrv/spi_flash/main_scpu/ex_flash_main.c b/build/example_kdrv/spi_flash/main_scpu/ex_flash_main.c new file mode 100644 index 0000000..52f4409 --- /dev/null +++ b/build/example_kdrv/spi_flash/main_scpu/ex_flash_main.c @@ -0,0 +1,634 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" +#include "io.h" + +#include "kdrv_system.h" +#include "kdrv_uart.h" +#include "rtc.h" +#include "kdrv_pwm.h" +#include "kdrv_spif.h" +#include "kdrv_ddr.h" +#include "kdrv_pinmux.h" + +#include "kdev_flash.h" +#include "kdev_flash_winbond.h" + +#include "kmdw_console.h" +#include "kmdw_memory.h" //for ddr_malloc + +extern void kdev_flash_4Bytes_ctrl(uint8_t enable); +extern void kdev_flash_write_control(uint8_t enable); +struct rtc_time_s mytime; + + +#define DDR1_DST 0x60000000 +#define FLASH_SRC 0x00 +#define LENGTH (1024*1024*5) +#define DDR2_DST (DDR1_DST+LENGTH) + +#undef err_msg +#define err_msg DSG_NOLF +#define _get_min(x,y) ( x < y ? x: y ) + +extern spi_flash_t flash_info; +extern void kdev_flash_read_flash_id(void); + +int _kdp_memxfer_flash_to_ddr(uint32_t dst, uint32_t src, size_t bytes, uint8_t mode) +{ + int32_t total_lens; + int32_t access_byte; + uint32_t write_addr; + uint32_t read_data; + int32_t rx_fifo_depth; + + if ((bytes & 0x3) > 0) return -1; + + total_lens = bytes; + write_addr = dst; + rx_fifo_depth = (int32_t)kdrv_spif_rxfifo_depth(); + //read from flash + //write to ddr + +#if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(src)) + { + kdev_flash_4Bytes_ctrl(1); + switch(mode) + { + case 0xEC: + kdrv_spif_set_commands(src, SPI020_EC_CMD1, total_lens, SPI020_EC_CMD3); + break; + case 0x6C: + kdrv_spif_set_commands(src, SPI020_6C_CMD1, total_lens, SPI020_6C_CMD3); + break; + case 0x13: + default: + kdrv_spif_set_commands(src, SPI020_13_CMD1, total_lens, SPI020_13_CMD3); + break; + } + } + else +#endif + { + switch(mode) + { + case 0xEC: + kdrv_spif_set_commands(src, SPI020_EB_CMD1, total_lens, SPI020_EB_CMD3); + break; + case 0x6C: + kdrv_spif_set_commands(src, SPI020_6B_CMD1, total_lens, SPI020_6B_CMD3); + break; + case 0x13: + default: + kdrv_spif_set_commands(src, SPI020_03_CMD1, total_lens, SPI020_03_CMD3); + break; + } + } + + while (total_lens > 0) + { + kdrv_spif_wait_rx_full(); + + access_byte = _get_min(total_lens, rx_fifo_depth); + total_lens -= access_byte; + + while (access_byte > 0) + { + read_data = regSPIF_data->dw.kdrv_spif_dp;//u32Lib_LeRead32((unsigned char* )SPI020REG_DATAPORT); + *(volatile unsigned int *)(write_addr) = read_data;//outw(write_addr, read_data); + write_addr += 4; + access_byte -= 4; + } + } +#ifndef MIXING_MODE_OPEN_RENDERER + kdrv_spif_wait_command_complete();/* wait for command complete */ +#endif + +#if FLASH_4BYTES_CMD_EN + kdev_flash_4Bytes_ctrl(0); +#endif + + return 0; +} + +extern void kdev_flash_64kErase(uint32_t offset); +void mySPItest(void) +{ + uint32_t RDSR1=0; //05h + uint32_t RDSR2=0; //35h + uint32_t RDCR=0; //15h + u32 reg; + u32 m,k, err, Qmode = 0x13, block_erase=0; + char s[48]; + char Ch; + int mA; + int flash_op_driving; + uint8_t manufacturer_ID = 0; + uint8_t buf[2]; + uint32_t size=0; + uint32_t st_tick, sp_tick; + uint32_t block = 0; + uint32_t block_addr = 0; + + //config to 25MHz and single mode + regSPIF_ctrl->st.bf.kdrv_spif_cr.abort = 1;//vLib_LeWrite32(SPI020REG_CONTROL, SPI020_ABORT); + do + { + //if((u32Lib_LeRead32(SPI020REG_CONTROL)&SPI020_ABORT)==0x00) + if(regSPIF_ctrl->st.bf.kdrv_spif_cr.abort == 0) + break; + }while(1); + + /* Set control register */ + reg = regSPIF_ctrl->st.dw.kdrv_spif_cr;//u32Lib_LeRead32(SPI020REG_CONTROL); // 0x80 + reg &= ~(SPI020_CLK_MODE | SPI020_CLK_DIVIDER); + reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_8; // System:200MHz, DIV_8:25MHz + regSPIF_ctrl->st.dw.kdrv_spif_cr = reg;//vLib_LeWrite32(SPI020REG_CONTROL, reg); + + /*16mA*/ + //mA = 0; //4mA + //mA = 1; //8mA + //mA = 2; //12mA + mA = 3; //16mA + for(uint32_t addr=0xC2380104; addr<=0xC2380114; addr+=4) + { + reg = inw(addr); //SPI IO control + reg &= ~0x000000C0; //clear bit6, bit7 + reg |= (mA<<6); //select driving strength sun1023 + outw(addr, reg); + } + + kdev_flash_read_flash_id(); + err_msg("read_spi_flash_id %x OK!\n",flash_info.flash_id); + err_msg("read_spi_flash_manufacture %x OK!\n",flash_info.manufacturer); + + kdev_flash_4Bytes_ctrl(1); + + //full fill buffer by 0x99 to clear previous data + memset((void*)DDR1_DST, 0x99, LENGTH); + //read data by 25MHz and Quad mode as a golden sample + _kdp_memxfer_flash_to_ddr(DDR1_DST, FLASH_SRC, LENGTH, Qmode); + +//start testing +/*******************************************************************************/ + + regSPIF_ctrl->st.bf.kdrv_spif_cr.abort = 1;//vLib_LeWrite32(SPI020REG_CONTROL, SPI020_ABORT); + do + { + //if((u32Lib_LeRead32(SPI020REG_CONTROL)&SPI020_ABORT)==0x00) + if(regSPIF_ctrl->st.bf.kdrv_spif_cr.abort == 0) + break; + }while(1); + + /* Set control register */ + reg = regSPIF_ctrl->st.dw.kdrv_spif_cr;//u32Lib_LeRead32(SPI020REG_CONTROL); // 0x80 + reg &= ~(SPI020_CLK_MODE | SPI020_CLK_DIVIDER); + + //input clock + while(1) + { + err_msg("SPI speed (5)50Mhz, (2)25MHz, (1)100MHz: "); + Ch = kmdw_console_getc(); + err_msg("%c", Ch); + if(Ch == '5') + { + reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_4; // System:200MHz, DIV_4:50MHz + strcpy(s, " 50MHz_"); + break; + } + else if(Ch == '2') + { + reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_8; // System:200MHz, DIV_8:25MHz + strcpy(s, " 25MHz_"); + break; + } + else if(Ch == '1') + { + reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_2; // System:200MHz, DIV_2:100MHz + strcpy(s, "100MHz_"); + break; + } + + err_msg("\r"); + } + regSPIF_ctrl->st.dw.kdrv_spif_cr = reg;//vLib_LeWrite32(SPI020REG_CONTROL, reg); + kdev_flash_4Bytes_ctrl(1); + err_msg("\r\n"); + + //input CLK driving + while(1) + { + err_msg("CLK pin driving (0)4mA, (1)8mA, (2)12mA, (3)16mA: "); + Ch = kmdw_console_getc(); + err_msg("%c", Ch); + if((Ch == '0') || (Ch == '1') || (Ch == '2') || (Ch == '3')) + { + uint32_t addr=0xC2380104; //SPI_CLK IO control Register + reg = inw(addr); + reg &= ~0x000000C0; //clear bit6, bit7 + reg |= ((Ch - 0x30)<<6); //select driving strength + outw(addr, reg); + + switch(Ch) + { + case '0': strcpy(&s[7], "CLK04mA_"); + break; + case '1': strcpy(&s[7], "CLK08mA_"); + break; + case '2': strcpy(&s[7], "CLK12mA_"); + break; + case '3': strcpy(&s[7], "CLK16mA_"); + break; + } + + break; + } + err_msg("\r"); + } + err_msg("\r\n"); + + //input DAT driving + while(1) + { + err_msg("DATA pin driving (0)4mA, (1)8mA, (2)12mA, (3)16mA: "); + Ch = kmdw_console_getc(); + err_msg("%c", Ch); + if((Ch == '0') || (Ch == '1') || (Ch == '2') || (Ch == '3')) + { + for(uint32_t addr=0xC2380108; addr<=0xC2380114; addr+=4) + { + reg = inw(addr); //SPI IO control + reg &= ~0x000000C0; //clear bit6, bit7 + reg |= ((Ch - 0x30)<<6); //select driving strength + outw(addr, reg); + } + + switch(Ch) + { + case '0': strcpy(&s[15], "DAT04mA_"); + break; + case '1': strcpy(&s[15], "DAT08mA_"); + break; + case '2': strcpy(&s[15], "DAT12mA_"); + break; + case '3': strcpy(&s[15], "DAT16mA_"); + break; + } + + break; + } + err_msg("\r"); + } + err_msg("\r\n"); + + //input single/quad mode + while(1) + { +//sun1009 err_msg("(i)quad io mode, (o)quad output, (s)single mode: "); + err_msg("(1)quad io mode, (2)quad output, (3)single mode, (4)single block erase: "); + + Ch = kmdw_console_getc(); + err_msg("%c", Ch); + block_erase = 0; + if(Ch == '1') + { + Qmode = 0xEC; + strcpy(&s[23], "quadio"); + break; + } + else if(Ch == '2') + { + Qmode = 0x6C; + strcpy(&s[23], "quad-o"); + break; + } + else if(Ch == '3') + { + Qmode = 0x13; + strcpy(&s[23], "single"); + break; + } + else if(Ch == '4') + { + Qmode = 0x13; + block_erase = 0xDC; + strcpy(&s[23], "single"); + break; + } + err_msg("\r"); + } + err_msg("\r\n"); + + //Flash Output Driver Strength + manufacturer_ID = flash_info.manufacturer; + while(1) + { + size = flash_info.flash_size; + if(manufacturer_ID==FLASH_MXIC_DEV) + { + err_msg("Flash Output Driver Strength(1)30 Ohms, (2)45 Ohms, (3)90 Ohms, (4)15 Ohms :"); + } + else + { + err_msg("Flash Output Driver Strength(1)100%%, (2)75%%, (3)50%%, (4)25%% :"); + } + + Ch = kmdw_console_getc(); + err_msg("%c\n", Ch); + flash_op_driving = Ch - '0'; + //err_msg("%d\n", flash_op_driving); + if( flash_op_driving > 0 && flash_op_driving <= 4 ) + { + strcpy(&s[29], " flash_op_dr"); + s[41] = Ch; + + err_msg("kdev_flash_write_control done\n"); + err_msg("SPI020_05_CMD %4X %4X %4X %4X\n",SPI020_05_CMD0_w , SPI020_05_CMD1_w, SPI020_05_CMD2_w, SPI020_05_CMD3_w); + kdrv_spif_set_commands( SPI020_05_CMD0_w , SPI020_05_CMD1_w, SPI020_05_CMD2_w, SPI020_05_CMD3_w ); + kdrv_spif_read_data( &RDSR1, 0x01 ); + err_msg("SPI020_05_CMD1 buf[0]=0x%2X\n", RDSR1 ); + kdrv_spif_wait_command_complete(); + + kdrv_spif_set_commands(SPI020_15_CMD0, SPI020_15_CMD1, SPI020_15_CMD2, SPI020_15_CMD3 ); + kdrv_spif_read_data( &RDCR, 0x01 ); + err_msg("SPI020_15_CMD1 buf[1]=0x%2X\n", RDCR ); + kdrv_spif_wait_command_complete(); + + kdev_flash_write_control(1); + err_msg("manufacturer_ID 0x%2X\n",manufacturer_ID); + switch(manufacturer_ID) + { + case FLASH_ZBIT_DEV: + case FLASH_WB_DEV: + case FLASH_GD_DEV: + if( (RDCR & BIT2) ) + { + err_msg("WPS is enabled!!\n", RDCR ); + } + //enable volatile bit + kdrv_spif_set_commands(SPI020_50_CMD0, SPI020_50_CMD1, SPI020_50_CMD2, SPI020_50_CMD3); + kdrv_spif_wait_command_complete(); + err_msg("SPI020_50_CMD0 done\n"); +#if 1 + err_msg("original driving strength (%d) \n", ((RDCR&0x60)>>5)+1 ); + err_msg("RDCR (0x%4X) \n", RDCR ); + RDCR &= ~0x60; + err_msg("RDCR&~0x60 (0x%4X) \n", RDCR ); + RDCR |= (flash_op_driving-1) << 5; + err_msg("RDCR|flash_op_driving (0x%4X) \n", RDCR ); + err_msg("New driving strength (%d) \n", ((RDCR&0x60)>>5)+1 ); + kdrv_spif_set_commands(SPI020_11_CMD0, SPI020_11_CMD1, SPI020_11_CMD2, SPI020_11_CMD3 ); + kdrv_spif_write_data((uint8_t*)(&RDCR), 1); + kdrv_spif_wait_command_complete();//spi020_check_status_til_ready(); +#else + err_msg("original driving strength (%d) \n", ((RDCR&0x60)>>5)+1 ); + err_msg("RDCR (0x%4X) \n", RDCR ); + RDCR &= ~0x60; + err_msg("RDCR&~0x60 (0x%4X) \n", RDCR ); + RDCR |= (flash_op_driving-1) << 5; + err_msg("RDCR|flash_op_driving (0x%4X) \n", RDCR ); + err_msg("New driving strength (%d) \n", ((RDCR&0x60)>>5)+1 ); + kdrv_spif_set_commands(((uint8_t)RDCR), 0x01000001, 0, SPI020_11_CMD3 ); + //kdrv_spif_write_data((uint8_t*)&RDCR, 1); + kdrv_spif_wait_command_complete();//spi020_check_status_til_ready(); +#endif + //Qmode + if(( Qmode == 0xEC )||( Qmode == 0x6C )) + { + err_msg("FLASH_WB/GD/ZBIT QE need to enable!! \n"); + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3 ); + kdrv_spif_read_data( &RDSR2, 0x01 ); + err_msg("SPI020_35_CMD1 buf[1]=0x%2X\n", RDSR2 ); + kdrv_spif_wait_command_complete(); + + if(!(RDSR2 & BIT1)) + { + RDSR2 |= BIT1; + kdrv_spif_set_commands(SPI020_31_CMD0, SPI020_31_CMD1, SPI020_31_CMD2, SPI020_31_CMD3 ); + kdrv_spif_write_data((uint8_t*)(&RDSR2), 1); + kdrv_spif_wait_command_complete();//spi020_check_status_til_ready(); + err_msg("FLASH_WB/GD/ZBIT Set QE OK!! \n"); + + err_msg("read FLASH_WB/GD/ZBIT status-2!! \n"); + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3 ); + kdrv_spif_read_data( &RDSR2, 0x01 ); + err_msg("SPI020_35_CMD1 buf[1]=0x%2X\n", RDSR2 ); + kdrv_spif_wait_command_complete(); + } + } + break; + case FLASH_MXIC_DEV: + kdev_flash_write_control(1); + err_msg("original driving strength (%d) \n", (RDCR&0x03)+1 ); + RDCR &= ~0x07; + if(size == 0x10000) + { + switch(flash_op_driving) + { + case 1: + RDCR |= 7; + break; + case 2: + RDCR |= 3; + break; + case 3: + RDCR |= 1; + break; + case 4: + RDCR |= 6; + break; + } + } + else + { + RDCR |= (flash_op_driving-1); + } + //Qmode + if(( Qmode == 0xEC )||( Qmode == 0x6C )) + { + err_msg("FLASH_MXIC_DEV QE enabled \n"); + RDSR1 |= BIT6; //QE enabled + } + else + { + err_msg("FLASH_MXIC_DEV QE disabled \n"); + RDSR1 &= ~BIT6; //QE disabled + } + buf[0] = (uint8_t)RDSR1; + buf[1] = (uint8_t)RDCR; + err_msg("New driving strength (%d) \n", (RDCR&0x03)+1 ); + err_msg("New driving strength (%4X %4X) \n", buf[0], buf[1] ); + + kdrv_spif_set_commands(SPI020_01_CMD0, SPI020_01_CMD1, SPI020_01_CMD2, SPI020_01_CMD3 ); + kdrv_spif_write_data(buf, 2); + err_msg("spi020_check_status_til_ready\n"); + kdrv_spif_wait_command_complete();//spi020_check_status_til_ready(); + break; + default: + err_msg("CAN'T support driving strength change!!"); + break; + } + kdrv_spif_set_commands(SPI020_15_CMD0, SPI020_15_CMD1, SPI020_15_CMD2, SPI020_15_CMD3 ); + kdrv_spif_read_data( &RDCR, 0x01 ); + err_msg("SPI020_15_CMD1 buf[0]=0x%2X\n", RDCR ); + kdrv_spif_wait_command_complete(); + + break; + } + } + s[42] = '\0'; + err_msg("%s\r\n",s); + kdev_flash_write_control(0); + mytime.hour = 0; + mytime.min = 0; + mytime.sec = 0; + rtc_init(&mytime, NULL); + err = 0; + k=0; + char buff[5]; + int while_count=100; + if(block_erase) + goto block_erase_test; + + while(1) + { + err_msg("How many time you would like to test? enter the number 0..10000(0 means endless) :"); + kmdw_console_echo_gets(buff, sizeof(buff)); + //err_msg("%s\n", buff); + while_count = atoi(buff); + //err_msg("%d\n", while_count); + if((while_count>=0)&&(while_count<=10000)) + break; + else + err_msg("%d is out of range!\n", while_count); + } + while_count += 1; + while(while_count) + { + memset((void*)DDR2_DST, 0x99, LENGTH); + _kdp_memxfer_flash_to_ddr(DDR2_DST, FLASH_SRC, LENGTH, Qmode); + for(m=0;m1) + { + while_count --; + if(while_count == 1) + break; + } + } + goto exit; +block_erase_test: + while(1) + { + err_msg("\nWhich block do you would want to do block erase test? enter the number 0..507 :\n"); + kmdw_console_echo_gets(buff, sizeof(buff)); + //err_msg("%s\n", buff); + while_count = atoi(buff); + if((while_count<0)||(while_count>507)) + { + err_msg("Block number is out of range, please enter again!!\n"); + } + else + { + err_msg("Test Block %d ~ %d !\n", while_count,while_count+3); + break; + } + } + + for(k=0; k<5; k++) + { + block = while_count+k; + block_addr = block*0x10000; + st_tick = kdrv_current_t1_tick(); + err_msg("\nblock_erase_test is erasing block%d, address=0x%X....",block, block_addr); + kdev_flash_64kErase(block_addr); + sp_tick = kdrv_current_t1_tick(); + err_msg("\ntotal time for erasing block%d is: %d....", block, sp_tick - st_tick); + } + err_msg("\nblock_erase_test is done....\n"); +exit: + err_msg("Press 'RESET' to leave or run the test again!!\n"); + kdev_flash_4Bytes_ctrl(0); + + //reset chip + kdrv_spif_set_commands( SPI020_66_CMD0 , SPI020_66_CMD1, SPI020_66_CMD2, SPI020_66_CMD3 ); + kdrv_spif_wait_command_complete(); + kdrv_spif_set_commands( SPI020_99_CMD0 , SPI020_99_CMD1, SPI020_99_CMD2, SPI020_99_CMD3 ); + kdrv_spif_wait_command_complete(); +} + + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kdrv_uart_initialize(); // for log printing + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // enable console mdw for printing + kdrv_pwmtimer_initialize(PWMTIMER1, PWMTMR_01MSEC_PERIOD); + + mySPItest(); + + while(1); +} + + diff --git a/build/example_kdrv/spi_flash/sn52096/project.h b/build/example_kdrv/spi_flash/sn52096/project.h new file mode 100644 index 0000000..447a48a --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/spi_flash/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/spi_flash/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/spi_flash/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/spi_flash/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..fe047be --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,405 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_flash_main.c + ex_flash_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\flash\kmdw_memxfer.c + kmdw_memxfer.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\rtc.c + rtc.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_spif.c + kdrv_spif.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + kdrv_pinmux.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + + + device_flash + 0 + 0 + 0 + 0 + + 4 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\dev\flash\kdev_flash_winbond.c + kdev_flash_winbond.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/spi_flash/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/spi_flash/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..fb6e75d --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,663 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\;..\..\..\..\..\platform\dev\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + project.h + 5 + ..\project.h + + + ex_flash_main.c + 1 + ..\..\main_scpu\ex_flash_main.c + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_memxfer.c + 1 + ..\..\..\..\..\mdw\flash\kmdw_memxfer.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + rtc.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\rtc.c + + + kdrv_spif.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_spif.c + + + kdrv_pinmux.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_ddr.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + + + device_flash + + + kdev_flash_winbond.c + 1 + ..\..\..\..\..\platform\dev\flash\kdev_flash_winbond.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/spi_flash/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/spi_flash/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/spi_flash/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/ssp_spi_master/main_scpu/ex_ssp_spi_master.c b/build/example_kdrv/ssp_spi_master/main_scpu/ex_ssp_spi_master.c new file mode 100644 index 0000000..3b41400 --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/main_scpu/ex_ssp_spi_master.c @@ -0,0 +1,263 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include +#include + + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" + +#include "kdrv_uart.h" +#include "kdrv_gpio.h" +#include "kdrv_system.h" +#include "rtc.h" +#include "io.h" +#include "kdrv_pwm.h" +#include "kdrv_ddr.h" +#include "kdrv_pinmux.h" +#include "kdrv_ssp.h" +#include "kdrv_pinmux.h" +#include "kdrv_clock.h" + +#include "kmdw_console.h" + +#define DDR1_DST 0x60000000 +#define FLASH_SRC 0x00 +#define LENGTH (1024*1024*5) +#define DDR2_DST (DDR1_DST+LENGTH) + +#undef err_msg +#define err_msg kmdw_printf +#define _get_min(x,y) ( x < y ? x: y ) + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; +extern struct st_ssp_spi driver_ssp_ctx; +#if(SSP_SPI_MASTER_DEV==COM_BUS_TYPE_SSP1 || SSP_SPI_MASTER_DEV==COM_BUS_TYPE_SSP0) +extern struct st_ssp_spi driver_ssp_master_ctx; +#endif +//--- +uint8_t kmdw_ssp_api_spi_init(kdrv_ssp_spi_dev_id_t handle, enum e_spi edata) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, edata, NULL ) == e_spi_ret_init_done ){ + return 1; + } + return 0; +} + +uint8_t kmdw_ssp_api_spi_enable(kdrv_ssp_spi_dev_id_t handle, struct st_ssp_spi *stspi) +{ + if( kdrv_ssp_statemachine( handle, stspi, e_spi_enable, NULL ) == e_spi_ret_enable_done ){ + return 1; + } + return 0; +} + +uint8_t kmdw_ssp_api_spi_disable(kdrv_ssp_spi_dev_id_t handle, struct st_ssp_spi *stspi) +{ + if( kdrv_ssp_statemachine( handle, stspi, e_spi_disable, NULL ) == e_spi_ret_disableDone ){ + return 1; + } + return 0; +} + +uint8_t kmdw_ssp_api_spi_receive(kdrv_ssp_spi_dev_id_t handle, struct st_ssp_spi *stspi) +{ + if( kdrv_ssp_statemachine( handle, stspi, e_spi_rx, NULL ) == e_spi_ret_rxbusy ){ + return 0; //rx on-going + } + else{ + return 1; //rx done + } +} + +uint8_t kmdw_ssp_api_spi_receive_xor(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, e_spi_rx_check, NULL ) == e_spi_ret_rx_xor_OK ){ + return 1; //rx data correct + } + else{ + return 0; //rx data fail + } +} + +uint8_t kmdw_ssp_api_spi_transfer(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, e_spi_tx, NULL ) == e_spi_ret_txbusy ){ + return 1; //rx data correct + } + else{ + return 0; //rx data fail + } +} + +uint8_t kmdw_ssp_api_spi_transfer_checks(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, e_spi_tx_status_check, NULL ) == e_spi_ret_txbusy ) + { + return 0; + } + else + { + return 1; + } +} + +void kmdw_ssp_api_spi_write_tx_buff( uint8_t *src, uint16_t nlen ) +{ + kdrv_ssp_write_buff( &driver_ssp_ctx, src, nlen ); +} + +uint8_t kmdw_ssp_api_spi_tx_xor(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, e_spi_tx_xor, NULL ) == e_spi_ret_tx_xor_done ) + { + return 0; + } + else + { + return 1; + } +} + +/* This is a spi master tx/rx loopback test example + * regSSP0_ctrl(driver_ssp_ctx.port_no)->st.bf.kdrv_ssp_sspcr0.LBM to enable loopback mode +*/ +uint8_t nsize = 0; +uint8_t ssp_spi_master_test(void) +{ + #define tx_temp_size (16) + //uint16_t ncount = 0; + uint16_t i = 0; + uint8_t temp_buffer[tx_temp_size]; + uint16_t temp_buffer_index = 0; + + for( i=0; i< tx_temp_size; i++ ) + { + temp_buffer[i] = 0x90+i; + temp_buffer_index++; + } + + err_msg(" ssp_spi_master_test : Init\n"); + if( kmdw_ssp_api_spi_init(DEBUG_SPI_PORT, e_spi_init_master) != 1 ) + { + return 0; + } + kdrv_ssp_spi_loopback_test(0); //for loop back test + + err_msg(" ssp_spi_master_test : Start\n"); + while(1) + { + //control GPIO + kdrv_ssp_spi_CS_set(chip_select_pin, SPI_CS_LOW); + + kmdw_ssp_api_spi_write_tx_buff( temp_buffer, temp_buffer_index ); + kmdw_ssp_api_spi_transfer(DEBUG_SPI_PORT); + + //kdrv_delay_us( 30 ); + while(!kmdw_ssp_api_spi_transfer_checks(DEBUG_SPI_PORT)); + + //control GPIO + kdrv_ssp_spi_CS_set(chip_select_pin, SPI_CS_HI); + + nsize = kdrv_ssp_rxfifo_valid_entries( driver_ssp_ctx.port_no ); + if(nsize) + { + driver_ssp_ctx.Rx_buffer_index=0; + kdrv_ssp_rx_polling_receive_all(&driver_ssp_ctx); + uint32_t k = driver_ssp_ctx.Rx_buffer_index; + if(k == nsize) + { + //ssp_write_word(SSP_REG_BASE_S, &driver_ssp_ctx.Rx_buffer ,k); + kmdw_printf("\nrx data "); + for(uint32_t i=0; icritical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..ba1c3cb --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_ssp_spi_master.c + ex_ssp_spi_master.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + kdrv_pinmux.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ssp.c + kdrv_ssp.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + kdrv_gpio.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..00189a7 --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,648 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, TARGET_SCPU, LOG_ENABLE, KL520 + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + project.h + 5 + ..\project.h + + + ex_ssp_spi_master.c + 1 + ..\..\main_scpu\ex_ssp_spi_master.c + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_pinmux.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_ddr.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kmdw_memory.c + 1 + ..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + kdrv_ssp.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ssp.c + + + kdrv_gpio.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/ssp_spi_master/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/ssp_spi_slave/main_scpu/ex_ssp_spi_slave.c b/build/example_kdrv/ssp_spi_slave/main_scpu/ex_ssp_spi_slave.c new file mode 100644 index 0000000..ba0af27 --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/main_scpu/ex_ssp_spi_slave.c @@ -0,0 +1,267 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include +#include + + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "project.h" + +#include "kdrv_system.h" +#include "rtc.h" +#include "io.h" +#include "kdrv_uart.h" +#include "kdrv_gpio.h" +#include "kdrv_pwm.h" +#include "kdrv_ddr.h" +#include "kdrv_pinmux.h" +#include "kdrv_ssp.h" +#include "kdrv_pinmux.h" +#include "kdrv_clock.h" + +#include "kmdw_console.h" + + +#define DDR1_DST 0x60000000 +#define FLASH_SRC 0x00 +#define LENGTH (1024*1024*5) +#define DDR2_DST (DDR1_DST+LENGTH) + +#undef err_msg +#define err_msg kmdw_printf +#define _get_min(x,y) ( x < y ? x: y ) + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; +extern struct st_ssp_spi driver_ssp_ctx; +#if(SSP_SPI_MASTER_DEV==COM_BUS_TYPE_SSP1 || SSP_SPI_MASTER_DEV==COM_BUS_TYPE_SSP0) +extern struct st_ssp_spi driver_ssp_master_ctx; +#endif +static void kmdw_ssp_spi1_callback(uint32_t event); +//--- +uint8_t kmdw_ssp_api_spi_init(kdrv_ssp_spi_dev_id_t handle, enum e_spi edata) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, edata, kmdw_ssp_spi1_callback ) == e_spi_ret_init_done ){ + return 1; + } + return 0; +} + +uint8_t kmdw_ssp_api_spi_enable(kdrv_ssp_spi_dev_id_t handle, struct st_ssp_spi *stspi) +{ + if( kdrv_ssp_statemachine( handle, stspi, e_spi_enable, NULL ) == e_spi_ret_enable_done ){ + return 1; + } + return 0; +} + +uint8_t kmdw_ssp_api_spi_disable(kdrv_ssp_spi_dev_id_t handle, struct st_ssp_spi *stspi) +{ + if( kdrv_ssp_statemachine( handle, stspi, e_spi_disable, NULL ) == e_spi_ret_disableDone ){ + return 1; + } + return 0; +} + +uint8_t kmdw_ssp_api_spi_receive(kdrv_ssp_spi_dev_id_t handle, struct st_ssp_spi *stspi) +{ + if( kdrv_ssp_statemachine( handle, stspi, e_spi_rx, NULL ) == e_spi_ret_rxbusy ){ + return 0; //rx on-going + } + else{ + return 1; //rx done + } +} + +uint8_t kmdw_ssp_api_spi_receive_xor(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, e_spi_rx_check, NULL ) == e_spi_ret_rx_xor_OK ){ + return 1; //rx data correct + } + else{ + return 0; //rx data fail + } +} + +uint8_t kmdw_ssp_api_spi_transfer(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, e_spi_tx, NULL ) == e_spi_ret_txbusy ){ + return 1; //rx data correct + } + else{ + return 0; //rx data fail + } +} + +uint8_t kmdw_ssp_api_spi_transfer_checks(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_ctx, e_spi_tx_status_check, NULL ) == e_spi_ret_txbusy ) + { + return 0; + } + else + { + return 1; + } +} + +void kmdw_ssp_api_spi_write_tx_buff( uint8_t *src, uint16_t nlen ) +{ + kdrv_ssp_write_buff( &driver_ssp_ctx, src, nlen ); +} + +/* This is a spi master tx/rx loopback test example + * regSSP0_ctrl(driver_ssp_ctx.port_no)->st.bf.kdrv_ssp_sspcr0.LBM to enable loopback mode +*/ +uint8_t nsize = 0; +static void ssp_spi_slave_thread(void *argument) +{ + err_msg(" ssp_spi_slave_test : Init\n"); + if( kmdw_ssp_api_spi_init(DEBUG_SPI_PORT, e_spi_init_slave) != 1 ) + { + err_msg(" ssp_spi_slave_test : error!!\n"); + return; + } + regSSP0_ctrl(driver_ssp_ctx.port_no)->st.bf.kdrv_ssp_sspcr0.LBM=0; //please set to 0 if not test in loop back mode + kmdw_ssp_api_spi_init(DEBUG_SPI_PORT, e_spi_txrx_reinit); + kmdw_ssp_api_spi_enable(DEBUG_SPI_PORT, &driver_ssp_ctx); + + memset((void *)driver_ssp_ctx.Rx_buffer, 0x55, 300); + err_msg(" ssp_spi_slave_test : Start\n"); + driver_ssp_ctx.pre_size = 40; + while(1) + { + if(driver_ssp_ctx.interrupt_en == 0x00) + { + kdrv_ssp_rx_polling_receive_all(&driver_ssp_ctx); + /*nsize = driver_ssp_ctx.Rx_buffer_index; + if(nsize) + { + //ssp_write_word(SSP_REG_BASE_S, &driver_ssp_ctx.Rx_buffer ,k); + err_msg("\nrx data "); + for(int i=0; icritical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..e095bd7 --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_ssp_spi_slave.c + ex_ssp_spi_slave.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + kdrv_pinmux.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ssp.c + kdrv_ssp.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + kdrv_gpio.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..71963b7 --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,648 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, TARGET_SCPU, LOG_ENABLE, KL520 + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + project.h + 5 + ..\project.h + + + ex_ssp_spi_slave.c + 1 + ..\..\main_scpu\ex_ssp_spi_slave.c + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_pinmux.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_ddr.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kmdw_memory.c + 1 + ..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + kdrv_ssp.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ssp.c + + + kdrv_gpio.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/ssp_spi_slave/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/timer/main_scpu/ex_timer_main.c b/build/example_kdrv/timer/main_scpu/ex_timer_main.c new file mode 100644 index 0000000..77a902e --- /dev/null +++ b/build/example_kdrv/timer/main_scpu/ex_timer_main.c @@ -0,0 +1,162 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ +#include +#include +#include + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "kdrv_system.h" +//#include "kdrv_pinmux.h" +#include "kdrv_timer.h" +#include "kdrv_scu_ext.h" + +#define PINMUX_SD_DATA2_GPIO26 3 +#define PINMUX_SD_DATA3_GPIO27 3 + +uint32_t btest[10]; +uint32_t Ftest[5]; +uint32_t timerid; +osThreadId_t nonblocktid; +void test(cb_event_t argu, void* argu2) +{ + Ftest[2] = argu; + Ftest[3] = *(uint32_t*)argu2; + Ftest[4]++; +} +void test1(cb_event_t argu, void* argu2) +{ +} +void test2(cb_event_t argu, void* argu2) +{ +} +void test3(cb_event_t argu, void* argu2) +{ +} +void test4(cb_event_t argu, void* argu2) +{ +} +void test5(cb_event_t argu, void* argu2) +{ +} +void myTIMERtest5(void *argument) +{ + uint32_t timerid; + while(1){ + kdrv_timer_open(&timerid, NULL, NULL); + kdrv_timer_set(&timerid, 3190000, TIMER_START); + if( btest[0] < 0xFFFFFFF0) + btest[5]++; + } +} +void myTIMERtest4(void *argument) +{ + uint32_t timerid; + while(1){ + kdrv_timer_open(&timerid, NULL, NULL); + kdrv_timer_set(&timerid, 5000000, TIMER_START); + if( btest[0] < 0xFFFFFFF0) + btest[4]++; + } +} +void myTIMERtest3(void *argument) +{ + uint32_t timerid; + while(1){ + kdrv_timer_open(&timerid, NULL, NULL); + kdrv_timer_set(&timerid, 3000000, TIMER_START); + if( btest[0] < 0xFFFFFFF0) + btest[3]++; + } +} +void myTIMERtest2(void *argument) +{ + uint32_t timerid; + while(1){ + kdrv_timer_open(&timerid, NULL, NULL); + kdrv_timer_set(&timerid, 1000000, TIMER_START); + if( btest[0] < 0xFFFFFFF0) + btest[2]++; + } +} +extern uint32_t perftimerid; +void myTIMERtest1(void *argument) +{ + uint32_t Cnt; + masked_outw(GPIO_FTGPIO010_PA_BASE + 0x8/*REG_GPIO_PINOUT_OFFSET*/, (1 << 26), (1 << 26)); + masked_outw(GPIO_FTGPIO010_PA_BASE + 0x0/*REG_GPIO_DOUT_OFFSET*/, (1 << 26), (1 << 26)); + while(1) + { + kdrv_timer_delay_ms(10); + if( btest[0] < 0xFFFFFFF0) + btest[1]++; + if(Cnt++%2) + masked_outw(GPIO_FTGPIO010_PA_BASE + 0x0/*REG_GPIO_DOUT_OFFSET*/, (1 << 26), (1 << 26)); + else + masked_outw(GPIO_FTGPIO010_PA_BASE + 0x0/*REG_GPIO_DOUT_OFFSET*/, 0, (1 << 26)); + } +} +void myTIMERtest(void *argument) +{ + uint32_t Cnt; + uint32_t perftime, perftime2; + masked_outw(GPIO_FTGPIO010_PA_BASE + 0x8/*REG_GPIO_PINOUT_OFFSET*/, (1 << 27), (1 << 27)); + masked_outw(GPIO_FTGPIO010_PA_BASE + 0x0/*REG_GPIO_DOUT_OFFSET*/, (1 << 27), (1 << 27)); + while(1) + { + kdrv_timer_delay_us(1000); + kdrv_timer_perf_get_instant(&perftimerid, &perftime, &perftime2); + Ftest[0] = perftime; + Ftest[1] = perftime2; + if( btest[0] < 0xFFFFFFF0) + btest[0]++; + if(Cnt++%2) + masked_outw(GPIO_FTGPIO010_PA_BASE + 0x0/*REG_GPIO_DOUT_OFFSET*/, (1 << 27), (1 << 27)); + else + masked_outw(GPIO_FTGPIO010_PA_BASE + 0x0/*REG_GPIO_DOUT_OFFSET*/, 0, (1 << 27)); + } +} + +int main(void) +{ + kdrv_system_init(); + SystemCoreClockUpdate(); // System Initialization + + kdrv_timer_initialize(); + SET_MASKED_BITS(SCU_EXTREG_SD_DATA2_IOCTRL, PINMUX_SD_DATA2_GPIO26, 0, 2) + SET_MASKED_BITS(SCU_EXTREG_SD_DATA3_IOCTRL, PINMUX_SD_DATA3_GPIO27, 0, 2) + osKernelInitialize(); // Initialize CMSIS-RTOS + kdrv_timer_perf_measure_start(); + + + osThreadNew(myTIMERtest, NULL, NULL); + osThreadNew(myTIMERtest1, NULL, NULL); + //osThreadNew(myTIMERtest2, NULL, NULL); + //osThreadNew(myTIMERtest3, NULL, NULL); + //osThreadNew(myTIMERtest4, NULL, NULL); + + osKernelStart(); + + while(1) { + } +} + + diff --git a/build/example_kdrv/timer/sn52096/project.h b/build/example_kdrv/timer/sn52096/project.h new file mode 100644 index 0000000..dc5c56f --- /dev/null +++ b/build/example_kdrv/timer/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/timer/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/timer/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/timer/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/timer/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/timer/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/timer/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/timer/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/timer/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/timer/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/timer/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/timer/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/timer/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/timer/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/timer/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/timer/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/timer/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/timer/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..226639f --- /dev/null +++ b/build/example_kdrv/timer/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,313 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_timer_main.c + ex_timer_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_timer.c + kdrv_timer.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/timer/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/timer/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..a639b6b --- /dev/null +++ b/build/example_kdrv/timer/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,623 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + project.h + 5 + ..\project.h + + + ex_timer_main.c + 1 + ..\..\main_scpu\ex_timer_main.c + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_timer.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_timer.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/timer/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/timer/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/timer/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/uart_simple_console/main_scpu/ex_hw_main.c b/build/example_kdrv/uart_simple_console/main_scpu/ex_hw_main.c new file mode 100644 index 0000000..4c63440 --- /dev/null +++ b/build/example_kdrv/uart_simple_console/main_scpu/ex_hw_main.c @@ -0,0 +1,112 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include +#include +#include "kdrv_cmsis_core.h" +#include "project.h" + +#include "kdrv_system.h" +#include "kdrv_uart.h" + +#define MSG_SIZE 4096 + +uint8_t msg_rbuf[MSG_SIZE + 4]; +uint8_t msg_tbuf[MSG_SIZE + 4]; + +static kdrv_uart_handle_t handle0; +void kmdw_console_init(kdrv_uart_dev_id_t uart_dev, uint32_t baudrate) +{ + kdrv_status_t sts = kdrv_uart_open(&handle0, uart_dev, UART_MODE_SYNC_RX | UART_MODE_SYNC_TX, NULL); + if (sts != KDRV_STATUS_OK) + { + //err_msg("Open failed\n"); + return; + } + + kdrv_uart_config_t cfg; + cfg.baudrate = baudrate; + cfg.data_bits = 8; + cfg.frame_length = 0; + cfg.stop_bits = 1; + cfg.parity_mode = PARITY_NONE; + cfg.fifo_en = false; + + if(kdrv_uart_configure(handle0, UART_CTRL_CONFIG, (void *)&cfg)) + { + //err_msg("UART%d config failed\n",uart_dev); + } +} + +void myConsoleTest(void) +{ + char cmd; + char *str = (char *)msg_rbuf; + int8_t str_len=0; + + strcpy(str, "\nPlease enter command 1~5:"); + str_len = strlen(str); + kdrv_uart_write(UART0_DEV, (uint8_t *)str, str_len); + + kdrv_uart_get_char(UART0_DEV,(char *)&cmd); + switch(cmd) + { + case '1': + strcpy(str, "1\nHELLO WORLD!"); + break; + case '2': + strcpy(str, "2\nGOOD MORNING!"); + break; + case '3': + strcpy(str, "3\nGOOD AFTERNOON!"); + break; + case '4': + strcpy(str, "4\nGOOD NIGHT!"); + break; + case '5': + strcpy(str, "5\nGOOD BYE!"); + break; + } + str_len = strlen(str); + kdrv_uart_write(MSG_PORT, (uint8_t *)str, str_len); +} + + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + kdrv_system_init(); + kdrv_system_init_ncpu(); + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); + + while(1) + { + myConsoleTest(); + } +} + + diff --git a/build/example_kdrv/uart_simple_console/sn52096/project.h b/build/example_kdrv/uart_simple_console/sn52096/project.h new file mode 100644 index 0000000..dc5c56f --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..1009d02 --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,276 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_hw_main.c + ex_hw_main.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + + + ::CMSIS + 1 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..57c63d5 --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,591 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + helloworld + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10100000 + 0x2000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, NON_OS + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + project.h + 5 + ..\project.h + + + ex_hw_main.c + 1 + ..\..\main_scpu\ex_hw_main.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/uart_simple_console/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/usb/usbd_async/main_scpu/ex_usbd_main.c b/build/example_kdrv/usb/usbd_async/main_scpu/ex_usbd_main.c new file mode 100644 index 0000000..5e264fb --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/main_scpu/ex_usbd_main.c @@ -0,0 +1,68 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "cmsis_os2.h" + +#include "kdrv_cmsis_core.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" + +#include "kmdw_memory.h" +#include "kmdw_console.h" + + +extern void usbd_async_example_init(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); + + /* init the application */ + usbd_async_example_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/usb/usbd_async/main_scpu/usbd_async_example.c b/build/example_kdrv/usb/usbd_async/main_scpu/usbd_async_example.c new file mode 100644 index 0000000..c8ca885 --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/main_scpu/usbd_async_example.c @@ -0,0 +1,343 @@ +/* + * Kneron system library test main code + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include + +#include "cmsis_os2.h" + +#include "kdrv_usbd.h" +#include "kmdw_console.h" +#include "kmdw_memory.h" + +#define FLAG_FOR_USB_EVENT 0x100 + +#define ENP_BULK_OUT 0x01 // bulk-out endpoint +#define ENP_BULK_IN 0x82 // bulk-in endpoint +#define ENP_INTERRUPT_IN 0x83 // interrupt-in endpoint + +// endpoint 0x01, bulk-out +static kdrv_usbd_endpoint_descriptor_t endp_bulkOut_desc = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = ENP_BULK_OUT, + .bmAttributes = 0x02, // TransferType = Bulk + .wMaxPacketSize = 0x0200, // max 512 bytes + .bInterval = 0x00, // never NAKs +}; + +// endpoint 0x81, bulk-in +static kdrv_usbd_endpoint_descriptor_t endp_bulkIn_desc = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = ENP_BULK_IN, + .bmAttributes = 0x02, // TransferType = Bulk + .wMaxPacketSize = 0x0200, // max 512 bytes + .bInterval = 0x00, // never NAKs +}; + +// endpoint 0x82, interrupt-in +static kdrv_usbd_endpoint_descriptor_t endp_intIn_desc = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = ENP_INTERRUPT_IN, + .bmAttributes = 0x03, // TransferType = Interrupt + .wMaxPacketSize = 0x0400, // max 1024 bytes + .bInterval = 4, // interval = 100 * frame period (125us) = 12 ms +}; + +static kdrv_usbd_interface_descriptor_t intf_desc = + { + .bLength = 0x9, // 9 bytes + .bDescriptorType = 0x04, // Inteface Descriptor + .bInterfaceNumber = 0x0, // Interface Number + .bAlternateSetting = 0x0, + .bNumEndpoints = 3, // 3 endpoints + .bInterfaceClass = 0xFF, // Vendor specific + .bInterfaceSubClass = 0x0, + .bInterfaceProtocol = 0x0, + .iInterface = 0x0, // No String Descriptor + .endpoint[0] = &endp_bulkOut_desc, + .endpoint[1] = &endp_bulkIn_desc, + .endpoint[2] = &endp_intIn_desc, +}; + +static kdrv_usbd_config_descriptor_t confg_desc = + { + .bLength = 0x09, // 9 bytes + .bDescriptorType = 0x02, // Type: Configuration Descriptor + .wTotalLength = (9 + 9 + 3 * sizeof(kdrv_usbd_endpoint_descriptor_t)), // stotal bytes including config/interface/endpoint descriptors + .bNumInterfaces = 0x1, // Number of interfaces + .bConfigurationValue = 0x1, // Configuration number + .iConfiguration = 0x0, // No String Descriptor + .bmAttributes = 0xC0, // Self-powered, no Remote wakeup + .MaxPower = 0x0, // 0 syould be ok for self-powered device + .interface[0] = &intf_desc, +}; + +static kdrv_usbd_device_descriptor_t dev_desc = + { + .bLength = 0x12, // 18 bytes + .bDescriptorType = 0x01, // Type : Device Descriptor + .bcdUSB = 0x200, // USB 2.0 + .bDeviceClass = 0x00, // Device class, 0x0: defined by the interface descriptors + .bDeviceSubClass = 0x00, // Device sub-class + .bDeviceProtocol = 0x00, // Device protocol + .bMaxPacketSize0 = 0x40, // Max EP0 packet size: 64 bytes + .idVendor = 0x3231, // Vendor ID + .idProduct = 0x0100, // Product ID + .bcdDevice = 0x0001, // Device release number + .iManufacturer = 0x00, // Manufacture string index, FIXME + .iProduct = 0x00, // Product string index, FIXME + .iSerialNumber = 0x0, // Serial number string index + .bNumConfigurations = 1, // Number of configurations, FIXME + .config[0] = &confg_desc, // configuration descriptor +}; + +// Device Qualifier Descriptor, plz see USB 2.0 SPEC +static kdrv_usbd_device_qualifier_descriptor_t dev_qual_desc = + { + .bLength = 0xA, + .bDescriptorType = 0x06, + .bcdUSB = 0x200, + .bDeviceClass = 0x0, + .bDeviceSubClass = 0x0, + .bDeviceProtocol = 0x0, + .bMaxPacketSize0 = 0x40, + .bNumConfigurations = 0x1, + .bReserved = 0x0, +}; + +static uint32_t sendBytes; + +static void handle_vendor_cmd(kdrv_usbd_setup_packet_t setup_packet) +{ + kmdw_printf("setup packet: bmRequestType 0x%x bRequest 0x%x wValue 0x%x wIndex 0x%x wLength %d\n", + setup_packet.bmRequestType, setup_packet.bRequest, + setup_packet.wValue, setup_packet.wIndex, setup_packet.wLength); + + int isDirIn = setup_packet.bmRequestType & 0x80; + int isDirOut = !isDirIn; + + // handle only sepcific commands + if (isDirOut && + setup_packet.bRequest == 0x1 && + setup_packet.wValue == 0x2 && + setup_packet.wIndex == 0x3 && + setup_packet.wLength > 0) + { + kdrv_status_t status; + uint32_t data_size = setup_packet.wLength; + uint8_t *data = (uint8_t *)malloc(data_size); + + status = kdrv_usbd_control_receive(data, &data_size, 1000); + if (status == KDRV_STATUS_OK) + { + uint32_t sum = 0; + for (int i = 0; i < data_size; i++) + sum += data[i]; + + kmdw_printf("cx cmd is done, received %d bytes, sum = 0x%x, respond OK to host\n", data_size, sum); + + kdrv_usbd_control_respond(KDRV_USBD_RESPOND_OK); + } + else + { + kmdw_printf("kdrv_usbd_control_receive() failed, received %d bytes, err = %d\n", data_size, status); + kdrv_usbd_control_respond(KDRV_USBD_RESPOND_ERROR); + } + + free(data); + } + else if (isDirIn && + setup_packet.bRequest == 0x2 && + setup_packet.wValue == 0x4 && + setup_packet.wIndex == 0x6 && + setup_packet.wLength > 0) + { + kdrv_status_t status; + uint32_t data_size = setup_packet.wLength; + uint8_t *data = (uint8_t *)malloc(data_size); + + uint32_t sum = 0; + for (int i = 0; i < data_size; i++) + { + data[i] = rand() % 0x100; + sum += data[i]; + } + + kmdw_printf("cx transfer data %d bytes, sum = 0x%x to host\n", data_size, sum); + + status = kdrv_usbd_control_send(data, data_size, 1000); + if (status == KDRV_STATUS_OK) + { + kmdw_printf("cx cmd is done, sent %d bytes, respond OK to host\n", data_size); + kdrv_usbd_control_respond(KDRV_USBD_RESPOND_OK); + } + else + { + kmdw_printf("kdrv_usbd_control_receive() failed, err = %d\n", status); + kdrv_usbd_control_respond(KDRV_USBD_RESPOND_ERROR); + } + + free(data); + } + else + { + kmdw_printf("cx cmd is not supported\n"); + kdrv_usbd_control_respond(KDRV_USBD_RESPOND_ERROR); + } +} + +static void usbd_test_thread(void *argument) +{ + // use DDR for buffers + uint32_t buf_size = 4 * 1024 * 1024; // 4MB + uint32_t *buf_bout = (uint32_t *)kmdw_ddr_reserve(buf_size); + uint32_t *buf_bin = (uint32_t *)kmdw_ddr_reserve(buf_size); + + kdrv_status_t status; + + kdrv_usbd_set_enable(true); + + srand(rand()); + + while (1) + { + uint32_t flags = osThreadFlagsWait(FLAG_FOR_USB_EVENT, osFlagsWaitAny, osWaitForever); + + // receiving an usb event, and handle it if interested + kdrv_usbd_event_t uevent; + while (KDRV_STATUS_OK == kdrv_usbd_get_event(&uevent)) + { + switch (uevent.ename) + { + case KDRV_USBD_EVENT_BUS_RESET: + kmdw_printf("bus reset\n"); + break; + + case KDRV_USBD_EVENT_BUS_SUSPEND: + kmdw_printf("bus suspend\n"); + break; + + case KDRV_USBD_EVENT_BUS_RESUME: + kmdw_printf("bus resume\n"); + break; + + case KDRV_USBD_EVENT_SETUP_PACKET: + { + handle_vendor_cmd(uevent.setup); + break; + } + case KDRV_USBD_EVENT_DEV_CONFIGURED: + { + kmdw_printf("\n==========================================\n"); + kmdw_printf("device is enumerated & configured\n"); + + // prepare some data on this endpoint for bulk-in + + for (int i = 0; i < 1 * 1024 * 1024; i++) + ((uint8_t *)buf_bin)[i] = (uint8_t)(i & 0xff); + + sendBytes = 5; // at first queue some bytes into the bulk-in buffer + status = kdrv_usbd_bulk_send_async(ENP_BULK_IN, buf_bin, sendBytes); + if (status != KDRV_STATUS_OK) + kmdw_printf("kdrv_usbd_bulk_send_async() failed, error: %d\n", status); + + break; + } + + case KDRV_USBD_EVENT_TRANSFER_OUT: + { + uint32_t endpoint = uevent.data1; + + if (endpoint == ENP_BULK_OUT) + { + // just receive some bytes from host + status = kdrv_usbd_bulk_receive_async(endpoint, buf_bout, buf_size); + if (status != KDRV_STATUS_OK) + { + kmdw_printf("kdrv_usbd_bulk_receive_async() failed, error: %d\n", status); + return; + } + } + break; + } + + case KDRV_USBD_EVENT_TRANSFER_DONE: + { + uint32_t endpoint = uevent.data1; + static uint32_t txfer_size = 0; + + if (endpoint == ENP_BULK_OUT) + { + txfer_size = uevent.data2; + kmdw_printf("bulk-out transferred %d bytes\n", txfer_size); + } + else if (endpoint == ENP_BULK_IN) + { + sendBytes += 5; + if (sendBytes > 4 * 1024 * 1024) + sendBytes = 5; + + kmdw_printf("bulk-in sending %d bytes\n", sendBytes); + + status = kdrv_usbd_bulk_send_async(ENP_BULK_IN, buf_bin, sendBytes); + if (status != KDRV_STATUS_OK) + kmdw_printf("kdrv_usbd_bulk_send_async() failed, error: %d\n", status); + } + + break; + } + + case KDRV_USBD_EVENT_TRANSFER_TERMINATED: + { + uint32_t endpoint = uevent.data1; + kmdw_printf("warning : endpoint 0x%x is terminated\n", endpoint); + + if (endpoint == ENP_BULK_IN) + { + sendBytes = 5; // queue some bytes into the bulk-in buffer + status = kdrv_usbd_bulk_send_async(ENP_BULK_IN, buf_bin, sendBytes); + if (status != KDRV_STATUS_OK) + kmdw_printf("kdrv_usbd_bulk_send_async() failed, error: %d\n", status); + } + + break; + } + + default: + kmdw_printf("got an unhandled event %d\n", uevent.ename); + break; + } + } + } +} + +void usbd_async_example_init(void) +{ + kmdw_printf("Testing async USBD API\n"); + + // create threads and start to listen USB events + + osThreadId_t tid_bulk = osThreadNew(usbd_test_thread, NULL, NULL); + + kdrv_usbd_initialize(); + + kdrv_usbd_register_thread_notification(tid_bulk, FLAG_FOR_USB_EVENT); + + // set up with one configuration / one interface / two endpoints + kdrv_usbd_set_device_descriptor(KDRV_USBD_HIGH_SPEED, &dev_desc); + kdrv_usbd_set_device_qualifier_descriptor(KDRV_USBD_HIGH_SPEED, &dev_qual_desc); + + kmdw_printf("configure endpoint 0x%02x for bulk-out transfer\n", ENP_BULK_OUT); + kmdw_printf("configure endpoint 0x%02x for bulk-in transfer\n", ENP_BULK_IN); + kmdw_printf("configure endpoint 0x%02x for interrupt-in transfer\n", ENP_INTERRUPT_IN); +} diff --git a/build/example_kdrv/usb/usbd_async/readme.txt b/build/example_kdrv/usb/usbd_async/readme.txt new file mode 100644 index 0000000..7205b05 --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/readme.txt @@ -0,0 +1,4 @@ +This example code demonstrates how to use USBD driver API to create a USB device +including descriptors and endpoints setup and use of bulk transfer. + +please refer to usbd_example.c. \ No newline at end of file diff --git a/build/example_kdrv/usb/usbd_async/sn52096/project.h b/build/example_kdrv/usb/usbd_async/sn52096/project.h new file mode 100644 index 0000000..b307d79 --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/project.h @@ -0,0 +1,164 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..bffe29f --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..34e0430 --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,337 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\usbd_async_example.c + usbd_async_example.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_usbd_main.c + ex_usbd_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd.c + kdrv_usbd.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..1add97a --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,773 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + usbd_async_example.c + 1 + ..\..\main_scpu\usbd_async_example.c + + + ex_usbd_main.c + 1 + ..\..\main_scpu\ex_usbd_main.c + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_usbd.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd.c + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/usb/usbd_async/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/usb/usbd_sync/main_scpu/ex_usbd_main.c b/build/example_kdrv/usb/usbd_sync/main_scpu/ex_usbd_main.c new file mode 100644 index 0000000..75dd1bc --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/main_scpu/ex_usbd_main.c @@ -0,0 +1,68 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "cmsis_os2.h" + +#include "kdrv_cmsis_core.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" + +#include "kmdw_memory.h" +#include "kmdw_console.h" + + +extern void usbd_sync_example_init(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); + + /* init the application */ + usbd_sync_example_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/usb/usbd_sync/main_scpu/usbd_sync_example.c b/build/example_kdrv/usb/usbd_sync/main_scpu/usbd_sync_example.c new file mode 100644 index 0000000..f9bd365 --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/main_scpu/usbd_sync_example.c @@ -0,0 +1,218 @@ +/* + * Kneron system library test main code + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include + +#include "cmsis_os2.h" + +#include "kdrv_usbd.h" +#include "kmdw_console.h" + +#define FLAG_FOR_USB_EVENT 0x100 + +#define ENP_BULK_OUT 0x01 // bulk-out endpoint +#define ENP_BULK_IN 0x81 // bulk-in endpoint +#define ENP_INTERRUPT_IN 0x82 // interrupt-in endpoint + +// endpoint 0x01, bulk-out +static kdrv_usbd_endpoint_descriptor_t endp_bulkOut_desc = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = ENP_BULK_OUT, + .bmAttributes = 0x02, // TransferType = Bulk + .wMaxPacketSize = 0x0200, // max 512 bytes + .bInterval = 0x00, // never NAKs +}; + +// endpoint 0x81, bulk-in +static kdrv_usbd_endpoint_descriptor_t endp_bulkIn_desc = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = ENP_BULK_IN, + .bmAttributes = 0x02, // TransferType = Bulk + .wMaxPacketSize = 0x0200, // max 512 bytes + .bInterval = 0x00, // never NAKs +}; + +// endpoint 0x82, interrupt-in +static kdrv_usbd_endpoint_descriptor_t endp_intIn_desc = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = ENP_INTERRUPT_IN, + .bmAttributes = 0x03, // TransferType = Interrupt + .wMaxPacketSize = 0x0400, // max 1024 bytes + .bInterval = 4, // interval = 100 * frame period (125us) = 12 ms +}; + +static kdrv_usbd_interface_descriptor_t intf_desc = + { + .bLength = 0x9, // 9 bytes + .bDescriptorType = 0x04, // Inteface Descriptor + .bInterfaceNumber = 0x0, // Interface Number + .bAlternateSetting = 0x0, + .bNumEndpoints = 3, // 3 endpoints + .bInterfaceClass = 0xFF, // Vendor specific + .bInterfaceSubClass = 0x0, + .bInterfaceProtocol = 0x0, + .iInterface = 0x0, // No String Descriptor + .endpoint[0] = &endp_bulkOut_desc, + .endpoint[1] = &endp_bulkIn_desc, + .endpoint[2] = &endp_intIn_desc, +}; + +static kdrv_usbd_config_descriptor_t confg_desc = + { + .bLength = 0x09, // 9 bytes + .bDescriptorType = 0x02, // Type: Configuration Descriptor + .wTotalLength = (9 + 9 + 3 * sizeof(kdrv_usbd_endpoint_descriptor_t)), // stotal bytes including config/interface/endpoint descriptors + .bNumInterfaces = 0x1, // Number of interfaces + .bConfigurationValue = 0x1, // Configuration number + .iConfiguration = 0x0, // No String Descriptor + .bmAttributes = 0xC0, // Self-powered, no Remote wakeup + .MaxPower = 0x0, // 0 syould be ok for self-powered device + .interface[0] = &intf_desc, +}; + +static kdrv_usbd_device_descriptor_t dev_desc = + { + .bLength = 0x12, // 18 bytes + .bDescriptorType = 0x01, // Type : Device Descriptor + .bcdUSB = 0x200, // USB 2.0 + .bDeviceClass = 0x00, // Device class, 0x0: defined by the interface descriptors + .bDeviceSubClass = 0x00, // Device sub-class + .bDeviceProtocol = 0x00, // Device protocol + .bMaxPacketSize0 = 0x40, // Max EP0 packet size: 64 bytes + .idVendor = 0x0D7D, // Vendor ID + .idProduct = 0x0100, // Product ID + .bcdDevice = 0x0001, // Device release number + .iManufacturer = 0x00, // Manufacture string index, FIXME + .iProduct = 0x00, // Product string index, FIXME + .iSerialNumber = 0x0, // Serial number string index + .bNumConfigurations = 1, // Number of configurations, FIXME + .config[0] = &confg_desc, // configuration descriptor +}; + +// Device Qualifier Descriptor, plz see USB 2.0 SPEC +static kdrv_usbd_device_qualifier_descriptor_t dev_qual_desc = +{ + .bLength = 0xA, + .bDescriptorType = 0x06, + .bcdUSB = 0x200, + .bDeviceClass = 0x0, + .bDeviceSubClass = 0x0, + .bDeviceProtocol = 0x0, + .bMaxPacketSize0 = 0x40, + .bNumConfigurations = 0x1, + .bReserved = 0x0, +}; + +static void bulk_out_thread(void *argument) +{ + // use DDR for buffers + uint32_t *buf = (uint32_t *)0x61000000; + uint32_t blen = 1 * 1024 * 1024; + kdrv_status_t status; + + kdrv_usbd_set_enable(true); + + kmdw_printf("waiting for device being configured\n"); + + while (!kdrv_usbd_is_dev_configured()) + osDelay(500); + + kmdw_printf("device is enumerated & configured\n"); + + while (1) + { + uint32_t txLen = blen; + status = kdrv_usbd_bulk_receive(ENP_BULK_OUT, buf, &txLen, 0); + if (status == KDRV_STATUS_OK) + { + kmdw_printf("endpoint 0x%x received %d bytes\n", ENP_BULK_OUT, txLen); + } + else + { + kmdw_printf("kdrv_usbd_bulk_receive(enp:0x%x) failed, error: %d\n", ENP_BULK_OUT, status); + } + } +} + +static void bulk_in_thread(void *argument) +{ + // use DDR for buffers + uint32_t *buf = (uint32_t *)(0x61000000 + 1 * 1024 * 1024); + //uint32_t blen = 1 * 1024 * 1024; + kdrv_status_t status; + + while (!kdrv_usbd_is_dev_configured()) + osDelay(500); + + osDelay(500); + + uint32_t sendBytes = 256; + + while (1) + { + status = kdrv_usbd_bulk_send(ENP_BULK_IN, buf, sendBytes, 0); + if (status == KDRV_STATUS_OK) + { + kmdw_printf("endpoint 0x%x sent %d bytes\n", ENP_BULK_IN, sendBytes); + } + else + { + kmdw_printf("kdrv_usbd_bulk_send(enp:0x%x) failed, error: %d\n", ENP_BULK_IN, status); + } + + if (sendBytes == 1 * 1024 * 1024) + sendBytes = 256; + else + sendBytes += (1 + (rand() % 2048)); + + if (sendBytes > 1 * 1024 * 1024) + sendBytes = 1 * 1024 * 1024; + } +} + +// this thread send some data to the host via interrupt-in transfer per 2 sec +static void interrupt_in_thread(void *argument) +{ + while (!kdrv_usbd_is_dev_configured()) + osDelay(500); + + uint32_t count = 0; + while (1) + { + kdrv_usbd_interrupt_send(ENP_INTERRUPT_IN, &count, sizeof(count), 100); + osDelay(2000); + ++count; + } +} + +void usbd_sync_example_init(void) +{ + kmdw_printf("==== Start to test USBD driver API ====\n"); + + // create threads to handle usb transfers + + osThreadNew(bulk_out_thread, NULL, NULL); + osThreadNew(bulk_in_thread, NULL, NULL); + osThreadNew(interrupt_in_thread, NULL, NULL); + + kdrv_usbd_initialize(); + + // set up with one configuration / one interface / two endpoints + kdrv_usbd_set_device_descriptor(KDRV_USBD_HIGH_SPEED, &dev_desc); + kdrv_usbd_set_device_qualifier_descriptor(KDRV_USBD_HIGH_SPEED, &dev_qual_desc); + + kmdw_printf("configure endpoint 0x%02x for bulk-out test\n", ENP_BULK_OUT); + kmdw_printf("configure endpoint 0x%02x for bulk-in test\n", ENP_BULK_IN); + kmdw_printf("configure endpoint 0x%02x for interrupt-in test\n", ENP_INTERRUPT_IN); +} diff --git a/build/example_kdrv/usb/usbd_sync/readme.txt b/build/example_kdrv/usb/usbd_sync/readme.txt new file mode 100644 index 0000000..7205b05 --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/readme.txt @@ -0,0 +1,4 @@ +This example code demonstrates how to use USBD driver API to create a USB device +including descriptors and endpoints setup and use of bulk transfer. + +please refer to usbd_example.c. \ No newline at end of file diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/project.h b/build/example_kdrv/usb/usbd_sync/sn52096/project.h new file mode 100644 index 0000000..82e157e --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..bffe29f --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..4d8beae --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,337 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\usbd_sync_example.c + usbd_sync_example.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_usbd_main.c + ex_usbd_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd.c + kdrv_usbd.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..1f97721 --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,775 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + usbd_sync_example.c + 1 + ..\..\main_scpu\usbd_sync_example.c + + + ex_usbd_main.c + 1 + ..\..\main_scpu\ex_usbd_main.c + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_usbd.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd.c + + + + + ::CMSIS + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + ::Device + + + 0 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/usb/usbd_sync/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/main_scpu/ex_usbh_cmsis_main.c b/build/example_kdrv/usb/usbh_cmsis_custom/main_scpu/ex_usbh_cmsis_main.c new file mode 100644 index 0000000..7b06c9e --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/main_scpu/ex_usbh_cmsis_main.c @@ -0,0 +1,67 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +#include "kdrv_cmsis_core.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" + +#include "kmdw_memory.h" //for ddr_malloc +#include "kmdw_console.h" + +extern void usbh_cmsis_example_init(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); // for memory alloc from ddr + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); + + /* init the application */ + usbh_cmsis_example_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/main_scpu/usbh_cmsis_custom.c b/build/example_kdrv/usb/usbh_cmsis_custom/main_scpu/usbh_cmsis_custom.c new file mode 100644 index 0000000..7f123be --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/main_scpu/usbh_cmsis_custom.c @@ -0,0 +1,209 @@ + +#include +#include "cmsis_os2.h" // CMSIS RTOS header file + +#include "rl_usb.h" // Keil.MDK-Pro::USB:CORE + +// Interface class, subclass and protocol of the device that is supported +#define CUSTOM_CLASS_IF_CLASS USB_DEVICE_CLASS_VENDOR_SPECIFIC +#define CUSTOM_CLASS_IF_SUBCLASS 0 +#define CUSTOM_CLASS_IF_PROTOCOL 0 + +static osThreadId_t usbh_app_thread; +static USBH_PIPE_HANDLE bulkout_pipe, bulkin_pipe, intin_pipe; + +extern void kmdw_printf(const char *f, ...); +extern uint32_t kmdw_ddr_reserve(uint32_t numbyte); + +/*---------------------------------------------------------------------------- +* Thread for usb host examples +*---------------------------------------------------------------------------*/ + +void usbh_cmsis_custom_thread(void *argument); // thread function + +void usbh_cmsis_example_init(void) +{ + usbh_app_thread = osThreadNew(usbh_cmsis_custom_thread, NULL, NULL); +} + +void usbh_cmsis_custom_thread(void *argument) +{ + usbStatus usb_status; // USB status + + uint8_t *bfptr = (uint8_t *)kmdw_ddr_reserve(4 * 1024 * 1024); + + kmdw_printf("bfptr = 0x%p\n"); + + // init USB host through MDK middleware + usb_status = USBH_Initialize(0U); + if (usb_status != usbOK) + { + kmdw_printf("USBH_Initialize() failed\n"); + } + + kmdw_printf("USBH_Initialize() OK\n"); + + kmdw_printf("waiting for usb device enumeration\n"); + + // wait for device init done + osThreadFlagsWait(0x01U, osFlagsWaitAny, osWaitForever); + + int test_run = 100; + + // below test bulk-out + { + kmdw_printf("\n==== starting bulk-out test ====\n\n"); + + uint32_t total_send = 1024; + + for (int i = 0; i < test_run; i++) + { + total_send += (1 + (rand() % 4000)); + if (total_send > 1024 * 1024) // make it <= 1 MB + total_send = (1 + (rand() % (512 * 1024))); + + uint32_t wanted_bytes = total_send; + + kmdw_printf("... bulk-out transferred %d bytes\n", wanted_bytes); + + while (1) + { + uint32_t sendBytes = 16 * 1024; // set a max pipe send + + if (wanted_bytes < sendBytes) + sendBytes = wanted_bytes; + + // NOTE: for now sendBytes MAX = 20 KB due to host driver implementation + usbStatus sts = USBH_PipeSend(bulkout_pipe, bfptr, sendBytes); + if (sts != usbOK) + { + kmdw_printf("... bulk-out transferred %d bytes failed, sts = %d\n", sendBytes, sts); + goto Test_Failed; + } + + sendBytes = USBH_PipeSendGetResult(bulkout_pipe); + + wanted_bytes -= sendBytes; + + if (wanted_bytes == 0) + { + if ((sendBytes % 512) == 0) + { + // zero-length packet + //kmdw_printf("\nsending zero-length packet ~\n"); + usbStatus sts = USBH_PipeSend(bulkout_pipe, bfptr, 0); + if (sts != usbOK) + { + kmdw_printf("... bulk-out transferring ZLP failed, sts = %d\n", sts); + goto Test_Failed; + } + } + break; + } + } + } + kmdw_printf("\nbulk-out test done ~\n"); + } + + // below test bulk-in + { + kmdw_printf("\n==== starting bulk-in test ====\n\n"); + for (int i = 0; i < test_run; i++) + { + uint32_t total_recvd = 0; + + while (1) + { + uint32_t recvBytes = 16384; // however only 16KB for one transfer at maximum + + // NOTE: for now recvBytes MAX = 20 KB due to host driver implementation + usbStatus sts = USBH_PipeReceive(bulkin_pipe, bfptr, recvBytes); + if (sts != usbOK) + { + kmdw_printf("... bulk-in transfer failed, sts = %d\n", sts); + goto Test_Failed; + } + + recvBytes = USBH_PipeReceiveGetResult(bulkin_pipe); + + total_recvd += recvBytes; + + if (recvBytes == 0 || (recvBytes % 512) != 0) + break; + } + + kmdw_printf("... bulk-in transferred %d bytes\n", total_recvd); + } + kmdw_printf("\nbulk-in test done ~\n"); + } + + // below test interrupt-in + { + kmdw_printf("\n==== starting interrupt-in test ====\n\n"); + for (int i = 0; i < test_run; i++) + { + uint32_t data = 0; + usbStatus sts = USBH_PipeReceive(intin_pipe, (uint8_t *)&data, 4); + if (sts != usbOK) + { + kmdw_printf("... interrupt-in transfer failed, sts = %d\n", sts); + goto Test_Failed; + } + + kmdw_printf("... interrupt-in get data = 0x%x\n", data); + } + kmdw_printf("\ninterrupt-in test done ~\n"); + } + + kmdw_printf("\nAll tests on control/bulk/interrupt transfer are passed ~\n"); + return; + +Test_Failed: + + kmdw_printf("\nSome tests are failing !!\n"); +} + +/************************** Class Driver Functions ****************************/ + +uint8_t USBH_CustomClass_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc) +{ + + kmdw_printf("%s()\n", __FUNCTION__); + + if (ptr_dev_desc->idVendor != 0xD7D || ptr_dev_desc->idProduct != 0x100) + { + kmdw_printf("Cannot recognize the device!\n"); + return 255U; // value 255 : configuration failed + } + + //usb_device = device; + + kmdw_printf("device = %u\n", device); + + // we do the hard-code way to create endpoint pipes for code size reduction + bulkout_pipe = USBH_PipeCreate(device, 0x01, USB_ENDPOINT_TYPE_BULK, 512, 0); + bulkin_pipe = USBH_PipeCreate(device, 0x81, USB_ENDPOINT_TYPE_BULK, 512, 0); + intin_pipe = USBH_PipeCreate(device, 0x82, USB_ENDPOINT_TYPE_INTERRUPT, 1024, 4); + + return 0; +} + +usbStatus USBH_CustomClass_Initialize(uint8_t instance) +{ + // Add code for initializing device + + kmdw_printf("%s()\n", __FUNCTION__); + + osThreadFlagsSet(usbh_app_thread, 0x01U); + + return usbOK; +} + +usbStatus USBH_CustomClass_Uninitialize(uint8_t instance) +{ + // Add code for de-initializing device + + kmdw_printf("%s()\n", __FUNCTION__); + + return usbOK; +} diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/readme.txt b/build/example_kdrv/usb/usbh_cmsis_custom/readme.txt new file mode 100644 index 0000000..7205b05 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/readme.txt @@ -0,0 +1,4 @@ +This example code demonstrates how to use USBD driver API to create a USB device +including descriptors and endpoints setup and use of bulk transfer. + +please refer to usbd_example.c. \ No newline at end of file diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/project.h b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/project.h new file mode 100644 index 0000000..82e157e --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c new file mode 100644 index 0000000..50a1dd0 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c @@ -0,0 +1,142 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_Config_0.c + * Purpose: USB Host Configuration + * Rev.: V5.2.1 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Host 0 +// Connect to hardware via Driver_USBH# <0-255> +// Select driver control block for hardware interface. +#define USBH0_HC_NUM 0 + +// Controller Interface Settings + +// Controller Interface +// Selects the USB Host Controller Interface +// <0=> Custom <1=> OHCI <2=> EHCI +// Custom Controller Interface is used for any non-standard USB Host +// Controller. +#define USBH0_HC_IF 0 + +// Custom Host Controller Interface +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by Custom Controller +// in system simultaneously. +#define USBH0_HC_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_MEM_POOL_SIZE 512 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_MEM_POOL_ADDR 0x00000000 +// +// + +// Open Host Controller Interface (OHCI) +// Memory-mapped OHCI Host Controller registers base address +// This setting applies for OHCI Controller Interface. +#define USBH0_HC_OHCI_BASE_ADDRESS 0x5000C000 + +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_OHCI_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by OHCI Controller +// in system simultaneously. +// This setting affects memory allocated by OHCI controller. +#define USBH0_HC_OHCI_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_OHCI_MEM_POOL_SIZE 512 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_OHCI_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_OHCI_MEM_POOL_ADDR 0x00000000 +// +// + +// Enhanced Host Controller Interface (EHCI) +// Memory-mapped EHCI Host Controller registers base address +// These settings apply for EHCI Controller Interface. +#define USBH0_HC_EHCI_BASE_ADDRESS 0x40006100 + +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_EHCI_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by EHCI Controller +// in system simultaneously. +// This setting affects memory allocated by EHCI controller. +#define USBH0_HC_EHCI_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_EHCI_MEM_POOL_SIZE 4096 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_EHCI_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_EHCI_MEM_POOL_ADDR 0x00000000 +// +// +// + +// OS Resources Settings +// These settings are used to optimize usage of OS resources. +// Core Thread Stack Size <64-65536> +#define USBH0_CORE_THREAD_STACK_SIZE 1024 + +// Core Thread Priority +#define USBH0_CORE_THREAD_PRIORITY osPriorityAboveNormal + +// +// + + +#include "RTE_Components.h" + +#ifdef RTE_USB_Host_MSC +#include "USBH_Config_MSC.h" +#endif + +#ifdef RTE_USB_Host_HID +#include "USBH_Config_HID.h" +#endif + +#ifdef RTE_USB_Host_CDC +#include "USBH_Config_CDC.h" +#endif + +#ifdef RTE_USB_Host_CustomClass +#include "USBH_Config_CustomClass.h" +#endif + +#include "usbh_config.h" diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h new file mode 100644 index 0000000..9965741 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h @@ -0,0 +1,16 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_Config_CustomClass.h + * Purpose: USB Host Custom Class Configuration + * Rev.: V5.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Host: Custom Class +// Number of concurrent Custom Devices in system <0-15> +#define USBH_CUSTOM_CLASS_NUM 1 + +// diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_MSC.h b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_MSC.h new file mode 100644 index 0000000..68cb772 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_MSC.h @@ -0,0 +1,16 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_Config_MSC.h + * Purpose: USB Host Mass Storage Class (MSC) Configuration + * Rev.: V5.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Host: Mass Storage Class (MSC) +// Number of concurrent MSC Devices in system <0-15> +#define USBH_MSC_NUM 1 + +// diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h new file mode 100644 index 0000000..d63a133 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/_Target-SCPU/RTE_Components.h @@ -0,0 +1,32 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'Target-SCPU' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ +/* Keil.MDK-Pro::USB:CORE:Release:6.13.7 */ +#define RTE_USB_Core /* USB Core */ + #define RTE_USB_Core_Release /* USB Core Release Version */ +/* Keil.MDK-Pro::USB:Host:6.13.7 */ +#define RTE_USB_Host_0 /* USB Host 0 */ + +/* Keil.MDK-Pro::USB:Host:Custom Class:6.13.7 */ +#define RTE_USB_Host_CustomClass /* USB Host Custom Class */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..5e8de13 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,32 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ +/* Keil.MDK-Pro::USB:CORE:Release:6.13.7 */ +#define RTE_USB_Core /* USB Core */ + #define RTE_USB_Core_Release /* USB Core Release Version */ +/* Keil.MDK-Pro::USB:Host:6.13.7 */ +#define RTE_USB_Host_0 /* USB Host 0 */ + +/* Keil.MDK-Pro::USB:Host:Custom Class:6.13.7 */ +#define RTE_USB_Host_CustomClass /* USB Host Custom Class */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..15af3ac --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,427 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\vtor.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + d + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 1 + 0 + 0x62ec1762 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\Keil\MDK-Middleware\7.10.0\USB\USB.scvd + Keil.MDK-Middleware.7.10.0 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\usbh_cmsis_custom.c + usbh_cmsis_custom.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_usbh_cmsis_main.c + ex_usbh_cmsis_main.c + 0 + 0 + + + 1 + 3 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + kdrv_usbh.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::CMSIS Driver + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + + ::USB + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..f120181 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,678 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + usbh_cmsis_custom.c + 1 + ..\..\main_scpu\usbh_cmsis_custom.c + + + ex_usbh_cmsis_main.c + 1 + ..\..\main_scpu\ex_usbh_cmsis_main.c + + + project.h + 5 + ..\project.h + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_usbh.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Device + + + ::USB + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_custom/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/ex_usbh_cmsis_main.c b/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/ex_usbh_cmsis_main.c new file mode 100644 index 0000000..c40e69f --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/ex_usbh_cmsis_main.c @@ -0,0 +1,67 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "cmsis_os2.h" +#include "kdrv_cmsis_core.h" + +#include "kdrv_ddr.h" +#include "kdrv_system.h" +#include "kmdw_memory.h" +#include "kmdw_console.h" + + +extern void usbh_cmsis_example_init(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); // for memory alloc from ddr + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); + + /* init the application */ + usbh_cmsis_example_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_cmsis_msc.c b/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_cmsis_msc.c new file mode 100644 index 0000000..21b684a --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_cmsis_msc.c @@ -0,0 +1,85 @@ +#include "cmsis_os2.h" // CMSIS RTOS header file + +#include "rl_fs.h" // Keil.MDK-Pro::File System:CORE +#include "rl_usb.h" // Keil.MDK-Pro::USB:CORE + +#include "USBH_MSC.h" + +#include "kmdw_console.h" +#include "kmdw_memory.h" + +/*---------------------------------------------------------------------------- + * Thread for usb host examples + *---------------------------------------------------------------------------*/ + + + +osThreadId_t tid_Thread; // thread id + +void usbh_cmsis_user_thread(void *argument); // thread function + +void usbh_cmsis_example_init(void) +{ + osThreadNew(usbh_cmsis_user_thread, NULL, NULL); +} + +void usbh_cmsis_user_thread(void *argument) +{ + usbStatus usb_status; // USB status + int32_t msc_status; // MSC status + FILE *f; // Pointer to stream object + uint8_t con = 0U; // Connection status of MSC(s) + + uint8_t *bfptr = (uint8_t *)kmdw_ddr_reserve(4*1024*1024); + + // init USB host through MDK middleware + USBH_Initialize(0U); + if (usb_status != usbOK) + { + for (;;) + { + } // Handle USB Host 0 init failure + } + + for (;;) + { + msc_status = USBH_MSC_DriveGetMediaStatus("U0:"); // Get MSC device status + if (msc_status == USBH_MSC_OK) + { + if (con == 0U) + { // If stick was not connected previously + con = 1U; // Stick got connected + msc_status = USBH_MSC_DriveMount("U0:"); + if (msc_status != USBH_MSC_OK) + { + continue; // Handle U0: mount failure + } + f = fopen("test.txt", "wb"); // Open/create file for writing + if (f == NULL) + { + continue; // Handle file opening/creation failure + } + + size_t wsize = fwrite(bfptr, 1, 4*1024*1024, f); + + fclose(f); // Close file + + kmdw_printf("Write file done, wsize %u\n", wsize); + + msc_status = USBH_MSC_DriveUnmount("U0:"); + if (msc_status != USBH_MSC_OK) + { + continue; // Handle U0: dismount failure + } + } + } + else + { + if (con == 1U) + { // If stick was connected previously + con = 0U; // Stick got disconnected + } + } + osDelay(100U); + } +} diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_msc.c b/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_msc.c new file mode 100644 index 0000000..4bb9dca --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_msc.c @@ -0,0 +1,164 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host:MSC + * Copyright (c) 2004-2017 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_MSC.c + * Purpose: Functions to access USB storage device via USB Host + * Rev.: V6.4.2 + *----------------------------------------------------------------------------*/ +/* + * USBH_MSC.c is a code template for the application specific functionality of + * the USB Host MSC class. It implements the access to a USB storage device and + * allows file I/O via the File System component. + * + * USBH_MSC.h is the related header file. + * + * First to enable USB Host Controller (if not already enabled) call: + * USBH_Initialize (ctrl_num); + * + * To access files on a USB storage device use below code sample: + * int32_t media_status, media_status_previous = USBH_MSC_ERROR_DRIVE; + * for (;;) { + * media_status = USBH_MSC_DriveGetMediaStatus (drive_name); + * if ((media_status == USBH_MSC_OK) && + * (media_status_previous != USBH_MSC_OK)) { + * switch (USBH_MSC_DriveMount (drive_name)) { + * case USBH_MSC_OK: + * fopen (...); + * break; + * case USBH_MSC_ERROR_FORMAT: + * fformat (drive_name, "/FAT32"); + * fopen (...); + * break; + * case USBH_MSC_ERROR: + * // Mount error + * break; + * } + * } + * media_status_previous = media_status; + * osWait (1000); // polling interval for media status (1 second) + * } + * + * Now file I/O can be performed using fopen, fread, fwrite, fclose and other + * functions of the File System component + * + * When drive is not to be used any more call: + * USBH_MSC_DriveUnmount (drive_name); + * + * When USB Host Controller is not to be used any more call: + * USBH_Uninitialize (ctrl_num); + */ + +#include "RTE_Components.h" // Component selection +#include "USBH_MSC.h" // Access storage via USB Host + +#if (!defined (RTE_FileSystem_Drive_USB_0) && !defined (RTE_FileSystem_Drive_USB_1)) + #error "Project does not contain USB storage device support" +#endif + + +//! [usbh_msc_drive_getmediastatus] +/// \brief Get status of drive media (USB storage connected or not connected) +/// \param[in] drive_name USB storage drive name ("U0:", "U1:") +/// \return execution status +/// - USBH_MSC_OK = USB storage device connected and enumerated +/// - USBH_MSC_ERROR_DRIVE = USB storage device not connected or not enumerated +int32_t USBH_MSC_DriveGetMediaStatus (const char *drive_name) { + usbStatus ustatus; + uint8_t drive_num; + + drive_num = drive_name[1] - '0'; // get drive number from drive name + + ustatus = USBH_MSC_GetStatus (drive_num); + if (ustatus != usbOK) return USBH_MSC_ERROR_DRIVE; + + return USBH_MSC_OK; +} +//! [usbh_msc_drive_getmediastatus] + + +//! [usbh_msc_drive_mount] +/// \brief Mount drive and initialize USB storage device for file I/O access +/// \param[in] drive_name USB storage drive name ("U0:", "U1:") +/// \return execution status +/// - USBH_MSC_OK = USB drive mounted, file system ready +/// - USBH_MSC_ERROR = unspecified error +/// - USBH_MSC_ERROR_DRIVE = USB storage device not connected +/// - USBH_MSC_ERROR_FORMAT = USB drive mounted, but unformatted +int32_t USBH_MSC_DriveMount (const char *drive_name) { + fsStatus fstatus; + + fstatus = finit (drive_name); + if (fstatus != fsOK) return USBH_MSC_ERROR; + + fstatus = fmount (drive_name); + switch (fstatus) { + case fsOK: + break; + case fsNoFileSystem: + return USBH_MSC_ERROR_FORMAT; + case fsError: + case fsUnsupported: + case fsAccessDenied: + case fsInvalidParameter: + case fsInvalidDrive: + case fsInvalidPath: + case fsUninitializedDrive: + case fsDriverError: + case fsMediaError: + case fsNoMedia: + case fsNoFreeSpace: + case fsFileNotFound: + case fsDirNotEmpty: + case fsTooManyOpenFiles: + return USBH_MSC_ERROR; + } + + return USBH_MSC_OK; +} +//! [usbh_msc_drive_mount] + + +//! [usbh_msc_drive_unmount] +/// \brief Unmount drive and de-initialize USB storage device before eject +/// \param[in] drive_name USB storage drive name ("U0:", "U1:") +/// \return execution status +/// - USBH_MSC_OK = USB drive unmounted +/// - USBH_MSC_ERROR = unspecified error +int32_t USBH_MSC_DriveUnmount (const char *drive_name) { + fsStatus fstatus; + + fstatus = funmount (drive_name); + if (fstatus != fsOK) return USBH_MSC_ERROR; + + fstatus = funinit (drive_name); + if (fstatus != fsOK) return USBH_MSC_ERROR; + + return USBH_MSC_OK; +} +//! [usbh_msc_drive_unmount] + + +//! [usbh_msc_drive_getcapacity] +/// \brief Check the physical capacity of USB storage device +/// \param[in] drive_name USB storage drive name ("U0:", "U1:") +/// \return execution status +/// - value != 0 = size of USB storage device in bytes +/// - value == 0 = no drive connected or unspecified error +uint64_t USBH_MSC_DriveGetCapacity (const char *drive_name) { + usbStatus ustatus; + uint32_t block_count; + uint32_t block_size; + uint8_t drive_num; + + drive_num = drive_name[1] - '0'; // get drive number from drive name + + ustatus = USBH_MSC_GetStatus (drive_num); + if (ustatus != usbOK) return 0; + + ustatus = USBH_MSC_ReadCapacity (drive_num, &block_count, &block_size); + if (ustatus != usbOK) return 0; + + return (((uint64_t)block_count) * ((uint64_t)block_size)); +} +//! [usbh_msc_drive_getcapacity] diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_msc.h b/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_msc.h new file mode 100644 index 0000000..23e9401 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/main_scpu/usbh_msc.h @@ -0,0 +1,58 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host:MSC + * Copyright (c) 2004-2017 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_MSC.h + * Purpose: Functions to access USB storage device via USB Host + * Rev.: V6.2.0 + *----------------------------------------------------------------------------*/ + +#ifndef USBH_MSC_H +#define USBH_MSC_H + +#include "stdint.h" // data type definitions +#include "stdio.h" // file I/O functions +#include "rl_usb.h" // Keil.MDK-Pro::USB:CORE +#include "rl_fs.h" // Keil.MDK-Pro::File System:CORE + +/* Execution status codes */ +#define USBH_MSC_OK 0 ///< Function succeeded +#define USBH_MSC_ERROR -1 ///< Unspecified error +#define USBH_MSC_ERROR_DRIVE -2 ///< USB storage device not connected +#define USBH_MSC_ERROR_FORMAT -3 ///< USB drive mounted, but unformatted + + +/// \brief Get status of drive media (USB storage connected or not connected) +/// \param[in] drive_name USB storage drive name ("U0:", "U1:") +/// \return execution status +/// - USBH_MSC_OK = USB storage device connected and enumerated +/// - USBH_MSC_ERROR_DRIVE = USB storage device not connected or not enumerated +extern int32_t USBH_MSC_DriveGetMediaStatus (const char *drive_name); + + +/// \brief Mount drive and initialize USB storage device for file I/O access +/// \param[in] drive_name USB storage drive name ("U0:", "U1:") +/// \return execution status +/// - USBH_MSC_OK = USB drive mounted, file system ready +/// - USBH_MSC_ERROR = unspecified error +/// - USBH_MSC_ERROR_DRIVE = USB storage device not connected +/// - USBH_MSC_ERROR_FORMAT = USB drive mounted, but unformatted +extern int32_t USBH_MSC_DriveMount (const char *drive_name); + + +/// \brief Unmount drive and de-initialize USB storage device before eject +/// \param[in] drive_name USB storage drive name ("U0:", "U1:") +/// \return execution status +/// - USBH_MSC_OK = USB drive unmounted +/// - USBH_MSC_ERROR = unspecified error +extern int32_t USBH_MSC_DriveUnmount (const char *drive_name); + + +/// \brief Check the physical capacity of USB storage device +/// \param[in] drive_name USB storage drive name ("U0:", "U1:") +/// \return execution status +/// - value != 0 = size of USB storage device in bytes +/// - value == 0 = no drive connected or unspecified error +extern uint64_t USBH_MSC_DriveGetCapacity (const char *drive_name); + +#endif diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/readme.txt b/build/example_kdrv/usb/usbh_cmsis_msc/readme.txt new file mode 100644 index 0000000..7205b05 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/readme.txt @@ -0,0 +1,4 @@ +This example code demonstrates how to use USBD driver API to create a USB device +including descriptors and endpoints setup and use of bulk transfer. + +please refer to usbd_example.c. \ No newline at end of file diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/project.h b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/project.h new file mode 100644 index 0000000..82e157e --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Compiler/EventRecorderConf.h b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Compiler/EventRecorderConf.h new file mode 100644 index 0000000..bf3b1c0 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Compiler/EventRecorderConf.h @@ -0,0 +1,34 @@ +/*------------------------------------------------------------------------------ + * MDK - Component ::Event Recorder + * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.1.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 64U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 0 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines default time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4/startup_ARMCM4.s b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4/startup_ARMCM4.s new file mode 100644 index 0000000..d7ff0e6 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x000000000000000004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4/system_ARMCM4.c b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4/system_ARMCM4.c new file mode 100644 index 0000000..60ee677 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4/system_ARMCM4.c @@ -0,0 +1,88 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL//(XTAL / 2U) + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Config.c b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Config.c new file mode 100644 index 0000000..5d02be1 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Config.c @@ -0,0 +1,78 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config.c + * Purpose: File System Configuration + * Rev.: V6.3.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// FAT File System +// Define FAT File System parameters + +// Number of open files <1-16> +// Define number of files that can be opened at the same time. +// Default: 4 +#define FAT_MAX_OPEN_FILES 4 + +// + +// Embedded File System +// Define Embedded File System parameters + +// Number of open files <1-16> +// Define number of files that can be opened at the same time. +// Default: 4 +#define EFS_MAX_OPEN_FILES 4 + +// + +// Initial Current Drive <0=>F0: <1=>F1: +// <2=>M0: <3=>M1: +// <4=>N0: <5=>N1: +// <6=>R0: <9=>R1: +// <7=>U0: <8=>U1: +// Set initial setting for current drive. Current drive is used for File System functions +// that are invoked with the "" string and can be altered anytime during run-time. +#define FS_INITIAL_CDRIVE 7 + +#include "RTE_Components.h" + +#ifdef RTE_FileSystem_Drive_RAM_0 +#include "FS_Config_RAM_0.h" +#endif +#ifdef RTE_FileSystem_Drive_RAM_1 +#include "FS_Config_RAM_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NOR_0 +#include "FS_Config_NOR_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NOR_1 +#include "FS_Config_NOR_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_NAND_0 +#include "FS_Config_NAND_0.h" +#endif +#ifdef RTE_FileSystem_Drive_NAND_1 +#include "FS_Config_NAND_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_MC_0 +#include "FS_Config_MC_0.h" +#endif +#ifdef RTE_FileSystem_Drive_MC_1 +#include "FS_Config_MC_1.h" +#endif + +#ifdef RTE_FileSystem_Drive_USB_0 +#include "FS_Config_USB_0.h" +#endif +#ifdef RTE_FileSystem_Drive_USB_1 +#include "FS_Config_USB_1.h" +#endif + +#include "fs_config.h" diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Config_USB_0.h b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Config_USB_0.h new file mode 100644 index 0000000..e5711d3 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Config_USB_0.h @@ -0,0 +1,32 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System:Drive + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Config_USB_0.h + * Purpose: File System Configuration for USB Drive + * Rev.: V6.2.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Drive 0 +// Configuration for USB device assigned to drive letter "U0:" +#define USB0_ENABLE 1 + +// Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB +// <8=>8 KB <16=>16 KB <32=>32 KB +// Drive Cache stores data sectors and may be increased to speed-up +// file read/write operations on this drive (default: 4 KB) +#define USB0_CACHE_SIZE 4 + +// Filename Cache Size <0-1000000> +// Define number of cached file or directory names. +// 48 bytes of RAM is required for each cached name. +#define USB0_NAME_CACHE_SIZE 0 + +// Use FAT Journal +// Protect File Allocation Table and Directory Entries for +// fail-safe operation. +#define USB0_FAT_JOURNAL 0 + +// diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Debug.c b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Debug.c new file mode 100644 index 0000000..38e37f5 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/File_System/FS_Debug.c @@ -0,0 +1,50 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::File System + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: FS_Debug.c + * Purpose: File System Debug Configuration + * Rev.: V1.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// File System Debug +// Enable File System event recording +#define FS_DEBUG_EVR_ENABLE 0 + +// Core Management <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsCore: Core Management event recording +#define FS_DEBUG_EVR_CORE 1 + +// FAT File System <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsFAT: FAT File System event recording +#define FS_DEBUG_EVR_FAT 1 + +// EFS File System <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsEFS: EFS File System event recording +#define FS_DEBUG_EVR_EFS 1 + +// I/O Control Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsIOC: I/O Control Interface event recording +#define FS_DEBUG_EVR_IOC 1 + +// NAND Flash Translation Layer <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsNFTL: NAND Flash Translation Layer event recording +#define FS_DEBUG_EVR_NFTL 1 + +// NAND Device Interface <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsNAND: NAND Device Interface event recording +#define FS_DEBUG_EVR_NAND 1 + +// Memory Card MCI <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsMcMCI: Memory Card MCI event recording +#define FS_DEBUG_EVR_MC_MCI 1 + +// Memory Card SPI <0=>Off <1=>Errors <2=>Errors + API <3=>All +// Configure FsMcSPI: Memory Card SPI event recording +#define FS_DEBUG_EVR_MC_SPI 1 + +// + +#include "fs_debug.h" diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c new file mode 100644 index 0000000..50a1dd0 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c @@ -0,0 +1,142 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_Config_0.c + * Purpose: USB Host Configuration + * Rev.: V5.2.1 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Host 0 +// Connect to hardware via Driver_USBH# <0-255> +// Select driver control block for hardware interface. +#define USBH0_HC_NUM 0 + +// Controller Interface Settings + +// Controller Interface +// Selects the USB Host Controller Interface +// <0=> Custom <1=> OHCI <2=> EHCI +// Custom Controller Interface is used for any non-standard USB Host +// Controller. +#define USBH0_HC_IF 0 + +// Custom Host Controller Interface +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by Custom Controller +// in system simultaneously. +#define USBH0_HC_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_MEM_POOL_SIZE 512 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_MEM_POOL_ADDR 0x00000000 +// +// + +// Open Host Controller Interface (OHCI) +// Memory-mapped OHCI Host Controller registers base address +// This setting applies for OHCI Controller Interface. +#define USBH0_HC_OHCI_BASE_ADDRESS 0x5000C000 + +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_OHCI_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by OHCI Controller +// in system simultaneously. +// This setting affects memory allocated by OHCI controller. +#define USBH0_HC_OHCI_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_OHCI_MEM_POOL_SIZE 512 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_OHCI_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_OHCI_MEM_POOL_ADDR 0x00000000 +// +// + +// Enhanced Host Controller Interface (EHCI) +// Memory-mapped EHCI Host Controller registers base address +// These settings apply for EHCI Controller Interface. +#define USBH0_HC_EHCI_BASE_ADDRESS 0x40006100 + +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_EHCI_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by EHCI Controller +// in system simultaneously. +// This setting affects memory allocated by EHCI controller. +#define USBH0_HC_EHCI_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_EHCI_MEM_POOL_SIZE 4096 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_EHCI_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_EHCI_MEM_POOL_ADDR 0x00000000 +// +// +// + +// OS Resources Settings +// These settings are used to optimize usage of OS resources. +// Core Thread Stack Size <64-65536> +#define USBH0_CORE_THREAD_STACK_SIZE 1024 + +// Core Thread Priority +#define USBH0_CORE_THREAD_PRIORITY osPriorityAboveNormal + +// +// + + +#include "RTE_Components.h" + +#ifdef RTE_USB_Host_MSC +#include "USBH_Config_MSC.h" +#endif + +#ifdef RTE_USB_Host_HID +#include "USBH_Config_HID.h" +#endif + +#ifdef RTE_USB_Host_CDC +#include "USBH_Config_CDC.h" +#endif + +#ifdef RTE_USB_Host_CustomClass +#include "USBH_Config_CustomClass.h" +#endif + +#include "usbh_config.h" diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h new file mode 100644 index 0000000..9965741 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h @@ -0,0 +1,16 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_Config_CustomClass.h + * Purpose: USB Host Custom Class Configuration + * Rev.: V5.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Host: Custom Class +// Number of concurrent Custom Devices in system <0-15> +#define USBH_CUSTOM_CLASS_NUM 1 + +// diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_MSC.h b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_MSC.h new file mode 100644 index 0000000..68cb772 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/USB/USBH_Config_MSC.h @@ -0,0 +1,16 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_Config_MSC.h + * Purpose: USB Host Mass Storage Class (MSC) Configuration + * Rev.: V5.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Host: Mass Storage Class (MSC) +// Number of concurrent MSC Devices in system <0-15> +#define USBH_MSC_NUM 1 + +// diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..4198819 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,44 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ +/* Keil.ARM Compiler::Compiler:I/O:File:File System:1.2.0 */ +#define RTE_Compiler_IO_File /* Compiler I/O: File */ + #define RTE_Compiler_IO_File_FS /* Compiler I/O: File (File System) */ +/* Keil.MDK-Pro::File System:CORE:LFN:6.13.0 */ +#define RTE_FileSystem_Core /* File System Core */ + #define RTE_FileSystem_LFN /* File System with Long Filename support */ + #define RTE_FileSystem_Release /* File System Release Version */ +/* Keil.MDK-Pro::File System:Drive:USB:6.13.0 */ +#define RTE_FileSystem_Drive_USB_0 /* File System USB Drive 0 */ + +/* Keil.MDK-Pro::USB:CORE:Release:6.13.7 */ +#define RTE_USB_Core /* USB Core */ + #define RTE_USB_Core_Release /* USB Core Release Version */ +/* Keil.MDK-Pro::USB:Host:6.13.7 */ +#define RTE_USB_Host_0 /* USB Host 0 */ + +/* Keil.MDK-Pro::USB:Host:Custom Class:6.13.7 */ +#define RTE_USB_Host_CustomClass /* USB Host Custom Class */ +/* Keil.MDK-Pro::USB:Host:MSC:6.13.7 */ +#define RTE_USB_Host_MSC /* USB Host MSC */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..1409d30 --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,448 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\vtor.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + d + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 1 + 0 + 0x62ec1762 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\Keil\MDK-Middleware\7.10.0\USB\USB.scvd + Keil.MDK-Middleware.7.10.0 + 1 + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\Keil\MDK-Middleware\7.10.0\FileSystem\FileSystem.scvd + Keil.MDK-Middleware.7.10.0 + 1 + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\usbh_msc.c + usbh_msc.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\usbh_cmsis_msc.c + usbh_cmsis_msc.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_usbh_cmsis_main.c + ex_usbh_cmsis_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + kdrv_usbh.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::CMSIS Driver + 0 + 0 + 0 + 1 + + + + ::Compiler + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + + ::File System + 0 + 0 + 0 + 1 + + + + ::USB + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..29bdcdb --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,714 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + usbh_msc.c + 1 + ..\..\main_scpu\usbh_msc.c + + + usbh_cmsis_msc.c + 1 + ..\..\main_scpu\usbh_cmsis_msc.c + + + ex_usbh_cmsis_main.c + 1 + ..\..\main_scpu\ex_usbh_cmsis_main.c + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_usbh.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + + + + + ::CMSIS + + + ::CMSIS Driver + + + ::Compiler + + + ::Device + + + ::File System + + + ::USB + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + + + diff --git a/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/usb/usbh_cmsis_msc/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/usb/usbh_mdw_custom/main_scpu/ex_usbh_main.c b/build/example_kdrv/usb/usbh_mdw_custom/main_scpu/ex_usbh_main.c new file mode 100644 index 0000000..e717bb4 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/main_scpu/ex_usbh_main.c @@ -0,0 +1,68 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "cmsis_os2.h" + +#include "kdrv_cmsis_core.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" + +#include "kmdw_memory.h" +#include "kmdw_console.h" + + +extern void usbh_mdw_custom_init(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); + + /* init the application */ + usbh_mdw_custom_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/usb/usbh_mdw_custom/main_scpu/usbh_mdw_custom.c b/build/example_kdrv/usb/usbh_mdw_custom/main_scpu/usbh_mdw_custom.c new file mode 100644 index 0000000..c92c52e --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/main_scpu/usbh_mdw_custom.c @@ -0,0 +1,204 @@ + +#include +#include "cmsis_os2.h" // CMSIS RTOS header file + +#include "kmdw_usbh.h" // Kneron's USB middleware + +static osThreadId_t usbh_app_thread; +static USBH_PIPE_HANDLE bulkout_pipe, bulkin_pipe, intin_pipe; + +extern void kmdw_printf(const char *f, ...); +extern uint32_t kmdw_ddr_reserve(uint32_t numbyte); + +/*---------------------------------------------------------------------------- +* Thread for usb host examples +*---------------------------------------------------------------------------*/ + +void usbh_mdw_user_thread(void *argument); // thread function + +void usbh_mdw_custom_init(void) +{ + usbh_app_thread = osThreadNew(usbh_mdw_user_thread, NULL, NULL); +} + +void usbh_mdw_user_thread(void *argument) +{ + usbStatus usb_status; // USB status + + uint8_t *bfptr = (uint8_t *)kmdw_ddr_reserve(4 * 1024 * 1024); + + kmdw_printf("bfptr = 0x%p\n"); + + // init USB host through MDK middleware + usb_status = USBH_Initialize(0U); + if (usb_status != usbOK) + { + kmdw_printf("USBH_Initialize() failed\n"); + } + + kmdw_printf("USBH_Initialize() OK\n"); + + kmdw_printf("waiting for usb device enumeration\n"); + + // wait for device init done + osThreadFlagsWait(0x01U, osFlagsWaitAny, osWaitForever); + + int test_run = 1000; + + // below test bulk-out + { + kmdw_printf("\n==== starting bulk-out test ====\n\n"); + + uint32_t total_send = 1024; + + for (int i = 0; i < test_run; i++) + { + total_send += (1 + (rand() % 4000)); + if (total_send > 1024 * 1024) // make it <= 1 MB + total_send = (1 + (rand() % (512 * 1024))); + + uint32_t wanted_bytes = total_send; + + kmdw_printf("... bulk-out transferred %d bytes\n", wanted_bytes); + + while (1) + { + uint32_t sendBytes = 16 * 1024; // set a max pipe send + + if (wanted_bytes < sendBytes) + sendBytes = wanted_bytes; + + // NOTE: for now sendBytes MAX = 20 KB due to host driver implementation + usbStatus sts = USBH_PipeSend(bulkout_pipe, bfptr, sendBytes); + if (sts != usbOK) + { + kmdw_printf("... bulk-out transferred %d bytes failed, sts = %d\n", sendBytes, sts); + goto Test_Failed; + } + + sendBytes = USBH_PipeSendGetResult(bulkout_pipe); + + wanted_bytes -= sendBytes; + + if (wanted_bytes == 0) + { + if ((sendBytes % 512) == 0) + { + // zero-length packet + //kmdw_printf("\nsending zero-length packet ~\n"); + usbStatus sts = USBH_PipeSend(bulkout_pipe, bfptr, 0); + if (sts != usbOK) + { + kmdw_printf("... bulk-out transferring ZLP failed, sts = %d\n", sts); + goto Test_Failed; + } + } + break; + } + } + } + kmdw_printf("\nbulk-out test done ~\n"); + } + + // below test bulk-in + { + kmdw_printf("\n==== starting bulk-in test ====\n\n"); + for (int i = 0; i < test_run; i++) + { + uint32_t total_recvd = 0; + + while (1) + { + uint32_t recvBytes = 16384; // however only 16KB for one transfer at maximum + + // NOTE: for now recvBytes MAX = 20 KB due to host driver implementation + usbStatus sts = USBH_PipeReceive(bulkin_pipe, bfptr, recvBytes); + if (sts != usbOK) + { + kmdw_printf("... bulk-in transfer failed, sts = %d\n", sts); + goto Test_Failed; + } + + recvBytes = USBH_PipeReceiveGetResult(bulkin_pipe); + + total_recvd += recvBytes; + + if (recvBytes == 0 || (recvBytes % 512) != 0) + break; + } + + kmdw_printf("... bulk-in transferred %d bytes\n", total_recvd); + } + kmdw_printf("\nbulk-in test done ~\n"); + } + + // below test interrupt-in + { + kmdw_printf("\n==== starting interrupt-in test ====\n\n"); + for (int i = 0; i < test_run; i++) + { + uint32_t data = 0; + usbStatus sts = USBH_PipeReceive(intin_pipe, (uint8_t *)&data, 4); + if (sts != usbOK) + { + kmdw_printf("... interrupt-in transfer failed, sts = %d\n", sts); + goto Test_Failed; + } + + kmdw_printf("... interrupt-in get data = 0x%x\n", data); + } + kmdw_printf("\ninterrupt-in test done ~\n"); + } + + kmdw_printf("\nAll tests on control/bulk/interrupt transfer are passed ~\n"); + return; + +Test_Failed: + + kmdw_printf("\nSome tests are failing !!\n"); +} + +/************************** Class Driver Functions ****************************/ + +uint8_t USBH_CustomClass_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc) +{ + + kmdw_printf("%s()\n", __FUNCTION__); + + if (ptr_dev_desc->idVendor != 0xD7D || ptr_dev_desc->idProduct != 0x100) + { + kmdw_printf("Cannot recognize the device!\n"); + return 255U; // value 255 : configuration failed + } + + //usb_device = device; + + kmdw_printf("device = %u\n", device); + + // we do the hard-code way to create endpoint pipes for code size reduction + bulkout_pipe = USBH_PipeCreate(device, 0x01, USB_ENDPOINT_TYPE_BULK, 512, 0); + bulkin_pipe = USBH_PipeCreate(device, 0x81, USB_ENDPOINT_TYPE_BULK, 512, 0); + intin_pipe = USBH_PipeCreate(device, 0x82, USB_ENDPOINT_TYPE_INTERRUPT, 1024, 4); + + return 0; +} + +usbStatus USBH_CustomClass_Initialize(uint8_t instance) +{ + // Add code for initializing device + + kmdw_printf("%s()\n", __FUNCTION__); + + osThreadFlagsSet(usbh_app_thread, 0x01U); + + return usbOK; +} + +usbStatus USBH_CustomClass_Uninitialize(uint8_t instance) +{ + // Add code for de-initializing device + + kmdw_printf("%s()\n", __FUNCTION__); + + return usbOK; +} diff --git a/build/example_kdrv/usb/usbh_mdw_custom/readme.txt b/build/example_kdrv/usb/usbh_mdw_custom/readme.txt new file mode 100644 index 0000000..7205b05 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/readme.txt @@ -0,0 +1,4 @@ +This example code demonstrates how to use USBD driver API to create a USB device +including descriptors and endpoints setup and use of bulk transfer. + +please refer to usbd_example.c. \ No newline at end of file diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/project.h b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/project.h new file mode 100644 index 0000000..82e157e --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c new file mode 100644 index 0000000..50a1dd0 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_0.c @@ -0,0 +1,142 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_Config_0.c + * Purpose: USB Host Configuration + * Rev.: V5.2.1 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Host 0 +// Connect to hardware via Driver_USBH# <0-255> +// Select driver control block for hardware interface. +#define USBH0_HC_NUM 0 + +// Controller Interface Settings + +// Controller Interface +// Selects the USB Host Controller Interface +// <0=> Custom <1=> OHCI <2=> EHCI +// Custom Controller Interface is used for any non-standard USB Host +// Controller. +#define USBH0_HC_IF 0 + +// Custom Host Controller Interface +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by Custom Controller +// in system simultaneously. +#define USBH0_HC_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_MEM_POOL_SIZE 512 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_MEM_POOL_ADDR 0x00000000 +// +// + +// Open Host Controller Interface (OHCI) +// Memory-mapped OHCI Host Controller registers base address +// This setting applies for OHCI Controller Interface. +#define USBH0_HC_OHCI_BASE_ADDRESS 0x5000C000 + +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_OHCI_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by OHCI Controller +// in system simultaneously. +// This setting affects memory allocated by OHCI controller. +#define USBH0_HC_OHCI_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_OHCI_MEM_POOL_SIZE 512 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_OHCI_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_OHCI_MEM_POOL_ADDR 0x00000000 +// +// + +// Enhanced Host Controller Interface (EHCI) +// Memory-mapped EHCI Host Controller registers base address +// These settings apply for EHCI Controller Interface. +#define USBH0_HC_EHCI_BASE_ADDRESS 0x40006100 + +// Maximum Port Power Consumption<2-500:2> +// Specifies the maximum power consumption per port (in mA) +#define USBH0_HC_EHCI_POWER 500 + +// Maximum Pipes in system +// Maximum number of Pipes that will be used by EHCI Controller +// in system simultaneously. +// This setting affects memory allocated by EHCI controller. +#define USBH0_HC_EHCI_PIPE_NUM 3 + +// Memory Pool Size <512-1048576:4> +// Specify size of memory pool (in bytes) that the USB Host Controller +// will use for USB communication data. +#define USBH0_HC_EHCI_MEM_POOL_SIZE 4096 + +// Relocate Memory Pool +// Locate the Memory Pool at a specific address. +#define USBH0_HC_EHCI_MEM_POOL_RELOC 0 + +// Memory Pool Address <0-0xFFFFFE00:0x200> +// Start address of the Memory Pool. +#define USBH0_HC_EHCI_MEM_POOL_ADDR 0x00000000 +// +// +// + +// OS Resources Settings +// These settings are used to optimize usage of OS resources. +// Core Thread Stack Size <64-65536> +#define USBH0_CORE_THREAD_STACK_SIZE 1024 + +// Core Thread Priority +#define USBH0_CORE_THREAD_PRIORITY osPriorityAboveNormal + +// +// + + +#include "RTE_Components.h" + +#ifdef RTE_USB_Host_MSC +#include "USBH_Config_MSC.h" +#endif + +#ifdef RTE_USB_Host_HID +#include "USBH_Config_HID.h" +#endif + +#ifdef RTE_USB_Host_CDC +#include "USBH_Config_CDC.h" +#endif + +#ifdef RTE_USB_Host_CustomClass +#include "USBH_Config_CustomClass.h" +#endif + +#include "usbh_config.h" diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h new file mode 100644 index 0000000..9965741 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/USB/USBH_Config_CustomClass.h @@ -0,0 +1,16 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB:Host + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: USBH_Config_CustomClass.h + * Purpose: USB Host Custom Class Configuration + * Rev.: V5.0.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// USB Host: Custom Class +// Number of concurrent Custom Devices in system <0-15> +#define USBH_CUSTOM_CLASS_NUM 1 + +// diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..bffe29f --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..0f69719 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,349 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\usbh_mdw_custom.c + usbh_mdw_custom.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_usbh_main.c + ex_usbh_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\usbh\kmdw_usbh.c + kmdw_usbh.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + kdrv_usbh.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..45b0e0f --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,638 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + usbh_mdw_custom.c + 1 + ..\..\main_scpu\usbh_mdw_custom.c + + + ex_usbh_main.c + 1 + ..\..\main_scpu\ex_usbh_main.c + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_usbh.c + 1 + ..\..\..\..\..\..\mdw\usbh\kmdw_usbh.c + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_usbh.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_custom/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/main_scpu/ex_uvc_main.c b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/main_scpu/ex_uvc_main.c new file mode 100644 index 0000000..6a8cfec --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/main_scpu/ex_uvc_main.c @@ -0,0 +1,69 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "cmsis_os2.h" + +#include "kdrv_cmsis_core.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" + +#include "kmdw_memory.h" +#include "kmdw_console.h" + +extern void uvc_example_init(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // uart console + + /* init the application */ + uvc_example_init(); + + DSG("Starting the USBH UVC example..."); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/main_scpu/uvc_aveo.c b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/main_scpu/uvc_aveo.c new file mode 100644 index 0000000..2698c8e --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/main_scpu/uvc_aveo.c @@ -0,0 +1,132 @@ + +#include +#include "cmsis_os2.h" // CMSIS RTOS header file + +#include "kmdw_usbh.h" // Kneron's USB middleware +#include "kmdw_uvc.h" // Kneron's USB-UVC class middleware + +//#define UVC_USER_ERR + +static osThreadId_t usbh_example_uvc_thread; +static USBH_PIPE_HANDLE isoch_pipe; + +extern void kmdw_printf(const char *f, ...); +extern uint32_t kmdw_ddr_reserve(uint32_t numbyte); + +/*---------------------------------------------------------------------------- +* Thread for usb host examples +*---------------------------------------------------------------------------*/ + +void usbh_mdw_uvc_thread(void *argument); // thread function + +void uvc_example_init(void) +{ + usbh_example_uvc_thread = osThreadNew(usbh_mdw_uvc_thread, NULL, NULL); +} + +void usbh_mdw_uvc_thread(void *argument) +{ + usbStatus usb_status; // USB status + + uint8_t *bfptr = (uint8_t *)kmdw_ddr_reserve(4 * 1024 * 1024); + + kmdw_printf("bfptr = 0x%p\n"); + + // init USB host through MDK middleware + usb_status = USBH_Initialize(0U); + if (usb_status != usbOK) + { + kmdw_printf("USBH_Initialize() failed\n"); + } + + kmdw_printf("USBH_Initialize() OK\n"); + + kmdw_printf("waiting for usb device enumeration\n"); + + // wait for device init done + osThreadFlagsWait(0x01U, osFlagsWaitAny, osWaitForever); + + osDelay(100); // give the camera some time to go ?? + + kmdw_printf("Starting isoch transfer..\n"); + + USBH_UVC_PipeStart_Isoch(isoch_pipe); +} + +#define NUM_FRAME 4 +#define FRMAE_SIZE (640 * 480 * 2) // VGA YUV420 + +/************************** Class Driver Functions ****************************/ + +uint8_t USBH_UVC_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc) +{ + kmdw_printf("%s()\n", __FUNCTION__); + + // interface 1, alternate 5 + isoch_pipe = USBH_UVC_PipeCreate_Isoch(device, 0x83, 0x13FC, 1); + + // allocate some frame buffers + uint32_t all_frame_buf = kmdw_ddr_reserve(NUM_FRAME * FRMAE_SIZE); + + kmdw_printf("UVC_USER: allocated %d bytes start from address 0x%p\n", NUM_FRAME * FRMAE_SIZE, all_frame_buf); + + // queue all frames into UVC middleware + for (int i = 0; i < NUM_FRAME; i++) + USBH_UVC_Queue_Frame(isoch_pipe, (uint32_t *)(all_frame_buf + i * FRMAE_SIZE), FRMAE_SIZE); + + // set class interface 1 altr 0 for VideoStreaming interface + USBH_DeviceRequest_SetInterface(device, 1, 0); + + { + UVC_PROBE_COMMIT_CONTROL uvc_ctrl; + uvc_ctrl.bmHint = 0x0001; + uvc_ctrl.bFormatIndex = 1; + uvc_ctrl.bFrameIndex = 1; + uvc_ctrl.dwFrameInterval = 333333; + uvc_ctrl.wKeyFrameRate = 0; + uvc_ctrl.wPFrameRate = 0; + uvc_ctrl.wCompQuality = 0; + uvc_ctrl.wCompWindowSize = 0; + uvc_ctrl.wDelay = 0; + uvc_ctrl.dwMaxVideoFrameSize = 0; + uvc_ctrl.dwMaxPayloadTransferSize = 0; + + // VideoStreaming request - SET_CUR - Probe Control + USBH_UVC_VS_Control(device, SET_CUR, VS_PROBE_CONTROL, &uvc_ctrl); + + // VideoStreaming request - GET_CUR - Probe Control + USBH_UVC_VS_Control(device, GET_CUR, VS_PROBE_CONTROL, &uvc_ctrl); + + // VideoStreaming request - SET_CUR - Commit Control + USBH_UVC_VS_Control(device, SET_CUR, VS_COMMIT_CONTROL, &uvc_ctrl); + } + + // set class interface 1 altr 5 to start video streaming + USBH_DeviceRequest_SetInterface(device, 1, 5); + + return 0; +} + +usbStatus USBH_UVC_Initialize(uint8_t instance) +{ + // Add code for initializing device + + kmdw_printf("%s()\n", __FUNCTION__); + + osThreadFlagsSet(usbh_example_uvc_thread, 0x01U); + + return usbOK; +} + +void USBH_UVC_Get_Frame(uint32_t *frame_ptr, uint32_t frame_size) +{ +#ifdef UVC_USER_ERR + if (frame_size != FRMAE_SIZE) + kmdw_printf("uvc_example: frame_ptr 0x%p frame_size %u is wrong\n", frame_ptr, frame_size); +#endif + + kmdw_printf("UVC_USER: frame_ptr 0x%p frame_size %u\n", frame_ptr, frame_size); + + // and enqueue this frame to UVC middleware again + USBH_UVC_Queue_Frame(isoch_pipe, frame_ptr, FRMAE_SIZE); +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/project.h b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/project.h new file mode 100644 index 0000000..82e157e --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/AVEO_VID1871_PID0142 b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/AVEO_VID1871_PID0142 new file mode 100644 index 0000000..0bf19fc --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/AVEO_VID1871_PID0142 @@ -0,0 +1,1430 @@ + + =========================== USB Port10 =========================== + +Connection Status : 0x01 (Device is connected) +Port Chain : 1-10 +Properties : 0x01 + IsUserConnectable : yes + PortIsDebugCapable : no + PortHasMultiCompanions : no + PortConnectorIsTypeC : no + + ======================== USB Device ======================== + + +++++++++++++++++ Device Information ++++++++++++++++++ +Device Description : USB Composite Device +Device Path : \\?\usb#vid_1871&pid_0142#5&36a3b657&0&10#{a5dcbf10-6530-11d2-901f-00c04fb951ed} +Device ID : USB\VID_1871&PID_0142\5&36A3B657&0&10 +Hardware IDs : USB\VID_1871&PID_0142&REV_000< USB\VID_1871&PID_0142 +Driver KeyName : {36fc9e60-c465-11cf-8056-444553540000}\0017 (GUID_DEVCLASS_USB) +Driver : \SystemRoot\System32\drivers\usbccgp.sys (Version: 10.0.18362.1 Date: 2019-03-19) +Driver Inf : C:\WINDOWS\inf\usb.inf +Legacy BusType : PNPBus +Class : USB +Class GUID : {36fc9e60-c465-11cf-8056-444553540000} (GUID_DEVCLASS_USB) +Interface GUID : {a5dcbf10-6530-11d2-901f-00c04fb951ed} (GUID_DEVINTERFACE_USB_DEVICE) +Service : usbccgp +Enumerator : USB +Location Info : Port_#0010.Hub_#0001 +Location IDs : PCIROOT(0)#PCI(1400)#USBROOT(0)#USB(10), ACPI(_SB_)#ACPI(PCI0)#ACPI(XHC_)#ACPI(RHUB)#ACPI(HS10) +Container ID : {831a926d-ddaa-11e9-8956-7c2a318bba54} +Manufacturer Info : (標準 USB 主控制器) +Capabilities : 0x84 (Removable, SurpriseRemovalOK) +Status : 0x0180600A (DN_DRIVER_LOADED, DN_STARTED, DN_DISABLEABLE, DN_REMOVABLE, DN_NT_ENUMERATOR, DN_NT_DRIVER) +Problem Code : 0 +Address : 10 +Power State : D0 (supported: D0, D3, wake from D0) + Child Device 1 : USB2.0 Camera (USB 音效è£ç½®) + DevicePath : \\?\usb#vid_1871&pid_0142&mi_02#6&20486672&0&0002#{6994ad04-93ef-11d0-a3cc-00a0c9223196} + KernelName : \Device\000000ab + Device ID : USB\VID_1871&PID_0142&MI_02\6&20486672&0&0002 + Class : MEDIA + Child Device 1 : 麥克風 (USB2.0 Camera) (音訊端點) + Device ID : SWD\MMDEVAPI\{0.0.1.00000000}.{02954FF9-F551-4B3A-B021-6D7C9551C2C2} + Class : AudioEndpoint + Child Device 2 : USB2.0 Camera (USB 視訊è£ç½®) + Device ID : USB\VID_1871&PID_0142&MI_00\6&20486672&0&0000 + Class : Camera + + +++++++++++++++++ Registry USB Flags +++++++++++++++++ +HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\usbflags\18710142000C + osvc : REG_BINARY 00 00 + NewInterfaceUsage : REG_DWORD 00000000 (0) + + ---------------- Connection Information --------------- +Connection Index : 0x0A (10) +Connection Status : 0x01 (DeviceConnected) +Current Config Value : 0x01 +Device Address : 0x22 (34) +Is Hub : 0x00 (no) +Device Bus Speed : 0x02 (High-Speed) +Number Of Open Pipes : 0x02 (2 pipes to data endpoints) +Pipe[0] : EndpointID=5 Direction=IN ScheduleOffset=0 Type=Interrupt +Pipe[1] : EndpointID=4 Direction=IN ScheduleOffset=0 Type=Isochronous +Data (HexDump) : 0A 00 00 00 12 01 00 02 EF 02 01 40 71 18 42 01 ...........@q.B. + 0C 00 01 02 00 01 01 02 00 22 00 02 00 00 00 01 ........."...... + 00 00 00 07 05 85 03 40 00 07 00 00 00 00 09 05 .......@........ + 84 01 00 00 04 00 00 00 00 ......... + + --------------- Connection Information V2 ------------- +Connection Index : 0x0A (10) +Length : 0x10 (16 bytes) +SupportedUsbProtocols : 0x03 + Usb110 : 1 (yes) + Usb200 : 1 (yes) + Usb300 : 0 (no) + ReservedMBZ : 0x00 +Flags : 0x00 + DevIsOpAtSsOrHigher : 0 (Is not operating at SuperSpeed or higher) + DevIsSsCapOrHigher : 0 (Is not SuperSpeed capable or higher) + DevIsOpAtSsPlusOrHigher : 0 (Is not operating at SuperSpeedPlus or higher) + DevIsSsPlusCapOrHigher : 0 (Is not SuperSpeedPlus capable or higher) + ReservedMBZ : 0x00 +Data (HexDump) : 0A 00 00 00 10 00 00 00 03 00 00 00 00 00 00 00 ................ + + ---------------------- Device Descriptor ---------------------- +bLength : 0x12 (18 bytes) +bDescriptorType : 0x01 (Device Descriptor) +bcdUSB : 0x200 (USB Version 2.00) +bDeviceClass : 0xEF (Miscellaneous) +bDeviceSubClass : 0x02 +bDeviceProtocol : 0x01 (IAD - Interface Association Descriptor) +bMaxPacketSize0 : 0x40 (64 bytes) +idVendor : 0x1871 +idProduct : 0x0142 +bcdDevice : 0x000C +iManufacturer : 0x01 (String Descriptor 1) + Language 0x0409 : "AVEO Technology Corp." +iProduct : 0x02 (String Descriptor 2) + Language 0x0409 : "USB2.0 Camera" +iSerialNumber : 0x00 (No String Descriptor) +bNumConfigurations : 0x01 (1 Configuration) +Data (HexDump) : 12 01 00 02 EF 02 01 40 71 18 42 01 0C 00 01 02 .......@q.B..... + 00 01 .. + + ------------------ Configuration Descriptor ------------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x02 (Configuration Descriptor) +wTotalLength : 0x0222 (546 bytes) +bNumInterfaces : 0x04 (4 Interfaces) +bConfigurationValue : 0x01 (Configuration 1) +iConfiguration : 0x00 (No String Descriptor) +bmAttributes : 0x80 + D7: Reserved, set 1 : 0x01 + D6: Self Powered : 0x00 (no) + D5: Remote Wakeup : 0x00 (no) + D4..0: Reserved, set 0 : 0x00 +MaxPower : 0xFA (500 mA) +Data (HexDump) : 09 02 22 02 04 01 00 80 FA 08 0B 00 02 0E 03 00 .."............. + 02 09 04 00 00 01 0E 01 00 02 0D 24 01 00 01 4D ...........$...M + 00 80 C3 C9 01 01 01 12 24 02 01 01 02 00 00 00 ........$....... + 00 00 00 00 00 03 00 00 00 09 24 03 02 01 01 00 ..........$..... + 04 00 0B 24 05 03 01 00 00 02 3B 05 00 1A 24 06 ...$......;...$. + 04 52 F2 B8 AA D1 8E 72 49 8C ED 96 B1 7F 04 40 .R.....rI......@ + 8B 01 01 03 01 01 00 07 05 85 03 40 00 07 05 25 ...........@...% + 03 40 00 09 04 01 00 00 0E 02 00 00 0E 24 01 01 .@...........$.. + DF 00 83 00 02 02 01 00 01 00 1B 24 04 01 05 59 ...........$...Y + 55 59 32 00 00 10 00 80 00 00 AA 00 38 9B 71 10 UY2.........8.q. + 01 00 00 00 00 1E 24 05 01 00 80 02 E0 01 00 00 ......$......... + CA 08 00 00 CA 08 00 60 09 00 15 16 05 00 01 15 .......`........ + 16 05 00 1E 24 05 02 00 A0 00 78 00 00 A0 8C 00 ....$.....x..... + 00 A0 8C 00 00 96 00 00 15 16 05 00 01 15 16 05 ................ + 00 1E 24 05 03 00 40 01 F0 00 00 80 32 02 00 80 ..$...@.....2... + 32 02 00 58 02 00 15 16 05 00 01 15 16 05 00 1E 2..X............ + 24 05 04 00 B0 00 90 00 00 A0 B9 00 00 A0 B9 00 $............... + 00 C6 00 00 15 16 05 00 01 15 16 05 00 1E 24 05 ..............$. + 05 00 60 01 20 01 00 80 E6 02 00 80 E6 02 00 18 ..`. ........... + 03 00 15 16 05 00 01 15 16 05 00 1A 24 03 00 05 ............$... + 80 02 E0 01 A0 00 78 00 40 01 F0 00 B0 00 90 00 ......x.@....... + 60 01 20 01 00 06 24 0D 01 01 04 09 04 01 01 01 `. ...$......... + 0E 02 00 00 07 05 83 05 0C 02 01 09 04 01 02 01 ................ + 0E 02 00 00 07 05 83 05 0C 03 01 09 04 01 03 01 ................ + 0E 02 00 00 07 05 83 05 FC 03 01 09 04 01 04 01 ................ + 0E 02 00 00 07 05 83 05 FC 0B 01 09 04 01 05 01 ................ + 0E 02 00 00 07 05 83 05 FC 13 01 08 0B 02 02 01 ................ + 01 00 00 09 04 02 00 00 01 01 00 00 09 24 01 00 .............$.. + 01 29 00 01 03 0C 24 02 01 01 02 00 01 00 00 00 .)....$......... + 00 0B 24 06 03 01 02 01 00 02 00 00 09 24 03 02 ..$..........$.. + 01 01 00 03 00 09 04 03 00 01 01 02 00 00 09 05 ................ + 84 01 00 00 04 00 00 09 04 03 01 01 01 02 00 00 ................ + 07 24 01 02 01 01 00 0B 24 02 01 01 02 10 01 80 .$......$....... + BB 00 09 05 84 01 80 01 04 00 00 07 25 01 01 00 ............%... + 00 00 .. + + ------------------- IAD Descriptor -------------------- +bLength : 0x08 (8 bytes) +bDescriptorType : 0x0B +bFirstInterface : 0x00 +bInterfaceCount : 0x02 +bFunctionClass : 0x0E (Video) +bFunctionSubClass : 0x03 (Video Interface Collection) +bFunctionProtocol : 0x00 (PC_PROTOCOL_UNDEFINED protocol) +iFunction : 0x02 (String Descriptor 2) + Language 0x0409 : "USB2.0 Camera" +Data (HexDump) : 08 0B 00 02 0E 03 00 02 ........ + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x00 +bAlternateSetting : 0x00 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x01 (Video Control) +bInterfaceProtocol : 0x00 +iInterface : 0x02 (String Descriptor 2) + Language 0x0409 : "USB2.0 Camera" +Data (HexDump) : 09 04 00 00 01 0E 01 00 02 ......... + + ------- Video Control Interface Header Descriptor ----- +bLength : 0x0D (13 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x01 (Video Control Header) +bcdUVC : 0x0100 (UVC Version 1.00) +wTotalLength : 0x004D (77 bytes) +dwClockFreq : 0x01C9C380 (30 MHz) +bInCollection : 0x01 (1 VideoStreaming interface) +baInterfaceNr[1] : 0x01 +Data (HexDump) : 0D 24 01 00 01 4D 00 80 C3 C9 01 01 01 .$...M....... + + -------- Video Control Input Terminal Descriptor ------ +bLength : 0x12 (18 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x02 (Input Terminal) +bTerminalID : 0x01 +wTerminalType : 0x0201 (ITT_CAMERA) +bAssocTerminal : 0x00 (Not associated with an Output Terminal) +iTerminal : 0x00 +Camera Input Terminal Data: +wObjectiveFocalLengthMin : 0x0000 +wObjectiveFocalLengthMax : 0x0000 +wOcularFocalLength : 0x0000 +bControlSize : 0x03 +bmControls : 0x00, 0x00, 0x00 + D00 : 0 no - Scanning Mode + D01 : 0 no - Auto-Exposure Mode + D02 : 0 no - Auto-Exposure Priority + D03 : 0 no - Exposure Time (Absolute) + D04 : 0 no - Exposure Time (Relative) + D05 : 0 no - Focus (Absolute) + D06 : 0 no - Focus (Relative) + D07 : 0 no - Iris (Absolute) + D08 : 0 no - Iris (Relative) + D09 : 0 no - Zoom (Absolute) + D10 : 0 no - Zoom (Relative) + D11 : 0 no - Pan (Absolute) + D12 : 0 no - Pan (Relative) + D13 : 0 no - Roll (Absolute) + D14 : 0 no - Roll (Relative) + D15 : 0 no - Tilt (Absolute) + D16 : 0 no - Tilt (Relative) + D17 : 0 no - Focus Auto + D18 : 0 no - Reserved + D19 : 0 no - Reserved + D20 : 0 no - Reserved + D21 : 0 no - Reserved + D22 : 0 no - Reserved + D23 : 0 no - Reserved +Data (HexDump) : 12 24 02 01 01 02 00 00 00 00 00 00 00 00 03 00 .$.............. + 00 00 .. + + ------- Video Control Output Terminal Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x03 (Output Terminal) +bTerminalID : 0x02 +wTerminalType : 0x0101 (TT_STREAMING) +bAssocTerminal : 0x00 (Not associated with an Input Terminal) +bSourceID : 0x04 +iTerminal : 0x00 +Data (HexDump) : 09 24 03 02 01 01 00 04 00 .$....... + + -------- Video Control Processing Unit Descriptor ----- +bLength : 0x0B (11 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x05 (Processing Unit) +bUnitID : 0x03 +bSourceID : 0x01 +wMaxMultiplier : 0x0000 +bControlSize : 0x02 +bmControls : 0x3B, 0x05 + D00 : 1 yes - Brightness + D01 : 1 yes - Contrast + D02 : 0 no - Hue + D03 : 1 yes - Saturation + D04 : 1 yes - Sharpness + D05 : 1 yes - Gamma + D06 : 0 no - White Balance Temperature + D07 : 0 no - White Balance Component + D08 : 1 yes - Backlight Compensation + D09 : 0 no - Gain + D10 : 1 yes - Power Line Frequency + D11 : 0 no - Hue, Auto + D12 : 0 no - White Balance Temperature, Auto + D13 : 0 no - White Balance Component, Auto + D14 : 0 no - Digital Multiplier + D15 : 0 no - Digital Multiplier Limit +iProcessing : 0x00 +Data (HexDump) : 0B 24 05 03 01 00 00 02 3B 05 00 .$......;.. + + --------- Video Control Extension Unit Descriptor ----- +bLength : 0x1A (26 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x06 (Extension Unit) +bUnitID : 0x04 +guidExtensionCode : {AAB8F252-8ED1-4972-8CED-96B17F04408B} +bNumControls : 0x01 +bNrInPins : 0x01 (1 pins) +baSourceID[1] : 0x03 +bControlSize : 0x01 +bmControls : 0x01 + D0 : 1 yes - Vendor-Specific (Optional) + D1 : 0 no - Vendor-Specific (Optional) + D2 : 0 no - Vendor-Specific (Optional) + D3 : 0 no - Vendor-Specific (Optional) + D4 : 0 no - Vendor-Specific (Optional) + D5 : 0 no - Vendor-Specific (Optional) + D6 : 0 no - Vendor-Specific (Optional) + D7 : 0 no - Vendor-Specific (Optional) +iExtension : 0x00 +Data (HexDump) : 1A 24 06 04 52 F2 B8 AA D1 8E 72 49 8C ED 96 B1 .$..R.....rI.... + 7F 04 40 8B 01 01 03 01 01 00 ..@....... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x85 (Direction=IN EndpointID=5) +bmAttributes : 0x03 (TransferType=Interrupt) +wMaxPacketSize : 0x0040 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x40 (64 bytes per packet) +bInterval : 0x07 (7 ms) +Data (HexDump) : 07 05 85 03 40 00 07 ....@.. + + --- Class-specific VC Interrupt Endpoint Descriptor --- +bLength : 0x05 (5 bytes) +bDescriptorType : 0x25 (Video Control Endpoint) +bDescriptorSubtype : 0x03 (Interrupt) +wMaxTransferSize : 0x0040 (64 bytes) +Data (HexDump) : 05 25 03 40 00 .%.@. + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x00 +bNumEndpoints : 0x00 (Default Control Pipe only) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 00 00 0E 02 00 00 ......... + + ---- VC-Specific VS Video Input Header Descriptor ----- +bLength : 0x0E (14 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x01 (Input Header) +bNumFormats : 0x01 +wTotalLength : 0x00DF (223 bytes) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmInfo : 0x00 (Dynamic Format Change not supported) +bTerminalLink : 0x02 +bStillCaptureMethod : 0x02 (Still Capture Method 2) +nbTriggerSupport : 0x00 (Hardware Triggering not supported) +bTriggerUsage : 0x00 (Host will initiate still image capture) +nbControlSize : 0x01 +Video Payload Format 1 : 0x00 + D0 : 0 no - Key Frame Rate + D1 : 0 no - P Frame Rate + D2 : 0 no - Compression Quality + D3 : 0 no - Compression Window Size + D4 : 0 no - Generate Key Frame + D5 : 0 no - Update Frame Segment + D6 : 0 no - Reserved + D7 : 0 no - Reserved +Data (HexDump) : 0E 24 01 01 DF 00 83 00 02 02 01 00 01 00 .$............ + + ------- VS Uncompressed Format Type Descriptor -------- +bLength : 0x1B (27 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x04 (Uncompressed Format Type) +bFormatIndex : 0x01 (1) +bNumFrameDescriptors : 0x05 (5) +guidFormat : {32595559-0000-0010-8000-00AA00389B71} (YUY2) +bBitsPerPixel : 0x10 (16 bits) +bDefaultFrameIndex : 0x01 (1) +bAspectRatioX : 0x00 +bAspectRatioY : 0x00 +bmInterlaceFlags : 0x00 + D0 IL stream or variable: 0 (no) + D1 Fields per frame : 0 (2 fields) + D2 Field 1 first : 0 (no) + D3 Reserved : 0 + D4..5 Field pattern : 0 (Field 1 only) + D6..7 Display Mode : 0 (Bob only) +bCopyProtect : 0x00 (No restrictions) +Data (HexDump) : 1B 24 04 01 05 59 55 59 32 00 00 10 00 80 00 00 .$...YUY2....... + AA 00 38 9B 71 10 01 00 00 00 00 ..8.q...... + + -------- VS Uncompressed Frame Type Descriptor -------- +---> This is the Default (optimum) Frame index +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x01 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x01E0 (480) +dwMinBitRate : 0x08CA0000 (147456000 bps -> 18.4 MB/s) +dwMaxBitRate : 0x08CA0000 (147456000 bps -> 18.4 MB/s) +dwMaxVideoFrameBufferSize: 0x00096000 (614400 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +Data (HexDump) : 1E 24 05 01 00 80 02 E0 01 00 00 CA 08 00 00 CA .$.............. + 08 00 60 09 00 15 16 05 00 01 15 16 05 00 ..`........... + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x02 +bmCapabilities : 0x00 +wWidth : 0x00A0 (160) +wHeight : 0x0078 (120) +dwMinBitRate : 0x008CA000 (9216000 bps -> 1.1 MB/s) +dwMaxBitRate : 0x008CA000 (9216000 bps -> 1.1 MB/s) +dwMaxVideoFrameBufferSize: 0x00009600 (38400 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +Data (HexDump) : 1E 24 05 02 00 A0 00 78 00 00 A0 8C 00 00 A0 8C .$.....x........ + 00 00 96 00 00 15 16 05 00 01 15 16 05 00 .............. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x03 +bmCapabilities : 0x00 +wWidth : 0x0140 (320) +wHeight : 0x00F0 (240) +dwMinBitRate : 0x02328000 (36864000 bps -> 4.6 MB/s) +dwMaxBitRate : 0x02328000 (36864000 bps -> 4.6 MB/s) +dwMaxVideoFrameBufferSize: 0x00025800 (153600 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +Data (HexDump) : 1E 24 05 03 00 40 01 F0 00 00 80 32 02 00 80 32 .$...@.....2...2 + 02 00 58 02 00 15 16 05 00 01 15 16 05 00 ..X........... + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x04 +bmCapabilities : 0x00 +wWidth : 0x00B0 (176) +wHeight : 0x0090 (144) +dwMinBitRate : 0x00B9A000 (12165120 bps -> 1.5 MB/s) +dwMaxBitRate : 0x00B9A000 (12165120 bps -> 1.5 MB/s) +dwMaxVideoFrameBufferSize: 0x0000C600 (50688 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +Data (HexDump) : 1E 24 05 04 00 B0 00 90 00 00 A0 B9 00 00 A0 B9 .$.............. + 00 00 C6 00 00 15 16 05 00 01 15 16 05 00 .............. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x05 +bmCapabilities : 0x00 +wWidth : 0x0160 (352) +wHeight : 0x0120 (288) +dwMinBitRate : 0x02E68000 (48660480 bps -> 6 MB/s) +dwMaxBitRate : 0x02E68000 (48660480 bps -> 6 MB/s) +dwMaxVideoFrameBufferSize: 0x00031800 (202752 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +Data (HexDump) : 1E 24 05 05 00 60 01 20 01 00 80 E6 02 00 80 E6 .$...`. ........ + 02 00 18 03 00 15 16 05 00 01 15 16 05 00 .............. + + ---------- Still Image Frame Type Descriptor ---------- +bLength : 0x1A (26 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x03 (Still Image Frame Type) +bEndpointAddress : 0x00 (no endpoint) +bNumImageSizePatterns : 0x05 +1: wWidth x wHeight : 0x0280 x 0x01E0 (640 x 480) +2: wWidth x wHeight : 0x00A0 x 0x0078 (160 x 120) +3: wWidth x wHeight : 0x0140 x 0x00F0 (320 x 240) +4: wWidth x wHeight : 0x00B0 x 0x0090 (176 x 144) +5: wWidth x wHeight : 0x0160 x 0x0120 (352 x 288) +bNumCompressionPattern : 0x00 +Data (HexDump) : 1A 24 03 00 05 80 02 E0 01 A0 00 78 00 40 01 F0 .$.........x.@.. + 00 B0 00 90 00 60 01 20 01 00 .....`. .. + + ------- VS Color Matching Descriptor Descriptor ------- +bLength : 0x06 (6 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x0D (Color Matching) +bColorPrimaries : 0x01 (BT.709, sRGB) +bTransferCharacteristics : 0x01 (BT.709) +bMatrixCoefficients : 0x04 (SMPTE 170M) +Data (HexDump) : 06 24 0D 01 01 04 .$.... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x01 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 01 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x020C + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x20C (524 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 0C 02 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x02 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 02 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x030C + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x30C (780 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 0C 03 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x03 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 03 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x03FC + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x3FC (1020 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 FC 03 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x04 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 04 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0BFC + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x01 (1 additional transactions per microframe -> allows 513..1024 byte per packet) + Bits 10..0 : 0x3FC (1020 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 FC 0B 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x05 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 05 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x13FC + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x02 (2 additional transactions per microframe -> allows 683..1024 bytes per packet) + Bits 10..0 : 0x3FC (1020 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 FC 13 01 ....... + + ------------------- IAD Descriptor -------------------- +bLength : 0x08 (8 bytes) +bDescriptorType : 0x0B +bFirstInterface : 0x02 +bInterfaceCount : 0x02 +bFunctionClass : 0x01 (Audio) +bFunctionSubClass : 0x01 (Audio Control) +bFunctionProtocol : 0x00 +iFunction : 0x00 (No String Descriptor) +Data (HexDump) : 08 0B 02 02 01 01 00 00 ........ + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x00 +bNumEndpoints : 0x00 (Default Control Pipe only) +bInterfaceClass : 0x01 (Audio) +bInterfaceSubClass : 0x01 (Audio Control) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 00 00 01 01 00 00 ......... + + ------ Audio Control Interface Header Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x01 (Header) +bcdADC : 0x0100 +wTotalLength : 0x0029 (41 bytes) +bInCollection : 0x01 +baInterfaceNr[1] : 0x03 +Data (HexDump) : 09 24 01 00 01 29 00 01 03 .$...)... + + ------- Audio Control Input Terminal Descriptor ------- +bLength : 0x0C (12 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x02 (Input Terminal) +bTerminalID : 0x01 +wTerminalType : 0x0201 (Microphone) +bAssocTerminal : 0x00 +bNrChannels : 0x01 (1 channel) +wChannelConfig : 0x0000 (-) +iChannelNames : 0x00 (No String Descriptor) +iTerminal : 0x00 (No String Descriptor) +Data (HexDump) : 0C 24 02 01 01 02 00 01 00 00 00 00 .$.......... + + -------- Audio Control Feature Unit Descriptor -------- +bLength : 0x0B (11 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x06 (Feature Unit) +bUnitID : 0x03 (3) +bSourceID : 0x01 (1) +bControlSize : 0x02 (2 bytes per control) +bmaControls[0] : 0x01, 0x00 + D0: Mute : 1 + D1: Volume : 0 + D2: Bass : 0 + D3: Mid : 0 + D4: Treble : 0 + D5: Graphic Equalizer : 0 + D6: Automatic Gain : 0 + D7: Delay : 0 + D8: Bass Boost : 0 + D9: Loudness : 0 + D10: Reserved : 0 + D11: Reserved : 0 + D12: Reserved : 0 + D13: Reserved : 0 + D14: Reserved : 0 + D15: Reserved : 0 +bmaControls[1] : 0x02, 0x00 + D0: Mute : 0 + D1: Volume : 1 + D2: Bass : 0 + D3: Mid : 0 + D4: Treble : 0 + D5: Graphic Equalizer : 0 + D6: Automatic Gain : 0 + D7: Delay : 0 + D8: Bass Boost : 0 + D9: Loudness : 0 + D10: Reserved : 0 + D11: Reserved : 0 + D12: Reserved : 0 + D13: Reserved : 0 + D14: Reserved : 0 + D15: Reserved : 0 +iFeature : 0x00 (No String Descriptor) +Data (HexDump) : 0B 24 06 03 01 02 01 00 02 00 00 .$......... + + ------- Audio Control Output Terminal Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x03 (Output Terminal) +bTerminalID : 0x02 +wTerminalType : 0x0101 (USB streaming) +bAssocTerminal : 0x00 (0) +bSourceID : 0x03 (3) +iTerminal : 0x00 (No String Descriptor) +Data (HexDump) : 09 24 03 02 01 01 00 03 00 .$....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x03 +bAlternateSetting : 0x00 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x01 (Audio) +bInterfaceSubClass : 0x02 (Audio Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 03 00 01 01 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x84 (Direction=IN EndpointID=4) +bmAttributes : 0x01 (TransferType=Isochronous SyncType=None EndpointType=Data) +wMaxPacketSize : 0x0000 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x00 (0 bytes per packet) + *!*ERROR Invalid maximum packet size, should be between 1 and 1024 +bInterval : 0x04 (4 ms) +bRefresh : 0x00 +bSynchAddress : 0x00 +Data (HexDump) : 09 05 84 01 00 00 04 00 00 ......... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x03 +bAlternateSetting : 0x01 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x01 (Audio) +bInterfaceSubClass : 0x02 (Audio Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 03 01 01 01 02 00 00 ......... + + -------- Audio Streaming Interface Descriptor --------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x01 +bTerminalLink : 0x02 +bDelay : 0x01 +wFormatTag : 0x0001 (PCM) +Data (HexDump) : 07 24 01 02 01 01 00 .$..... + + ------- Audio Streaming Format Type Descriptor -------- +bLength : 0x0B (11 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x02 (Format Type) +bFormatType : 0x01 (FORMAT_TYPE_I) +bNrChannels : 0x01 (1 channel) +bSubframeSize : 0x02 (2 bytes per subframe) +bBitResolution : 0x10 (16 bits per sample) +bSamFreqType : 0x01 (supports 1 sample frequence) +tSamFreq[1] : 0x0BB80 (48000 Hz) +Data (HexDump) : 0B 24 02 01 01 02 10 01 80 BB 00 .$......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x84 (Direction=IN EndpointID=4) +bmAttributes : 0x01 (TransferType=Isochronous SyncType=None EndpointType=Data) +wMaxPacketSize : 0x0180 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x180 (384 bytes per packet) +bInterval : 0x04 (4 ms) +bRefresh : 0x00 +bSynchAddress : 0x00 +Data (HexDump) : 09 05 84 01 80 01 04 00 00 ......... + + ----------- Audio Data Endpoint Descriptor ------------ +bLength : 0x07 (7 bytes) +bDescriptorType : 0x25 (Audio Endpoint Descriptor) +bDescriptorSubtype : 0x01 (General) +bmAttributes : 0x01 +bLockDelayUnits : 0x00 +wLockDelay : 0x0000 +Data (HexDump) : 07 25 01 01 00 00 00 .%..... + + ----------------- Device Qualifier Descriptor ----------------- +bLength : 0x0A (10 bytes) +bDescriptorType : 0x06 (Device_qualifier Descriptor) +bcdUSB : 0x200 (USB Version 2.00) +bDeviceClass : 0xEF (Miscellaneous) +bDeviceSubClass : 0x02 +bDeviceProtocol : 0x01 (IAD - Interface Association Descriptor) +bMaxPacketSize0 : 0x40 (64 Bytes) +bNumConfigurations : 0x01 (1 other-speed configuration) +bReserved : 0x00 + + ------------ Other Speed Configuration Descriptor ------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x07 (Other_speed_configuration Descriptor) +wTotalLength : 0x01BC (444 bytes) +bNumInterfaces : 0x04 (4 Interfaces) +bConfigurationValue : 0x01 (Configuration 1) +iConfiguration : 0x00 (No String Descriptor) +bmAttributes : 0x80 + D7: Reserved, set 1 : 0x01 + D6: Self Powered : 0x00 (no) + D5: Remote Wakeup : 0x00 (no) + D4..0: Reserved, set 0 : 0x00 +MaxPower : 0xFA (500 mA) +Data (HexDump) : 09 07 BC 01 04 01 00 80 FA 08 0B 00 02 0E 03 00 ................ + 02 09 04 00 00 01 0E 01 00 02 0D 24 01 00 01 4D ...........$...M + 00 80 C3 C9 01 01 01 12 24 02 01 01 02 00 00 00 ........$....... + 00 00 00 00 00 03 00 00 00 09 24 03 02 01 01 00 ..........$..... + 04 00 0B 24 05 03 01 00 00 02 3B 05 00 1A 24 06 ...$......;...$. + 04 52 F2 B8 AA D1 8E 72 49 8C ED 96 B1 7F 04 40 .R.....rI......@ + 8B 01 01 03 01 01 00 07 05 85 03 40 00 01 05 25 ...........@...% + 03 40 00 09 04 01 00 00 0E 02 00 00 0E 24 01 01 .@...........$.. + 79 00 83 00 02 02 01 00 01 00 1B 24 04 01 02 59 y..........$...Y + 55 59 32 00 00 10 00 80 00 00 AA 00 38 9B 71 10 UY2.........8.q. + 01 00 00 00 00 1E 24 05 01 00 40 01 F0 00 00 C0 ......$...@..... + 5D 00 00 C0 5D 00 00 58 02 00 80 84 1E 00 01 80 ]...]..X........ + 84 1E 00 1E 24 05 02 00 A0 00 78 00 00 E0 2E 00 ....$.....x..... + 00 E0 2E 00 00 96 00 00 40 42 0F 00 01 40 42 0F ........@B...@B. + 00 0E 24 03 00 02 40 01 F0 00 A0 00 78 00 00 06 ..$...@.....x... + 24 0D 01 01 04 09 04 01 01 01 0E 02 00 00 07 05 $............... + 83 05 0C 01 01 09 04 01 02 01 0E 02 00 00 07 05 ................ + 83 05 8C 01 01 09 04 01 03 01 0E 02 00 00 07 05 ................ + 83 05 0C 02 01 09 04 01 04 01 0E 02 00 00 07 05 ................ + 83 05 0C 03 01 09 04 01 05 01 0E 02 00 00 07 05 ................ + 83 05 FC 03 01 08 0B 02 02 01 01 00 00 09 04 02 ................ + 00 00 01 01 00 00 09 24 01 00 01 29 00 01 03 0C .......$...).... + 24 02 01 01 02 00 01 00 00 00 00 0B 24 06 03 01 $...........$... + 02 01 00 02 00 00 09 24 03 02 01 01 00 03 00 09 .......$........ + 04 03 00 01 01 02 00 00 09 05 84 01 00 00 04 00 ................ + 00 09 04 03 01 01 01 02 00 00 07 24 01 02 01 01 ...........$.... + 00 0B 24 02 01 01 02 10 01 80 BB 00 09 05 84 01 ..$............. + 64 00 04 00 00 07 25 01 01 00 00 00 d.....%..... + + ------------------- IAD Descriptor -------------------- +bLength : 0x08 (8 bytes) +bDescriptorType : 0x0B +bFirstInterface : 0x00 +bInterfaceCount : 0x02 +bFunctionClass : 0x0E (Video) +bFunctionSubClass : 0x03 (Video Interface Collection) +bFunctionProtocol : 0x00 (PC_PROTOCOL_UNDEFINED protocol) +iFunction : 0x02 (String Descriptor 2) + Language 0x0409 : "USB2.0 Camera" +Data (HexDump) : 08 0B 00 02 0E 03 00 02 ........ + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x00 +bAlternateSetting : 0x00 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x01 (Video Control) +bInterfaceProtocol : 0x00 +iInterface : 0x02 (String Descriptor 2) + Language 0x0409 : "USB2.0 Camera" +Data (HexDump) : 09 04 00 00 01 0E 01 00 02 ......... + + ------- Video Control Interface Header Descriptor ----- +bLength : 0x0D (13 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x01 (Video Control Header) +bcdUVC : 0x0100 (UVC Version 1.00) +wTotalLength : 0x004D (77 bytes) +dwClockFreq : 0x01C9C380 (30 MHz) +bInCollection : 0x01 (1 VideoStreaming interface) +baInterfaceNr[1] : 0x01 +Data (HexDump) : 0D 24 01 00 01 4D 00 80 C3 C9 01 01 01 .$...M....... + + -------- Video Control Input Terminal Descriptor ------ +bLength : 0x12 (18 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x02 (Input Terminal) +bTerminalID : 0x01 +wTerminalType : 0x0201 (ITT_CAMERA) +bAssocTerminal : 0x00 (Not associated with an Output Terminal) +iTerminal : 0x00 +Camera Input Terminal Data: +wObjectiveFocalLengthMin : 0x0000 +wObjectiveFocalLengthMax : 0x0000 +wOcularFocalLength : 0x0000 +bControlSize : 0x03 +bmControls : 0x00, 0x00, 0x00 + D00 : 0 no - Scanning Mode + D01 : 0 no - Auto-Exposure Mode + D02 : 0 no - Auto-Exposure Priority + D03 : 0 no - Exposure Time (Absolute) + D04 : 0 no - Exposure Time (Relative) + D05 : 0 no - Focus (Absolute) + D06 : 0 no - Focus (Relative) + D07 : 0 no - Iris (Absolute) + D08 : 0 no - Iris (Relative) + D09 : 0 no - Zoom (Absolute) + D10 : 0 no - Zoom (Relative) + D11 : 0 no - Pan (Absolute) + D12 : 0 no - Pan (Relative) + D13 : 0 no - Roll (Absolute) + D14 : 0 no - Roll (Relative) + D15 : 0 no - Tilt (Absolute) + D16 : 0 no - Tilt (Relative) + D17 : 0 no - Focus Auto + D18 : 0 no - Reserved + D19 : 0 no - Reserved + D20 : 0 no - Reserved + D21 : 0 no - Reserved + D22 : 0 no - Reserved + D23 : 0 no - Reserved +Data (HexDump) : 12 24 02 01 01 02 00 00 00 00 00 00 00 00 03 00 .$.............. + 00 00 .. + + ------- Video Control Output Terminal Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x03 (Output Terminal) +bTerminalID : 0x02 +wTerminalType : 0x0101 (TT_STREAMING) +bAssocTerminal : 0x00 (Not associated with an Input Terminal) +bSourceID : 0x04 +iTerminal : 0x00 +Data (HexDump) : 09 24 03 02 01 01 00 04 00 .$....... + + -------- Video Control Processing Unit Descriptor ----- +bLength : 0x0B (11 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x05 (Processing Unit) +bUnitID : 0x03 +bSourceID : 0x01 +wMaxMultiplier : 0x0000 +bControlSize : 0x02 +bmControls : 0x3B, 0x05 + D00 : 1 yes - Brightness + D01 : 1 yes - Contrast + D02 : 0 no - Hue + D03 : 1 yes - Saturation + D04 : 1 yes - Sharpness + D05 : 1 yes - Gamma + D06 : 0 no - White Balance Temperature + D07 : 0 no - White Balance Component + D08 : 1 yes - Backlight Compensation + D09 : 0 no - Gain + D10 : 1 yes - Power Line Frequency + D11 : 0 no - Hue, Auto + D12 : 0 no - White Balance Temperature, Auto + D13 : 0 no - White Balance Component, Auto + D14 : 0 no - Digital Multiplier + D15 : 0 no - Digital Multiplier Limit +iProcessing : 0x00 +Data (HexDump) : 0B 24 05 03 01 00 00 02 3B 05 00 .$......;.. + + --------- Video Control Extension Unit Descriptor ----- +bLength : 0x1A (26 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x06 (Extension Unit) +bUnitID : 0x04 +guidExtensionCode : {AAB8F252-8ED1-4972-8CED-96B17F04408B} +bNumControls : 0x01 +bNrInPins : 0x01 (1 pins) +baSourceID[1] : 0x03 +bControlSize : 0x01 +bmControls : 0x01 + D0 : 1 yes - Vendor-Specific (Optional) + D1 : 0 no - Vendor-Specific (Optional) + D2 : 0 no - Vendor-Specific (Optional) + D3 : 0 no - Vendor-Specific (Optional) + D4 : 0 no - Vendor-Specific (Optional) + D5 : 0 no - Vendor-Specific (Optional) + D6 : 0 no - Vendor-Specific (Optional) + D7 : 0 no - Vendor-Specific (Optional) +iExtension : 0x00 +Data (HexDump) : 1A 24 06 04 52 F2 B8 AA D1 8E 72 49 8C ED 96 B1 .$..R.....rI.... + 7F 04 40 8B 01 01 03 01 01 00 ..@....... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x85 (Direction=IN EndpointID=5) +bmAttributes : 0x03 (TransferType=Interrupt) +wMaxPacketSize : 0x0040 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x40 (64 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 85 03 40 00 01 ....@.. + + --- Class-specific VC Interrupt Endpoint Descriptor --- +bLength : 0x05 (5 bytes) +bDescriptorType : 0x25 (Video Control Endpoint) +bDescriptorSubtype : 0x03 (Interrupt) +wMaxTransferSize : 0x0040 (64 bytes) +Data (HexDump) : 05 25 03 40 00 .%.@. + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x00 +bNumEndpoints : 0x00 (Default Control Pipe only) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 00 00 0E 02 00 00 ......... + + ---- VC-Specific VS Video Input Header Descriptor ----- +bLength : 0x0E (14 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x01 (Input Header) +bNumFormats : 0x01 +wTotalLength : 0x0079 (121 bytes) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmInfo : 0x00 (Dynamic Format Change not supported) +bTerminalLink : 0x02 +bStillCaptureMethod : 0x02 (Still Capture Method 2) +nbTriggerSupport : 0x00 (Hardware Triggering not supported) +bTriggerUsage : 0x00 (Host will initiate still image capture) +nbControlSize : 0x01 +Video Payload Format 1 : 0x00 + D0 : 0 no - Key Frame Rate + D1 : 0 no - P Frame Rate + D2 : 0 no - Compression Quality + D3 : 0 no - Compression Window Size + D4 : 0 no - Generate Key Frame + D5 : 0 no - Update Frame Segment + D6 : 0 no - Reserved + D7 : 0 no - Reserved +Data (HexDump) : 0E 24 01 01 79 00 83 00 02 02 01 00 01 00 .$..y......... + + ------- VS Uncompressed Format Type Descriptor -------- +bLength : 0x1B (27 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x04 (Uncompressed Format Type) +bFormatIndex : 0x01 (1) +bNumFrameDescriptors : 0x02 (2) +guidFormat : {32595559-0000-0010-8000-00AA00389B71} (YUY2) +bBitsPerPixel : 0x10 (16 bits) +bDefaultFrameIndex : 0x01 (1) +bAspectRatioX : 0x00 +bAspectRatioY : 0x00 +bmInterlaceFlags : 0x00 + D0 IL stream or variable: 0 (no) + D1 Fields per frame : 0 (2 fields) + D2 Field 1 first : 0 (no) + D3 Reserved : 0 + D4..5 Field pattern : 0 (Field 1 only) + D6..7 Display Mode : 0 (Bob only) +bCopyProtect : 0x00 (No restrictions) +Data (HexDump) : 1B 24 04 01 02 59 55 59 32 00 00 10 00 80 00 00 .$...YUY2....... + AA 00 38 9B 71 10 01 00 00 00 00 ..8.q...... + + -------- VS Uncompressed Frame Type Descriptor -------- +---> This is the Default (optimum) Frame index +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x01 +bmCapabilities : 0x00 +wWidth : 0x0140 (320) +wHeight : 0x00F0 (240) +dwMinBitRate : 0x005DC000 (6144000 bps -> 768 KB/s) +dwMaxBitRate : 0x005DC000 (6144000 bps -> 768 KB/s) +dwMaxVideoFrameBufferSize: 0x00025800 (153600 bytes) +dwDefaultFrameInterval : 0x001E8480 (200.0000 ms -> 5.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 1E 24 05 01 00 40 01 F0 00 00 C0 5D 00 00 C0 5D .$...@.....]...] + 00 00 58 02 00 80 84 1E 00 01 80 84 1E 00 ..X........... + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x02 +bmCapabilities : 0x00 +wWidth : 0x00A0 (160) +wHeight : 0x0078 (120) +dwMinBitRate : 0x002EE000 (3072000 bps -> 384 KB/s) +dwMaxBitRate : 0x002EE000 (3072000 bps -> 384 KB/s) +dwMaxVideoFrameBufferSize: 0x00009600 (38400 bytes) +dwDefaultFrameInterval : 0x000F4240 (100.0000 ms -> 10.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x000F4240 (100.0000 ms -> 10.000 fps) +Data (HexDump) : 1E 24 05 02 00 A0 00 78 00 00 E0 2E 00 00 E0 2E .$.....x........ + 00 00 96 00 00 40 42 0F 00 01 40 42 0F 00 .....@B...@B.. + + ---------- Still Image Frame Type Descriptor ---------- +bLength : 0x0E (14 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x03 (Still Image Frame Type) +bEndpointAddress : 0x00 (no endpoint) +bNumImageSizePatterns : 0x02 +1: wWidth x wHeight : 0x0140 x 0x00F0 (320 x 240) +2: wWidth x wHeight : 0x00A0 x 0x0078 (160 x 120) +bNumCompressionPattern : 0x00 +Data (HexDump) : 0E 24 03 00 02 40 01 F0 00 A0 00 78 00 00 .$...@.....x.. + + ------- VS Color Matching Descriptor Descriptor ------- +bLength : 0x06 (6 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x0D (Color Matching) +bColorPrimaries : 0x01 (BT.709, sRGB) +bTransferCharacteristics : 0x01 (BT.709) +bMatrixCoefficients : 0x04 (SMPTE 170M) +Data (HexDump) : 06 24 0D 01 01 04 .$.... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x01 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 01 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x010C + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x10C (268 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 0C 01 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x02 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 02 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x018C + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x18C (396 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 8C 01 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x03 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 03 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x020C + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x20C (524 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 0C 02 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x04 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 04 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x030C + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x30C (780 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 0C 03 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x05 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 05 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x03FC + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x3FC (1020 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 83 05 FC 03 01 ....... + + ------------------- IAD Descriptor -------------------- +bLength : 0x08 (8 bytes) +bDescriptorType : 0x0B +bFirstInterface : 0x02 +bInterfaceCount : 0x02 +bFunctionClass : 0x01 (Audio) +bFunctionSubClass : 0x01 (Audio Control) +bFunctionProtocol : 0x00 +iFunction : 0x00 (No String Descriptor) +Data (HexDump) : 08 0B 02 02 01 01 00 00 ........ + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x00 +bNumEndpoints : 0x00 (Default Control Pipe only) +bInterfaceClass : 0x01 (Audio) +bInterfaceSubClass : 0x01 (Audio Control) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 00 00 01 01 00 00 ......... + + ------ Audio Control Interface Header Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x01 (Header) +bcdADC : 0x0100 +wTotalLength : 0x0029 (41 bytes) +bInCollection : 0x01 +baInterfaceNr[1] : 0x03 +Data (HexDump) : 09 24 01 00 01 29 00 01 03 .$...)... + + ------- Audio Control Input Terminal Descriptor ------- +bLength : 0x0C (12 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x02 (Input Terminal) +bTerminalID : 0x01 +wTerminalType : 0x0201 (Microphone) +bAssocTerminal : 0x00 +bNrChannels : 0x01 (1 channel) +wChannelConfig : 0x0000 (-) +iChannelNames : 0x00 (No String Descriptor) +iTerminal : 0x00 (No String Descriptor) +Data (HexDump) : 0C 24 02 01 01 02 00 01 00 00 00 00 .$.......... + + -------- Audio Control Feature Unit Descriptor -------- +bLength : 0x0B (11 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x06 (Feature Unit) +bUnitID : 0x03 (3) +bSourceID : 0x01 (1) +bControlSize : 0x02 (2 bytes per control) +bmaControls[0] : 0x01, 0x00 + D0: Mute : 1 + D1: Volume : 0 + D2: Bass : 0 + D3: Mid : 0 + D4: Treble : 0 + D5: Graphic Equalizer : 0 + D6: Automatic Gain : 0 + D7: Delay : 0 + D8: Bass Boost : 0 + D9: Loudness : 0 + D10: Reserved : 0 + D11: Reserved : 0 + D12: Reserved : 0 + D13: Reserved : 0 + D14: Reserved : 0 + D15: Reserved : 0 +bmaControls[1] : 0x02, 0x00 + D0: Mute : 0 + D1: Volume : 1 + D2: Bass : 0 + D3: Mid : 0 + D4: Treble : 0 + D5: Graphic Equalizer : 0 + D6: Automatic Gain : 0 + D7: Delay : 0 + D8: Bass Boost : 0 + D9: Loudness : 0 + D10: Reserved : 0 + D11: Reserved : 0 + D12: Reserved : 0 + D13: Reserved : 0 + D14: Reserved : 0 + D15: Reserved : 0 +iFeature : 0x00 (No String Descriptor) +Data (HexDump) : 0B 24 06 03 01 02 01 00 02 00 00 .$......... + + ------- Audio Control Output Terminal Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x03 (Output Terminal) +bTerminalID : 0x02 +wTerminalType : 0x0101 (USB streaming) +bAssocTerminal : 0x00 (0) +bSourceID : 0x03 (3) +iTerminal : 0x00 (No String Descriptor) +Data (HexDump) : 09 24 03 02 01 01 00 03 00 .$....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x03 +bAlternateSetting : 0x00 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x01 (Audio) +bInterfaceSubClass : 0x02 (Audio Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 03 00 01 01 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x84 (Direction=IN EndpointID=4) +bmAttributes : 0x01 (TransferType=Isochronous SyncType=None EndpointType=Data) +wMaxPacketSize : 0x0000 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x00 (0 bytes per packet) + *!*ERROR Invalid maximum packet size, should be between 1 and 1024 +bInterval : 0x04 (4 ms) +bRefresh : 0x00 +bSynchAddress : 0x00 +Data (HexDump) : 09 05 84 01 00 00 04 00 00 ......... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x03 +bAlternateSetting : 0x01 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x01 (Audio) +bInterfaceSubClass : 0x02 (Audio Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 03 01 01 01 02 00 00 ......... + + -------- Audio Streaming Interface Descriptor --------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x01 +bTerminalLink : 0x02 +bDelay : 0x01 +wFormatTag : 0x0001 (PCM) +Data (HexDump) : 07 24 01 02 01 01 00 .$..... + + ------- Audio Streaming Format Type Descriptor -------- +bLength : 0x0B (11 bytes) +bDescriptorType : 0x24 (Audio Interface Descriptor) +bDescriptorSubtype : 0x02 (Format Type) +bFormatType : 0x01 (FORMAT_TYPE_I) +bNrChannels : 0x01 (1 channel) +bSubframeSize : 0x02 (2 bytes per subframe) +bBitResolution : 0x10 (16 bits per sample) +bSamFreqType : 0x01 (supports 1 sample frequence) +tSamFreq[1] : 0x0BB80 (48000 Hz) +Data (HexDump) : 0B 24 02 01 01 02 10 01 80 BB 00 .$......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x84 (Direction=IN EndpointID=4) +bmAttributes : 0x01 (TransferType=Isochronous SyncType=None EndpointType=Data) +wMaxPacketSize : 0x0064 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x64 (100 bytes per packet) +bInterval : 0x04 (4 ms) +bRefresh : 0x00 +bSynchAddress : 0x00 +Data (HexDump) : 09 05 84 01 64 00 04 00 00 ....d.... + + ----------- Audio Data Endpoint Descriptor ------------ +bLength : 0x07 (7 bytes) +bDescriptorType : 0x25 (Audio Endpoint Descriptor) +bDescriptorSubtype : 0x01 (General) +bmAttributes : 0x01 +bLockDelayUnits : 0x00 +wLockDelay : 0x0000 +Data (HexDump) : 07 25 01 01 00 00 00 .%..... + + -------------------- String Descriptors ------------------- + ------ String Descriptor 0 ------ +bLength : 0x04 (4 bytes) +bDescriptorType : 0x03 (String Descriptor) +Language ID[0] : 0x0409 (English - United States) +Data (HexDump) : 04 03 09 04 .... + ------ String Descriptor 1 ------ +bLength : 0x2C (44 bytes) +bDescriptorType : 0x03 (String Descriptor) +Language 0x0409 : "AVEO Technology Corp." +Data (HexDump) : 2C 03 41 00 56 00 45 00 4F 00 20 00 54 00 65 00 ,.A.V.E.O. .T.e. + 63 00 68 00 6E 00 6F 00 6C 00 6F 00 67 00 79 00 c.h.n.o.l.o.g.y. + 20 00 43 00 6F 00 72 00 70 00 2E 00 .C.o.r.p... + ------ String Descriptor 2 ------ +bLength : 0x1C (28 bytes) +bDescriptorType : 0x03 (String Descriptor) +Language 0x0409 : "USB2.0 Camera" +Data (HexDump) : 1C 03 55 00 53 00 42 00 32 00 2E 00 30 00 20 00 ..U.S.B.2...0. . + 43 00 61 00 6D 00 65 00 72 00 61 00 C.a.m.e.r.a. diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..bffe29f --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..f8d19a7 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,385 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\uvc_aveo.c + uvc_aveo.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_uvc_main.c + ex_uvc_main.c + 0 + 0 + + + 1 + 3 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\usbh\kmdw_usbh.c + kmdw_usbh.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\usbh\kmdw_uvc.c + kmdw_uvc.c + 0 + 0 + + + 2 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + kdrv_usbh.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + kdrv_gdma.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..1e0f75e --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,653 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + uvc_aveo.c + 1 + ..\..\main_scpu\uvc_aveo.c + + + ex_uvc_main.c + 1 + ..\..\main_scpu\ex_uvc_main.c + + + project.h + 5 + ..\project.h + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_usbh.c + 1 + ..\..\..\..\..\..\mdw\usbh\kmdw_usbh.c + + + kmdw_uvc.c + 1 + ..\..\..\..\..\..\mdw\usbh\kmdw_uvc.c + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_usbh.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + + + kdrv_gdma.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_aveo/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/main_scpu/ex_uvc_main.c b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/main_scpu/ex_uvc_main.c new file mode 100644 index 0000000..98b5384 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/main_scpu/ex_uvc_main.c @@ -0,0 +1,70 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2013-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Name: main.c + * Purpose: RTX for Kneron + * + *---------------------------------------------------------------------------*/ + +#include +#include + +#include "project.h" +#include "cmsis_os2.h" + +#include "kdrv_cmsis_core.h" +#include "kdrv_ddr.h" +#include "kdrv_system.h" + +#include "kmdw_memory.h" +#include "kmdw_console.h" + + +extern void uvc_example_init(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + SystemCoreClockUpdate(); // System Initialization + osKernelInitialize(); // Initialize CMSIS-RTOS + + /* below is some primiary system init settings */ + kdrv_system_init(); // primary system init + kdrv_system_init_ncpu(); // this is a must for ddr + kdrv_ddr_system_init(DDR_INIT_ALL); // enable ddr + + /* below is some middleware init settings */ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // uart console + + /* init the application */ + uvc_example_init(); + + DSG("Starting the USBH UVC example..."); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/main_scpu/uvc_sonix.c b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/main_scpu/uvc_sonix.c new file mode 100644 index 0000000..066dde8 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/main_scpu/uvc_sonix.c @@ -0,0 +1,127 @@ + +#include +#include "cmsis_os2.h" // CMSIS RTOS header file + +#include "kmdw_usbh.h" +#include "kmdw_uvc.h" + +//#define UVC_USER_ERR + +static osThreadId_t usbh_example_uvc_thread; +static USBH_PIPE_HANDLE isoch_pipe; + +extern void kmdw_printf(const char *f, ...); +extern uint32_t kmdw_ddr_reserve(uint32_t numbyte); + +/*---------------------------------------------------------------------------- +* Thread for usb host examples +*---------------------------------------------------------------------------*/ + +void usbh_mdw_uvc_thread(void *argument); // thread function + +void uvc_example_init(void) +{ + usbh_example_uvc_thread = osThreadNew(usbh_mdw_uvc_thread, NULL, NULL); +} + +void usbh_mdw_uvc_thread(void *argument) +{ + usbStatus usb_status; // USB status + + // init USB host through MDK middleware + usb_status = USBH_Initialize(0U); + if (usb_status != usbOK) + { + kmdw_printf("uvc_example: USBH_Initialize() failed\n"); + } + + kmdw_printf("uvc_example: USBH_Initialize() OK\n"); + kmdw_printf("uvc_example: waiting for usb device enumeration\n"); + + // wait for device init done + osThreadFlagsWait(0x01U, osFlagsWaitAny, osWaitForever); + + osDelay(100); // give the camera some time to go ?? + + kmdw_printf("uvc_example: starting isoch transfer..\n"); + + USBH_UVC_PipeStart_Isoch(isoch_pipe); +} + +#define NUM_FRAME 4 +#define FRMAE_SIZE (640 * 480 * 2) // VGA YUV420 + +/************************** Class Driver Functions ****************************/ + +uint8_t USBH_UVC_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc) +{ + kmdw_printf("uvc_example: %s()\n", __FUNCTION__); + + // interface 1, alternate 5 + isoch_pipe = USBH_UVC_PipeCreate_Isoch(device, 0x81, 0x1320, 1); + + // allocate some frame buffers + uint32_t all_frame_buf = kmdw_ddr_reserve(NUM_FRAME * FRMAE_SIZE); + + kmdw_printf("uvc_example: allocated %d bytes start from address 0x%p\n", NUM_FRAME * FRMAE_SIZE, all_frame_buf); + + // queue all frames into UVC middleware + for (int i = 0; i < NUM_FRAME; i++) + USBH_UVC_Queue_Frame(isoch_pipe, (uint32_t *)(all_frame_buf + i * FRMAE_SIZE), FRMAE_SIZE); + + // set class interface 1 altr 0 for VideoStreaming interface + USBH_DeviceRequest_SetInterface(device, 1, 0); + + { + UVC_PROBE_COMMIT_CONTROL uvc_ctrl; + uvc_ctrl.bmHint = 0x0001; + uvc_ctrl.bFormatIndex = 2; + uvc_ctrl.bFrameIndex = 7; + uvc_ctrl.dwFrameInterval = 333333; + uvc_ctrl.wKeyFrameRate = 0; + uvc_ctrl.wPFrameRate = 0; + uvc_ctrl.wCompQuality = 0; + uvc_ctrl.wCompWindowSize = 0; + uvc_ctrl.wDelay = 0; + uvc_ctrl.dwMaxVideoFrameSize = 0; + uvc_ctrl.dwMaxPayloadTransferSize = 0; + + // VideoStreaming request - SET_CUR - Probe Control + USBH_UVC_VS_Control(device, SET_CUR, VS_PROBE_CONTROL, &uvc_ctrl); + + // VideoStreaming request - GET_CUR - Probe Control + USBH_UVC_VS_Control(device, GET_CUR, VS_PROBE_CONTROL, &uvc_ctrl); + + // VideoStreaming request - SET_CUR - Commit Control + USBH_UVC_VS_Control(device, SET_CUR, VS_COMMIT_CONTROL, &uvc_ctrl); + } + + // set class interface 1 altr 5 to start video streaming + USBH_DeviceRequest_SetInterface(device, 1, 5); + + return 0; +} + +usbStatus USBH_UVC_Initialize(uint8_t instance) +{ + // Add code for initializing device + + kmdw_printf("uvc_example: %s()\n", __FUNCTION__); + + osThreadFlagsSet(usbh_example_uvc_thread, 0x01U); + + return usbOK; +} + +void USBH_UVC_Get_Frame(uint32_t *frame_ptr, uint32_t frame_size) +{ +#ifdef UVC_USER_ERR + if (frame_size != FRMAE_SIZE) + kmdw_printf("uvc_example: frame_ptr 0x%p frame_size %u is wrong\n", frame_ptr, frame_size); +#endif + + kmdw_printf("UVC_USER: frame_ptr 0x%p frame_size %u\n", frame_ptr, frame_size); + + // and enqueue this frame to UVC middleware again + USBH_UVC_Queue_Frame(isoch_pipe, frame_ptr, FRMAE_SIZE); +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/readme.txt b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/readme.txt new file mode 100644 index 0000000..7205b05 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/readme.txt @@ -0,0 +1,4 @@ +This example code demonstrates how to use USBD driver API to create a USB device +including descriptors and endpoints setup and use of bulk transfer. + +please refer to usbd_example.c. \ No newline at end of file diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/project.h b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/project.h new file mode 100644 index 0000000..82e157e --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */ +//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */ +//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */ +//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +//#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/Microdia_VID0C45_PID6366 b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/Microdia_VID0C45_PID6366 new file mode 100644 index 0000000..e1de3c4 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/Microdia_VID0C45_PID6366 @@ -0,0 +1,2205 @@ + + =========================== USB Port10 =========================== + +Connection Status : 0x01 (Device is connected) +Port Chain : 1-10 +Properties : 0x01 + IsUserConnectable : yes + PortIsDebugCapable : no + PortHasMultiCompanions : no + PortConnectorIsTypeC : no + + ======================== USB Device ======================== + + +++++++++++++++++ Device Information ++++++++++++++++++ +Device Description : USB Composite Device +Device Path : \\?\usb#vid_0c45&pid_6366#sn0001#{a5dcbf10-6530-11d2-901f-00c04fb951ed} +Device ID : USB\VID_0C45&PID_6366\SN0001 +Hardware IDs : USB\VID_0C45&PID_6366&REV_0100 USB\VID_0C45&PID_6366 +Driver KeyName : {36fc9e60-c465-11cf-8056-444553540000}\0043 (GUID_DEVCLASS_USB) +Driver : \SystemRoot\System32\drivers\usbccgp.sys (Version: 10.0.18362.1 Date: 2019-03-19) +Driver Inf : C:\WINDOWS\inf\usb.inf +Legacy BusType : PNPBus +Class : USB +Class GUID : {36fc9e60-c465-11cf-8056-444553540000} (GUID_DEVCLASS_USB) +Interface GUID : {a5dcbf10-6530-11d2-901f-00c04fb951ed} (GUID_DEVINTERFACE_USB_DEVICE) +Service : usbccgp +Enumerator : USB +Location Info : Port_#0010.Hub_#0001 +Location IDs : PCIROOT(0)#PCI(1400)#USBROOT(0)#USB(10), ACPI(_SB_)#ACPI(PCI0)#ACPI(XHC_)#ACPI(RHUB)#ACPI(HS10) +Container ID : {940f9849-5f87-5764-a6cb-3b282371c5fc} +Manufacturer Info : (標準 USB 主控制器) +Capabilities : 0x94 (Removable, UniqueID, SurpriseRemovalOK) +Status : 0x0180600A (DN_DRIVER_LOADED, DN_STARTED, DN_DISABLEABLE, DN_REMOVABLE, DN_NT_ENUMERATOR, DN_NT_DRIVER) +Problem Code : 0 +Address : 10 +Power State : D0 (supported: D0, D3, wake from D0) + Child Device 1 : WellDo 4.5 (USB 視訊è£ç½®) + DevicePath : \\?\usb#vid_0c45&pid_6366&mi_00#6&183af011&0&0000#{6994ad05-93ef-11d0-a3cc-00a0c9223196} + KernelName : \Device\000000b8 + Device ID : USB\VID_0C45&PID_6366&MI_00\6&183AF011&0&0000 + Class : Camera + + +++++++++++++++++ Registry USB Flags +++++++++++++++++ +HKEY_LOCAL_MACHINE\SYSTEM\CurrentControlSet\Control\usbflags\0C4563660100 + osvc : REG_BINARY 00 00 + + ---------------- Connection Information --------------- +Connection Index : 0x0A (10) +Connection Status : 0x01 (DeviceConnected) +Current Config Value : 0x01 +Device Address : 0x24 (36) +Is Hub : 0x00 (no) +Device Bus Speed : 0x02 (High-Speed) +Number Of Open Pipes : 0x01 (1 pipe to data endpoints) +Pipe[0] : EndpointID=3 Direction=IN ScheduleOffset=0 Type=Interrupt +Data (HexDump) : 0A 00 00 00 12 01 00 02 EF 02 01 40 45 0C 66 63 ...........@E.fc + 00 01 02 01 03 01 01 02 00 24 00 01 00 00 00 01 .........$...... + 00 00 00 07 05 83 03 10 00 06 00 00 00 00 .............. + + --------------- Connection Information V2 ------------- +Connection Index : 0x0A (10) +Length : 0x10 (16 bytes) +SupportedUsbProtocols : 0x03 + Usb110 : 1 (yes) + Usb200 : 1 (yes) + Usb300 : 0 (no) + ReservedMBZ : 0x00 +Flags : 0x00 + DevIsOpAtSsOrHigher : 0 (Is not operating at SuperSpeed or higher) + DevIsSsCapOrHigher : 0 (Is not SuperSpeed capable or higher) + DevIsOpAtSsPlusOrHigher : 0 (Is not operating at SuperSpeedPlus or higher) + DevIsSsPlusCapOrHigher : 0 (Is not SuperSpeedPlus capable or higher) + ReservedMBZ : 0x00 +Data (HexDump) : 0A 00 00 00 10 00 00 00 03 00 00 00 00 00 00 00 ................ + + ---------------------- Device Descriptor ---------------------- +bLength : 0x12 (18 bytes) +bDescriptorType : 0x01 (Device Descriptor) +bcdUSB : 0x200 (USB Version 2.00) +bDeviceClass : 0xEF (Miscellaneous) +bDeviceSubClass : 0x02 +bDeviceProtocol : 0x01 (IAD - Interface Association Descriptor) +bMaxPacketSize0 : 0x40 (64 bytes) +idVendor : 0x0C45 (Sonix Technology Co., Ltd.) +idProduct : 0x6366 +bcdDevice : 0x0100 +iManufacturer : 0x02 (String Descriptor 2) + Language 0x0409 : "WellDo 4.5" +iProduct : 0x01 (String Descriptor 1) + Language 0x0409 : "WellDo 4.5" +iSerialNumber : 0x03 (String Descriptor 3) + Language 0x0409 : "SN0001" +bNumConfigurations : 0x01 (1 Configuration) +Data (HexDump) : 12 01 00 02 EF 02 01 40 45 0C 66 63 00 01 02 01 .......@E.fc.... + 03 01 .. + + ------------------ Configuration Descriptor ------------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x02 (Configuration Descriptor) +wTotalLength : 0x0AAE (2734 bytes) +bNumInterfaces : 0x03 (3 Interfaces) +bConfigurationValue : 0x01 (Configuration 1) +iConfiguration : 0x00 (No String Descriptor) +bmAttributes : 0x80 + D7: Reserved, set 1 : 0x01 + D6: Self Powered : 0x00 (no) + D5: Remote Wakeup : 0x00 (no) + D4..0: Reserved, set 0 : 0x00 +MaxPower : 0xFA (500 mA) +Data (HexDump) : 09 02 AE 0A 03 01 00 80 FA 08 0B 00 03 0E 03 00 ................ + 05 09 04 00 00 01 0E 01 00 05 0E 24 01 00 01 73 ...........$...s + 00 C0 E1 E4 00 02 01 02 09 24 03 05 01 01 00 04 .........$...... + 00 1C 24 06 03 70 33 F0 28 11 63 2E 4A BA 2C 68 ..$..p3.(.c.J.,h + 90 EB 33 40 16 18 01 02 03 FF FF FF 00 1A 24 06 ..3@..........$. + 04 94 73 DF DD 3E 97 27 47 BE D9 04 ED 64 26 DC ..s..>.'G....d&. + 67 08 01 03 01 FF 00 12 24 02 01 01 02 00 00 00 g.......$....... + 00 00 00 00 00 03 0E 20 00 0B 24 05 02 01 00 00 ....... ..$..... + 02 7F 17 00 09 24 03 06 01 01 00 04 00 07 05 83 .....$.......... + 03 10 00 06 05 25 03 80 00 09 04 01 00 00 0E 02 .....%.......... + 00 00 0F 24 01 02 FF 05 81 00 05 00 00 00 01 00 ...$............ + 00 0B 24 06 01 10 00 01 00 00 00 00 32 24 07 01 ..$.........2$.. + 00 80 07 38 04 00 40 E3 09 00 80 53 3B 4D 4A 3F ...8..@....S;MJ? + 00 15 16 05 00 06 15 16 05 00 80 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00 05 .8...K...z...... + 00 00 00 00 80 1A 06 00 20 A1 07 00 2A 2C 0A 00 ........ ...*,.. + 40 42 0F 00 80 84 1E 00 06 24 0D 01 01 04 09 04 @B.......$...... + 02 01 01 0E 02 00 00 07 05 82 05 80 00 01 09 04 ................ + 02 02 01 0E 02 00 00 07 05 82 05 00 01 01 09 04 ................ + 02 03 01 0E 02 00 00 07 05 82 05 20 03 01 09 04 ........... .... + 02 04 01 0E 02 00 00 07 05 82 05 20 0B 01 09 04 ........... .... + 02 05 01 0E 02 00 00 07 05 82 05 20 13 01 09 04 ........... .... + 02 06 01 0E 02 00 00 07 05 82 05 00 14 01 .............. + + ------------------- IAD Descriptor -------------------- +bLength : 0x08 (8 bytes) +bDescriptorType : 0x0B +bFirstInterface : 0x00 +bInterfaceCount : 0x03 +bFunctionClass : 0x0E (Video) +bFunctionSubClass : 0x03 (Video Interface Collection) +bFunctionProtocol : 0x00 (PC_PROTOCOL_UNDEFINED protocol) +iFunction : 0x05 (String Descriptor 5) + Language 0x0409 : "WellDo 4.5" +Data (HexDump) : 08 0B 00 03 0E 03 00 05 ........ + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x00 +bAlternateSetting : 0x00 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x01 (Video Control) +bInterfaceProtocol : 0x00 +iInterface : 0x05 (String Descriptor 5) + Language 0x0409 : "WellDo 4.5" +Data (HexDump) : 09 04 00 00 01 0E 01 00 05 ......... + + ------- Video Control Interface Header Descriptor ----- +bLength : 0x0E (14 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x01 (Video Control Header) +bcdUVC : 0x0100 (UVC Version 1.00) +wTotalLength : 0x0073 (115 bytes) +dwClockFreq : 0x00E4E1C0 (15 MHz) +bInCollection : 0x02 (2 VideoStreaming interfaces) +baInterfaceNr[1] : 0x01 +baInterfaceNr[2] : 0x02 +Data (HexDump) : 0E 24 01 00 01 73 00 C0 E1 E4 00 02 01 02 .$...s........ + + ------- Video Control Output Terminal Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x03 (Output Terminal) +bTerminalID : 0x05 +wTerminalType : 0x0101 (TT_STREAMING) +bAssocTerminal : 0x00 (Not associated with an Input Terminal) +bSourceID : 0x04 +iTerminal : 0x00 +Data (HexDump) : 09 24 03 05 01 01 00 04 00 .$....... + + --------- Video Control Extension Unit Descriptor ----- +bLength : 0x1C (28 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x06 (Extension Unit) +bUnitID : 0x03 +guidExtensionCode : {28F03370-6311-4A2E-BA2C-6890EB334016} +bNumControls : 0x18 +bNrInPins : 0x01 (1 pins) +baSourceID[1] : 0x02 +bControlSize : 0x03 +bmControls : 0xFF, 0xFF, 0xFF + D00 : 1 yes - Vendor-Specific (Optional) + D01 : 1 yes - Vendor-Specific (Optional) + D02 : 1 yes - Vendor-Specific (Optional) + D03 : 1 yes - Vendor-Specific (Optional) + D04 : 1 yes - Vendor-Specific (Optional) + D05 : 1 yes - Vendor-Specific (Optional) + D06 : 1 yes - Vendor-Specific (Optional) + D07 : 1 yes - Vendor-Specific (Optional) + D08 : 1 yes - Vendor-Specific (Optional) + D09 : 1 yes - Vendor-Specific (Optional) + D10 : 1 yes - Vendor-Specific (Optional) + D11 : 1 yes - Vendor-Specific (Optional) + D12 : 1 yes - Vendor-Specific (Optional) + D13 : 1 yes - Vendor-Specific (Optional) + D14 : 1 yes - Vendor-Specific (Optional) + D15 : 1 yes - Vendor-Specific (Optional) + D16 : 1 yes - Vendor-Specific (Optional) + D17 : 1 yes - Vendor-Specific (Optional) + D18 : 1 yes - Vendor-Specific (Optional) + D19 : 1 yes - Vendor-Specific (Optional) + D20 : 1 yes - Vendor-Specific (Optional) + D21 : 1 yes - Vendor-Specific (Optional) + D22 : 1 yes - Vendor-Specific (Optional) + D23 : 1 yes - Vendor-Specific (Optional) +iExtension : 0x00 +Data (HexDump) : 1C 24 06 03 70 33 F0 28 11 63 2E 4A BA 2C 68 90 .$..p3.(.c.J.,h. + EB 33 40 16 18 01 02 03 FF FF FF 00 .3@......... + + --------- Video Control Extension Unit Descriptor ----- +bLength : 0x1A (26 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x06 (Extension Unit) +bUnitID : 0x04 +guidExtensionCode : {DDDF7394-973E-4727-BED9-04ED6426DC67} +bNumControls : 0x08 +bNrInPins : 0x01 (1 pins) +baSourceID[1] : 0x03 +bControlSize : 0x01 +bmControls : 0xFF + D0 : 1 yes - Vendor-Specific (Optional) + D1 : 1 yes - Vendor-Specific (Optional) + D2 : 1 yes - Vendor-Specific (Optional) + D3 : 1 yes - Vendor-Specific (Optional) + D4 : 1 yes - Vendor-Specific (Optional) + D5 : 1 yes - Vendor-Specific (Optional) + D6 : 1 yes - Vendor-Specific (Optional) + D7 : 1 yes - Vendor-Specific (Optional) +iExtension : 0x00 +Data (HexDump) : 1A 24 06 04 94 73 DF DD 3E 97 27 47 BE D9 04 ED .$...s..>.'G.... + 64 26 DC 67 08 01 03 01 FF 00 d&.g...... + + -------- Video Control Input Terminal Descriptor ------ +bLength : 0x12 (18 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x02 (Input Terminal) +bTerminalID : 0x01 +wTerminalType : 0x0201 (ITT_CAMERA) +bAssocTerminal : 0x00 (Not associated with an Output Terminal) +iTerminal : 0x00 +Camera Input Terminal Data: +wObjectiveFocalLengthMin : 0x0000 +wObjectiveFocalLengthMax : 0x0000 +wOcularFocalLength : 0x0000 +bControlSize : 0x03 +bmControls : 0x0E, 0x20, 0x00 + D00 : 0 no - Scanning Mode + D01 : 1 yes - Auto-Exposure Mode + D02 : 1 yes - Auto-Exposure Priority + D03 : 1 yes - Exposure Time (Absolute) + D04 : 0 no - Exposure Time (Relative) + D05 : 0 no - Focus (Absolute) + D06 : 0 no - Focus (Relative) + D07 : 0 no - Iris (Absolute) + D08 : 0 no - Iris (Relative) + D09 : 0 no - Zoom (Absolute) + D10 : 0 no - Zoom (Relative) + D11 : 0 no - Pan (Absolute) + D12 : 0 no - Pan (Relative) + D13 : 1 yes - Roll (Absolute) + D14 : 0 no - Roll (Relative) + D15 : 0 no - Tilt (Absolute) + D16 : 0 no - Tilt (Relative) + D17 : 0 no - Focus Auto + D18 : 0 no - Reserved + D19 : 0 no - Reserved + D20 : 0 no - Reserved + D21 : 0 no - Reserved + D22 : 0 no - Reserved + D23 : 0 no - Reserved +Data (HexDump) : 12 24 02 01 01 02 00 00 00 00 00 00 00 00 03 0E .$.............. + 20 00 . + + -------- Video Control Processing Unit Descriptor ----- +bLength : 0x0B (11 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x05 (Processing Unit) +bUnitID : 0x02 +bSourceID : 0x01 +wMaxMultiplier : 0x0000 +bControlSize : 0x02 +bmControls : 0x7F, 0x17 + D00 : 1 yes - Brightness + D01 : 1 yes - Contrast + D02 : 1 yes - Hue + D03 : 1 yes - Saturation + D04 : 1 yes - Sharpness + D05 : 1 yes - Gamma + D06 : 1 yes - White Balance Temperature + D07 : 0 no - White Balance Component + D08 : 1 yes - Backlight Compensation + D09 : 1 yes - Gain + D10 : 1 yes - Power Line Frequency + D11 : 0 no - Hue, Auto + D12 : 1 yes - White Balance Temperature, Auto + D13 : 0 no - White Balance Component, Auto + D14 : 0 no - Digital Multiplier + D15 : 0 no - Digital Multiplier Limit +iProcessing : 0x00 +Data (HexDump) : 0B 24 05 02 01 00 00 02 7F 17 00 .$......... + + ------- Video Control Output Terminal Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x03 (Output Terminal) +bTerminalID : 0x06 +wTerminalType : 0x0101 (TT_STREAMING) +bAssocTerminal : 0x00 (Not associated with an Input Terminal) +bSourceID : 0x04 +iTerminal : 0x00 +Data (HexDump) : 09 24 03 06 01 01 00 04 00 .$....... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x83 (Direction=IN EndpointID=3) +bmAttributes : 0x03 (TransferType=Interrupt) +wMaxPacketSize : 0x0010 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x10 (16 bytes per packet) +bInterval : 0x06 (6 ms) +Data (HexDump) : 07 05 83 03 10 00 06 ....... + + --- Class-specific VC Interrupt Endpoint Descriptor --- +bLength : 0x05 (5 bytes) +bDescriptorType : 0x25 (Video Control Endpoint) +bDescriptorSubtype : 0x03 (Interrupt) +wMaxTransferSize : 0x0080 (128 bytes) +Data (HexDump) : 05 25 03 80 00 .%... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x00 +bNumEndpoints : 0x00 (Default Control Pipe only) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 00 00 0E 02 00 00 ......... + + ---- VC-Specific VS Video Input Header Descriptor ----- +bLength : 0x0F (15 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x01 (Input Header) +bNumFormats : 0x02 +wTotalLength : 0x05FF (1535 bytes) +bEndpointAddress : 0x81 (Direction=IN EndpointID=1) +bmInfo : 0x00 (Dynamic Format Change not supported) +bTerminalLink : 0x05 +bStillCaptureMethod : 0x00 (No Still Capture) +nbTriggerSupport : 0x00 (Hardware Triggering not supported) +bTriggerUsage : 0x00 (Host will initiate still image capture) +nbControlSize : 0x01 +Video Payload Format 1 : 0x00 + D0 : 0 no - Key Frame Rate + D1 : 0 no - P Frame Rate + D2 : 0 no - Compression Quality + D3 : 0 no - Compression Window Size + D4 : 0 no - Generate Key Frame + D5 : 0 no - Update Frame Segment + D6 : 0 no - Reserved + D7 : 0 no - Reserved +Video Payload Format 2 : 0x00 + D0 : 0 no - Key Frame Rate + D1 : 0 no - P Frame Rate + D2 : 0 no - Compression Quality + D3 : 0 no - Compression Window Size + D4 : 0 no - Generate Key Frame + D5 : 0 no - Update Frame Segment + D6 : 0 no - Reserved + D7 : 0 no - Reserved +Data (HexDump) : 0F 24 01 02 FF 05 81 00 05 00 00 00 01 00 00 .$............. + + ----- Video Streaming MJPEG Format Type Descriptor ---- +bLength : 0x0B (11 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x06 (Format MJPEG) +bFormatIndex : 0x01 (1) +bNumFrameDescriptors : 0x10 (16) +bmFlags : 0x00 (Sample size is not fixed) +bDefaultFrameIndex : 0x01 (1) +bAspectRatioX : 0x00 +bAspectRatioY : 0x00 +bmInterlaceFlags : 0x00 + D0 IL stream or variable: 0 (no) + D1 Fields per frame : 0 (2 fields) + D2 Field 1 first : 0 (no) + D3 Reserved : 0 + D4..5 Field pattern : 0 (Field 1 only) + D6..7 Display Mode : 0 (Bob only) +bCopyProtect : 0x00 (No restrictions) +*!*ERROR: no Color Matching Descriptor for this format +Data (HexDump) : 0B 24 06 01 10 00 01 00 00 00 00 .$......... + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +---> This is the Default (optimum) Frame index +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x01 +bmCapabilities : 0x00 +wWidth : 0x0780 (1920) +wHeight : 0x0438 (1080) +dwMinBitRate : 0x09E34000 (165888000 bps -> 20.7 MB/s) +dwMaxBitRate : 0x3B538000 (995328000 bps -> 124.4 MB/s) +dwMaxVideoFrameBufferSize: 0x003F4A4D (4147789 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 01 00 80 07 38 04 00 40 E3 09 00 80 53 2$.....8..@....S + 3B 4D 4A 3F 00 15 16 05 00 06 15 16 05 00 80 1A ;MJ?............ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x02 +bmCapabilities : 0x00 +wWidth : 0x0500 (1280) +wHeight : 0x02D0 (720) +dwMinBitRate : 0x04650000 (73728000 bps -> 9.2 MB/s) +dwMaxBitRate : 0x1A5E0000 (442368000 bps -> 55.2 MB/s) +dwMaxVideoFrameBufferSize: 0x001C224D (1843789 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 02 00 00 05 D0 02 00 00 65 04 00 00 5E 2$.........e...^ + 1A 4D 22 1C 00 15 16 05 00 06 15 16 05 00 80 1A .M"............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x03 +bmCapabilities : 0x00 +wWidth : 0x0400 (1024) +wHeight : 0x0240 (576) +dwMinBitRate : 0x02D00000 (47185920 bps -> 5.8 MB/s) +dwMaxBitRate : 0x10E00000 (283115520 bps -> 35.3 MB/s) +dwMaxVideoFrameBufferSize: 0x0012024D (1180237 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 03 00 00 04 40 02 00 00 D0 02 00 00 E0 2$.....@........ + 10 4D 02 12 00 15 16 05 00 06 15 16 05 00 80 1A .M.............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x04 +bmCapabilities : 0x00 +wWidth : 0x03C0 (960) +wHeight : 0x02D0 (720) +dwMinBitRate : 0x034BC000 (55296000 bps -> 6.9 MB/s) +dwMaxBitRate : 0x13C68000 (331776000 bps -> 41.4 MB/s) +dwMaxVideoFrameBufferSize: 0x00151A4D (1382989 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 04 00 C0 03 D0 02 00 C0 4B 03 00 80 C6 2$.........K.... + 13 4D 1A 15 00 15 16 05 00 06 15 16 05 00 80 1A .M.............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x05 +bmCapabilities : 0x00 +wWidth : 0x0350 (848) +wHeight : 0x01E0 (480) +dwMinBitRate : 0x01F0E000 (32563200 bps -> 4 MB/s) +dwMaxBitRate : 0x0BA54000 (195379200 bps -> 24.4 MB/s) +dwMaxVideoFrameBufferSize: 0x000C6E4D (814669 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 05 00 50 03 E0 01 00 E0 F0 01 00 40 A5 2$...P........@. + 0B 4D 6E 0C 00 15 16 05 00 06 15 16 05 00 80 1A .Mn............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x06 +bmCapabilities : 0x00 +wWidth : 0x0320 (800) +wHeight : 0x0258 (600) +dwMinBitRate : 0x0249F000 (38400000 bps -> 4.8 MB/s) +dwMaxBitRate : 0x0DBBA000 (230400000 bps -> 28.8 MB/s) +dwMaxVideoFrameBufferSize: 0x000EA84D (960589 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 06 00 20 03 58 02 00 F0 49 02 00 A0 BB 2$... .X...I.... + 0D 4D A8 0E 00 15 16 05 00 06 15 16 05 00 80 1A .M.............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x07 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x01E0 (480) +dwMinBitRate : 0x01770000 (24576000 bps -> 3 MB/s) +dwMaxBitRate : 0x08CA0000 (147456000 bps -> 18.4 MB/s) +dwMaxVideoFrameBufferSize: 0x0009624D (614989 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 07 00 80 02 E0 01 00 00 77 01 00 00 CA 2$.........w.... + 08 4D 62 09 00 15 16 05 00 06 15 16 05 00 80 1A .Mb............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x08 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x0168 (360) +dwMinBitRate : 0x01194000 (18432000 bps -> 2.3 MB/s) +dwMaxBitRate : 0x06978000 (110592000 bps -> 13.8 MB/s) +dwMaxVideoFrameBufferSize: 0x00070A4D (461389 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 08 00 80 02 68 01 00 40 19 01 00 80 97 2$.....h..@..... + 06 4D 0A 07 00 15 16 05 00 06 15 16 05 00 80 1A .M.............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x09 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x0140 (320) +dwMinBitRate : 0x00FA0000 (16384000 bps -> 2 MB/s) +dwMaxBitRate : 0x05DC0000 (98304000 bps -> 12.2 MB/s) +dwMaxVideoFrameBufferSize: 0x0006424D (410189 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 09 00 80 02 40 01 00 00 FA 00 00 00 DC 2$.....@........ + 05 4D 42 06 00 15 16 05 00 06 15 16 05 00 80 1A .MB............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x0A +bmCapabilities : 0x00 +wWidth : 0x01B0 (432) +wHeight : 0x00F0 (240) +dwMinBitRate : 0x007E9000 (8294400 bps -> 1 MB/s) +dwMaxBitRate : 0x02F76000 (49766400 bps -> 6.2 MB/s) +dwMaxVideoFrameBufferSize: 0x00032C4D (207949 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 0A 00 B0 01 F0 00 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+adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 0B 00 60 01 20 01 00 C0 7B 00 00 80 E6 2$...`. ...{.... + 02 4D 1A 03 00 15 16 05 00 06 15 16 05 00 80 1A .M.............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x0C +bmCapabilities : 0x00 +wWidth : 0x0140 (320) +wHeight : 0x00F0 (240) +dwMinBitRate : 0x005DC000 (6144000 bps -> 768 KB/s) +dwMaxBitRate : 0x02328000 (36864000 bps -> 4.6 MB/s) +dwMaxVideoFrameBufferSize: 0x00025A4D (154189 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 0C 00 40 01 F0 00 00 C0 5D 00 00 80 32 2$...@.....]...2 + 02 4D 5A 02 00 15 16 05 00 06 15 16 05 00 80 1A .MZ............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x0D +bmCapabilities : 0x00 +wWidth : 0x0140 (320) +wHeight : 0x00B4 (180) +dwMinBitRate : 0x00465000 (4608000 bps -> 576 KB/s) +dwMaxBitRate : 0x01A5E000 (27648000 bps -> 3.4 MB/s) +dwMaxVideoFrameBufferSize: 0x0001C44D (115789 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 0D 00 40 01 B4 00 00 50 46 00 00 E0 A5 2$...@....PF.... + 01 4D C4 01 00 15 16 05 00 06 15 16 05 00 80 1A .M.............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x0E +bmCapabilities : 0x00 +wWidth : 0x0120 (288) +wHeight : 0x00A0 (160) +dwMinBitRate : 0x00384000 (3686400 bps -> 460.7 KB/s) +dwMaxBitRate : 0x01518000 (22118400 bps -> 2.7 MB/s) +dwMaxVideoFrameBufferSize: 0x00016A4D (92749 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 0E 00 20 01 A0 00 00 40 38 00 00 80 51 2$... ....@8...Q + 01 4D 6A 01 00 15 16 05 00 06 15 16 05 00 80 1A .Mj............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x0F +bmCapabilities : 0x00 +wWidth : 0x00B0 (176) +wHeight : 0x0090 (144) +dwMinBitRate : 0x001EF000 (2027520 bps -> 253.3 KB/s) +dwMaxBitRate : 0x00B9A000 (12165120 bps -> 1.5 MB/s) +dwMaxVideoFrameBufferSize: 0x0000C84D (51277 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 0F 00 B0 00 90 00 00 F0 1E 00 00 A0 B9 2$.............. + 00 4D C8 00 00 15 16 05 00 06 15 16 05 00 80 1A .M.............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- Video Streaming MJPEG Frame Type Descriptor ----- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x07 (MJPEG Frame Type) +bFrameIndex : 0x10 +bmCapabilities : 0x00 +wWidth : 0x0780 (1920) +wHeight : 0x0438 (1080) +dwMinBitRate : 0x09E34000 (165888000 bps -> 20.7 MB/s) +dwMaxBitRate : 0x3B538000 (995328000 bps -> 124.4 MB/s) +dwMaxVideoFrameBufferSize: 0x003F4A4D (4147789 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 07 10 00 80 07 38 04 00 40 E3 09 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Uncompressed Frame Type Descriptor -------- +---> This is the Default (optimum) Frame index +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x01 +bmCapabilities : 0x00 +wWidth : 0x0780 (1920) +wHeight : 0x0438 (1080) +dwMinBitRate : 0x09E34000 (165888000 bps -> 20.7 MB/s) +dwMaxBitRate : 0x09E34000 (165888000 bps -> 20.7 MB/s) +dwMaxVideoFrameBufferSize: 0x003F4800 (4147200 bytes) +dwDefaultFrameInterval : 0x001E8480 (200.0000 ms -> 5.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 1E 24 05 01 00 80 07 38 04 00 40 E3 09 00 40 E3 .$.....8..@...@. + 09 00 48 3F 00 80 84 1E 00 01 80 84 1E 00 ..H?.......... + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x02 +bmCapabilities : 0x00 +wWidth : 0x0500 (1280) +wHeight : 0x02D0 (720) +dwMinBitRate : 0x08CA0000 (147456000 bps -> 18.4 MB/s) +dwMaxBitRate : 0x08CA0000 (147456000 bps -> 18.4 MB/s) +dwMaxVideoFrameBufferSize: 0x001C2000 (1843200 bytes) +dwDefaultFrameInterval : 0x000F4240 (100.0000 ms -> 10.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x000F4240 (100.0000 ms -> 10.000 fps) +Data (HexDump) : 1E 24 05 02 00 00 05 D0 02 00 00 CA 08 00 00 CA .$.............. + 08 00 20 1C 00 40 42 0F 00 01 40 42 0F 00 .. ..@B...@B.. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x22 (34 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x03 +bmCapabilities : 0x00 +wWidth : 0x0400 (1024) +wHeight : 0x0240 (576) +dwMinBitRate : 0x02D00000 (47185920 bps -> 5.8 MB/s) +dwMaxBitRate : 0x05A00000 (94371840 bps -> 11.7 MB/s) +dwMaxVideoFrameBufferSize: 0x00120000 (1179648 bytes) +dwDefaultFrameInterval : 0x000F4240 (100.0000 ms -> 10.000 fps) +bFrameIntervalType : 0x02 (2 discrete frame intervals supported) +adwFrameInterval[1] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[2] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 22 24 05 03 00 00 04 40 02 00 00 D0 02 00 00 A0 "$.....@........ + 05 00 00 12 00 40 42 0F 00 02 40 42 0F 00 80 84 .....@B...@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x22 (34 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x04 +bmCapabilities : 0x00 +wWidth : 0x03C0 (960) +wHeight : 0x02D0 (720) +dwMinBitRate : 0x034BC000 (55296000 bps -> 6.9 MB/s) +dwMaxBitRate : 0x06978000 (110592000 bps -> 13.8 MB/s) +dwMaxVideoFrameBufferSize: 0x00151800 (1382400 bytes) +dwDefaultFrameInterval : 0x000F4240 (100.0000 ms -> 10.000 fps) +bFrameIntervalType : 0x02 (2 discrete frame intervals supported) +adwFrameInterval[1] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[2] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 22 24 05 04 00 C0 03 D0 02 00 C0 4B 03 00 80 97 "$.........K.... + 06 00 18 15 00 40 42 0F 00 02 40 42 0F 00 80 84 .....@B...@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x22 (34 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x05 +bmCapabilities : 0x00 +wWidth : 0x0350 (848) +wHeight : 0x01E0 (480) +dwMinBitRate : 0x01F0E000 (32563200 bps -> 4 MB/s) +dwMaxBitRate : 0x03E1C000 (65126400 bps -> 8.1 MB/s) +dwMaxVideoFrameBufferSize: 0x000C6C00 (814080 bytes) +dwDefaultFrameInterval : 0x000F4240 (100.0000 ms -> 10.000 fps) +bFrameIntervalType : 0x02 (2 discrete frame intervals supported) +adwFrameInterval[1] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[2] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 22 24 05 05 00 50 03 E0 01 00 E0 F0 01 00 C0 E1 "$...P.......... + 03 00 6C 0C 00 40 42 0F 00 02 40 42 0F 00 80 84 ..l..@B...@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x22 (34 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x06 +bmCapabilities : 0x00 +wWidth : 0x0320 (800) +wHeight : 0x0258 (600) +dwMinBitRate : 0x0249F000 (38400000 bps -> 4.8 MB/s) +dwMaxBitRate : 0x0493E000 (76800000 bps -> 9.6 MB/s) +dwMaxVideoFrameBufferSize: 0x000EA600 (960000 bytes) +dwDefaultFrameInterval : 0x000F4240 (100.0000 ms -> 10.000 fps) +bFrameIntervalType : 0x02 (2 discrete frame intervals supported) +adwFrameInterval[1] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[2] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 22 24 05 06 00 20 03 58 02 00 F0 49 02 00 E0 93 "$... .X...I.... + 04 00 A6 0E 00 40 42 0F 00 02 40 42 0F 00 80 84 .....@B...@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x07 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x01E0 (480) +dwMinBitRate : 0x01770000 (24576000 bps -> 3 MB/s) +dwMaxBitRate : 0x08CA0000 (147456000 bps -> 18.4 MB/s) +dwMaxVideoFrameBufferSize: 0x00096000 (614400 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 07 00 80 02 E0 01 00 00 77 01 00 00 CA 2$.........w.... + 08 00 60 09 00 15 16 05 00 06 15 16 05 00 80 1A ..`............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x08 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x0168 (360) +dwMinBitRate : 0x01194000 (18432000 bps -> 2.3 MB/s) +dwMaxBitRate : 0x06978000 (110592000 bps -> 13.8 MB/s) +dwMaxVideoFrameBufferSize: 0x00070800 (460800 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 08 00 80 02 68 01 00 40 19 01 00 80 97 2$.....h..@..... + 06 00 08 07 00 15 16 05 00 06 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x09 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x0140 (320) +dwMinBitRate : 0x00FA0000 (16384000 bps -> 2 MB/s) +dwMaxBitRate : 0x05DC0000 (98304000 bps -> 12.2 MB/s) +dwMaxVideoFrameBufferSize: 0x00064000 (409600 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 09 00 80 02 40 01 00 00 FA 00 00 00 DC 2$.....@........ + 05 00 40 06 00 15 16 05 00 06 15 16 05 00 80 1A ..@............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x0A +bmCapabilities : 0x00 +wWidth : 0x01B0 (432) +wHeight : 0x00F0 (240) +dwMinBitRate : 0x007E9000 (8294400 bps -> 1 MB/s) +dwMaxBitRate : 0x02F76000 (49766400 bps -> 6.2 MB/s) +dwMaxVideoFrameBufferSize: 0x00032A00 (207360 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 0A 00 B0 01 F0 00 00 90 7E 00 00 60 F7 2$.........~..`. + 02 00 2A 03 00 15 16 05 00 06 15 16 05 00 80 1A ..*............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x0B +bmCapabilities : 0x00 +wWidth : 0x0160 (352) +wHeight : 0x0120 (288) +dwMinBitRate : 0x007BC000 (8110080 bps -> 1 MB/s) +dwMaxBitRate : 0x02E68000 (48660480 bps -> 6 MB/s) +dwMaxVideoFrameBufferSize: 0x00031800 (202752 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 0B 00 60 01 20 01 00 C0 7B 00 00 80 E6 2$...`. ...{.... + 02 00 18 03 00 15 16 05 00 06 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x0C +bmCapabilities : 0x00 +wWidth : 0x0140 (320) +wHeight : 0x00F0 (240) +dwMinBitRate : 0x005DC000 (6144000 bps -> 768 KB/s) +dwMaxBitRate : 0x02328000 (36864000 bps -> 4.6 MB/s) +dwMaxVideoFrameBufferSize: 0x00025800 (153600 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 0C 00 40 01 F0 00 00 C0 5D 00 00 80 32 2$...@.....]...2 + 02 00 58 02 00 15 16 05 00 06 15 16 05 00 80 1A ..X............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x0D +bmCapabilities : 0x00 +wWidth : 0x0140 (320) +wHeight : 0x00B4 (180) +dwMinBitRate : 0x00465000 (4608000 bps -> 576 KB/s) +dwMaxBitRate : 0x01A5E000 (27648000 bps -> 3.4 MB/s) +dwMaxVideoFrameBufferSize: 0x0001C200 (115200 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 0D 00 40 01 B4 00 00 50 46 00 00 E0 A5 2$...@....PF.... + 01 00 C2 01 00 15 16 05 00 06 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x0E +bmCapabilities : 0x00 +wWidth : 0x0120 (288) +wHeight : 0x00A0 (160) +dwMinBitRate : 0x00384000 (3686400 bps -> 460.7 KB/s) +dwMaxBitRate : 0x01518000 (22118400 bps -> 2.7 MB/s) +dwMaxVideoFrameBufferSize: 0x00016800 (92160 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 0E 00 20 01 A0 00 00 40 38 00 00 80 51 2$... ....@8...Q + 01 00 68 01 00 15 16 05 00 06 15 16 05 00 80 1A ..h............. + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x0F +bmCapabilities : 0x00 +wWidth : 0x00B0 (176) +wHeight : 0x0090 (144) +dwMinBitRate : 0x001EF000 (2027520 bps -> 253.3 KB/s) +dwMaxBitRate : 0x00B9A000 (12165120 bps -> 1.5 MB/s) +dwMaxVideoFrameBufferSize: 0x0000C600 (50688 bytes) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 05 0F 00 B0 00 90 00 00 F0 1E 00 00 A0 B9 2$.............. + 00 00 C6 00 00 15 16 05 00 06 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + -------- VS Uncompressed Frame Type Descriptor -------- +bLength : 0x1E (30 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x05 (Uncompressed Frame Type) +bFrameIndex : 0x10 +bmCapabilities : 0x00 +wWidth : 0x0780 (1920) +wHeight : 0x0438 (1080) +dwMinBitRate : 0x09E34000 (165888000 bps -> 20.7 MB/s) +dwMaxBitRate : 0x09E34000 (165888000 bps -> 20.7 MB/s) +dwMaxVideoFrameBufferSize: 0x003F4800 (4147200 bytes) +dwDefaultFrameInterval : 0x001E8480 (200.0000 ms -> 5.000 fps) +bFrameIntervalType : 0x01 (1 discrete frame interval supported) +adwFrameInterval[1] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 1E 24 05 10 00 80 07 38 04 00 40 E3 09 00 40 E3 .$.....8..@...@. + 09 00 48 3F 00 80 84 1E 00 01 80 84 1E 00 ..H?.......... + + ------- VS Color Matching Descriptor Descriptor ------- +bLength : 0x06 (6 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x0D (Color Matching) +bColorPrimaries : 0x01 (BT.709, sRGB) +bTransferCharacteristics : 0x01 (BT.709) +bMatrixCoefficients : 0x04 (SMPTE 170M) +Data (HexDump) : 06 24 0D 01 01 04 .$.... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x01 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 01 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x81 (Direction=IN EndpointID=1) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0080 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x80 (128 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 81 05 80 00 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x02 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 02 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x81 (Direction=IN EndpointID=1) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0100 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x100 (256 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 81 05 00 01 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x03 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 03 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x81 (Direction=IN EndpointID=1) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0320 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x320 (800 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 81 05 20 03 01 .... .. + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x04 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 04 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x81 (Direction=IN EndpointID=1) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0B20 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x01 (1 additional transactions per microframe -> allows 513..1024 byte per packet) + Bits 10..0 : 0x320 (800 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 81 05 20 0B 01 .... .. + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x05 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 05 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x81 (Direction=IN EndpointID=1) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x1320 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x02 (2 additional transactions per microframe -> allows 683..1024 bytes per packet) + Bits 10..0 : 0x320 (800 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 81 05 20 13 01 .... .. + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x01 +bAlternateSetting : 0x06 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 01 06 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x81 (Direction=IN EndpointID=1) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x1400 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x02 (2 additional transactions per microframe -> allows 683..1024 bytes per packet) + Bits 10..0 : 0x400 (1024 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 81 05 00 14 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x00 +bNumEndpoints : 0x00 (Default Control Pipe only) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 00 00 0E 02 00 00 ......... + + ---- VC-Specific VS Video Input Header Descriptor ----- +bLength : 0x0E (14 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x01 (Input Header) +bNumFormats : 0x01 +wTotalLength : 0x0344 (836 bytes) +bEndpointAddress : 0x82 (Direction=IN EndpointID=2) +bmInfo : 0x00 (Dynamic Format Change not supported) +bTerminalLink : 0x06 +bStillCaptureMethod : 0x00 (No Still Capture) +nbTriggerSupport : 0x00 (Hardware Triggering not supported) +bTriggerUsage : 0x00 (Host will initiate still image capture) +nbControlSize : 0x01 +Video Payload Format 1 : 0x00 + D0 : 0 no - Key Frame Rate + D1 : 0 no - P Frame Rate + D2 : 0 no - Compression Quality + D3 : 0 no - Compression Window Size + D4 : 0 no - Generate Key Frame + D5 : 0 no - Update Frame Segment + D6 : 0 no - Reserved + D7 : 0 no - Reserved +Data (HexDump) : 0E 24 01 01 44 03 82 00 06 00 00 00 01 00 .$..D......... + + ---- VS Frame Based Payload Format Type Descriptor ---- +*!*ERROR: This format is NOT ALLOWED for UVC 1.0 devices +bLength : 0x1C (28 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x10 (Frame Based Format Type) +bFormatIndex : 0x01 (1) +bNumFrameDescriptors : 0x10 (16) +guidFormat : {34363248-0000-0010-8000-00AA00389B71} (H264) +bBitsPerPixel : 0x10 (16 bits) +bDefaultFrameIndex : 0x01 (1) +bAspectRatioX : 0x00 +bAspectRatioY : 0x00 +bmInterlaceFlags : 0x00 + D0 IL stream or variable: 0 (no) + D1 Fields per frame : 0 (2 fields) + D2 Field 1 first : 0 (no) + D3 Reserved : 0 + D4..5 Field pattern : 0 (Field 1 only) + D6..7 Display Mode : 0 (Bob only) +bCopyProtect : 0x00 (No restrictions) +bVariableSize : 0x01 (Variable Size) +Data (HexDump) : 1C 24 10 01 10 48 32 36 34 00 00 10 00 80 00 00 .$...H264....... + AA 00 38 9B 71 10 01 00 00 00 00 01 ..8.q....... + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x2E (46 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x01 +bmCapabilities : 0x00 +wWidth : 0x0780 (1920) +wHeight : 0x0438 (1080) +dwMinBitRate : 0x034BC000 (55296000 bps -> 6.9 MB/s) +dwMaxBitRate : 0x107AC000 (276480000 bps -> 34.5 MB/s) +dwDefaultFrameInterval : 0x00061A80 (40.0000 ms -> 25.000 fps) +bFrameIntervalType : 0x05 (5 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[2] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[3] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[4] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[5] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 2E 24 11 01 00 80 07 38 04 00 C0 4B 03 00 C0 7A .$.....8...K...z + 10 80 1A 06 00 05 00 00 00 00 80 1A 06 00 20 A1 .............. . + 07 00 2A 2C 0A 00 40 42 0F 00 80 84 1E 00 ..*,..@B...... + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x2E (46 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x02 +bmCapabilities : 0x00 +wWidth : 0x0500 (1280) +wHeight : 0x02D0 (720) +dwMinBitRate : 0x01770000 (24576000 bps -> 3 MB/s) +dwMaxBitRate : 0x07530000 (122880000 bps -> 15.3 MB/s) +dwDefaultFrameInterval : 0x00061A80 (40.0000 ms -> 25.000 fps) +bFrameIntervalType : 0x05 (5 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[2] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[3] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[4] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[5] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 2E 24 11 02 00 00 05 D0 02 00 00 77 01 00 00 53 .$.........w...S + 07 80 1A 06 00 05 00 00 00 00 80 1A 06 00 20 A1 .............. . + 07 00 2A 2C 0A 00 40 42 0F 00 80 84 1E 00 ..*,..@B...... + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x03 +bmCapabilities : 0x00 +wWidth : 0x0400 (1024) +wHeight : 0x0240 (576) +dwMinBitRate : 0x00F00000 (15728640 bps -> 1.9 MB/s) +dwMaxBitRate : 0x05A00000 (94371840 bps -> 11.7 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 03 00 00 04 40 02 00 00 F0 00 00 00 A0 2$.....@........ + 05 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x04 +bmCapabilities : 0x00 +wWidth : 0x03C0 (960) +wHeight : 0x02D0 (720) +dwMinBitRate : 0x01194000 (18432000 bps -> 2.3 MB/s) +dwMaxBitRate : 0x06978000 (110592000 bps -> 13.8 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 04 00 C0 03 D0 02 00 40 19 01 00 80 97 2$........@..... + 06 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x05 +bmCapabilities : 0x00 +wWidth : 0x0350 (848) +wHeight : 0x01E0 (480) +dwMinBitRate : 0x00A5A000 (10854400 bps -> 1.3 MB/s) +dwMaxBitRate : 0x03E1C000 (65126400 bps -> 8.1 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 05 00 50 03 E0 01 00 A0 A5 00 00 C0 E1 2$...P.......... + 03 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x06 +bmCapabilities : 0x00 +wWidth : 0x0320 (800) +wHeight : 0x0258 (600) +dwMinBitRate : 0x00C35000 (12800000 bps -> 1.6 MB/s) +dwMaxBitRate : 0x0493E000 (76800000 bps -> 9.6 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 06 00 20 03 58 02 00 50 C3 00 00 E0 93 2$... .X..P..... + 04 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x07 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x01E0 (480) +dwMinBitRate : 0x007D0000 (8192000 bps -> 1 MB/s) +dwMaxBitRate : 0x02EE0000 (49152000 bps -> 6.1 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 07 00 80 02 E0 01 00 00 7D 00 00 00 EE 2$.........}.... + 02 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x08 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x0168 (360) +dwMinBitRate : 0x005DC000 (6144000 bps -> 768 KB/s) +dwMaxBitRate : 0x02328000 (36864000 bps -> 4.6 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 08 00 80 02 68 01 00 C0 5D 00 00 80 32 2$.....h...]...2 + 02 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x09 +bmCapabilities : 0x00 +wWidth : 0x0280 (640) +wHeight : 0x0140 (320) +dwMinBitRate : 0x00535555 (5461333 bps -> 682.6 KB/s) +dwMaxBitRate : 0x01F40000 (32768000 bps -> 4 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 09 00 80 02 40 01 55 55 53 00 00 00 F4 2$.....@.UUS.... + 01 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x0A +bmCapabilities : 0x00 +wWidth : 0x01B0 (432) +wHeight : 0x00F0 (240) +dwMinBitRate : 0x002A3000 (2764800 bps -> 345.5 KB/s) +dwMaxBitRate : 0x00FD2000 (16588800 bps -> 2 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 0A 00 B0 01 F0 00 00 30 2A 00 00 20 FD 2$........0*.. . + 00 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x0B +bmCapabilities : 0x00 +wWidth : 0x0160 (352) +wHeight : 0x0120 (288) +dwMinBitRate : 0x00294000 (2703360 bps -> 337.8 KB/s) +dwMaxBitRate : 0x00F78000 (16220160 bps -> 2 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 0B 00 60 01 20 01 00 40 29 00 00 80 F7 2$...`. ..@).... + 00 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x0C +bmCapabilities : 0x00 +wWidth : 0x0140 (320) +wHeight : 0x00F0 (240) +dwMinBitRate : 0x001F4000 (2048000 bps -> 256 KB/s) +dwMaxBitRate : 0x00BB8000 (12288000 bps -> 1.5 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 0C 00 40 01 F0 00 00 40 1F 00 00 80 BB 2$...@....@..... + 00 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x0D +bmCapabilities : 0x00 +wWidth : 0x0140 (320) +wHeight : 0x00B4 (180) +dwMinBitRate : 0x00177000 (1536000 bps -> 192 KB/s) +dwMaxBitRate : 0x008CA000 (9216000 bps -> 1.1 MB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 0D 00 40 01 B4 00 00 70 17 00 00 A0 8C 2$...@....p..... + 00 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x0E +bmCapabilities : 0x00 +wWidth : 0x0120 (288) +wHeight : 0x00A0 (160) +dwMinBitRate : 0x0012C000 (1228800 bps -> 153.5 KB/s) +dwMaxBitRate : 0x00708000 (7372800 bps -> 921.5 KB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 0E 00 20 01 A0 00 00 C0 12 00 00 80 70 2$... .........p + 00 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x32 (50 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x0F +bmCapabilities : 0x00 +wWidth : 0x00B0 (176) +wHeight : 0x0090 (144) +dwMinBitRate : 0x000A5000 (675840 bps -> 84.3 KB/s) +dwMaxBitRate : 0x003DE000 (4055040 bps -> 506.8 KB/s) +dwDefaultFrameInterval : 0x00051615 (33.3333 ms -> 30.000 fps) +bFrameIntervalType : 0x06 (6 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00051615 (33.3333 ms -> 30.000 fps) +adwFrameInterval[2] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[3] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[4] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[5] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[6] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 32 24 11 0F 00 B0 00 90 00 00 50 0A 00 00 E0 3D 2$........P....= + 00 15 16 05 00 06 00 00 00 00 15 16 05 00 80 1A ................ + 06 00 20 A1 07 00 2A 2C 0A 00 40 42 0F 00 80 84 .. ...*,..@B.... + 1E 00 .. + + ----- VS Frame Based Payload Frame Type Descriptor ---- +*!*ERROR bDescriptorSubtype did not exist in UVC 1.0 +bLength : 0x2E (46 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x11 (Frame Based Payload Frame Type) +bFrameIndex : 0x10 +bmCapabilities : 0x00 +wWidth : 0x0780 (1920) +wHeight : 0x0438 (1080) +dwMinBitRate : 0x034BC000 (55296000 bps -> 6.9 MB/s) +dwMaxBitRate : 0x107AC000 (276480000 bps -> 34.5 MB/s) +dwDefaultFrameInterval : 0x00061A80 (40.0000 ms -> 25.000 fps) +bFrameIntervalType : 0x05 (5 discrete frame intervals supported) +dwBytesPerLine : 0x00 (0 bytes) +adwFrameInterval[1] : 0x00061A80 (40.0000 ms -> 25.000 fps) +adwFrameInterval[2] : 0x0007A120 (50.0000 ms -> 20.000 fps) +adwFrameInterval[3] : 0x000A2C2A (66.6666 ms -> 15.000 fps) +adwFrameInterval[4] : 0x000F4240 (100.0000 ms -> 10.000 fps) +adwFrameInterval[5] : 0x001E8480 (200.0000 ms -> 5.000 fps) +Data (HexDump) : 2E 24 11 10 00 80 07 38 04 00 C0 4B 03 00 C0 7A .$.....8...K...z + 10 80 1A 06 00 05 00 00 00 00 80 1A 06 00 20 A1 .............. . + 07 00 2A 2C 0A 00 40 42 0F 00 80 84 1E 00 ..*,..@B...... + + ------- VS Color Matching Descriptor Descriptor ------- +bLength : 0x06 (6 bytes) +bDescriptorType : 0x24 (Video Streaming Interface) +bDescriptorSubtype : 0x0D (Color Matching) +bColorPrimaries : 0x01 (BT.709, sRGB) +bTransferCharacteristics : 0x01 (BT.709) +bMatrixCoefficients : 0x04 (SMPTE 170M) +Data (HexDump) : 06 24 0D 01 01 04 .$.... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x01 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 01 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x82 (Direction=IN EndpointID=2) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0080 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x80 (128 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 82 05 80 00 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x02 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 02 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x82 (Direction=IN EndpointID=2) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0100 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x100 (256 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 82 05 00 01 01 ....... + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x03 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 03 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x82 (Direction=IN EndpointID=2) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0320 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x00 (0 additional transactions per microframe -> allows 1..1024 bytes per packet) + Bits 10..0 : 0x320 (800 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 82 05 20 03 01 .... .. + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x04 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 04 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x82 (Direction=IN EndpointID=2) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x0B20 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x01 (1 additional transactions per microframe -> allows 513..1024 byte per packet) + Bits 10..0 : 0x320 (800 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 82 05 20 0B 01 .... .. + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x05 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 05 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x82 (Direction=IN EndpointID=2) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x1320 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x02 (2 additional transactions per microframe -> allows 683..1024 bytes per packet) + Bits 10..0 : 0x320 (800 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 82 05 20 13 01 .... .. + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x02 +bAlternateSetting : 0x06 +bNumEndpoints : 0x01 (1 Endpoint) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x02 (Video Streaming) +bInterfaceProtocol : 0x00 +iInterface : 0x00 (No String Descriptor) +Data (HexDump) : 09 04 02 06 01 0E 02 00 00 ......... + + ----------------- Endpoint Descriptor ----------------- +bLength : 0x07 (7 bytes) +bDescriptorType : 0x05 (Endpoint Descriptor) +bEndpointAddress : 0x82 (Direction=IN EndpointID=2) +bmAttributes : 0x05 (TransferType=Isochronous SyncType=Asynchronous EndpointType=Data) +wMaxPacketSize : 0x1400 + Bits 15..13 : 0x00 (reserved, must be zero) + Bits 12..11 : 0x02 (2 additional transactions per microframe -> allows 683..1024 bytes per packet) + Bits 10..0 : 0x400 (1024 bytes per packet) +bInterval : 0x01 (1 ms) +Data (HexDump) : 07 05 82 05 00 14 01 ....... + + ----------------- Device Qualifier Descriptor ----------------- +bLength : 0x0A (10 bytes) +bDescriptorType : 0x06 (Device_qualifier Descriptor) +bcdUSB : 0x200 (USB Version 2.00) +bDeviceClass : 0xEF (Miscellaneous) +bDeviceSubClass : 0x02 +bDeviceProtocol : 0x01 (IAD - Interface Association Descriptor) +bMaxPacketSize0 : 0x40 (64 Bytes) +bNumConfigurations : 0x01 (1 other-speed configuration) +bReserved : 0x00 + + ------------ Other Speed Configuration Descriptor ------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x07 (Other_speed_configuration Descriptor) +wTotalLength : 0x0040 (64 bytes) +bNumInterfaces : 0x01 (1 Interface) +bConfigurationValue : 0x01 (Configuration 1) +iConfiguration : 0x00 (No String Descriptor) +bmAttributes : 0x80 + D7: Reserved, set 1 : 0x01 + D6: Self Powered : 0x00 (no) + D5: Remote Wakeup : 0x00 (no) + D4..0: Reserved, set 0 : 0x00 +MaxPower : 0xFA (500 mA) +Data (HexDump) : 09 07 40 00 01 01 00 80 FA 08 0B 00 01 0E 03 00 ..@............. + 01 09 04 00 00 00 0E 01 00 01 0C 24 01 00 01 26 ...........$...& + 00 80 8D 5B 00 00 09 24 03 05 01 01 00 02 00 11 ...[...$........ + 24 02 01 01 02 00 00 00 00 00 00 00 00 02 00 00 $............... + + ------------------- IAD Descriptor -------------------- +bLength : 0x08 (8 bytes) +bDescriptorType : 0x0B +bFirstInterface : 0x00 +bInterfaceCount : 0x01 +*!*ERROR bInterfaceCount must be greater than 1 +bFunctionClass : 0x0E (Video) +bFunctionSubClass : 0x03 (Video Interface Collection) +bFunctionProtocol : 0x00 (PC_PROTOCOL_UNDEFINED protocol) +iFunction : 0x01 (String Descriptor 1) + Language 0x0409 : "WellDo 4.5" +Data (HexDump) : 08 0B 00 01 0E 03 00 01 ........ + + ---------------- Interface Descriptor ----------------- +bLength : 0x09 (9 bytes) +bDescriptorType : 0x04 (Interface Descriptor) +bInterfaceNumber : 0x00 +bAlternateSetting : 0x00 +bNumEndpoints : 0x00 (Default Control Pipe only) +bInterfaceClass : 0x0E (Video) +bInterfaceSubClass : 0x01 (Video Control) +bInterfaceProtocol : 0x00 +iInterface : 0x01 (String Descriptor 1) + Language 0x0409 : "WellDo 4.5" +Data (HexDump) : 09 04 00 00 00 0E 01 00 01 ......... + + ------- Video Control Interface Header Descriptor ----- +bLength : 0x0C (12 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x01 (Video Control Header) +bcdUVC : 0x0100 (UVC Version 1.00) +wTotalLength : 0x0026 (38 bytes) +dwClockFreq : 0x005B8D80 (6 MHz) +bInCollection : 0x00 (0 VideoStreaming interface) +Data (HexDump) : 0C 24 01 00 01 26 00 80 8D 5B 00 00 .$...&...[.. + + ------- Video Control Output Terminal Descriptor ------ +bLength : 0x09 (9 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x03 (Output Terminal) +bTerminalID : 0x05 +wTerminalType : 0x0101 (TT_STREAMING) +bAssocTerminal : 0x00 (Not associated with an Input Terminal) +bSourceID : 0x02 +iTerminal : 0x00 +Data (HexDump) : 09 24 03 05 01 01 00 02 00 .$....... + + -------- Video Control Input Terminal Descriptor ------ +bLength : 0x11 (17 bytes) +bDescriptorType : 0x24 (Video Control Interface) +bDescriptorSubtype : 0x02 (Input Terminal) +bTerminalID : 0x01 +wTerminalType : 0x0201 (ITT_CAMERA) +bAssocTerminal : 0x00 (Not associated with an Output Terminal) +iTerminal : 0x00 +Camera Input Terminal Data: +wObjectiveFocalLengthMin : 0x0000 +wObjectiveFocalLengthMax : 0x0000 +wOcularFocalLength : 0x0000 +bControlSize : 0x02 +bmControls : 0x00, 0x00 + D00 : 0 no - Scanning Mode + D01 : 0 no - Auto-Exposure Mode + D02 : 0 no - Auto-Exposure Priority + D03 : 0 no - Exposure Time (Absolute) + D04 : 0 no - Exposure Time (Relative) + D05 : 0 no - Focus (Absolute) + D06 : 0 no - Focus (Relative) + D07 : 0 no - Iris (Absolute) + D08 : 0 no - Iris (Relative) + D09 : 0 no - Zoom (Absolute) + D10 : 0 no - Zoom (Relative) + D11 : 0 no - Pan (Absolute) + D12 : 0 no - Pan (Relative) + D13 : 0 no - Roll (Absolute) + D14 : 0 no - Roll (Relative) + D15 : 0 no - Tilt (Absolute) +Data (HexDump) : 11 24 02 01 01 02 00 00 00 00 00 00 00 00 02 00 .$.............. + 00 . + + -------------------- String Descriptors ------------------- + ------ String Descriptor 0 ------ +bLength : 0x04 (4 bytes) +bDescriptorType : 0x03 (String Descriptor) +Language ID[0] : 0x0409 (English - United States) +Data (HexDump) : 04 03 09 04 .... + ------ String Descriptor 1 ------ +bLength : 0x16 (22 bytes) +bDescriptorType : 0x03 (String Descriptor) +Language 0x0409 : "WellDo 4.5" +Data (HexDump) : 16 03 57 00 65 00 6C 00 6C 00 44 00 6F 00 20 00 ..W.e.l.l.D.o. . + 34 00 2E 00 35 00 4...5. + ------ String Descriptor 2 ------ +bLength : 0x16 (22 bytes) +bDescriptorType : 0x03 (String Descriptor) +Language 0x0409 : "WellDo 4.5" +Data (HexDump) : 16 03 57 00 65 00 6C 00 6C 00 44 00 6F 00 20 00 ..W.e.l.l.D.o. . + 34 00 2E 00 35 00 4...5. + ------ String Descriptor 3 ------ +bLength : 0x0E (14 bytes) +bDescriptorType : 0x03 (String Descriptor) +Language 0x0409 : "SN0001" +Data (HexDump) : 0E 03 53 00 4E 00 30 00 30 00 30 00 31 00 ..S.N.0.0.0.1. + ------ String Descriptor 5 ------ +bLength : 0x16 (22 bytes) +bDescriptorType : 0x03 (String Descriptor) +Language 0x0409 : "WellDo 4.5" +Data (HexDump) : 16 03 57 00 65 00 6C 00 6C 00 44 00 6F 00 20 00 ..W.e.l.l.D.o. . + 34 00 2E 00 35 00 4...5. diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h new file mode 100644 index 0000000..bffe29f --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/RTE/_scpu/RTE_Components.h @@ -0,0 +1,24 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'scpu' + * Target: 'scpu' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "ARMCM4_FP.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Library:5.5.1 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..da4eafb --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,373 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\uvc_sonix.c + uvc_sonix.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_uvc_main.c + ex_uvc_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 3 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\usbh\kmdw_usbh.c + kmdw_usbh.c + 0 + 0 + + + 2 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\usbh\kmdw_uvc.c + kmdw_uvc.c + 0 + 0 + + + 2 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + kdrv_usbh.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + kdrv_gdma.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..a925499 --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,648 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4099 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\..\include;..\..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\..\platform\kl520\common;..\..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\..\scpu\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + uvc_sonix.c + 1 + ..\..\main_scpu\uvc_sonix.c + + + ex_uvc_main.c + 1 + ..\..\main_scpu\ex_uvc_main.c + + + + + mdw + + + kmdw_memory.c + 1 + ..\..\..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_usbh.c + 1 + ..\..\..\..\..\..\mdw\usbh\kmdw_usbh.c + + + kmdw_uvc.c + 1 + ..\..\..\..\..\..\mdw\usbh\kmdw_uvc.c + + + kmdw_console.c + 1 + ..\..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_ddr.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_clock.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_usbh.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_usbh.c + + + kdrv_gdma.c + 1 + ..\..\..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/usb/usbh_mdw_uvc_sonix/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/example_kdrv/wdt/main_scpu/ex_wdt_main.c b/build/example_kdrv/wdt/main_scpu/ex_wdt_main.c new file mode 100644 index 0000000..83f513c --- /dev/null +++ b/build/example_kdrv/wdt/main_scpu/ex_wdt_main.c @@ -0,0 +1,27 @@ +#include +#include +#include "cmsis_os2.h" +#include "project.h" +#include "kdrv_system.h" +#include "kdrv_cmsis_core.h" +#include "kdrv_uart.h" +#include "base.h" +#include "io.h" + +extern void wdt_test_main(void); + +/** + * @brief main, main dispatch function + */ +int main(void) +{ + kdrv_system_init(); + kdrv_uart_initialize(); + kdrv_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE, NULL); // for log + wdt_test_main(); + SystemCoreClockUpdate(); // System Initialization + + osKernelInitialize(); // Initialize CMSIS-RTOS + while(1) { + } +} diff --git a/build/example_kdrv/wdt/main_scpu/kdp_wdt_main.c b/build/example_kdrv/wdt/main_scpu/kdp_wdt_main.c new file mode 100644 index 0000000..da7ad71 --- /dev/null +++ b/build/example_kdrv/wdt/main_scpu/kdp_wdt_main.c @@ -0,0 +1,207 @@ +/* + * Kneron WDT test code driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include "kdrv_cmsis_core.h" +#include "io.h" +#include "kdrv_pwm.h" +#include "time.h" +#include "kdrv_wdt.h" +#include "kdrv_uart.h" +#include "kmdw_console.h" + + +volatile uint32_t wd_int_flag; + +#define QC_MODE 0x80 + +#define EXIT_TUBE_FAIL false +#define EXIT_TUBE_PASS true + +/** + * @brief wdt_isr(), WDT ISR function + */ +void wdt_isr() +{ + wd_int_flag = 1; + DSG("\n\rWDT Interrupt occured\n"); + kdrv_wdt_set_clear_status(); +} + + + +void wdt_start(void) +{ + kdrv_wdt_set_int_counter(0xff); //signal asserting 256 clock cycles + kdrv_wdt_set_auto_reload(APB_CLOCK); + kdrv_wdt_reset(); + kdrv_wdt_enable(); //Enable WDT +} + + +void reset_board() +{ + kdrv_wdt_disable(); + kdrv_wdt_set_int_counter(1); + kdrv_wdt_set_auto_reload(1); + kdrv_wdt_reset(); + kdrv_wdt_enable(); //Enable WDT + kdrv_wdt_sys_reset_enable(); +} + + +// -------------------------------------------------------------------- +// check whether watch dog will generate interrupt (should within 1 sec) within 3 sec +// -------------------------------------------------------------------- +int wdt_test(uint32_t mode) +{ + uint32_t j; + int result = 0; + unsigned long start_jiffies; + char buf[40]; + + DSG("\rWatchDog Test...\n"); + if (mode & QC_MODE) { + j=(mode & 0xF); + } else { + //DSG("Please select clock source:(1)PCLK (2)32.768KHz(external)\r\n"); + DSG("Please select clock source:(1)PCLK \r\n"); + kdrv_uart_read(DRVUART_PORT0, (uint8_t *)buf, 1); + j=atoi(buf); + } + + if(j == 1) { + //*(unsigned int *)(REG_WDT_CR)=*(unsigned int *)(REG_WDT_CR)&(~0x10); + outw(REG_WDT_CR, inw(REG_WDT_CR) & ~WDT_CR_EXTCLK); + //} else if(j == 2) { + // //*(unsigned int *)(REG_WDT_CR)=*(unsigned int *)(REG_WDT_CR)| (0x10); + // outw(REG_WDT_CR, inw(REG_WDT_CR) | WDT_CR_EXTCLK); + } else { + return 0; + } + /* set initial status */ + wd_int_flag = 0; + result = false; + + kdrv_wdt_disable(); + kdrv_wdt_sys_int_enable(); + NVIC_EnableIRQ(WDT_FTWDT010_IRQ); + + wdt_start(); + + start_jiffies = kdrv_current_t1_tick(); + DSG("\rstart!\n"); + while (wd_int_flag == 0) { + if ((kdrv_current_t1_tick() - start_jiffies) >= (3*1000)) { + /* msTicks* >= (3*1000) // JIFF_TO_SEC(jiffies - start_jiffies) >= 3*1000), 3sec */ + break; + } + } + + if (wd_int_flag == 1) + result = true; + + kdrv_wdt_disable(); + NVIC_DisableIRQ(WDT_FTWDT010_IRQ); + + if (result) { + DSG("\rPass!\n"); + result = 1; + } else { + DSG("\rFail!\n"); + result = 0; + } + + DSG("End WatchDog Test!\n"); + + return result; +} + + +#define LOOP_RESET_COUNTER 0x50000 /// program will continue to reset watch dog counter +/// when loop count is lower than this value +#define LOOP_END_TEST 0x2000000 /// if loop count reach this value and still not hw reset +/// then watch dog is fail +// -------------------------------------------------------------------- +// check whether watchDog restart is useful (can stop watch dog to reboot) +// 1. for loop to execute watchdog restart +// 2. after reach LOOP_RESET_COUNTER, wait for cpu reset +// -------------------------------------------------------------------- +void wdt_reset_test() +{ + int i; + + kdrv_wdt_disable(); + kdrv_wdt_sys_reset_enable(); + wdt_start(); + + DSG("Running\n"); + + for (i=0; icritical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c b/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..b2fa58c --- /dev/null +++ b/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" +#include "kmdw_power_manager.h" +#include "kmdw_console.h" + +__WEAK __NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + while(1); +} + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + kmdw_power_manager_cpu_idle(); +} + +__WEAK void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; +#if 0 + err_msg("scpu: osRtxErrorNotify: code=%d, object_id=0x%p\n", code, object_id); + + switch (code) { + case osRtxErrorStackUnderflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +#else + kmdw_power_manager_error_notify(code, object_id); + return 0; +#endif +} diff --git a/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h b/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..74bb73f --- /dev/null +++ b/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,544 @@ +/* + * Copyright (c) 2013-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.4.0 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 4096 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 4096 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 1 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 10 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 10 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 256 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 1024 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 256 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 256 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch. +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 1 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 256 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 256 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial event filter settings applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Event filter settings for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Filter enable settings for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_FILTER +#define OS_EVR_MEMORY_FILTER 0x81U +#endif + +// Kernel +// Filter enable settings for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_FILTER +#define OS_EVR_KERNEL_FILTER 0x81U +#endif + +// Thread +// Filter enable settings for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_FILTER +#define OS_EVR_THREAD_FILTER 0x85U +#endif + +// Timer +// Filter enable settings for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_FILTER +#define OS_EVR_TIMER_FILTER 0x81U +#endif + +// Event Flags +// Filter enable settings for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_FILTER +#define OS_EVR_EVFLAGS_FILTER 0x81U +#endif + +// Mutex +// Filter enable settings for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_FILTER +#define OS_EVR_MUTEX_FILTER 0x81U +#endif + +// Semaphore +// Filter enable settings for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_FILTER +#define OS_EVR_SEMAPHORE_FILTER 0x81U +#endif + +// Memory Pool +// Filter enable settings for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_FILTER +#define OS_EVR_MEMPOOL_FILTER 0x81U +#endif + +// Message Queue +// Filter enable settings for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_FILTER +#define OS_EVR_MSGQUEUE_FILTER 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#define OS_THREAD_LIBSPACE_NUM 4 +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s b/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s new file mode 100644 index 0000000..2e8eb67 --- /dev/null +++ b/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/startup_ARMCM4.s @@ -0,0 +1,162 @@ +;/**************************************************************************//** +; * @file startup_ARMCM4.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device +; * @version V5.3.1 +; * @date 09. July 2018 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2018 Arm Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00004000 + AREA STACK, NOINIT, READWRITE, ALIGN=3 +__stack_limit +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00002000 + + IF Heap_Size != 0 ; Heap is provided + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + ENDIF + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; -14 NMI Handler + DCD HardFault_Handler ; -13 Hard Fault Handler + DCD MemManage_Handler ; -12 MPU Fault Handler + DCD BusFault_Handler ; -11 Bus Fault Handler + DCD UsageFault_Handler ; -10 Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; -5 SVCall Handler + DCD DebugMon_Handler ; -4 Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; -2 PendSV Handler + DCD SysTick_Handler ; -1 SysTick Handler + + ; Interrupts + DCD Interrupt0_Handler ; 0 Interrupt 0 + DCD Interrupt1_Handler ; 1 Interrupt 1 + DCD Interrupt2_Handler ; 2 Interrupt 2 + DCD AHB_DMA_IRQHandler ; 3 Interrupt 3 + DCD Interrupt4_Handler ; 4 Interrupt 4 + DCD Interrupt5_Handler ; 5 Interrupt 5 + DCD Interrupt6_Handler ; 6 Interrupt 6 + DCD Interrupt7_Handler ; 7 Interrupt 7 + DCD Interrupt8_Handler ; 8 Interrupt 8 + DCD Interrupt9_Handler ; 9 Interrupt 9 + + SPACE (214 * 4) ; Interrupts 10 .. 224 are left out +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Macro to define default exception/interrupt handlers. +; Default handler are weak symbols with an endless loop. +; They can be overwritten by real handlers. + MACRO + Set_Default_Handler $Handler_Name +$Handler_Name PROC + EXPORT $Handler_Name [WEAK] + B . + ENDP + MEND + + +; Default exception/interrupt handler + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler Interrupt0_Handler + Set_Default_Handler Interrupt1_Handler + Set_Default_Handler Interrupt2_Handler + Set_Default_Handler AHB_DMA_IRQHandler + Set_Default_Handler Interrupt4_Handler + Set_Default_Handler Interrupt5_Handler + Set_Default_Handler Interrupt6_Handler + Set_Default_Handler Interrupt7_Handler + Set_Default_Handler Interrupt8_Handler + Set_Default_Handler Interrupt9_Handler + + ALIGN + + +; User setup Stack & Heap + + EXPORT __stack_limit + EXPORT __initial_sp + IF Heap_Size != 0 ; Heap is provided + EXPORT __heap_base + EXPORT __heap_limit + ENDIF + + END diff --git a/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c b/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c new file mode 100644 index 0000000..82bd7ed --- /dev/null +++ b/build/example_kdrv/wdt/sn52096/scpu_keil/RTE/Device/ARMCM4_FP/system_ARMCM4.c @@ -0,0 +1,89 @@ +/**************************************************************************//** + * @file system_ARMCM4.c + * @brief CMSIS Device System Source File for + * ARMCM4 Device + * @version V5.3.1 + * @date 09. July 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM4) +// #include "ARMCM4.h" + #include "kdrv_cmsis_core.h" +#elif defined (ARMCM4_FP) +// #include "ARMCM4_FP.h" + #include "kdrv_cmsis_core.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#ifdef KL520 +#define XTAL (200000000UL) /* Oscillator frequency */ +#else +#define XTAL (50000000UL) /* Oscillator frequency */ +#endif + +#define SYSTEM_CLOCK XTAL + + +/*---------------------------------------------------------------------------- + Externals + *----------------------------------------------------------------------------*/ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + extern uint32_t __Vectors; +#endif + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t) &__Vectors; +#endif + +#if defined (__FPU_USED) && (__FPU_USED == 1U) + SCB->CPACR |= ((3U << 10U*2U) | /* enable CP10 Full Access */ + (3U << 11U*2U) ); /* enable CP11 Full Access */ +#endif + +#ifdef UNALIGNED_SUPPORT_DISABLE + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} diff --git a/build/example_kdrv/wdt/sn52096/scpu_keil/mozart_96.sct b/build/example_kdrv/wdt/sn52096/scpu_keil/mozart_96.sct new file mode 100644 index 0000000..c6ee811 --- /dev/null +++ b/build/example_kdrv/wdt/sn52096/scpu_keil/mozart_96.sct @@ -0,0 +1,55 @@ +#!armcc -E +#define IRAM_START 0x10102000 +#define IRAM_SIZE 0x00016000 +#define DRAM_START 0x10200000 +#define DRAM_SIZE 0x00016000 + +LR_IROM1 IRAM_START IRAM_SIZE { ; load region size_region + ER_IROM1 IRAM_START IRAM_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + ;ENTRANCE_SECTION0_TEXT +0 { + ; .ANY (entr_section0) + ;} + ENTRANCE_SECTION1_TEXT +0 { + .ANY (entr_section1) + } + ENTRANCE_SECTION2_TEXT +0 { + .ANY (entr_section2) + } + ENTRANCE_SECTION3_TEXT +0 { + .ANY (entr_section3) + } + ENTRANCE_SECTION4_TEXT +0 { + .ANY (entr_section4) + } + ENTRANCE_SECTION5_TEXT +0 { + .ANY (entr_section5) + } + ENTRANCE_SECTION6_TEXT +0 { + .ANY (entr_section6) + } + EXIT_SECTION_TEXT +0 { + .ANY (exit_section) + } + INIT_TEXT +0 { + .ANY (init_text) + } + FINI_TEXT +0 { + .ANY (fini_text) + } + INIT_DATA +0 { + .ANY (init_data) + } + + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } + +} diff --git a/build/example_kdrv/wdt/sn52096/scpu_keil/scpu.uvoptx b/build/example_kdrv/wdt/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..a669147 --- /dev/null +++ b/build/example_kdrv/wdt/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,337 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + scpu + 0x4 + ARM-ADS + + 12000000 + + 0 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + + + + + + + + + + + BIN\UL2CM3.DLL + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + C:\Users\vincent.shen\AppData\Local\Arm\Packs\ARM\CMSIS\5.6.0\CMSIS\RTOS2\RTX\RTX5.scvd + ARM.CMSIS.5.6.0 + 1 + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_scpu\kdp_wdt_main.c + kdp_wdt_main.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\main_scpu\ex_wdt_main.c + ex_wdt_main.c + 0 + 0 + + + + + mdw + 0 + 0 + 0 + 0 + + 2 + 4 + 1 + 0 + 0 + 0 + ..\..\..\..\..\mdw\console\kmdw_console.c + kmdw_console.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 3 + 5 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_wdt.c + kdrv_wdt.c + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + + + + ::Device + 0 + 0 + 0 + 1 + + + diff --git a/build/example_kdrv/wdt/sn52096/scpu_keil/scpu.uvprojx b/build/example_kdrv/wdt/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..c61fe41 --- /dev/null +++ b/build/example_kdrv/wdt/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,633 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + scpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + companion + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + fromelf.exe --bin ".\Objects\@L.axf" --output ".\Objects\fw_scpu_tmp.bin" + post_build.bat + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4100 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, KNERON_USBH_MDW + + ..\..\..\..\..\platform\board\board_sn52096;..\..\..\..\..\include;..\..\..\..\..\platform\kl520\common;..\..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\..\mdw\include;..\ + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + .\mozart_96.sct + + + + + + + + + + + main + + + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + ..\..\..\..\scpu\\lib\kapp\include + + + + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + project.h + 5 + ..\project.h + + + kdp_wdt_main.c + 1 + ..\..\main_scpu\kdp_wdt_main.c + + + ex_wdt_main.c + 1 + ..\..\main_scpu\ex_wdt_main.c + + + + + mdw + + + kmdw_console.c + 1 + ..\..\..\..\..\mdw\console\kmdw_console.c + + + + + driver + + + kdrv_clock.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_system.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_power.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_uart.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_pwm.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + kdrv_wdt.c + 1 + ..\..\..\..\..\platform\kl520\scpu\drv\kdrv_wdt.c + + + + + ::CMSIS + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + RTE\File_System\FS_Config.c + + + + + + RTE\File_System\FS_Config_USB_0.h + + + + + + RTE\File_System\FS_Debug.c + + + + + + RTE\USB\USBH_Config_0.c + + + + + + RTE\USB\USBH_Config_CustomClass.h + + + + + + RTE\USB\USBH_Config_MSC.h + + + + + + + + diff --git a/build/example_kdrv/wdt/sn52096/scpu_keil/vtor.ini b/build/example_kdrv/wdt/sn52096/scpu_keil/vtor.ini new file mode 100644 index 0000000..016692d --- /dev/null +++ b/build/example_kdrv/wdt/sn52096/scpu_keil/vtor.ini @@ -0,0 +1,6 @@ +MEMSET(0x10200000, 0x10000, 0) +MEMSET(0x10210000, 0x08000, 0) +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10102000) // Set Stack Pointer +PC=_RDWORD(0x10102004) // Set Program Counter = Reset_Handler +BS main diff --git a/build/lib/system_520/main_scpu/include/bootloader.h b/build/lib/system_520/main_scpu/include/bootloader.h new file mode 100644 index 0000000..3d883ff --- /dev/null +++ b/build/lib/system_520/main_scpu/include/bootloader.h @@ -0,0 +1,8 @@ +#ifndef __BOOTLOADER_H__ +#define __BOOTLOADER_H__ + + +int bootloader_handler(void); + + +#endif diff --git a/build/lib/system_520/main_scpu/include/kdp_system.h b/build/lib/system_520/main_scpu/include/kdp_system.h new file mode 100644 index 0000000..c9da46b --- /dev/null +++ b/build/lib/system_520/main_scpu/include/kdp_system.h @@ -0,0 +1,22 @@ +/* + * Kneron System API + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ +#ifndef __KDP_SYSTEM_H__ +#define __KDP_SYSTEM_H__ + +#include + +uint32_t kdp_sys_get_unique_id(void); +uint32_t kdp_sys_get_ncpu_version(void); +uint32_t kdp_sys_get_ncpu_build(void); +uint32_t kdp_sys_get_spl_version(void); +uint32_t kdp_sys_get_spl_build(void); +uint32_t kdp_sys_update_spl_image(uint32_t addr, uint32_t size); +uint32_t kdp_sys_get_key_status(void); +uint32_t kdp_sys_get_kn_number(void); +uint32_t kdp_sys_program_key(uint32_t cust_key); + +#endif diff --git a/build/solution_kdp2_hico_mipi/main_ncpu/main.c b/build/solution_kdp2_hico_mipi/main_ncpu/main.c new file mode 100644 index 0000000..fb0021a --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_ncpu/main.c @@ -0,0 +1,33 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2019 Kneron Inc. All rights reserved. + * + * Name: main.c + * Purpose: Kneron NCPU + * + *---------------------------------------------------------------------------*/ + + +#include "cmsis_os2.h" +#include "kdpio.h" + +extern void SystemCoreClockUpdate(void); + +/*---------------------------------------------------------------------------- + * Main: Initialize OS Kernel and NCPU SDK + *---------------------------------------------------------------------------*/ +int main(void) +{ + SystemCoreClockUpdate(); + osKernelInitialize(); + + /* init NCPU */ + kdpio_sdk_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + ; +} diff --git a/build/solution_kdp2_hico_mipi/main_ncpu/model_ftr_table.c b/build/solution_kdp2_hico_mipi/main_ncpu/model_ftr_table.c new file mode 100644 index 0000000..6f51916 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_ncpu/model_ftr_table.c @@ -0,0 +1,48 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2020 Kneron Inc. All rights reserved. + * + * Name: ncpu_extend_ftr.c + * Purpose: Extend new features implementation + * + *---------------------------------------------------------------------------*/ + +#include "kdpio.h" +#include "model_type.h" +#include "model_ppp.h" + +/********************************************************************************* + Registered model pre-process features list + +only need to register functions for models that default builtin pre-proc can't support +*********************************************************************************/ +model_pre_post_func_t model_pre_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < pre-process function > */ + /* -------------------------------------------------------------------------- */ + 0 // no pre-process function specified + + /* Put customized pre-process functions below: + { CUSTOMER_MODEL_1, preproc_customer_model_1 }, + { CUSTOMER_MODEL_2, preproc_customer_model_2 }, + { CUSTOMER_MODEL_3, preproc_customer_model_3 }, + */ +}; + +/********************************************************************************* + Registered model post-process features list +*********************************************************************************/ +model_pre_post_func_t model_post_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < post-process function > */ + /* -------------------------------------------------------------------------- */ + + { TINY_YOLO_V3_224_224_3, post_yolov3_optimized }, + { TINY_YOLO_V3_416_416_3, post_yolov3_optimized }, + { TINY_YOLO_V3_608_608_3, post_yolov3_optimized }, + { KNERON_YOLOV5S_PersonBicycleCarMotorcycleBusTruckCatDog8_480_256_3, post_yolov5_optimized }, + + /* Put customized post-process functions below: + { CUSTOMER_MODEL_1, post_customer_model_1 }, + { CUSTOMER_MODEL_2, post_customer_model_2 }, + { CUSTOMER_MODEL_3, post_customer_model_3 }, + */ +}; + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/application_init.c b/build/solution_kdp2_hico_mipi/main_scpu/application_init.c new file mode 100644 index 0000000..57928ec --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/application_init.c @@ -0,0 +1,82 @@ +/* + * Kneron Application initialization + * + * Copyright (C) 2022 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" + +// power manager +#include "kmdw_power_manager.h" + +// inference core +#include "kp_struct.h" +#include "kmdw_console.h" +#include "kmdw_inference_app.h" + +// inference app +#include "kdp2_inf_app_yolo.h" + + +// inference client +extern int kdp2_hico_mipi_init(void); + +#define MAX_IMAGE_COUNT 10 /**< MAX inference input queue slot count */ +#define MAX_RESULT_COUNT 10 /**< MAX inference output queue slot count */ +//sync with kdp2_hico_mipi.c + +/** + * @brief To register AI applications + * @param[in] num_input_buf number of data inputs in list + * @param[in] inf_input_buf_list list of data input for inference task + * @return N/A + * @note Add a switch case item for a new inf_app application + */ +static void _app_func(int num_input_buf, void** inf_input_buf_list); + + +void _app_func(int num_input_buf, void** inf_input_buf_list) +{ + // check header stamp + if (0 >= num_input_buf) { + kmdw_printf("No input buffer for app function\n"); + return; + } + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)inf_input_buf_list[0]; + uint32_t job_id = header_stamp->job_id; + + switch (header_stamp->job_id) + { + case KDP2_INF_ID_APP_YOLO: + kdp2_app_yolo_inference(job_id, num_input_buf, inf_input_buf_list); + break; + case KDP2_JOB_ID_APP_YOLO_CONFIG_POST_PROC: + kdp2_app_yolo_config_post_process_parameters(job_id, num_input_buf, inf_input_buf_list); + break; + default: + kmdw_inference_app_send_status_code(job_id, KP_FW_ERROR_UNKNOWN_APP); + break; + } +} + + +void app_initialize(void) +{ + info_msg(">> Start running KL520 KDP2 HICO MIPI mode ...\n"); + + // for shutdown command + kmdw_power_manager_init(); + + /* initialize inference app */ + /* register APP functions */ + /* specify depth of inference queues */ + kmdw_inference_app_init(_app_func, MAX_IMAGE_COUNT, MAX_RESULT_COUNT); + + /* HICO mode init */ + kdp2_hico_mipi_init(); + + return; +} diff --git a/build/solution_kdp2_hico_mipi/main_scpu/device_init.c b/build/solution_kdp2_hico_mipi/main_scpu/device_init.c new file mode 100644 index 0000000..72ff34c --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/device_init.c @@ -0,0 +1,25 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +#include "project.h" +#if defined(FLASH_TYPE) && (FLASH_TYPE == FLASH_TYPE_NULL) +#include "kdev_flash_null.h" +#else +#include "kdev_flash.h" +#endif + +//Function +void dev_initialize(void) +{ + kdev_flash_initialize(); +} + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/display_init.c b/build/solution_kdp2_hico_mipi/main_scpu/display_init.c new file mode 100644 index 0000000..5862cbd --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/display_init.c @@ -0,0 +1,41 @@ +/* + * + * Copyright (C) 2020 Kneron, Inc. All rights reserved. + * + */ + + +#include +#include +#include "cmsis_os2.h" +#include "kmdw_display.h" + +#include "kmdw_console.h" + +static int display_inited = 0; + +void display_init(uint32_t input_fmt, uint16_t xres, uint16_t yres, uint8_t cam_idx) +{ + struct video_input_params params; + + if (display_inited == 0) { + params.input_fmt = input_fmt; + params.input_xres = xres; + params.input_yres = yres; + kmdw_video_renderer_open(¶ms); + kmdw_video_renderer_set_camera(cam_idx); + kmdw_display_set_pen_rgb565(BLACK, 1); + kmdw_video_renderer_buffer_initialize(¶ms); + kmdw_video_renderer_start(); + display_inited = 1; + kmdw_printf("input_fmt=0x%x, input_xres=%d, input_yres=%d, cam_idx=%d \n",params.input_fmt, params.input_xres, params.input_yres, cam_idx); + } +} + +void display_exit(void) +{ + if (display_inited == 1) { + kmdw_video_renderer_stop(); + display_inited = 0; + } +} diff --git a/build/solution_kdp2_hico_mipi/main_scpu/driver_init.c b/build/solution_kdp2_hico_mipi/main_scpu/driver_init.c new file mode 100644 index 0000000..c5c1068 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/driver_init.c @@ -0,0 +1,47 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kdrv_uart.h" +#include "kdrv_ddr.h" +#include "kdrv_pinmux.h" +#include "kdrv_timer.h" +#include "kdrv_i2c.h" +#include "kdrv_gpio.h" +#include "kmdw_camera.h" + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; + +void drv_initialize(void) +{ + kdrv_uart_initialize(); + kdrv_pinmux_initialize(PIN_NUM, pinmux_array); + + kdrv_ddr_system_init(DDR_INIT_ALL); // TODO, not 720 style + kdrv_i2c_initialize(KDRV_I2C_CTRL_0, KDRV_I2C_SPEED_400K); + //kdrv_gpio_initialize(GPIO_NUM, gpio_attr_ctx); + //kdrv_timer_initialize(); + //kdrv_timer_perf_measure_start(); + + /* Init these functions in kmdw_camera_init on 520 + for(uint32_t cam_id = 0; cam_id < CAM_ID_MAX ; cam_id++) + { + if(cam_ctx[cam_id].cam_input_type!= IMG_SRC_IN_PORT_NONE) + { + kdrv_csirx_initialize(cam_id); + kdrv_dpi2ahb_initialize(cam_id); + } + } + */ +} + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/include/application_init.h b/build/solution_kdp2_hico_mipi/main_scpu/include/application_init.h new file mode 100644 index 0000000..980f71b --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/include/application_init.h @@ -0,0 +1,31 @@ +/******************************************************************** + * Copyright (c) 2022 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup APPLICATION_INIT + * @{ + * @brief Kneron application init + * @copyright Copyright (C) 2022 Kneron, Inc. All rights reserved. + */ +#ifndef __APPLICATION_INIT_H__ +#define __APPLICATION_INIT_H__ + +/** + * @brief app_initialize + * + * Add application layer initialization code + * + * @return void + */ +void app_initialize(void); +#endif + + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/include/device_init.h b/build/solution_kdp2_hico_mipi/main_scpu/include/device_init.h new file mode 100644 index 0000000..9b1ae22 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/include/device_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup DEVICE_INIT + * @{ + * @brief Kneron device init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __DEVICE_INIT_H__ +#define __DEVICE_INIT_H__ + +/** + * @brief dev_initialize + * + * @return void + */ +void dev_initialize(void); +#endif + + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/include/driver_init.h b/build/solution_kdp2_hico_mipi/main_scpu/include/driver_init.h new file mode 100644 index 0000000..d564484 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/include/driver_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup SYSTEM_INIT + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __DRIVER_INIT_H__ +#define __DRIVER_INIT_H__ + +/** + * @brief drv_initialize + * + * @return void + */ +void drv_initialize(void); +#endif + + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/include/hico_mipi.h b/build/solution_kdp2_hico_mipi/main_scpu/include/hico_mipi.h new file mode 100644 index 0000000..876da66 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/include/hico_mipi.h @@ -0,0 +1,70 @@ +/** + * @file hico_mipi.h + * @brief macros and data structure for hico application of mipi camera + * @version 0.1 + * @date 2021-07-02 + * + * @copyright Copyright (c) 2021 Kneron Inc. All rights reserved. + */ + +#pragma once + +#define JID_START_HICO_MIPI 1000 // job ID to tell FW that this customized command attends to configure camera and hico mipi parameters + +#define JID_CAM_0_IMAGE 2000 // job ID for camera sensor 0 image +#define JID_CAM_1_IMAGE 2001 // job ID for camera sensor 1 image +#define JID_CAM_2_IMAGE 2002 // job ID for camera sensor 2 image +#define JID_CAM_3_IMAGE 2003 // job ID for camera sensor 3 image + +#define JID_CAM_0_INF_RESULT 3000 // job ID for camera sensor 0 inference result +#define JID_CAM_1_INF_RESULT 3001 // job ID for camera sensor 1 inference result +#define JID_CAM_2_INF_RESULT 3002 // job ID for camera sensor 2 inference result +#define JID_CAM_3_INF_RESULT 3003 // job ID for camera sensor 3 inference result + +#define KDP2_INF_ID_APP_YOLO 11 // job ID for configuring yolo application + +typedef enum +{ + // MODE_SELF_TEST = 0, add this one ? + MODE_NONE = 0, + MODE_LIVE_VIEW = 1, // only show image, not doing inference + MODE_LIVE_VIEW_INF = 2, // show image with the inference result +} hico_mode_t; + +typedef enum +{ + CAM_SENSOR_NONE = 0x0, + CAM_SENSOR_0 = 0x1, + CAM_SENSOR_1 = 0x2, + CAM_SENSOR_2 = 0x4, + CAM_SENSOR_3 = 0x8, +} sensor_selection_t; + +// FIXME: Add resolution and inference model type as the future work ?? +// need to know how to adjust the resolution of the camera +// currently model type is yolo v5s only +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t mode; // hico_mode_t + uint32_t sensor_sel; // sensor_selection_t bit fields + uint32_t app_job_id; // job id for application +} __attribute__((aligned(4))) hico_mipi_config_command_t; + +typedef struct +{ + uint32_t img_width; // in pixel + uint32_t img_height; // in pixel + uint32_t img_format; // kp_image_format_t +} __attribute__((aligned(4))) hico_mipi_camera_settings_t; + +#define MAX_NUM_SENSOR 4 + +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t num_cam_sensors; + hico_mipi_camera_settings_t cam_settings[MAX_NUM_SENSOR]; +} __attribute__((aligned(4))) hico_mipi_config_response_t; diff --git a/build/solution_kdp2_hico_mipi/main_scpu/include/middleware_init.h b/build/solution_kdp2_hico_mipi/main_scpu/include/middleware_init.h new file mode 100644 index 0000000..f86a89e --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/include/middleware_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup MIDDLEWARE_INIT + * @{ + * @brief Kneron middleware init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __MIDDLEWARE_INIT_H__ +#define __MIDDLEWARE_INIT_H__ + +/** + * @brief mdw_initialize + * + * @return void + */ +void mdw_initialize(void); +#endif + + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/include/system_init.h b/build/solution_kdp2_hico_mipi/main_scpu/include/system_init.h new file mode 100644 index 0000000..32fe0c2 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/include/system_init.h @@ -0,0 +1,28 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup SYSTEM_INIT + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __SYSTEM_INIT_H__ +#define __SYSTEM_INIT_H__ + +/** + * @brief sys_initialize + * + * @return void + */ +void sys_initialize(void); +#endif + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/include/task_handler.h b/build/solution_kdp2_hico_mipi/main_scpu/include/task_handler.h new file mode 100644 index 0000000..4bf449b --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/include/task_handler.h @@ -0,0 +1,89 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup TASK_HANDLER + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef _TASK_HANDLER_H +#define _TASK_HANDLER_H +#include "cmsis_os2.h" +// #include "project.h" +#define USB_HOST +/****************************************************************************** +Declaration of data structure +******************************************************************************/ +// Sec 5: structure, uniou, enum, linked list +typedef struct +{ + //parameters for creating tasks + const char caName[8]; //now, len=8 + + osThreadId_t *tTaskHandle; + osThreadFunc_t fpEntry; + const uint32_t dwStackSize; + osPriority_t dwPriority; + + //parameters for creating queue + osMessageQueueId_t *tQueueHandle; + const uint32_t tQmsg_count; + const uint32_t tQmsg_size; +}T_S_KneronTask; + +osThreadId_t task_log_handle; +osThreadId_t task_infdata_handle; +osThreadId_t task_infcb_handle; +osThreadId_t task_usb_cmd_handle; +osThreadId_t task_usb_image_handle; +osThreadId_t task_usb_result_handle; +osThreadId_t task_buf_mgr_handle; + +// put osMessageQueueId_t objects here for setting tQueueHandle + +extern void logger_thread(void *arg); +extern void kmdw_inference_image_dispatcher_thread(void *argument); +extern void kmdw_inference_result_handler_callback_thread(void *argument); +extern void kdp2_hico_mipi_usb_cmd_thread(void *arg); +extern void kdp2_hico_mipi_usb_img_send_back_thread(void *arg); +extern void kdp2_hico_mipi_usb_result_thread(void *arg); +extern void kdp2_fifoq_manager_enqueue_image_thread(void *arg); + +/****************************************************************************** +Declaration of Global Variables & Functions +******************************************************************************/ +// Sec 6: declaration of global variable +T_S_KneronTask g_atKneronTaskPool[]= +{ +// TaskName TaskHandle TaskFuncEntry TaskStack TaskPriority QueueHandle QueueMsgCount QueueMsgSize +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + {"LogTask", &task_log_handle, logger_thread, 1024, osPriorityBelowNormal, NULL, 0, 0 }, + {"Infdata", &task_infdata_handle, kmdw_inference_image_dispatcher_thread, 2048, osPriorityNormal, NULL, 0, 0 }, + {"Infcb", &task_infcb_handle, kmdw_inference_result_handler_callback_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"usbcmd", &task_usb_cmd_handle, kdp2_hico_mipi_usb_cmd_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"usbimg", &task_usb_image_handle, kdp2_hico_mipi_usb_img_send_back_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"usbrslt ", &task_usb_result_handle, kdp2_hico_mipi_usb_result_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"buf_mgr", &task_buf_mgr_handle, kdp2_fifoq_manager_enqueue_image_thread, 1024, osPriorityHigh, NULL, 0, 0 }, + +// +//Follow above format to add your TASK here +// + + +//end of table, don't remove it +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + {NULL,NULL,NULL,0,0,NULL,0,0} +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +}; + +#endif + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/kdp2_hico_mipi.c b/build/solution_kdp2_hico_mipi/main_scpu/kdp2_hico_mipi.c new file mode 100644 index 0000000..938ebf1 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/kdp2_hico_mipi.c @@ -0,0 +1,577 @@ +//#define ENABLE_DBG_LOG + +#include +#include "cmsis_os2.h" +#include "kmdw_power_manager.h" + +#include "kmdw_console.h" +#include "kmdw_memory.h" +#include "kdrv_gdma.h" +#include "kdrv_power.h" +#include "kdrv_scu_ext.h" +#include "kdp_system.h" + +#include "usbd_hal.h" + +#include "model_type.h" + +#include "buffer_object.h" + +#include "kmdw_fifoq_manager.h" +#include "kdp2_ipc_cmd.h" +#include "kdp2_inf_app_yolo.h" +#include "kdp2_usb_companion.h" + +#include "kmdw_display.h" +// --- hico mipi include --- +#include "hico_mipi.h" + +#include "kmdw_camera.h" +#include "kdrv_timer.h" +#include "kdrv_i2c.h" +#include "project.h" + +extern uint32_t kdrv_efuse_get_kn_number(void); + +#define NUM_MIPI_INIT_BUFS 2 // 2 (ping-pong buffers) or 3 (triple-buffers for skipping frames) +#define NUM_IMAGE_BUF 10 +#define IMAGE_BUF_SIZE (1 * 1024 * 1024) +#define NUM_RESULT_BUF 10 +#define RESULT_BUF_SIZE (400 * 1024) + +#if 0//KL720_Scott +#define JTAG_MAGIC_ADDRESS 0x1FFFFFFC +#define JTAG_MAGIC_VALUE 0xFEDCBA01 +#define USB_BOOT_MAGIC_HB 0xaabbccdd +#define USB_BOOT_MAGIC_LB 0x11223344 + +#else +#define JTAG_MAGIC_ADDRESS 0x10100000 +#define KDP2_BOOT_CONFIG_ADDRESS 0x10100100 + +#define JTAG_MAGIC_VALUE 0xFEDCBA01 +#define BOOT_FROM_FLASH 0xA +typedef struct +{ + uint32_t boot_type; // 0xA = flash-boot, others = usb-boot + uint8_t loader_ver[4]; // fw loader version numbers + uint8_t scpu_fw_ver[4]; // SCPU fw version numbers + uint8_t ncpu_fw_ver[4]; // NCPU fw version numbers +} kdp2_boot_config_t; +#endif + +//static osThreadId_t usb_img_tid = 0; +//#define SHOW_SENSOR_IMAGE_ON_LCD//debug purpose: show sensor image directly without inference on LCD + +#ifdef ENABLE_DBG_LOG +#define dbg_log(__format__, ...) kmdw_printf("[kp hico mipi]"__format__, ##__VA_ARGS__) +#else +#define dbg_log(__format__, ...) +#endif + +typedef struct +{ + uint32_t cam_idx; + uint32_t buf_addr; + uint32_t img_width; + uint32_t img_height; + uint32_t img_format; +} mipi_img_object_t; + +#define FLAG_WAIT_USB_CONNECTION 0x1 + +static osThreadId_t _usb_cmd_tid = NULL; +static osMessageQueueId_t _img_queue = NULL; +static uint32_t _hico_mode = MODE_LIVE_VIEW; + +//static osThreadId_t task_usb_cmd_handle = NULL; +//static osThreadId_t task_usb_image_handle = NULL; +//static osThreadId_t task_usb_result_handle = NULL; +extern void display_init(uint32_t input_fmt, uint16_t xres, uint16_t yres, uint8_t cam_idx); +extern void display_exit(void); + +extern uint32_t lcdc_kdp2_get_disp_idx(int *read_done_idx); +extern uint32_t lcdc_kdp2_set_disp_buf(uint32_t buf_addr, int write_done_idx); +extern uint32_t lcdc_kdp2_get_disp_buf(int cam_idx, int *disp_idx); + +static uint32_t _app_job_id = 0xFFFFFFFF; + +// usb link status notify +static void usb_user_link_status_callback(usbd_hal_link_status_t link_status) +{ + switch (link_status) + { + case USBD_STATUS_DISCONNECTED: + kmdw_printf("USB is disconnected\n"); + break; + + case USBD_STATUS_CONFIGURED: + kmdw_printf("USB is connected\n"); + osThreadFlagsSet(_usb_cmd_tid, FLAG_WAIT_USB_CONNECTION); + break; + } +} + +// vendor-specific control transfer setup packet notify +bool usb_user_control_callback(usbd_hal_setup_packet_t *setup) +{ + bool ret = false; + + dbg_log("control bRequest = 0x%x\n", setup->bRequest); + + switch (setup->bRequest) + { + case KDP2_CONTROL_REBOOT: + { + dbg_log("control reboot\n"); + kdrv_power_sw_reset(); + break; + } + case KDP2_CONTROL_SHUTDOWN: + { + dbg_log("control shutdown\n"); + kmdw_power_manager_shutdown(); + break; + } + case KDP2_CONTROL_FIFOQ_RESET: + { + dbg_log("control fifoq reset\n"); + + // FIXME + //kmdw_printf("wakeup USB cmd thread\n"); + //osThreadFlagsSet(_usb_cmd_tid, FLAG_WAIT_USB_CONNECTION); + //osThreadFlagsSet(image_thread_id, 0x1); + ret = true; + break; + } + + default: + ret = false; + break; + } + + return ret; +} + +//static cam_format _cams_fmt[2] = {0}; +static struct cam_format _cams_fmt[2] = {0}; + +// image ISR callback +void image_coming_callback(uint32_t cam_idx, uint32_t img_buf, uint32_t *p_new_img) +{ + osStatus_t sts; + mipi_img_object_t img_obj; + uint32_t new_inf_buf; + int buf_size; + sts = kmdw_fifoq_manager_image_get_free_buffer(&new_inf_buf, &buf_size, 0, true); + if (sts != osOK) + { + sts = osMessageQueueGet(_img_queue, (void *)&img_obj, NULL, 0); + if (sts != osOK) + { + dbg_log("(ISR) error !! retrieving new buf failed, osMessageQueueGet() ret = %d\n", sts); + // Due to highest priority ISR has, + // image input is so fast that fifoq can't provide a free buffer even force_grab is set + *p_new_img = img_buf; + return; + } + + new_inf_buf = img_obj.buf_addr; + } + + // get inf_buf address by shift back by the size of XXX_inference_header_t + uint32_t inf_buf = img_buf - sizeof(kdp2_ipc_app_yolo_inf_header_t); + + img_obj.cam_idx = cam_idx; + img_obj.buf_addr = inf_buf; + img_obj.img_width = _cams_fmt[cam_idx].width; + img_obj.img_height = _cams_fmt[cam_idx].height; + if (_cams_fmt[cam_idx].pixelformat == IMG_FORMAT_RGB565) + img_obj.img_format = KP_IMAGE_FORMAT_RGB565; + else if (_cams_fmt[cam_idx].pixelformat == IMG_FORMAT_RAW8) + img_obj.img_format = KP_IMAGE_FORMAT_RAW8; + else if (_cams_fmt[cam_idx].pixelformat == IMG_FORMAT_YCBCR) + img_obj.img_format = KP_IMAGE_FORMAT_YUYV; +#ifdef SHOW_SENSOR_IMAGE_ON_LCD + if(cam_idx == 0) + lcdc_kdp2_set_disp_buf(img_buf,0);//show sensor image directly + //DSG("image_coming_callback, img_buf=0x%x, cam_idx=%d, pixelformat=0x%x, img_width=%d img_height=%d",img_buf, cam_idx, _cams_fmt[cam_idx].pixelformat, _cams_fmt[cam_idx].width, _cams_fmt[cam_idx].height); +#endif + sts = osMessageQueuePut(_img_queue, (const void *)&img_obj, 0U, 0); + if (sts != osOK) + { + dbg_log("(ISR) error !! osMessageQueuePut() failed, sts = %d\n", sts); + *p_new_img = img_buf; + return; + } + + *p_new_img = new_inf_buf + sizeof(kdp2_ipc_app_yolo_inf_header_t); + + return; +} + +uint32_t camera_start(uint8_t cam_idx, uint32_t width, uint32_t height, uint32_t pixelformat) +{ + uint32_t ret; + + struct cam_capability cap; + + _cams_fmt[cam_idx].width = width; + _cams_fmt[cam_idx].height = height; + _cams_fmt[cam_idx].pixelformat = pixelformat; + + char fmtstr[8]; + memset(&cap, 0, sizeof(cap)); + + if (0 != (ret = kmdw_camera_open(cam_idx))) + return ret; + + if (0 != (ret = kmdw_camera_get_device_info(cam_idx, &cap))) + return ret; + + if (0 != (ret = kmdw_camera_set_frame_format(cam_idx, &_cams_fmt[cam_idx])))//scpu: exception: code=1, object_id=0x102021d4 + return ret; + + if (0 != (ret = kmdw_camera_get_frame_format(cam_idx, &_cams_fmt[cam_idx]))) + return ret; + + memset(fmtstr, 0, 8); + memcpy(fmtstr, &_cams_fmt[cam_idx].pixelformat, 4); + + int buf_size; + uint32_t buf_addr[NUM_MIPI_INIT_BUFS] = {0}; + + // mipi needs some buffers at initialization + for (int i = 0; i < NUM_MIPI_INIT_BUFS; i++) + { + kmdw_fifoq_manager_image_get_free_buffer(&buf_addr[i], &buf_size, osWaitForever, false); + buf_addr[i] += sizeof(kdp2_ipc_app_yolo_inf_header_t); + } + + if (0 != (ret = kmdw_camera_buffer_init(cam_idx, buf_addr[0], buf_addr[1]))) + return ret; + + if (0 != (ret = kmdw_camera_start(cam_idx, image_coming_callback))) + return ret; + + return 0; +} + + +#define CMD_BUF_SIZE (1 * 1024) +//#define CMD_BUF_SIZE (1 * 1024 * 1024) + + +// this thread receive the command from host SW +void kdp2_hico_mipi_usb_cmd_thread(void *arg) +{ + kmdw_printf("[%s] start !\n", __FUNCTION__); + + _usb_cmd_tid = osThreadGetId(); + if (_usb_cmd_tid == NULL) + kmdw_printf("%s creation failed !\n", __FUNCTION__); + + // wait until usb connection is established + osThreadFlagsWait(FLAG_WAIT_USB_CONNECTION, osFlagsWaitAny, osWaitForever); + kmdw_printf("[%s] FLAG_WAIT_USB_CONNECTION OK !\n", __FUNCTION__); + + uint32_t cmd_buf = kmdw_ddr_reserve(CMD_BUF_SIZE); + + while (1) + { + uint32_t txLen = CMD_BUF_SIZE; + kdrv_status_t usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (void *)cmd_buf, &txLen, osWaitForever); + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + { + dbg_log("[%s] bulk receive is terminated, sts %d\n", __FUNCTION__, usb_sts); + continue; + } + + dbg_log("[%s] usb recv addr 0x%x len %d\n", __FUNCTION__, (void *)cmd_buf, txLen); + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)cmd_buf; + + if (header_stamp->magic_type == KDP2_MAGIC_TYPE_COMMAND) // standard KDP2 commands + { + // borrow image fifo to handle KDP2 commands as well + dbg_log("[%s] handle kdp2 command = 0x%x\n", __FUNCTION__, header_stamp->job_id); + // handle kdp2 commands ... + kdp2_cmd_handle_kp_command(cmd_buf); + continue; + } + else if (header_stamp->magic_type == KDP2_MAGIC_TYPE_CUSTOMIZED) // customized commands + { + // customized command to configure mipi camera + if (header_stamp->job_id == JID_START_HICO_MIPI) + { + dbg_log("[%s] configuration command received\n", __FUNCTION__); + + hico_mipi_config_command_t *hico_mipi_cmd = (hico_mipi_config_command_t *)cmd_buf; + hico_mipi_config_response_t hico_mipi_resp; + + hico_mipi_resp.header_stamp.magic_type = KDP2_MAGIC_TYPE_CUSTOMIZED; + hico_mipi_resp.header_stamp.job_id = JID_START_HICO_MIPI; + hico_mipi_resp.header_stamp.status_code = KP_SUCCESS; + hico_mipi_resp.header_stamp.total_size = sizeof(hico_mipi_resp); + hico_mipi_resp.num_cam_sensors = 0; + + _hico_mode = hico_mipi_cmd->mode; + _app_job_id = hico_mipi_cmd->app_job_id; + + // Configure the mipi camera + if (hico_mipi_cmd->sensor_sel & CAM_SENSOR_0) + { + if (0 == camera_start(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT)) + { + dbg_log("[%s] camera_start 0, ok\n",__FUNCTION__); + hico_mipi_resp.num_cam_sensors++; + hico_mipi_resp.cam_settings[0].img_width = IMGSRC_0_WIDTH; + hico_mipi_resp.cam_settings[0].img_height = IMGSRC_0_HEIGHT; + hico_mipi_resp.cam_settings[0].img_format = KP_IMAGE_FORMAT_RGB565; + } + else + { + hico_mipi_resp.header_stamp.status_code = KP_ERROR_OTHER_99; // FIXME, give it a specific error code + } + } + + if (hico_mipi_cmd->sensor_sel & CAM_SENSOR_1) + { + dbg_log("[%s] camera_start 1, ok\n",__FUNCTION__); + + if (0 == camera_start(1, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, IMGSRC_1_FORMAT)) + { + hico_mipi_resp.num_cam_sensors++; + hico_mipi_resp.cam_settings[1].img_width = IMGSRC_1_WIDTH; + hico_mipi_resp.cam_settings[1].img_height = IMGSRC_1_HEIGHT; + hico_mipi_resp.cam_settings[1].img_format = KP_IMAGE_FORMAT_RAW8; + } + else + { + hico_mipi_resp.header_stamp.status_code = KP_ERROR_OTHER_99; // FIXME, give it a specific error code + } + } + + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&hico_mipi_resp, sizeof(hico_mipi_resp), 1000); + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + { + dbg_log("error ! usbd_hal_bulk_send() ret = %d\n", usb_sts); + //return; + } + } + else + { + dbg_log("error !!! wrong job_id = %d\n", __FUNCTION__, header_stamp->job_id); + } + } + else if ((header_stamp->magic_type & 0xFFFF) == KDP_MSG_HDR_CMD) // very speical case for old arch. fw update + { + // handle legendary kdp commands, should be as few as possible + dbg_log("[%s] handle legendary kdp command = 0x%x\n",__FUNCTION__, header_stamp->job_id); + kdp2_cmd_handle_legend_kdp_command(cmd_buf); + } + else + { + dbg_log("[%s] error ! buffer begin with incorrect magic_type 0x%x, txLen %d\n", __FUNCTION__, header_stamp->magic_type, txLen); + } + } +} + +// this thread sends inference result to host +void kdp2_hico_mipi_usb_result_thread(void *arg) +{ + kmdw_printf("[%s] start !\n", __FUNCTION__); + + while (1) + { + uint32_t result_buf_addr; + int result_buf_length; + + // get result data from result fifo queue with blocking wait + kmdw_fifoq_manager_result_dequeue(&result_buf_addr, &result_buf_length, osWaitForever); + dbg_log("[%s] result_buf_addr=0x%x, result_buf_length=%d\n", __FUNCTION__, result_buf_addr,result_buf_length); + // then send inference result + kdp2_ipc_app_yolo_result_t *yolo_result = (kdp2_ipc_app_yolo_result_t *)result_buf_addr; + + yolo_result->header_stamp.job_id = JID_CAM_0_INF_RESULT + yolo_result->inf_number; // for now it tells host SW that this is an inference result + + #if 1 + //yolo_result->header_stamp.total_size = result_buf_length; + #endif + // send result to the host SW, blocking wait + dbg_log("[%s] send usb data size %d\n", __FUNCTION__, yolo_result->header_stamp.total_size); + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)result_buf_addr, yolo_result->header_stamp.total_size, osWaitForever); + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + { + dbg_log("error ! usbd_hal_bulk_send() ret = %d \n", usb_sts); + } + + // return free buf back to queue + kmdw_fifoq_manager_result_put_free_buffer(result_buf_addr, result_buf_length, osWaitForever); + } +} + +// this thread sends raw image from image sensor to host SW (and also enqueues it to image fifo queue ?) +void kdp2_hico_mipi_usb_img_send_back_thread(void *arg) +{ + kmdw_printf("[%s] start !\n", __FUNCTION__); + + while (1) + { + mipi_img_object_t img_obj; + osMessageQueueGet(_img_queue, (void *)&img_obj, NULL, osWaitForever); + dbg_log("[%s] _hico_mode = %d\n",__FUNCTION__, _hico_mode); + dbg_log("[%s] got inf-buf (cam_idx %d buf_addr 0x%p img_width %d img_height %d img_format %d)\n", + __FUNCTION__,img_obj.cam_idx, img_obj.buf_addr, img_obj.img_width, img_obj.img_height, img_obj.img_format); + + kdp2_ipc_app_yolo_inf_header_t *inf_header = (kdp2_ipc_app_yolo_inf_header_t *)img_obj.buf_addr; + + int byte_ppix; + switch (img_obj.img_format) + { + case KP_IMAGE_FORMAT_RGB565: + case KP_IMAGE_FORMAT_YUYV: + byte_ppix = 2; + break; + case KP_IMAGE_FORMAT_RGBA8888: + byte_ppix = 3; + break; + case KP_IMAGE_FORMAT_RAW8: + byte_ppix = 1; + } + + inf_header->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + inf_header->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_inf_header_t) + (img_obj.img_width * img_obj.img_height * byte_ppix); + inf_header->header_stamp.job_id = JID_CAM_0_IMAGE + img_obj.cam_idx; + inf_header->header_stamp.status_code = KP_SUCCESS; + + inf_header->inf_number = img_obj.cam_idx; + inf_header->width = img_obj.img_width; + inf_header->height = img_obj.img_height; + inf_header->channel = (img_obj.img_format == KP_IMAGE_FORMAT_RAW8) ? 1 : 3; + #if 0//KL720_Scott + inf_header->model_id = KNERON_YOLOV5S_COCO80_640_640_3;// + #else + inf_header->model_id = TINY_YOLO_V3_224_224_3; + #endif + inf_header->image_format = img_obj.img_format; + inf_header->model_normalize = KP_NORMALIZE_KNERON; + + dbg_log("[%s] send usb data size %d\n", __FUNCTION__, inf_header->header_stamp.total_size); + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)inf_header, inf_header->header_stamp.total_size, osWaitForever); + + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + { + dbg_log("error ! usbd_hal_bulk_send() ret = %d\n", usb_sts); + return; + } + + if (_hico_mode == MODE_LIVE_VIEW) + { + dbg_log("[%s] kmdw_fifoq_manager_image_put_free_buffer %d\n",__FUNCTION__); + kmdw_fifoq_manager_image_put_free_buffer((uint32_t)inf_header, IMAGE_BUF_SIZE, osWaitForever); + } + else // MODE_LIVE_VIEW_INF + { + dbg_log("[%s] kmdw_fifoq_manager_image_enqueue %d\n",__FUNCTION__); + inf_header->header_stamp.job_id = _app_job_id; + kmdw_fifoq_manager_image_enqueue(1, 0, (uint32_t)inf_header, IMAGE_BUF_SIZE, osWaitForever, false); + } + } +} + +//////////////////////////////////////////////////////////// +#define RECOVERY_MARK_POS (SdRAM_MEM_BASE + SdRAM_MEM_SIZE - 64) + +// KDP2 Inference Interface for HICO MIPI code +// image input +// image + inference output +int kdp2_hico_mipi_init() +{ + // retrieve real serial number here from efuse + // then convert it to hex string format + uint32_t uid = 0; + + uid = kdp_sys_get_kn_number(); + + int32_t sidx = 0; + uint8_t kn_num_string[32] = {0}; + for (int i = 7; i >= 0; i--) + { + uint32_t hex = (uid >> i * 4) & 0xF; + kn_num_string[sidx] = (hex < 10) ? '0' + hex : 'A' + (hex - 10); + sidx += 2; + } + + // HICO Mode + uint16_t bcdDevice = KP_KDP2_FW_HICO_MODE; + + if (*((uint32_t *)JTAG_MAGIC_ADDRESS) == JTAG_MAGIC_VALUE) + { + kmdw_printf("FW is running in JTAG mode\n"); + bcdDevice |= KP_KDP2_FW_JTAG_TYPE; + } + else + { + kdp2_boot_config_t *bConfig = (kdp2_boot_config_t *)KDP2_BOOT_CONFIG_ADDRESS; + if (bConfig->boot_type == BOOT_FROM_FLASH) + { + kmdw_printf("KDP2 FW is running in flash-boot mode\n"); + bcdDevice |= KP_KDP2_FW_FLASH_TYPE; + + kmdw_printf("boot ncpu fw from flash\n"); + SCU_EXTREG_CM4_NCPU_CTRL_SET_wakeup(1); // run ncpu + } + else + { + kmdw_printf("KDP2 FW is running in usb-boot mode\n"); + bcdDevice |= KP_KDP2_FW_USB_TYPE; + } + } + + // this is about recovery mode + *(uint32_t *)RECOVERY_MARK_POS = 0; + + usbd_hal_initialize(kn_num_string, bcdDevice, usb_user_link_status_callback, usb_user_control_callback); + + usbd_hal_set_enable(true); + + /* Allocate memory for image and result buffers */ + uint32_t buf_addr = kmdw_ddr_reserve(NUM_IMAGE_BUF * IMAGE_BUF_SIZE + NUM_RESULT_BUF * RESULT_BUF_SIZE); + if (buf_addr == 0) + { + dbg_log("error !!! kmdw_ddr_reserve() failed for image/result buffers\n"); + return -1; + } + + // queue buffers into image free-queue + for (uint32_t i = 0; i < NUM_IMAGE_BUF; i++) + { + kmdw_fifoq_manager_image_put_free_buffer(buf_addr, IMAGE_BUF_SIZE, osWaitForever); + buf_addr += IMAGE_BUF_SIZE; + } + + // queue buffers into result free-queue + for (uint32_t i = 0; i < NUM_RESULT_BUF; i++) + { + kmdw_fifoq_manager_result_put_free_buffer(buf_addr, RESULT_BUF_SIZE, osWaitForever); + buf_addr += RESULT_BUF_SIZE; + } + + // prepare an internal image queue between ISR callback and image-processing thread + _img_queue = osMessageQueueNew(NUM_IMAGE_BUF, sizeof(mipi_img_object_t), NULL); + if (_img_queue == NULL) + { + dbg_log("error !!! osMessageQueueNew() failed\n"); + } + + kmdw_fifoq_manager_store_fifoq_config(NUM_IMAGE_BUF, IMAGE_BUF_SIZE, NUM_RESULT_BUF, RESULT_BUF_SIZE); + + // wow ! fifoq can also handle command + kdp2_cmd_handler_initialize(); + +#ifdef SHOW_SENSOR_IMAGE_ON_LCD + display_init(V2K_PIX_FMT_RGB565, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, 0); +#endif + return 0; +} diff --git a/build/solution_kdp2_hico_mipi/main_scpu/main.c b/build/solution_kdp2_hico_mipi/main_scpu/main.c new file mode 100644 index 0000000..017ab58 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/main.c @@ -0,0 +1,57 @@ +/* + * Kneron Main Entry driver + * + * Copyright (C) 2020 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +#include "project.h" +#include "version.h" + +// Customized configuration and implementation +#include "system_init.h" +#include "driver_init.h" +#include "device_init.h" +#include "middleware_init.h" +#include "application_init.h" + +#include "kmdw_console.h" + +extern void task_initialize(void); + +/** + * @brief main, main function + */ +int main(void) +{ + osKernelInitialize(); // Initialize CMSIS-RTOS + sys_initialize(); + drv_initialize(); /* customize driver initialization, see driver_init.c */ + dev_initialize(); /* customize device initialization, see device_init.c */ + mdw_initialize(); /* customize middleware initialization, see middlewre_init.c */ + + + printf("SDK v%u.%u.%u-:build.%03u\n", + (uint8_t)(IMG_FW_MAJOR), + (uint8_t)(IMG_FW_MINOR), + (uint8_t)(IMG_FW_UPDATE), + (uint32_t)(IMG_FW_BUILD)); + + app_initialize(); /* customize application initialization, see application_init.c */ + + /* New task threads */ + task_initialize(); + + /* Start RTOS Kernel */ + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/solution_kdp2_hico_mipi/main_scpu/middleware_init.c b/build/solution_kdp2_hico_mipi/main_scpu/middleware_init.c new file mode 100644 index 0000000..af0331b --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/middleware_init.c @@ -0,0 +1,34 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kmdw_memory.h" +#include "kmdw_model.h" +#include "kmdw_dfu.h" +#include "kmdw_camera.h" +#include "kmdw_display.h" +#include "kmdw_console.h" + +void mdw_initialize(void) +{ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kmdw_ddr_store_system_reserve(DDR_SYSTEM_RESERVED_BEGIN, DDR_SYSTEM_RESERVED_END); + kmdw_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE); // uart console + kmdw_dfu_init(NULL, NULL); + kmdw_model_init(); + + //load_ncpu_fw(1/*reset_flag*/); // (kmdw_system.h) load ncpu fw from flash + kmdw_camera_init(); // init cameras + kmdw_display_initialize(); // init display +} + diff --git a/build/solution_kdp2_hico_mipi/main_scpu/system_init.c b/build/solution_kdp2_hico_mipi/main_scpu/system_init.c new file mode 100644 index 0000000..a89c8f3 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/main_scpu/system_init.c @@ -0,0 +1,23 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +//#include "project.h" +#include "kdrv_system.h" + + + //Function +void sys_initialize(void) +{ + /* SDK main init for companion mode */ + kdrv_system_init(); + kdrv_system_init_ncpu(); +} diff --git a/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.sct b/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.sct new file mode 100644 index 0000000..7e4a57e --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.sct @@ -0,0 +1,19 @@ +#!armcc -E +#define DRAM_START 0x0FFF0000 +#define DRAM_SIZE 0x00010000 + +LR_IROM1 0x00000000 0x00010000 { ; load region size_region + ER_IROM1 0x00000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } +} + diff --git a/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.uvoptx b/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.uvoptx new file mode 100644 index 0000000..5f40fd7 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.uvoptx @@ -0,0 +1,552 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ncpu + 0x4 + ARM-ADS + + 250000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ULP2CM3 + -UAny -O905 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO3 -FD20000000 -FC1000 -FN0 + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U63610859 -O1 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO1 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 169 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 0 + D:\3_code\mozart_sw_kdp2.git\scpu\project\companion_kdp2\main\main.c + + + + + + + 1 + 2 + 0x30ff0140 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\model_ftr_table.c + model_ftr_table.c + 0 + 0 + + + + + libs + 0 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + kdp2_ncpu_sdk.lib + 0 + 0 + + + 2 + 4 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + kdp2_ncpu_model_ppp.lib + 0 + 0 + + + + + rtx + 0 + 0 + 0 + 0 + + 3 + 5 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + irq_cm4f.s + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + os_systick.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + RTX_Config.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + rtx_delay.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + rtx_evflags.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + rtx_evr.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + rtx_kernel.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + rtx_lib.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + rtx_memory.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + rtx_mempool.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + rtx_msgqueue.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + rtx_mutex.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + rtx_semaphore.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + rtx_system.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + rtx_thread.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + startup.c + 0 + 0 + + + 4 + 22 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + diff --git a/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.uvprojx b/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.uvprojx new file mode 100644 index 0000000..f1f8e6e --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/ncpu.uvprojx @@ -0,0 +1,547 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ncpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Mozart_ncpu + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_ncpu.bin" + post_build.bat fw_ncpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0xfff0000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + ARM_MATH_CM4, TARGET_NCPU, LOG_ENABLE, KL520 + + ..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\ncpu\model_ppp\include;..\..\..\..\platform\kl520\ncpu\drv\include;..\..\..\..\platform\kl520\ncpu\rtos\rtx\include;..\..\..\..\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\..\..\include + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x00000000 + 0x20000000 + + ..\..\..\..\platform\kl520\ncpu\mozart_ncpu.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_ncpu\main.c + + + model_ftr_table.c + 1 + ..\..\main_ncpu\model_ftr_table.c + + + + + libs + + + kdp2_ncpu_sdk.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + + + kdp2_ncpu_model_ppp.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/post_build.bat b/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/post_build.bat new file mode 100644 index 0000000..1ac5a9c --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/ncpu_keil/post_build.bat @@ -0,0 +1,10 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_ncpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ diff --git a/build/solution_kdp2_hico_mipi/sn52096/proj.uvmpw b/build/solution_kdp2_hico_mipi/sn52096/proj.uvmpw new file mode 100644 index 0000000..c1b2c26 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/proj.uvmpw @@ -0,0 +1,22 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + + .\scpu_keil\scpu.uvprojx + 1 + + + + + + .\ncpu_keil\ncpu.uvprojx + + + diff --git a/build/solution_kdp2_hico_mipi/sn52096/project.h b/build/solution_kdp2_hico_mipi/sn52096/project.h new file mode 100644 index 0000000..6583b19 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/project.h @@ -0,0 +1,182 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +CAM setting +=============================================================================*/ +#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 + +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +#define FLASH_FW_NCPU0_ADDR 0x00018000 /**< fw_ncpu.bin */ +#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +#define FLASH_MODEL_ALL_ADDR 0x00301000 /**< all_models.bin */ +#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/kdp2_scpu_jlink.ini b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/kdp2_scpu_jlink.ini new file mode 100644 index 0000000..d4099c3 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/kdp2_scpu_jlink.ini @@ -0,0 +1,13 @@ +MEMSET(0x10200000, 0x18000, 0) +MEMSET(0x10210000, 0x08000, 0) + +// to let USB know this is running in JTAG mode +MEMSET(0x10100000, 1, 0x01) +MEMSET(0x10100001, 1, 0xBA) +MEMSET(0x10100002, 1, 0xDC) +MEMSET(0x10100003, 1, 0xFE) + +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10104000) // Set Stack Pointer +PC=_RDWORD(0x10104004) // Set Program Counter = Reset_Handler +BS main \ No newline at end of file diff --git a/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/post_build.bat b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/post_build.bat new file mode 100644 index 0000000..f839167 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/post_build.bat @@ -0,0 +1,12 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_scpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ + + diff --git a/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/pre_build.bat b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/pre_build.bat new file mode 100644 index 0000000..dba1dc6 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/pre_build.bat @@ -0,0 +1 @@ +REM "prebuild script" diff --git a/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/scpu.uvoptx b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..80c7ea4 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,1230 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + dev + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\kdp2_scpu_jlink.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + 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..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + 7 + 74 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + task_handler.c + 0 + 0 + + + + + startup + 1 + 0 + 0 + 0 + + 8 + 75 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + startup.c + 0 + 0 + + + 8 + 76 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + + libs + 1 + 0 + 0 + 0 + + 9 + 77 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\system_520.lib + system_520.lib + 0 + 0 + + + + diff --git a/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/scpu.uvprojx b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..3f8b969 --- /dev/null +++ b/build/solution_kdp2_hico_mipi/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,847 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + dev + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + scpu_fw + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + pre_build.bat + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_scpu.bin" + post_build.bat fw_scpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, BOARD_96 + + ..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\platform\kl520\scpu\rtos\rtx\include;..\..\..\..\platform\board\board_sn52096;..\..\..\..\platform\dev\include;..\..\..\..\mdw\include;..\..\..\..\mdw\inference;..\..\..\..\app;..\..\main_scpu\include;..\;..\..\..\lib\system_520\main_scpu\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\sn52096;..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\board\board_sn52096 + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + ..\..\..\..\platform\kl520\scpu\scatter_load.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_scpu\main.c + + + project.h + 5 + ..\project.h + + + application_init.c + 1 + ..\..\main_scpu\application_init.c + + + device_init.c + 1 + ..\..\main_scpu\device_init.c + + + driver_init.c + 1 + ..\..\main_scpu\driver_init.c + + + middleware_init.c + 1 + ..\..\main_scpu\middleware_init.c + + + system_init.c + 1 + ..\..\main_scpu\system_init.c + + + task_handler.h + 5 + ..\..\main_scpu\include\task_handler.h + + + display_init.c + 1 + ..\..\main_scpu\display_init.c + + + + + inf_app + + + demo_customize_inf_single_model.c + 1 + ..\..\..\..\app\demo_customize_inf_single_model.c + + + demo_customize_inf_multiple_models.c + 1 + ..\..\..\..\app\demo_customize_inf_multiple_models.c + + + kdp2_inf_app_yolo.c + 1 + ..\..\..\..\app\kdp2_inf_app_yolo.c + + + + + inf_client + + + kdp2_cmd_handler_520.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_cmd_handler_520.c + + + usbd_hal_520.c + 1 + ..\..\..\..\mdw\usb_companion\usbd_hal_520.c + + + kdp2_usb_log.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_usb_log.c + + + kdp2_hico_mipi.c + 1 + ..\..\main_scpu\kdp2_hico_mipi.c + + + + + middleware + + + kmdw_memory.c + 1 + ..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_memxfer.c + 1 + ..\..\..\..\mdw\flash\kmdw_memxfer.c + + + kmdw_console.c + 1 + ..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_power_manager.c + 1 + ..\..\..\..\mdw\power\kmdw_power_manager.c + + + kmdw_dfu.c + 1 + ..\..\..\..\mdw\dfu\kmdw_dfu.c + + + kdp_crc.c + 1 + ..\..\..\..\mdw\utils\kmdw_utils_crc.c + + + kmdw_system.c + 1 + ..\..\..\..\mdw\system\kmdw_system.c + + + kmdw_ipc.c + 1 + ..\..\..\..\mdw\ipc\kmdw_ipc.c + + + kmdw_model.c + 1 + ..\..\..\..\mdw\model\kmdw_model.c + + + dual_fifo2.c + 1 + ..\..\..\..\mdw\inference\dual_fifo2.c + + + kdp2_inf_generic_raw.c + 1 + ..\..\..\..\mdw\inference\kdp2_inf_generic_raw.c + + + kmdw_inference_520.c + 1 + ..\..\..\..\mdw\inference\kmdw_inference_520.c + + + kmdw_camera.c + 1 + ..\..\..\..\mdw\camera\kmdw_camera.c + + + kmdw_camera_kl520.c + 1 + ..\..\..\..\mdw\camera\kmdw_camera_kl520.c + + + kmdw_sensor.c + 1 + ..\..\..\..\mdw\camera\kmdw_sensor.c + + + kmdw_display.c + 1 + ..\..\..\..\mdw\display\kmdw_display.c + + + kmdw_fifoq_manager.c + 1 + ..\..\..\..\mdw\inference\kmdw_fifoq_manager.c + + + + + device + + + kdev_flash_winbond.c + 1 + ..\..\..\..\platform\dev\flash\kdev_flash_winbond.c + + + kdev_sensor_gc2145.c + 1 + ..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c + + + kdev_sensor_sc132gs.c + 1 + ..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c + + + kdev_mzt_480x272.c + 1 + ..\..\..\..\platform\dev\panel\kdev_mzt_480x272.c + + + + + driver + + + kdrv_pinmux.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_gpio.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + + + kdrv_spif.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_spif.c + + + kdrv_uart.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_ipc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ipc.c + + + kdrv_usbd2.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2.c + + + kdrv_usbd2v.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2v.c + + + kdrv_clock.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_mpu.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mpu.c + + + kdrv_ddr.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_power.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_system.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_wdt.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_wdt.c + + + kdrv_gdma.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + + + rtc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\rtc.c + + + kdrv_pwm.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + kdrv_lcdc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_lcdc.c + + + kdrv_i2c.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + + + kdrv_mipicsirx.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c + + + kdrv_dpi2ahb.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + + + task_handler.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + + + + + libs + + + system_520.lib + 4 + ..\..\..\..\lib\system_520.lib + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/build/solution_kdp2_host_in_uart_out/main_ncpu/main.c b/build/solution_kdp2_host_in_uart_out/main_ncpu/main.c new file mode 100644 index 0000000..fb0021a --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_ncpu/main.c @@ -0,0 +1,33 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2019 Kneron Inc. All rights reserved. + * + * Name: main.c + * Purpose: Kneron NCPU + * + *---------------------------------------------------------------------------*/ + + +#include "cmsis_os2.h" +#include "kdpio.h" + +extern void SystemCoreClockUpdate(void); + +/*---------------------------------------------------------------------------- + * Main: Initialize OS Kernel and NCPU SDK + *---------------------------------------------------------------------------*/ +int main(void) +{ + SystemCoreClockUpdate(); + osKernelInitialize(); + + /* init NCPU */ + kdpio_sdk_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + ; +} diff --git a/build/solution_kdp2_host_in_uart_out/main_ncpu/model_ftr_table.c b/build/solution_kdp2_host_in_uart_out/main_ncpu/model_ftr_table.c new file mode 100644 index 0000000..12d0bc9 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_ncpu/model_ftr_table.c @@ -0,0 +1,48 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2020 Kneron Inc. All rights reserved. + * + * Name: ncpu_extend_ftr.c + * Purpose: Extend new features implementation + * + *---------------------------------------------------------------------------*/ + +#include "kdpio.h" +#include "model_type.h" +#include "model_ppp.h" + +/********************************************************************************* + Registered model pre-process features list + +only need to register functions for models that default builtin pre-proc can't support +*********************************************************************************/ +model_pre_post_func_t model_pre_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < pre-process function > */ + /* -------------------------------------------------------------------------- */ + 0 // no pre-process function is specified + + /* Put customized pre-process functions below: + { CUSTOMER_MODEL_1, preproc_customer_model_1 }, + { CUSTOMER_MODEL_2, preproc_customer_model_2 }, + { CUSTOMER_MODEL_3, preproc_customer_model_3 }, + */ +}; + +/********************************************************************************* + Registered model post-process features list +*********************************************************************************/ +model_pre_post_func_t model_post_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < post-process function > */ + /* -------------------------------------------------------------------------- */ + + { TINY_YOLO_V3_224_224_3, post_yolov3_optimized }, + { TINY_YOLO_V3_416_416_3, post_yolov3_optimized }, + { TINY_YOLO_V3_608_608_3, post_yolov3_optimized }, + { KNERON_YOLOV5S_PersonBicycleCarMotorcycleBusTruckCatDog8_480_256_3, post_yolov5_optimized }, + + /* Put customized post-process functions below: + { CUSTOMER_MODEL_1, post_customer_model_1 }, + { CUSTOMER_MODEL_2, post_customer_model_2 }, + { CUSTOMER_MODEL_3, post_customer_model_3 }, + */ +}; + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/application_init.c b/build/solution_kdp2_host_in_uart_out/main_scpu/application_init.c new file mode 100644 index 0000000..536baea --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/application_init.c @@ -0,0 +1,81 @@ +/* + * Kneron Application initialization + * + * Copyright (C) 2022 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" + +// power manager +#include "kmdw_power_manager.h" + +// inference core +#include "kp_struct.h" +#include "kmdw_console.h" +#include "kmdw_inference_app.h" + +// inference app +#include "kdp2_inf_app_yolo.h" + +// inference client +extern int kdp2_host_in_uart_out_init(void); + +#define MAX_IMAGE_COUNT 12 /**< MAX inference input queue slot count */ +#define MAX_RESULT_COUNT 12 /**< MAX inference output queue slot count */ + + +/** + * @brief To register AI applications + * @param[in] num_input_buf number of data inputs in list + * @param[in] inf_input_buf_list list of data input for inference task + * @return N/A + * @note Add a switch case item for a new inf_app application + */ +static void _app_func(int num_input_buf, void** inf_input_buf_list); + + +void _app_func(int num_input_buf, void** inf_input_buf_list) +{ + // check header stamp + if (0 >= num_input_buf) { + kmdw_printf("No input buffer for app function\n"); + return; + } + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)inf_input_buf_list[0]; + uint32_t job_id = header_stamp->job_id; + + switch (header_stamp->job_id) + { + case KDP2_INF_ID_APP_YOLO: + kdp2_app_yolo_inference(job_id, num_input_buf, inf_input_buf_list); + break; + case KDP2_JOB_ID_APP_YOLO_CONFIG_POST_PROC: + kdp2_app_yolo_config_post_process_parameters(job_id, num_input_buf, inf_input_buf_list); + break; + default: + kmdw_inference_app_send_status_code(job_id, KP_FW_ERROR_UNKNOWN_APP); + break; + } +} + + +void app_initialize(void) +{ + info_msg(">> Start running KL520 KDP2 HOST MIPI mode ...\n"); + + // for shutdown command + kmdw_power_manager_init(); + + /* initialize inference app */ + /* register APP functions */ + /* specify depth of inference queues */ + kmdw_inference_app_init(_app_func, MAX_IMAGE_COUNT, MAX_RESULT_COUNT); + + /* HOST mode init */ + kdp2_host_in_uart_out_init(); + + return; +} diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/device_init.c b/build/solution_kdp2_host_in_uart_out/main_scpu/device_init.c new file mode 100644 index 0000000..72ff34c --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/device_init.c @@ -0,0 +1,25 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +#include "project.h" +#if defined(FLASH_TYPE) && (FLASH_TYPE == FLASH_TYPE_NULL) +#include "kdev_flash_null.h" +#else +#include "kdev_flash.h" +#endif + +//Function +void dev_initialize(void) +{ + kdev_flash_initialize(); +} + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/driver_init.c b/build/solution_kdp2_host_in_uart_out/main_scpu/driver_init.c new file mode 100644 index 0000000..fd5f1c2 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/driver_init.c @@ -0,0 +1,33 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kdrv_uart.h" +#include "kdrv_ddr.h" +#include "kdrv_pinmux.h" +#include "kdrv_timer.h" +#include "kdrv_i2c.h" +#include "kdrv_gpio.h" +#include "kmdw_camera.h" + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; + +void drv_initialize(void) +{ + kdrv_uart_initialize(); + kdrv_pinmux_initialize(PIN_NUM, pinmux_array); + + kdrv_ddr_system_init(DDR_INIT_ALL); // TODO, not 720 style + kdrv_i2c_initialize(KDRV_I2C_CTRL_0, KDRV_I2C_SPEED_400K); +} + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/include/application_init.h b/build/solution_kdp2_host_in_uart_out/main_scpu/include/application_init.h new file mode 100644 index 0000000..980f71b --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/include/application_init.h @@ -0,0 +1,31 @@ +/******************************************************************** + * Copyright (c) 2022 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup APPLICATION_INIT + * @{ + * @brief Kneron application init + * @copyright Copyright (C) 2022 Kneron, Inc. All rights reserved. + */ +#ifndef __APPLICATION_INIT_H__ +#define __APPLICATION_INIT_H__ + +/** + * @brief app_initialize + * + * Add application layer initialization code + * + * @return void + */ +void app_initialize(void); +#endif + + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/include/device_init.h b/build/solution_kdp2_host_in_uart_out/main_scpu/include/device_init.h new file mode 100644 index 0000000..9b1ae22 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/include/device_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup DEVICE_INIT + * @{ + * @brief Kneron device init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __DEVICE_INIT_H__ +#define __DEVICE_INIT_H__ + +/** + * @brief dev_initialize + * + * @return void + */ +void dev_initialize(void); +#endif + + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/include/driver_init.h b/build/solution_kdp2_host_in_uart_out/main_scpu/include/driver_init.h new file mode 100644 index 0000000..d564484 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/include/driver_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup SYSTEM_INIT + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __DRIVER_INIT_H__ +#define __DRIVER_INIT_H__ + +/** + * @brief drv_initialize + * + * @return void + */ +void drv_initialize(void); +#endif + + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/include/host_in_uart_out.h b/build/solution_kdp2_host_in_uart_out/main_scpu/include/host_in_uart_out.h new file mode 100644 index 0000000..73b4062 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/include/host_in_uart_out.h @@ -0,0 +1,38 @@ +/** + * @file host_in_uart_out.h + * @brief macros and data structure for host application of mipi camera in and uart out + * @version 0.1 + * @date 2021-09-30 + * + * @copyright Copyright (c) 2021 Kneron Inc. All rights reserved. + */ + +#pragma once + +/* + === host image buffer layout === + +head_buf -> --------------------------------------- + | buf_header_t | BUF_HEADER_SIZE +img_buf -> |-------------------------------------- + | | + | | + | | + | image body | + | | + | | + | | + |-------------------------------------| + +*/ + +/** + * @brief describe the specific data (especially reference count) required by host mode only + */ +typedef struct +{ + uint32_t img_buf_offset; // image buffer offset from this header + uint32_t read_ref_count; // reference count, [NOT USED] in host in uart out scenario, but add to sync with other host mode scenarios + uint32_t cam_index; // sensor_selection_e + kdp2_ipc_app_yolo_inf_header_t inf_header; +} __attribute__((aligned(4))) buf_header_t; diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/include/middleware_init.h b/build/solution_kdp2_host_in_uart_out/main_scpu/include/middleware_init.h new file mode 100644 index 0000000..f86a89e --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/include/middleware_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup MIDDLEWARE_INIT + * @{ + * @brief Kneron middleware init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __MIDDLEWARE_INIT_H__ +#define __MIDDLEWARE_INIT_H__ + +/** + * @brief mdw_initialize + * + * @return void + */ +void mdw_initialize(void); +#endif + + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/include/system_init.h b/build/solution_kdp2_host_in_uart_out/main_scpu/include/system_init.h new file mode 100644 index 0000000..32fe0c2 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/include/system_init.h @@ -0,0 +1,28 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup SYSTEM_INIT + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __SYSTEM_INIT_H__ +#define __SYSTEM_INIT_H__ + +/** + * @brief sys_initialize + * + * @return void + */ +void sys_initialize(void); +#endif + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/include/task_handler.h b/build/solution_kdp2_host_in_uart_out/main_scpu/include/task_handler.h new file mode 100644 index 0000000..62e596a --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/include/task_handler.h @@ -0,0 +1,89 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup TASK_HANDLER + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef _TASK_HANDLER_H +#define _TASK_HANDLER_H +#include "cmsis_os2.h" +// #include "project.h" +#define USB_HOST +/****************************************************************************** +Declaration of data structure +******************************************************************************/ +// Sec 5: structure, uniou, enum, linked list +typedef struct +{ + //parameters for creating tasks + const char caName[8]; //now, len=8 + + osThreadId_t *tTaskHandle; + osThreadFunc_t fpEntry; + const uint32_t dwStackSize; + osPriority_t dwPriority; + + //parameters for creating queue + osMessageQueueId_t *tQueueHandle; + const uint32_t tQmsg_count; + const uint32_t tQmsg_size; +}T_S_KneronTask; + +osThreadId_t task_log_handle; +osThreadId_t task_infdata_handle; +osThreadId_t task_infcb_handle; +osThreadId_t task_usb_cmd_handle; +osThreadId_t task_uart_cmd_handle; +osThreadId_t task_update_result_handle; +osThreadId_t task_buf_mgr_handle; + +// put osMessageQueueId_t objects here for setting tQueueHandle + +extern void logger_thread(void *arg); +extern void kmdw_inference_image_dispatcher_thread(void *argument); +extern void kmdw_inference_result_handler_callback_thread(void *argument); +extern void kdp2_host_recv_usb_cmd_thread(void *arg); +extern void kdp2_host_recv_uart_cmd_thread(void *arg); +extern void kdp2_host_update_result_thread(void *arg); +extern void kdp2_fifoq_manager_enqueue_image_thread(void *arg); + +/****************************************************************************** +Declaration of Global Variables & Functions +******************************************************************************/ +// Sec 6: declaration of global variable +T_S_KneronTask g_atKneronTaskPool[]= +{ +// TaskName TaskHandle TaskFuncEntry TaskStack TaskPriority QueueHandle QueueMsgCount QueueMsgSize +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + {"LogTask", &task_log_handle, logger_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"Infdata", &task_infdata_handle, kmdw_inference_image_dispatcher_thread, 2048, osPriorityNormal, NULL, 0, 0 }, + {"Infcb", &task_infcb_handle, kmdw_inference_result_handler_callback_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"usbcmd", &task_usb_cmd_handle, kdp2_host_recv_usb_cmd_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"uartcmd", &task_uart_cmd_handle, kdp2_host_recv_uart_cmd_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"uartrslt", &task_update_result_handle, kdp2_host_update_result_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"buf_mgr", &task_buf_mgr_handle, kdp2_fifoq_manager_enqueue_image_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + +// +//Follow above format to add your TASK here +// + + +//end of table, don't remove it +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + {NULL,NULL,NULL,0,0,NULL,0,0} +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +}; + +#endif + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/kdp2_host_in_uart_out.c b/build/solution_kdp2_host_in_uart_out/main_scpu/kdp2_host_in_uart_out.c new file mode 100644 index 0000000..52de480 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/kdp2_host_in_uart_out.c @@ -0,0 +1,602 @@ +//#define ENABLE_DBG_LOG + +#include +#include "cmsis_os2.h" +#include "project.h" +#include "kmdw_power_manager.h" + +#include "kmdw_console.h" +#include "kdrv_power.h" +#include "kdrv_scu_ext.h" +#include "kdp_system.h" + +#include "usbd_hal.h" + +#include "model_type.h" +#include "buffer_object.h" + +#include "kmdw_camera.h" //review merge with 720 code base, kdrv_camera.h +#include "kmdw_fifoq_manager.h" +#include "kdp2_ipc_cmd.h" +#include "kdp2_inf_app_yolo.h" +#include "kdp2_usb_companion.h" + +#include "host_in_uart_out.h" + +#include "kmdw_camera.h" +#include "kdrv_timer.h" +#include "kdrv_i2c.h" + +#include "kmdw_model.h" + +#define BUF_HEADER_SIZE sizeof(buf_header_t) +#define OFFSET_INF_TO_HEAD_BUF (sizeof(buf_header_t) - sizeof(kdp2_ipc_app_yolo_inf_header_t)) + +#define IMG_BUF_TO_HEAD_BUF(img_buf) \ + (uint32_t)((uint32_t)img_buf - BUF_HEADER_SIZE) + +#define NUM_MIPI_INIT_BUFS 2 // ping-pong buffers + +#define NUM_IMG_BUF 10 +#define IMG_BUF_SIZE (1 * 1024 * 1024) +#define NUM_RESULT_BUF 10 +#define RESULT_BUF_SIZE (400 * 1024) +#define CMD_BUF_SIZE (1 * 1024) + +#define JTAG_MAGIC_ADDRESS 0x10100000 +#define KDP2_BOOT_CONFIG_ADDRESS 0x10100100 +#define RECOVERY_MARK_POS (SdRAM_MEM_BASE + SdRAM_MEM_SIZE - 64) + +#define JTAG_MAGIC_VALUE 0xFEDCBA01 +#define BOOT_FROM_FLASH 0xA + +typedef struct +{ + uint32_t boot_type; // 0xA = flash-boot, others = usb-boot + uint8_t loader_ver[4]; // fw loader version numbers + uint8_t scpu_fw_ver[4]; // SCPU fw version numbers + uint8_t ncpu_fw_ver[4]; // NCPU fw version numbers +} kdp2_boot_config_t; + +#ifdef ENABLE_DBG_LOG +#define dbg_log(__format__, ...) kmdw_printf("[kp host mipi]"__format__, ##__VA_ARGS__) +#else +#define dbg_log(__format__, ...) +#endif + +static int dbg_mipi_cnt = 0; +static uint32_t _img_buf_start_addr_backup = 0; +static osThreadId_t _uart_upd_result_tid = NULL; + +// usb link status notify +void usb_user_link_status_callback(usbd_hal_link_status_t link_status) +{ + switch (link_status) + { + case USBD_STATUS_DISCONNECTED: + kmdw_printf("USB is disconnected\n"); + break; + + case USBD_STATUS_CONFIGURED: + kmdw_printf("USB is connected\n"); + break; + } +} + +// vendor-specific control transfer setup packet notify +static bool usb_user_control_callback(usbd_hal_setup_packet_t *setup) +{ + bool ret = false; + + dbg_log("control bRequest = 0x%x\n", setup->bRequest); + + switch (setup->bRequest) + { + case KDP2_CONTROL_REBOOT: + { + dbg_log("control reboot\n"); + kdrv_power_sw_reset(); + break; + } + case KDP2_CONTROL_SHUTDOWN: + { + dbg_log("control shutdown\n"); + kmdw_power_manager_shutdown(); + break; + } + case KDP2_CONTROL_FIFOQ_RESET: + { + dbg_log("control fifoq reset\n"); + + if (true == kmdw_fifoq_manager_get_fifoq_allocated()) + { + usbd_hal_terminate_all_endpoint(); + } + + ret = true; + break; + } + + + default: + ret = false; + break; + } + + return ret; +} + +static uint32_t retrieve_new_buffer_for_mipi() +{ + uint32_t new_head_buf_addr = 0; + int buf_size; + + for (int i = 0; i < NUM_IMG_BUF; i++) // MAX try, not really a for-loop + { + uint32_t new_inf_buf_addr = 0; + + osStatus_t sts = kmdw_fifoq_manager_image_get_free_buffer(&new_inf_buf_addr, &buf_size, 0, true); + if (sts != osOK) { + kmdw_printf("(ISR %d) error !! kmdw_fifoq_manager_image_get_free_buffer() failed, sts = %d\n", dbg_mipi_cnt, sts); + return 0; + } + + new_head_buf_addr = new_inf_buf_addr - OFFSET_INF_TO_HEAD_BUF; + buf_header_t *new_bufHdr = (buf_header_t *)new_head_buf_addr; + + if (new_bufHdr->read_ref_count == 0) + break; // found available one + else + { + // this buf is still in use, return it back to free buf queue + sts = kmdw_fifoq_manager_image_put_free_buffer(new_inf_buf_addr, IMG_BUF_SIZE, 0); + if (sts != osOK) + kmdw_printf("(ISR %d) error !! kmdw_fifoq_manager_image_put_free_buffer() failed, sts = %d\n", dbg_mipi_cnt, sts); + + new_head_buf_addr = 0; + } + } + + if (new_head_buf_addr == 0) + { + kmdw_printf("(ISR %d) error !! cannot retrieve available free buffers\n", dbg_mipi_cnt); + return 0; + } + + return (new_head_buf_addr + BUF_HEADER_SIZE); +} + +static cam_format _cams_fmt[2] = {0}; + +// image ISR callback +void image_coming_callback(uint32_t cam_idx, uint32_t img_buf_addr, uint32_t *pNew_img_buf) +{ + dbg_mipi_cnt++; + + // retrieve a new free buf (from the inference free buffer queue) + *pNew_img_buf = retrieve_new_buffer_for_mipi(); + if ( NULL == pNew_img_buf ) { + *pNew_img_buf = img_buf_addr; + return; + } + + + uint32_t head_buf = img_buf_addr - BUF_HEADER_SIZE; + + // initialize host img header + buf_header_t *bufHdr = (buf_header_t *)head_buf; + bufHdr->img_buf_offset = BUF_HEADER_SIZE; + bufHdr->read_ref_count = 0; + bufHdr->cam_index = cam_idx; + + kdp2_ipc_app_yolo_inf_header_t *infHdr = &bufHdr->inf_header; + + infHdr->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + infHdr->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_inf_header_t) + _cams_fmt[cam_idx].width * _cams_fmt[cam_idx].height * 2; + infHdr->header_stamp.job_id = KDP2_INF_ID_APP_YOLO; + infHdr->header_stamp.status_code = KP_SUCCESS; + infHdr->inf_number = cam_idx; + infHdr->width = _cams_fmt[cam_idx].width; + infHdr->height = _cams_fmt[cam_idx].height; + infHdr->channel = 3; + infHdr->model_id = TINY_YOLO_V3_224_224_3; + + // Add support for more image formats if needed + if (_cams_fmt[cam_idx].pixelformat == IMG_FORMAT_RGB565) + infHdr->image_format = KP_IMAGE_FORMAT_RGB565; + else if (_cams_fmt[cam_idx].pixelformat == IMG_FORMAT_RAW8) + infHdr->image_format = KP_IMAGE_FORMAT_RAW8; + + infHdr->model_normalize = KP_NORMALIZE_KNERON; + + // non-blocking inference enqueue + osStatus_t sts = kmdw_fifoq_manager_image_enqueue(1, 0, (uint32_t)infHdr, IMG_BUF_SIZE, 0, false); + if (sts != osOK) + kmdw_printf("(ISR) error !! kmdw_fifoq_manager_image_enqueue() failed, sts = %d\n", sts); + + return; +} + + +uint32_t camera_start(uint8_t cam_idx, uint32_t width, uint32_t height, uint32_t pixelformat) +{ + uint32_t ret; + + struct cam_capability cap; + + _cams_fmt[cam_idx].width = width; + _cams_fmt[cam_idx].height = height; + _cams_fmt[cam_idx].pixelformat = pixelformat; + + char fmtstr[8]; + memset(&cap, 0, sizeof(cap)); + + if (0 != (ret = kmdw_camera_open(cam_idx))) + return ret; + + if (0 != (ret = kmdw_camera_get_device_info(cam_idx, &cap))) + return ret; + + if (0 != (ret = kmdw_camera_set_frame_format(cam_idx, &_cams_fmt[cam_idx]))) + return ret; + + if (0 != (ret = kmdw_camera_get_frame_format(cam_idx, &_cams_fmt[cam_idx]))) + return ret; + + memset(fmtstr, 0, 8); + memcpy(fmtstr, &_cams_fmt[cam_idx].pixelformat, 4); + + int buf_size; + uint32_t mipi_buf_addr[NUM_MIPI_INIT_BUFS] = {0}; + + // mipi needs some buffers at initialization + for (int i = 0; i < NUM_MIPI_INIT_BUFS; i++) + { + uint32_t head_buf; + // retrieve free hico buffer + kmdw_fifoq_manager_image_get_free_buffer(&head_buf, &buf_size, osWaitForever, false); + // and use its img buffer part for MIPI input + mipi_buf_addr[i] = head_buf + BUF_HEADER_SIZE; + } + + if (0 != (ret = kmdw_camera_buffer_init(cam_idx, mipi_buf_addr[0], mipi_buf_addr[1]))) + return ret; + + if (0 != (ret = kmdw_camera_start(cam_idx, image_coming_callback))) + return ret; + + return 0; +} + +// this thread receive the command from host SW by USB, only support updating FW or model to flash +void kdp2_host_recv_usb_cmd_thread(void *arg) +{ + dbg_log("[%s] start !\n", __FUNCTION__); + + while (USBD_STATUS_CONFIGURED != usbd_hal_get_link_status()) + osDelay(1); + + uint32_t cmd_buf = kmdw_ddr_reserve(CMD_BUF_SIZE); + + while (1) + { + uint32_t txLen = CMD_BUF_SIZE; + kdrv_status_t usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (void *)cmd_buf, &txLen, osWaitForever); + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + { + dbg_log("[%s] bulk receive is terminated, sts %d\n", __FUNCTION__, usb_sts); + continue; + } + + dbg_log("[%s] usb recv addr 0x%x len %d\n", __FUNCTION__, (void *)cmd_buf, txLen); + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)cmd_buf; + + if (header_stamp->magic_type == KDP2_MAGIC_TYPE_COMMAND) + { + dbg_log("handle kdp2 command = 0x%x\n", header_stamp->job_id); + // handle kdp2 commands ... + kdp2_cmd_handle_kp_command(cmd_buf); + } + else if ((header_stamp->magic_type & 0xFFFF) == KDP_MSG_HDR_CMD) // very speical case for old arch. fw update + { + // handle legendary kdp commands, should be as few as possible + dbg_log("handle legendary kdp command = 0x%x\n", header_stamp->job_id); + kdp2_cmd_handle_legend_kdp_command(cmd_buf); + } + else + { + dbg_log("[%s] error ! received un-recognized buffer beginning with incorrect magic_type 0x%x\n", __FUNCTION__, header_stamp->magic_type); + } + } +} + +enum { + UART_CMD_START_TINY_YOLO_V3_INF_RGB = 1, + UART_CMD_START_TINY_YOLO_V3_INF_NIR, + UART_CMD_START_TINY_YOLO_V3_INF_RGB_NIR, + UART_CMD_STOP_TINY_YOLO_V3_INF, + UART_CMD_QUIT, + UART_CMD_NUM +}; + +// this thread receive the command from UART or power button ? +void kdp2_host_recv_uart_cmd_thread(void *arg) +{ + int id = 0; + char buf[64]; + bool cam_started[2] = {false}; + bool quit_thread = false; + + // Implement it if needed ? Press power button to toggle inference + // power_button_register(power_btn_handler); + + while(1) + { + if (id) + goto cmd_prompt; + + DSG("\n === Menu === \n"); + DSG("( 1) Start Tiny YoloV3 Inference with RGB camera\n"); + DSG("( 2) Start Tiny YoloV3 Inference with NIR camera\n"); + DSG("( 3) Start Tiny YoloV3 Inference with RGB and NIR camera\n"); + DSG("( 4) Stop Inference\n"); + DSG("( 5) Quit\n"); + +cmd_prompt: + DSG_NOLF(" command >> "); + memset(buf, 0, sizeof(buf)); + kmdw_console_echo_gets(buf, sizeof(buf)); + + id = atoi(strtok(buf, " \r\n\t")); + + if (id > 0 && id <= UART_CMD_NUM) + { + // FIXME: add mechanism of releasing buffers used by mipi driver to mipi driver and kmdw_camera levels + // following code is just a workaround + if (UART_CMD_START_TINY_YOLO_V3_INF_RGB <= id && id <= UART_CMD_START_TINY_YOLO_V3_INF_RGB_NIR) + { + if (true == cam_started[0] || true == cam_started[1]) + { + DSG("Please stop the current running camera first"); + goto cmd_prompt; + } + + // Wait until all image buffers are not used + while (osThreadBlocked != osThreadGetState(_uart_upd_result_tid)) + osDelay(1); + + uint32_t temp_buf_addr; + int temp_buf_size; + + // clean up image buffers + while (osErrorResource != kmdw_fifoq_manager_image_get_free_buffer(&temp_buf_addr, &temp_buf_size, 0, true)); + + uint32_t img_buf_addr = _img_buf_start_addr_backup; + + // requeue buffers into image free-queue + for (uint32_t i = 0; i < NUM_IMG_BUF; i++) + { + buf_header_t *bufHdr = (buf_header_t *)(img_buf_addr); + bufHdr->read_ref_count = 0; + + kmdw_fifoq_manager_image_put_free_buffer((uint32_t)&bufHdr->inf_header, IMG_BUF_SIZE, osWaitForever); + img_buf_addr += IMG_BUF_SIZE; // next one + } + } + + switch(id) + { + case UART_CMD_START_TINY_YOLO_V3_INF_RGB: + if (0 != camera_start(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT)) + { + DSG("Error ! RGB camera start failed !"); + } + else + cam_started[0] = true; + break; + case UART_CMD_START_TINY_YOLO_V3_INF_NIR: + if (0 != camera_start(1, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, IMGSRC_1_FORMAT)) + { + DSG("Error ! NIR camera start failed !"); + } + else + cam_started[1] = true; + break; + case UART_CMD_START_TINY_YOLO_V3_INF_RGB_NIR: + if (0 != camera_start(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT) || 0 != camera_start(1, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, IMGSRC_1_FORMAT)) + { + DSG("Error ! RGB or NIR camera start failed !"); + } + else + cam_started[0] = cam_started[1] = true; + break; + case UART_CMD_STOP_TINY_YOLO_V3_INF: + case UART_CMD_QUIT: + if (true == cam_started[0]) + { + if (KMDW_STATUS_OK != kmdw_camera_stop(0)) + { + DSG("Error ! RGB camera stop failed !"); + } + kmdw_printf("kmdw_camera_close 0\n"); + if (KMDW_STATUS_OK != kmdw_camera_close(0)) + { + DSG("Error ! RGB camera close failed !"); + } + cam_started[0] = false; + } + if (true == cam_started[1]) + { + if (KMDW_STATUS_OK != kmdw_camera_stop(1)) + { + DSG("Error ! NIR camera stop failed !"); + } + if (KMDW_STATUS_OK != kmdw_camera_close(1)) + { + DSG("Error ! NIR camera close failed !"); + } + cam_started[1] = false; + } + if (id == UART_CMD_QUIT) + { + DSG("Quit"); + quit_thread = true; + } + break; + } + } + else { + if (id) + err_msg("Invalid command: %d\n", id); + continue; + } + + if (quit_thread) + { + kmdw_power_manager_shutdown(); + break; + } + + } +} + +// this thread print inference result to uart. show inference result on local display if there is one ! +void kdp2_host_update_result_thread(void *arg) +{ + dbg_log("[%s] start !\n", __FUNCTION__); + + _uart_upd_result_tid = osThreadGetId(); + + while (1) + { + uint32_t result_buf_addr; + int result_buf_length; + + // get result data from result fifo queue, blocking wait + kmdw_fifoq_manager_result_dequeue(&result_buf_addr, &result_buf_length, osWaitForever); + + // then send inference result + kdp2_ipc_app_yolo_result_t *yolo_result = (kdp2_ipc_app_yolo_result_t *)result_buf_addr; + + // get yolo result and print to uart + if (yolo_result->inf_number == 0) + kmdw_printf("RGB image inference result :\n"); + else if (yolo_result->inf_number == 1) + kmdw_printf("NIR image inference result :\n"); + kmdw_printf("box count : %d\n", yolo_result->yolo_data.box_count); + for (int i = 0; i < yolo_result->yolo_data.box_count; i++) + { + kmdw_printf("Box %d (x1, y1, x2, y2, score, class) = %.1f, %.1f, %.1f, %.1f, %f, %d\n", + i, + yolo_result->yolo_data.boxes[i].x1, yolo_result->yolo_data.boxes[i].y1, + yolo_result->yolo_data.boxes[i].x2, yolo_result->yolo_data.boxes[i].y2, + yolo_result->yolo_data.boxes[i].score, yolo_result->yolo_data.boxes[i].class_num); + } + + // return free buf back to queue + kmdw_fifoq_manager_result_put_free_buffer(result_buf_addr, result_buf_length, osWaitForever); + } +} + +//////////////////////////////////////////////////////////// + +// KDP2 Inference Interface for Host-in-uart-out code +// image input +// inference output (bounding box info in text) with UART +int kdp2_host_in_uart_out_init() +{ + // retrieve real serial number here from efuse + // then convert it to hex string format + + uint32_t uid = 0; + + uid = kdp_sys_get_kn_number(); + + int32_t sidx = 0; + uint8_t kn_num_string[32] = {0}; + for (int i = 7; i >= 0; i--) + { + uint32_t hex = (uid >> i * 4) & 0xF; + kn_num_string[sidx] = (hex < 10) ? '0' + hex : 'A' + (hex - 10); + sidx += 2; + } + + // Host Mode + uint16_t bcdDevice = KP_KDP2_FW_HOST_MODE; + + if (*((uint32_t *)JTAG_MAGIC_ADDRESS) == JTAG_MAGIC_VALUE) + { + kmdw_printf("FW is running in JTAG mode\n"); + bcdDevice |= KP_KDP2_FW_JTAG_TYPE; + } + else + { + kdp2_boot_config_t *bConfig = (kdp2_boot_config_t *)KDP2_BOOT_CONFIG_ADDRESS; + if (bConfig->boot_type == BOOT_FROM_FLASH) + { + kmdw_printf("KDP2 FW is running in flash-boot mode\n"); + bcdDevice |= KP_KDP2_FW_FLASH_TYPE; + + kmdw_printf("boot ncpu fw from flash\n"); + SCU_EXTREG_CM4_NCPU_CTRL_SET_wakeup(1); // run ncpu + } + else + { + kmdw_printf("KDP2 FW is running in usb-boot mode\n"); + bcdDevice |= KP_KDP2_FW_USB_TYPE; + } + } + + // this is about recovery mode + *(uint32_t *)RECOVERY_MARK_POS = 0; + + usbd_hal_initialize(kn_num_string, bcdDevice, usb_user_link_status_callback, usb_user_control_callback); + usbd_hal_set_enable(true); + + /* Allocate memory for image and result buffers */ + uint32_t img_buf_addr = kmdw_ddr_reserve(NUM_IMG_BUF * IMG_BUF_SIZE); + if (img_buf_addr == 0) + { + dbg_log("error !!! kmdw_ddr_reserve() failed for image/result buffers\n"); + return -1; + } + + // back up image buffer start address for reopening the camera + // FIXME: this is just a workaround + _img_buf_start_addr_backup = img_buf_addr; + + // queue buffers into image free-queue + for (uint32_t i = 0; i < NUM_IMG_BUF; i++) + { + buf_header_t *bufHdr = (buf_header_t *)(img_buf_addr); + bufHdr->read_ref_count = 0; + + kmdw_fifoq_manager_image_put_free_buffer((uint32_t)&bufHdr->inf_header, IMG_BUF_SIZE, osWaitForever); + img_buf_addr += IMG_BUF_SIZE; // next one + } + + uint32_t result_buf_addr = kmdw_ddr_reserve(NUM_RESULT_BUF * RESULT_BUF_SIZE); + + // queue buffers into result free-queue + for (uint32_t i = 0; i < NUM_RESULT_BUF; i++) + { + kmdw_fifoq_manager_result_put_free_buffer(result_buf_addr, RESULT_BUF_SIZE, osWaitForever); + result_buf_addr += RESULT_BUF_SIZE; + } + + kmdw_fifoq_manager_store_fifoq_config(NUM_IMG_BUF, IMG_BUF_SIZE, NUM_RESULT_BUF, RESULT_BUF_SIZE); + + // wow ! fifoq can also handle command + kdp2_cmd_handler_initialize(); + + // load model from flash + int32_t load_model_sts = kmdw_model_load_model(-1); + if (0 < load_model_sts) + { + dbg_log("error !!! kmdw_model_load_model() failed for loading model from flash\n"); + return -1; + } + + return 0; +} diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/main.c b/build/solution_kdp2_host_in_uart_out/main_scpu/main.c new file mode 100644 index 0000000..8496b5d --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/main.c @@ -0,0 +1,57 @@ +/* + * Kneron Main Entry driver + * + * Copyright (C) 2020 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +#include "project.h" +#include "version.h" + +// Customized configration and implementation +#include "system_init.h" +#include "driver_init.h" +#include "device_init.h" +#include "middleware_init.h" +#include "application_init.h" + +#include "kmdw_console.h" + +extern void task_initialize(void); + +/** + * @brief main, main function + */ +int main(void) +{ + osKernelInitialize(); // Initialize CMSIS-RTOS + sys_initialize(); + drv_initialize(); /* customize driver initialization, see driver_init.c */ + dev_initialize(); /* customize device initialization, see device_init.c */ + mdw_initialize(); /* customize middleware initialization, see middlewre_init.c */ + + + printf("SDK v%u.%u.%u-:build.%03u\n", + (uint8_t)(IMG_FW_MAJOR), + (uint8_t)(IMG_FW_MINOR), + (uint8_t)(IMG_FW_UPDATE), + (uint32_t)(IMG_FW_BUILD)); + + app_initialize(); /* customize application initialization, see application_init.c */ + + /* New task threads */ + task_initialize(); + + /* Start RTOS Kernel */ + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/middleware_init.c b/build/solution_kdp2_host_in_uart_out/main_scpu/middleware_init.c new file mode 100644 index 0000000..d46d779 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/middleware_init.c @@ -0,0 +1,39 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kmdw_memory.h" +#include "kmdw_model.h" +#include "kmdw_dfu.h" +#include "kmdw_camera.h" +#include "kmdw_display.h" +#include "kmdw_console.h" +/* config PROJ_NOT_USE_FW_LOADER in project.h */ +#if (defined(PROJ_NOT_USE_FW_LOADER) && (PROJ_NOT_USE_FW_LOADER != 0)) +#include "kmdw_system.h" /* for load_ncpu_fw */ +#endif + +void mdw_initialize(void) +{ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kmdw_ddr_store_system_reserve(DDR_SYSTEM_RESERVED_BEGIN, DDR_SYSTEM_RESERVED_END); + kmdw_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE); // uart console + kmdw_dfu_init(NULL, NULL); + kmdw_model_init(); + +#if (defined(PROJ_NOT_USE_FW_LOADER) && (PROJ_NOT_USE_FW_LOADER != 0)) + load_ncpu_fw(1/*reset_flag*/); // (kmdw_system.h) load ncpu fw from flash +#endif + kmdw_camera_init(); // init cameras +} + diff --git a/build/solution_kdp2_host_in_uart_out/main_scpu/system_init.c b/build/solution_kdp2_host_in_uart_out/main_scpu/system_init.c new file mode 100644 index 0000000..a89c8f3 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/main_scpu/system_init.c @@ -0,0 +1,23 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +//#include "project.h" +#include "kdrv_system.h" + + + //Function +void sys_initialize(void) +{ + /* SDK main init for companion mode */ + kdrv_system_init(); + kdrv_system_init_ncpu(); +} diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/Objects/fw_ncpu.bin b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/Objects/fw_ncpu.bin new file mode 100644 index 0000000..9028ab8 Binary files /dev/null and b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/Objects/fw_ncpu.bin differ diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.sct b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.sct new file mode 100644 index 0000000..7e4a57e --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.sct @@ -0,0 +1,19 @@ +#!armcc -E +#define DRAM_START 0x0FFF0000 +#define DRAM_SIZE 0x00010000 + +LR_IROM1 0x00000000 0x00010000 { ; load region size_region + ER_IROM1 0x00000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } +} + diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.uvoptx b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.uvoptx new file mode 100644 index 0000000..2d4b322 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.uvoptx @@ -0,0 +1,552 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ncpu + 0x4 + ARM-ADS + + 250000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ULP2CM3 + -UAny -O905 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO3 -FD20000000 -FC1000 -FN0 + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U63610859 -O1 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO1 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 169 + 1 +
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+ 0 + 0 + 0 + 0 + 0 + 0 + D:\3_code\mozart_sw_kdp2.git\scpu\project\companion_kdp2\main\main.c + + + + + + + 1 + 2 + 0x30ff0140 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\model_ftr_table.c + model_ftr_table.c + 0 + 0 + + + + + libs + 1 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + kdp2_ncpu_sdk.lib + 0 + 0 + + + 2 + 4 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + kdp2_ncpu_model_ppp.lib + 0 + 0 + + + + + rtx + 1 + 0 + 0 + 0 + + 3 + 5 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + irq_cm4f.s + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + os_systick.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + RTX_Config.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + rtx_delay.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + rtx_evflags.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + rtx_evr.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + rtx_kernel.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + rtx_lib.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + rtx_memory.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + rtx_mempool.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + rtx_msgqueue.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + rtx_mutex.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + rtx_semaphore.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + rtx_system.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + rtx_thread.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + startup.c + 0 + 0 + + + 4 + 22 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.uvprojx b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.uvprojx new file mode 100644 index 0000000..ddfadab --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/ncpu.uvprojx @@ -0,0 +1,547 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ncpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.5.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Mozart_ncpu + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_ncpu.bin" + post_build.bat fw_ncpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0xfff0000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + ARM_MATH_CM4, TARGET_NCPU, LOG_ENABLE, KL520 + + ..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\ncpu\drv\include;..\..\..\..\platform\kl520\ncpu\model_ppp\include;..\..\..\..\platform\kl520\ncpu\rtos\rtx\include;..\..\..\..\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\..\..\include + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x00000000 + 0x20000000 + + ..\..\..\..\platform\kl520\ncpu\mozart_ncpu.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_ncpu\main.c + + + model_ftr_table.c + 1 + ..\..\main_ncpu\model_ftr_table.c + + + + + libs + + + kdp2_ncpu_sdk.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + + + kdp2_ncpu_model_ppp.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/post_build.bat b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/post_build.bat new file mode 100644 index 0000000..1ac5a9c --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/ncpu_keil/post_build.bat @@ -0,0 +1,10 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_ncpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/proj.uvmpw b/build/solution_kdp2_host_in_uart_out/sn52096/proj.uvmpw new file mode 100644 index 0000000..b2cf24d --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/proj.uvmpw @@ -0,0 +1,23 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + + .\scpu_keil\scpu.uvprojx + 1 + 1 + + + + + + .\ncpu_keil\ncpu.uvprojx + + + diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/project.h b/build/solution_kdp2_host_in_uart_out/sn52096/project.h new file mode 100644 index 0000000..898af97 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/project.h @@ -0,0 +1,187 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +CAM setting +=============================================================================*/ +//project.h +#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 + +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +#define PROJ_NOT_USE_FW_LOADER 0 /**< no fw_loader.bin section in fw image + if set as 1, must rebuild with corresponding scatter, kdp.sct */ + +/* Flash table for PROJ_NOT_USE_FW_LOADER = 1*/ +/* Flash table */ +#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +#define FLASH_FW_NCPU0_ADDR 0x00018000 /**< fw_ncpu.bin */ +#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +#define FLASH_MODEL_ALL_ADDR 0x00301000 /**< all_models.bin */ +#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/kdp2_scpu_jlink.ini b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/kdp2_scpu_jlink.ini new file mode 100644 index 0000000..d4099c3 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/kdp2_scpu_jlink.ini @@ -0,0 +1,13 @@ +MEMSET(0x10200000, 0x18000, 0) +MEMSET(0x10210000, 0x08000, 0) + +// to let USB know this is running in JTAG mode +MEMSET(0x10100000, 1, 0x01) +MEMSET(0x10100001, 1, 0xBA) +MEMSET(0x10100002, 1, 0xDC) +MEMSET(0x10100003, 1, 0xFE) + +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10104000) // Set Stack Pointer +PC=_RDWORD(0x10104004) // Set Program Counter = Reset_Handler +BS main \ No newline at end of file diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/post_build.bat b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/post_build.bat new file mode 100644 index 0000000..f839167 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/post_build.bat @@ -0,0 +1,12 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_scpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ + + diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/pre_build.bat b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/pre_build.bat new file mode 100644 index 0000000..dba1dc6 --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/pre_build.bat @@ -0,0 +1 @@ +REM "prebuild script" diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/scpu.uvoptx b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..f6511dc --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,1206 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + dev + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\kdp2_scpu_jlink.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + 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kdrv_dpi2ahb.c + 0 + 0 + + + + + rtx + 0 + 0 + 0 + 0 + + 7 + 56 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\irq_cm4f.s + irq_cm4f.s + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\os_systick.c + os_systick.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\RTX_Config.c + RTX_Config.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_delay.c + rtx_delay.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evflags.c + rtx_evflags.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evr.c + rtx_evr.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_kernel.c + rtx_kernel.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_lib.c + rtx_lib.c + 0 + 0 + + + 7 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_memory.c + rtx_memory.c + 0 + 0 + + + 7 + 65 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mempool.c + rtx_mempool.c + 0 + 0 + + + 7 + 66 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_msgqueue.c + rtx_msgqueue.c + 0 + 0 + + + 7 + 67 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mutex.c + rtx_mutex.c + 0 + 0 + + + 7 + 68 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_semaphore.c + rtx_semaphore.c + 0 + 0 + + + 7 + 69 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_system.c + rtx_system.c + 0 + 0 + + + 7 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_thread.c + rtx_thread.c + 0 + 0 + + + 7 + 71 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + 7 + 72 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + task_handler.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 8 + 73 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + startup.c + 0 + 0 + + + 8 + 74 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + + libs + 0 + 0 + 0 + 0 + + 9 + 75 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\system_520.lib + system_520.lib + 0 + 0 + + + + diff --git a/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/scpu.uvprojx b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..9b4528e --- /dev/null +++ b/build/solution_kdp2_host_in_uart_out/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,837 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + dev + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.5.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + scpu_fw + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + pre_build.bat + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_scpu.bin" + post_build.bat fw_scpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, BOARD_96 + + ..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\platform\kl520\scpu\rtos\rtx\include;..\..\..\..\platform\board\board_sn52096;..\..\..\..\platform\dev\include;..\..\..\..\mdw\include;..\..\..\..\mdw\inference;..\..\..\..\app;..\..\main_scpu\include;..\;..\..\..\lib\system_520\main_scpu\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\sn52096;..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\board\board_sn52096 + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + ..\..\..\..\platform\kl520\scpu\scatter_load.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_scpu\main.c + + + project.h + 5 + ..\project.h + + + task_handler.h + 5 + ..\..\main_scpu\include\task_handler.h + + + application_init.c + 1 + ..\..\main_scpu\application_init.c + + + device_init.c + 1 + ..\..\main_scpu\device_init.c + + + driver_init.c + 1 + ..\..\main_scpu\driver_init.c + + + middleware_init.c + 1 + ..\..\main_scpu\middleware_init.c + + + system_init.c + 1 + ..\..\main_scpu\system_init.c + + + + + inf_app + + + demo_customize_inf_single_model.c + 1 + ..\..\..\..\app\demo_customize_inf_single_model.c + + + demo_customize_inf_multiple_models.c + 1 + ..\..\..\..\app\demo_customize_inf_multiple_models.c + + + kdp2_inf_app_yolo.c + 1 + ..\..\..\..\app\kdp2_inf_app_yolo.c + + + + + inf_client + + + kdp2_cmd_handler_520.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_cmd_handler_520.c + + + usbd_hal_520.c + 1 + ..\..\..\..\mdw\usb_companion\usbd_hal_520.c + + + kdp2_usb_log.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_usb_log.c + + + kdp2_host_in_uart_out.c + 1 + ..\..\main_scpu\kdp2_host_in_uart_out.c + + + + + middleware + + + kmdw_memory.c + 1 + ..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_memxfer.c + 1 + ..\..\..\..\mdw\flash\kmdw_memxfer.c + + + kmdw_console.c + 1 + ..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_power_manager.c + 1 + ..\..\..\..\mdw\power\kmdw_power_manager.c + + + kmdw_dfu.c + 1 + ..\..\..\..\mdw\dfu\kmdw_dfu.c + + + kdp_crc.c + 1 + ..\..\..\..\mdw\utils\kmdw_utils_crc.c + + + kmdw_system.c + 1 + ..\..\..\..\mdw\system\kmdw_system.c + + + kmdw_ipc.c + 1 + ..\..\..\..\mdw\ipc\kmdw_ipc.c + + + kmdw_model.c + 1 + ..\..\..\..\mdw\model\kmdw_model.c + + + dual_fifo2.c + 1 + ..\..\..\..\mdw\inference\dual_fifo2.c + + + kdp2_inf_generic_raw.c + 1 + ..\..\..\..\mdw\inference\kdp2_inf_generic_raw.c + + + kmdw_inference_520.c + 1 + ..\..\..\..\mdw\inference\kmdw_inference_520.c + + + kmdw_camera.c + 1 + ..\..\..\..\mdw\camera\kmdw_camera.c + + + kmdw_camera_kl520.c + 1 + ..\..\..\..\mdw\camera\kmdw_camera_kl520.c + + + kmdw_sensor.c + 1 + ..\..\..\..\mdw\camera\kmdw_sensor.c + + + kmdw_fifoq_manager.c + 1 + ..\..\..\..\mdw\inference\kmdw_fifoq_manager.c + + + + + device + + + kdev_flash_winbond.c + 1 + ..\..\..\..\platform\dev\flash\kdev_flash_winbond.c + + + kdev_sensor_gc2145.c + 1 + ..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c + + + kdev_sensor_sc132gs.c + 1 + ..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c + + + kdev_mzt_480x272.c + 1 + ..\..\..\..\platform\dev\panel\kdev_mzt_480x272.c + + + + + driver + + + kdrv_pinmux.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_gpio.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + + + kdrv_spif.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_spif.c + + + kdrv_uart.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_ipc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ipc.c + + + kdrv_usbd2.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2.c + + + kdrv_usbd2v.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2v.c + + + kdrv_clock.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_mpu.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mpu.c + + + kdrv_ddr.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_power.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_system.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_wdt.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_wdt.c + + + kdrv_gdma.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + + + rtc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\rtc.c + + + kdrv_pwm.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + kdrv_lcdc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_lcdc.c + + + kdrv_i2c.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + + + kdrv_mipicsirx.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c + + + kdrv_dpi2ahb.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + + + task_handler.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + + + + + libs + + + system_520.lib + 4 + ..\..\..\..\lib\system_520.lib + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/build/solution_kdp2_host_mipi/main_ncpu/main.c b/build/solution_kdp2_host_mipi/main_ncpu/main.c new file mode 100644 index 0000000..fb0021a --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_ncpu/main.c @@ -0,0 +1,33 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2019 Kneron Inc. All rights reserved. + * + * Name: main.c + * Purpose: Kneron NCPU + * + *---------------------------------------------------------------------------*/ + + +#include "cmsis_os2.h" +#include "kdpio.h" + +extern void SystemCoreClockUpdate(void); + +/*---------------------------------------------------------------------------- + * Main: Initialize OS Kernel and NCPU SDK + *---------------------------------------------------------------------------*/ +int main(void) +{ + SystemCoreClockUpdate(); + osKernelInitialize(); + + /* init NCPU */ + kdpio_sdk_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + ; +} diff --git a/build/solution_kdp2_host_mipi/main_ncpu/model_ftr_table.c b/build/solution_kdp2_host_mipi/main_ncpu/model_ftr_table.c new file mode 100644 index 0000000..12d0bc9 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_ncpu/model_ftr_table.c @@ -0,0 +1,48 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2020 Kneron Inc. All rights reserved. + * + * Name: ncpu_extend_ftr.c + * Purpose: Extend new features implementation + * + *---------------------------------------------------------------------------*/ + +#include "kdpio.h" +#include "model_type.h" +#include "model_ppp.h" + +/********************************************************************************* + Registered model pre-process features list + +only need to register functions for models that default builtin pre-proc can't support +*********************************************************************************/ +model_pre_post_func_t model_pre_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < pre-process function > */ + /* -------------------------------------------------------------------------- */ + 0 // no pre-process function is specified + + /* Put customized pre-process functions below: + { CUSTOMER_MODEL_1, preproc_customer_model_1 }, + { CUSTOMER_MODEL_2, preproc_customer_model_2 }, + { CUSTOMER_MODEL_3, preproc_customer_model_3 }, + */ +}; + +/********************************************************************************* + Registered model post-process features list +*********************************************************************************/ +model_pre_post_func_t model_post_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < post-process function > */ + /* -------------------------------------------------------------------------- */ + + { TINY_YOLO_V3_224_224_3, post_yolov3_optimized }, + { TINY_YOLO_V3_416_416_3, post_yolov3_optimized }, + { TINY_YOLO_V3_608_608_3, post_yolov3_optimized }, + { KNERON_YOLOV5S_PersonBicycleCarMotorcycleBusTruckCatDog8_480_256_3, post_yolov5_optimized }, + + /* Put customized post-process functions below: + { CUSTOMER_MODEL_1, post_customer_model_1 }, + { CUSTOMER_MODEL_2, post_customer_model_2 }, + { CUSTOMER_MODEL_3, post_customer_model_3 }, + */ +}; + diff --git a/build/solution_kdp2_host_mipi/main_scpu/application_init.c b/build/solution_kdp2_host_mipi/main_scpu/application_init.c new file mode 100644 index 0000000..3ff2952 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/application_init.c @@ -0,0 +1,81 @@ +/* + * Kneron Application initialization + * + * Copyright (C) 2022 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" + +// power manager +#include "kmdw_power_manager.h" + +// inference core +#include "kp_struct.h" +#include "kmdw_console.h" +#include "kmdw_inference_app.h" + +// inference app +#include "kdp2_inf_app_yolo.h" + +// inference client +extern int kdp2_host_mipi_init(void); + +#define MAX_IMAGE_COUNT 12 /**< MAX inference input queue slot count */ +#define MAX_RESULT_COUNT 12 /**< MAX inference output queue slot count */ + + +/** + * @brief To register AI applications + * @param[in] num_input_buf number of data inputs in list + * @param[in] inf_input_buf_list list of data input for inference task + * @return N/A + * @note Add a switch case item for a new inf_app application + */ +static void _app_func(int num_input_buf, void** inf_input_buf_list); + + +void _app_func(int num_input_buf, void** inf_input_buf_list) +{ + // check header stamp + if (0 >= num_input_buf) { + kmdw_printf("No input buffer for app function\n"); + return; + } + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)inf_input_buf_list[0]; + uint32_t job_id = header_stamp->job_id; + + switch (header_stamp->job_id) + { + case KDP2_INF_ID_APP_YOLO: + kdp2_app_yolo_inference(job_id, num_input_buf, inf_input_buf_list); + break; + case KDP2_JOB_ID_APP_YOLO_CONFIG_POST_PROC: + kdp2_app_yolo_config_post_process_parameters(job_id, num_input_buf, inf_input_buf_list); + break; + default: + kmdw_inference_app_send_status_code(job_id, KP_FW_ERROR_UNKNOWN_APP); + break; + } +} + + +void app_initialize(void) +{ + info_msg(">> Start running KL520 KDP2 HOST MIPI mode ...\n"); + + // for shutdown command + kmdw_power_manager_init(); + + /* initialize inference app */ + /* register APP functions */ + /* specify depth of inference queues */ + kmdw_inference_app_init(_app_func, MAX_IMAGE_COUNT, MAX_RESULT_COUNT); + + /* HOST mode init */ + kdp2_host_mipi_init(); + + return; +} diff --git a/build/solution_kdp2_host_mipi/main_scpu/device_init.c b/build/solution_kdp2_host_mipi/main_scpu/device_init.c new file mode 100644 index 0000000..72ff34c --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/device_init.c @@ -0,0 +1,25 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +#include "project.h" +#if defined(FLASH_TYPE) && (FLASH_TYPE == FLASH_TYPE_NULL) +#include "kdev_flash_null.h" +#else +#include "kdev_flash.h" +#endif + +//Function +void dev_initialize(void) +{ + kdev_flash_initialize(); +} + diff --git a/build/solution_kdp2_host_mipi/main_scpu/display_init.c b/build/solution_kdp2_host_mipi/main_scpu/display_init.c new file mode 100644 index 0000000..ea48efb --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/display_init.c @@ -0,0 +1,40 @@ +/* + * + * Copyright (C) 2020 Kneron, Inc. All rights reserved. + * + */ + + +#include +#include +#include "cmsis_os2.h" +#include "kmdw_display.h" +#include "kmdw_console.h" + +static int display_inited = 0; + +void display_init(uint32_t input_fmt, uint16_t xres, uint16_t yres, uint8_t cam_idx) +{ + struct video_input_params params; + + if (display_inited == 0) { + params.input_fmt = input_fmt; + params.input_xres = xres; + params.input_yres = yres; + kmdw_video_renderer_open(¶ms); + kmdw_video_renderer_set_camera(cam_idx); + kmdw_display_set_pen_rgb565(BLACK, 1); + kmdw_video_renderer_buffer_initialize(¶ms); + kmdw_video_renderer_start(); + display_inited = 1; + kmdw_printf("input_fmt=0x%x, input_xres=%d, input_yres=%d, cam_idx=%d \n",params.input_fmt, params.input_xres, params.input_yres, cam_idx); + } +} + +void display_exit(void) +{ + if (display_inited == 1) { + kmdw_video_renderer_stop(); + display_inited = 0; + } +} diff --git a/build/solution_kdp2_host_mipi/main_scpu/driver_init.c b/build/solution_kdp2_host_mipi/main_scpu/driver_init.c new file mode 100644 index 0000000..c5c1068 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/driver_init.c @@ -0,0 +1,47 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kdrv_uart.h" +#include "kdrv_ddr.h" +#include "kdrv_pinmux.h" +#include "kdrv_timer.h" +#include "kdrv_i2c.h" +#include "kdrv_gpio.h" +#include "kmdw_camera.h" + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; + +void drv_initialize(void) +{ + kdrv_uart_initialize(); + kdrv_pinmux_initialize(PIN_NUM, pinmux_array); + + kdrv_ddr_system_init(DDR_INIT_ALL); // TODO, not 720 style + kdrv_i2c_initialize(KDRV_I2C_CTRL_0, KDRV_I2C_SPEED_400K); + //kdrv_gpio_initialize(GPIO_NUM, gpio_attr_ctx); + //kdrv_timer_initialize(); + //kdrv_timer_perf_measure_start(); + + /* Init these functions in kmdw_camera_init on 520 + for(uint32_t cam_id = 0; cam_id < CAM_ID_MAX ; cam_id++) + { + if(cam_ctx[cam_id].cam_input_type!= IMG_SRC_IN_PORT_NONE) + { + kdrv_csirx_initialize(cam_id); + kdrv_dpi2ahb_initialize(cam_id); + } + } + */ +} + diff --git a/build/solution_kdp2_host_mipi/main_scpu/include/application_init.h b/build/solution_kdp2_host_mipi/main_scpu/include/application_init.h new file mode 100644 index 0000000..980f71b --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/include/application_init.h @@ -0,0 +1,31 @@ +/******************************************************************** + * Copyright (c) 2022 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup APPLICATION_INIT + * @{ + * @brief Kneron application init + * @copyright Copyright (C) 2022 Kneron, Inc. All rights reserved. + */ +#ifndef __APPLICATION_INIT_H__ +#define __APPLICATION_INIT_H__ + +/** + * @brief app_initialize + * + * Add application layer initialization code + * + * @return void + */ +void app_initialize(void); +#endif + + diff --git a/build/solution_kdp2_host_mipi/main_scpu/include/device_init.h b/build/solution_kdp2_host_mipi/main_scpu/include/device_init.h new file mode 100644 index 0000000..9b1ae22 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/include/device_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup DEVICE_INIT + * @{ + * @brief Kneron device init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __DEVICE_INIT_H__ +#define __DEVICE_INIT_H__ + +/** + * @brief dev_initialize + * + * @return void + */ +void dev_initialize(void); +#endif + + diff --git a/build/solution_kdp2_host_mipi/main_scpu/include/driver_init.h b/build/solution_kdp2_host_mipi/main_scpu/include/driver_init.h new file mode 100644 index 0000000..d564484 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/include/driver_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup SYSTEM_INIT + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __DRIVER_INIT_H__ +#define __DRIVER_INIT_H__ + +/** + * @brief drv_initialize + * + * @return void + */ +void drv_initialize(void); +#endif + + diff --git a/build/solution_kdp2_host_mipi/main_scpu/include/host_mipi.h b/build/solution_kdp2_host_mipi/main_scpu/include/host_mipi.h new file mode 100644 index 0000000..a624ce4 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/include/host_mipi.h @@ -0,0 +1,78 @@ +/** + * @file host_mipi.h + * @brief macros and data structure for hico application of mipi camera + * @version 0.1 + * @date 2021-09-30 + * + * @copyright Copyright (c) 2021 Kneron Inc. All rights reserved. + */ + +#pragma once + +/* + === host image buffer layout === + +head_buf -> --------------------------------------- + | buf_header_t | BUF_HEADER_SIZE +img_buf -> |-------------------------------------- + | | + | | + | | + | image body | + | | + | | + | | + |-------------------------------------| + +*/ + +#define MAX_NUM_CAMERA 4 + +enum user_cmd_e +{ + COMMAND_START_CAMERA = 0x1, + COMMAND_SELECT_CAMERA = 0x2, +}; + +typedef struct +{ + kp_inference_header_stamp_t header_stamp; + uint32_t cmd_id; // COMMAND_START_CAMERA +} __attribute__((aligned(4))) start_camera_cmd_t; + +typedef struct +{ + uint32_t img_width; // in pixel + uint32_t img_height; // in pixel + uint32_t img_format; // kp_image_format_t + uint32_t img_channel; + uint32_t img_buf_size; +} camera_settings_t; + +typedef struct +{ + kp_inference_header_stamp_t header_stamp; + uint32_t cmd_id; // COMMAND_START_CAMERA + uint32_t num_cam_sensors; + camera_settings_t cam_set[MAX_NUM_CAMERA]; +} __attribute__((aligned(4))) start_camera_resp_t; + +typedef struct +{ + kp_inference_header_stamp_t header_stamp; + uint32_t cmd_id; // COMMAND_SELECT_CAMERA + uint32_t sel_camera; // camera selection index, start from 0 +} __attribute__((aligned(4))) select_camera_cmd_t; + +#define HICO_IMAGE_RECEIVER_HEADER_MAGIC 0x11223344 // should avoid KDP2_MAGIC_TYPE_XXXX values, indicating this is an image header + +typedef struct +{ + uint32_t magic_type; // HICO_IMAGE_RECEIVER_HEADER_MAGIC + uint32_t img_buf_offset; // image buffer offset from this header + uint32_t read_ref_count; // only used in FW, ignored by SW + uint32_t cam_index; // sensor_selection_e +#ifdef FW_BUILD + kdp2_ipc_app_yolo_inf_header_t inf_header; +#endif +} __attribute__((aligned(4))) buf_header_t; diff --git a/build/solution_kdp2_host_mipi/main_scpu/include/middleware_init.h b/build/solution_kdp2_host_mipi/main_scpu/include/middleware_init.h new file mode 100644 index 0000000..f86a89e --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/include/middleware_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup MIDDLEWARE_INIT + * @{ + * @brief Kneron middleware init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __MIDDLEWARE_INIT_H__ +#define __MIDDLEWARE_INIT_H__ + +/** + * @brief mdw_initialize + * + * @return void + */ +void mdw_initialize(void); +#endif + + diff --git a/build/solution_kdp2_host_mipi/main_scpu/include/system_init.h b/build/solution_kdp2_host_mipi/main_scpu/include/system_init.h new file mode 100644 index 0000000..32fe0c2 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/include/system_init.h @@ -0,0 +1,28 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup SYSTEM_INIT + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __SYSTEM_INIT_H__ +#define __SYSTEM_INIT_H__ + +/** + * @brief sys_initialize + * + * @return void + */ +void sys_initialize(void); +#endif + diff --git a/build/solution_kdp2_host_mipi/main_scpu/include/task_handler.h b/build/solution_kdp2_host_mipi/main_scpu/include/task_handler.h new file mode 100644 index 0000000..c62cb98 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/include/task_handler.h @@ -0,0 +1,89 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup TASK_HANDLER + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef _TASK_HANDLER_H +#define _TASK_HANDLER_H +#include "cmsis_os2.h" +// #include "project.h" +#define USB_HOST +/****************************************************************************** +Declaration of data structure +******************************************************************************/ +// Sec 5: structure, uniou, enum, linked list +typedef struct +{ + //parameters for creating tasks + const char caName[8]; //now, len=8 + + osThreadId_t *tTaskHandle; + osThreadFunc_t fpEntry; + const uint32_t dwStackSize; + osPriority_t dwPriority; + + //parameters for creating queue + osMessageQueueId_t *tQueueHandle; + const uint32_t tQmsg_count; + const uint32_t tQmsg_size; +}T_S_KneronTask; + +osThreadId_t task_log_handle; +osThreadId_t task_infdata_handle; +osThreadId_t task_infcb_handle; +osThreadId_t task_uart_cmd_handle; +osThreadId_t task_update_result_handle; +osThreadId_t task_update_display_handle; +osThreadId_t task_buf_mgr_handle; + +// put osMessageQueueId_t objects here for setting tQueueHandle + +extern void logger_thread(void *arg); +extern void kmdw_inference_image_dispatcher_thread(void *argument); +extern void kmdw_inference_result_handler_callback_thread(void *argument); +extern void kdp2_host_recv_uart_cmd_thread(void *arg); +extern void kdp2_host_update_result_thread(void *arg); +extern void kdp2_host_update_display_thread(void *arg); +extern void kdp2_fifoq_manager_enqueue_image_thread(void *arg); + +/****************************************************************************** +Declaration of Global Variables & Functions +******************************************************************************/ +// Sec 6: declaration of global variable +T_S_KneronTask g_atKneronTaskPool[]= +{ +// TaskName TaskHandle TaskFuncEntry TaskStack TaskPriority QueueHandle QueueMsgCount QueueMsgSize +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + {"LogTask", &task_log_handle, logger_thread, 1024, osPriorityBelowNormal, NULL, 0, 0 }, + {"Infdata", &task_infdata_handle, kmdw_inference_image_dispatcher_thread, 2048, osPriorityNormal, NULL, 0, 0 }, + {"Infcb", &task_infcb_handle, kmdw_inference_result_handler_callback_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"uartcmd", &task_uart_cmd_handle, kdp2_host_recv_uart_cmd_thread, 1024, osPriorityBelowNormal, NULL, 0, 0 }, + {"updrslt", &task_update_result_handle, kdp2_host_update_result_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"upddisp", &task_update_display_handle, kdp2_host_update_display_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"buf_mgr", &task_buf_mgr_handle, kdp2_fifoq_manager_enqueue_image_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + +// +//Follow above format to add your TASK here +// + + +//end of table, don't remove it +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + {NULL,NULL,NULL,0,0,NULL,0,0} +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +}; + +#endif + diff --git a/build/solution_kdp2_host_mipi/main_scpu/kdp2_host_mipi.c b/build/solution_kdp2_host_mipi/main_scpu/kdp2_host_mipi.c new file mode 100644 index 0000000..7bc70c0 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/kdp2_host_mipi.c @@ -0,0 +1,1061 @@ + +#include +#include "cmsis_os2.h" +#include "project.h" +#include "kmdw_power_manager.h" + +#include "kmdw_console.h" +#include "kdrv_power.h" +#include "kdrv_scu_ext.h" +#include "kdp_system.h" + +#include "usbd_hal.h" + +#include "model_type.h" +#include "buffer_object.h" + +#include "kmdw_camera.h"//review merge with 720 code base, kdrv_camera.h +#include "kmdw_fifoq_manager.h" +#include "kdp2_ipc_cmd.h" +#include "kdp2_inf_app_yolo.h" +#include "kdp2_usb_companion.h" + +//for display format, e.g. #define V2K_PIX_FMT_RGB565 v2k_fourcc('R', 'G', 'B', 'P') +#include "kmdw_display.h" + +#define FW_BUILD // for host_mipi.h +#include "host_mipi.h" + +#include "kmdw_camera.h" +#include "kdrv_timer.h" +#include "kdrv_i2c.h" + + +#define BUF_HEADER_SIZE sizeof(buf_header_t) +#define OFFSET_INF_TO_HEAD_BUF (sizeof(buf_header_t) - sizeof(kdp2_ipc_app_yolo_inf_header_t)) + +#define IMG_BUF_TO_HEAD_BUF(img_buf) \ + (uint32_t)((uint32_t)img_buf - BUF_HEADER_SIZE) + +#define NUM_MIPI_INIT_BUFS 2 // 2 (ping-pong buffers) or 3 (triple-buffers for skipping frames) + +#define NUM_DISPLAY_QUEUE_DEPTH 3 + +#define NUM_IMG_BUF 12 +#define NUM_RESULT_BUF 12 + +#define IMG_BUF_SIZE (1 * 1024 * 1024) +#define RESULT_BUF_SIZE (400 * 1024) +#define CMD_BUF_SIZE (1 * 1024) + +#if 0//KL720_Scott +#define JTAG_MAGIC_ADDRESS 0x1FFFFFFC +#define JTAG_MAGIC_VALUE 0xFEDCBA01 +#define USB_BOOT_MAGIC_HB 0xaabbccdd +#define USB_BOOT_MAGIC_LB 0x11223344 + +#else +#define JTAG_MAGIC_ADDRESS 0x10100000 +#define KDP2_BOOT_CONFIG_ADDRESS 0x10100100 + +#define JTAG_MAGIC_VALUE 0xFEDCBA01 +#define BOOT_FROM_FLASH 0xA +typedef struct +{ + uint32_t boot_type; // 0xA = flash-boot, others = usb-boot + uint8_t loader_ver[4]; // fw loader version numbers + uint8_t scpu_fw_ver[4]; // SCPU fw version numbers + uint8_t ncpu_fw_ver[4]; // NCPU fw version numbers +} kdp2_boot_config_t; +#endif + +//#define ENABLE_DBG_LOG +#ifdef ENABLE_DBG_LOG +#define dbg_log(__format__, ...) kmdw_printf("[kp host mipi]"__format__, ##__VA_ARGS__) +#else +#define dbg_log(__format__, ...) +#endif + +//#define SHOW_SENSOR_IMAGE_ON_LCD +//debug: show sensor image directly without inference + +//#define SHOW_INF_RESULT +#ifdef SHOW_INF_RESULT +static char* classmap[] = {"person","bicycle","car","motorbike","aeroplane","bus","train","truck","boat","traffic_light", + "fire_hydrant","stop_sign","parking_meter","bench","bird","cat","dog","horse","sheep","cow", + "elephant","bear","zebra","giraffe","backpack","umbrella","handbag","tie","suitcase","frisbee", + "skis","snowboard","sports_ball","kite","baseball_bat","baseball_glove","skateboard","surfboard","tennis_racket","bottle", + "wine_glass","cup","fork","knife","spoon","bowl","banana","apple","sandwich","orange", + "broccoli","carrot","hot_dog","pizza","donut","cake","chair","sofa","pottedplant","bed", + "diningtable","toilet","tvmonitor","laptop","mouse","remote","keyboard","cell_phone","microwave","oven", + "toaster","sink","refrigerator","book","clock","vase","scissors","teddy_bear","hair_drier","toothbrush"}; +#endif + +typedef struct +{ + uint32_t buf_address; + uint32_t buf_size; +} kimg_buf_object_t; + +typedef struct +{ + uint32_t img_width; + uint32_t img_height; + uint32_t img_format; + uint32_t img_channel; + uint32_t img_buf_size; +} mipi_cam_settings_t; + +#define NUM_HOST_SENSOR 2 + +enum +{ + CAM_RGB_IDX = 0, + CAM_NIR_IDX = 1, +}; + +camera_settings_t _cam_settings[NUM_HOST_SENSOR] = {0}; + +//static osMessageQueueId_t _img_queue = NULL; + +//static bool _fifoq_mem_allocated = false; +//static bool _do_reset_queue = false; +//static bool _enable_inf_droppable = false; + +#define FLAG_WAIT_USB_CONNECTION 0x1 + +static osThreadId_t _usb_cmd_tid = NULL; +static osMessageQueueId_t _display_img_queue = NULL; + +static int _display_cam = CAM_RGB_IDX; // default send RGB images +static int dbg_mipi_cnt = 0; +static uint32_t _img_buf_start_addr_backup = 0; +static osThreadId_t _update_display_tid = NULL; + +static osMutexId_t _mutex_result; +static kp_app_yolo_result_t *_p_yolo_data[NUM_HOST_SENSOR] = {NULL}; + +extern int32_t kmdw_model_load_model(int8_t model_info_index_p); +extern void display_init(uint32_t input_fmt, uint16_t xres, uint16_t yres, uint8_t cam_idx); +extern void display_exit(void); +extern uint32_t lcdc_kdp2_get_disp_idx(int *read_done_idx); +extern uint32_t lcdc_kdp2_set_disp_buf(uint32_t buf_addr, int write_done_idx); +extern uint32_t lcdc_kdp2_get_disp_buf(int cam_idx, int *disp_idx); +// vendor-specific control transfer setup packet notify +static void usb_user_link_status_callback(usbd_hal_link_status_t link_status) +{ + switch (link_status) + { + case USBD_STATUS_DISCONNECTED: + kmdw_printf("USB is disconnected\n"); + break; + + case USBD_STATUS_CONFIGURED: + kmdw_printf("USB is connected\n"); + osThreadFlagsSet(_usb_cmd_tid, FLAG_WAIT_USB_CONNECTION); + break; + } +} +static bool usb_user_control_callback(usbd_hal_setup_packet_t *setup) +{ + bool ret = false; + + dbg_log("control bRequest = 0x%x\n", setup->bRequest); + + switch (setup->bRequest) + { + case KDP2_CONTROL_REBOOT: + { + dbg_log("control reboot\n"); + kdrv_power_sw_reset(); + break; + } + case KDP2_CONTROL_SHUTDOWN: + { + dbg_log("control shutdown\n"); + kmdw_power_manager_shutdown(); + break; + } + case KDP2_CONTROL_FIFOQ_RESET: + { + dbg_log("control fifoq reset\n"); + + // FIXME + kmdw_printf("wakeup USB cmd thread\n"); + osThreadFlagsSet(_usb_cmd_tid, FLAG_WAIT_USB_CONNECTION); + //osThreadFlagsSet(image_thread_id, 0x1); + + ret = true; + break; + } +#if 0 + case KDP2_CONTROL_FIFOQ_CONFIGURE: + { + if (_fifoq_mem_allocated) + break; // already inited + + uint16_t arg1_image = setup->wValue; + uint16_t arg2_result = setup->wIndex; + + uint32_t image_count = (arg1_image & 0x7) + 1; // lower 3 bits for number of image, 1~8 + uint32_t image_size = (10 * 1024) * (uint32_t)((arg1_image >> 3) + 1); // higher 13 bits for image buffer size in 10KB, 10KB~80MB + + uint32_t result_count = (arg2_result & 0x7) + 1; // lower 3 bits for number of image, 1~8 + uint32_t result_size = (10 * 1024) * (uint32_t)((arg2_result >> 3) + 1); // higher 13 bits for image buffer size in 10KB, 10KB~80MB + + ret = allocate_memory_for_inference_queue(image_count, image_size, result_count, result_size); + + break; + } + case KDP2_CONTROL_FIFOQ_ENABLE_DROPPABLE: + { + _enable_inf_droppable = (setup->wValue == 1); + ret = true; + } +#endif + default: + ret = false; + break; + } + + return ret; +} + +static void send_to_inference_queue(uint32_t head_buf, int cam_idx) +{ + buf_header_t *bufHdr = (buf_header_t *)head_buf; + kdp2_ipc_app_yolo_inf_header_t *infHdr = &bufHdr->inf_header; + + infHdr->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + infHdr->header_stamp.total_size = sizeof(kdp2_ipc_app_yolo_inf_header_t) + _cam_settings[cam_idx].img_buf_size; + infHdr->header_stamp.job_id = KDP2_INF_ID_APP_YOLO; + infHdr->header_stamp.status_code = KP_SUCCESS; + infHdr->inf_number = cam_idx; + infHdr->width = _cam_settings[cam_idx].img_width; + infHdr->height = _cam_settings[cam_idx].img_height; + infHdr->channel = _cam_settings[cam_idx].img_channel;//3 + infHdr->model_id = TINY_YOLO_V3_224_224_3;//211;//KNERON_YOLOV5S_COCO80_640_640_3;// + infHdr->image_format = _cam_settings[cam_idx].img_format; + infHdr->model_normalize = KP_NORMALIZE_KNERON; +//kmdw_printf("send_to_inference_queue,[infHdr] channel = %d, model_id=%d, image_format=%d\n", infHdr->channel, infHdr->model_id, infHdr->image_format); + // non-blocking inference enqueue + osStatus_t sts = kmdw_fifoq_manager_image_enqueue(1, 0, (uint32_t)infHdr, IMG_BUF_SIZE, 0, false); + if (sts != osOK) + kmdw_printf("(ISR) error !! kmdw_fifoq_manager_image_enqueue() failed, sts = %d\n", sts); +} + +static void send_to_display_queue(uint32_t hico_buf_addr, int cam_idx) +{ + // send to host thru USB (bottom-half mechanism) + buf_header_t *bufHdr = (buf_header_t *)hico_buf_addr; + kimg_buf_object_t bufobj; + bufobj.buf_address = hico_buf_addr; + bufobj.buf_size = BUF_HEADER_SIZE + _cam_settings[cam_idx].img_buf_size; + + osStatus_t sts = osMessageQueuePut(_display_img_queue, (const void *)&bufobj, NULL, 0); + if (sts != osOK) + return; + + bufHdr->read_ref_count++; +} + +static uint32_t retrieve_new_buffer_for_mipi() +{ + uint32_t new_head_buf_addr = 0; + int buf_size; + + for (int i = 0; i < NUM_IMG_BUF; i++) // MAX try, not really a for-loop + { + uint32_t new_inf_buf_addr = 0; + + osStatus_t sts = kmdw_fifoq_manager_image_get_free_buffer(&new_inf_buf_addr, &buf_size, 0, true); + if (sts != osOK) { + kmdw_printf("(ISR %d) error !! kmdw_fifoq_manager_image_get_free_buffer() failed, sts = %d\n", dbg_mipi_cnt, sts); + return 0; + } + + new_head_buf_addr = new_inf_buf_addr - OFFSET_INF_TO_HEAD_BUF; + buf_header_t *new_bufHdr = (buf_header_t *)new_head_buf_addr; + + if (new_bufHdr->read_ref_count == 0) + break; // found available one + else + { + // this buf is still in use, return it back to free buf queue + sts = kmdw_fifoq_manager_image_put_free_buffer(new_inf_buf_addr, IMG_BUF_SIZE, 0); + if (sts != osOK) + kmdw_printf("(ISR %d) error !! kmdw_fifoq_manager_image_put_free_buffer() failed, sts = %d\n", dbg_mipi_cnt, sts); + + new_head_buf_addr = 0; + } + } + + if (new_head_buf_addr == 0) + { + kmdw_printf("(ISR %d) error !! cannot retrieve available free buffers\n", dbg_mipi_cnt); + return 0; + } + + return (new_head_buf_addr + BUF_HEADER_SIZE); +} + +//cam_format cams_fmt = {0}; +static struct cam_format _cams_fmt[2] = {0}; + +// image ISR callback +void image_coming_callback(uint32_t cam_idx, uint32_t img_buf_addr, uint32_t *pNew_img_buf) +{ +#ifndef SHOW_SENSOR_IMAGE_ON_LCD// 1//send to inference queue + dbg_mipi_cnt++; + + // retrieve a new free buf (from the inference free buffer queue) + *pNew_img_buf = retrieve_new_buffer_for_mipi(); + if (NULL == pNew_img_buf) { + // Due to highest priority ISR has, + // image input is so fast that fifoq can't provide a free buffer even force_grab is set + *pNew_img_buf = img_buf_addr; + return; + } + + if(cam_idx == CAM_RGB_IDX) + { + _cam_settings[0].img_width = IMGSRC_0_WIDTH; + _cam_settings[0].img_height = IMGSRC_0_HEIGHT; + _cam_settings[0].img_format = KP_IMAGE_FORMAT_RGB565; + _cam_settings[0].img_channel = 3; + _cam_settings[0].img_buf_size = IMGSRC_0_WIDTH * IMGSRC_0_HEIGHT * 2; + } + else if(cam_idx == CAM_NIR_IDX) + { + _cam_settings[1].img_width = IMGSRC_1_WIDTH; + _cam_settings[1].img_height = IMGSRC_1_HEIGHT; + _cam_settings[1].img_format = KP_IMAGE_FORMAT_RAW8; + _cam_settings[1].img_channel = 1; + _cam_settings[1].img_buf_size = IMGSRC_1_WIDTH * IMGSRC_1_HEIGHT; + } + + + // // FIXME: reduce NIR camera FPS to 1/2 + // if (cam_idx == CAM_NIR_IDX) + // { + // static bool nir_skip = false; + // nir_skip = !nir_skip; + // if (!nir_skip) + // { + // *pNew_img_buf = img_buf_addr; + // return; + // } + // } + + uint32_t head_buf = img_buf_addr - BUF_HEADER_SIZE; + + // initialize hico img header + buf_header_t *bufHdr = (buf_header_t *)head_buf; + bufHdr->magic_type = HICO_IMAGE_RECEIVER_HEADER_MAGIC; + bufHdr->img_buf_offset = BUF_HEADER_SIZE; + bufHdr->read_ref_count = 0; + bufHdr->cam_index = cam_idx; + + //kmdw_printf("send_to_inference_queue, cam_idx=0%d, _display_cam=%d",cam_idx,_display_cam); + + // send both RGB and NIR images to infernece + send_to_inference_queue(head_buf, cam_idx); + + // send only selected image to display thread + if (_display_cam == cam_idx) + send_to_display_queue(head_buf, cam_idx); + + return; +#else//show sensor image directly + + //DSG("image_coming_callback,img_buf_addr=0x%x",img_buf_addr); + lcdc_kdp2_set_disp_buf(img_buf_addr,0);//show sensor image directly + + return; +#endif +} + + +uint32_t camera_start(uint8_t cam_idx, uint32_t width, uint32_t height, uint32_t pixelformat) +{ + uint32_t ret; + + struct cam_capability cap; + + _cams_fmt[cam_idx].width = width; + _cams_fmt[cam_idx].height = height; + _cams_fmt[cam_idx].pixelformat = pixelformat; + + char fmtstr[8]; + memset(&cap, 0, sizeof(cap)); + + if (0 != (ret = kmdw_camera_open(cam_idx))) + return ret; + + if (0 != (ret = kmdw_camera_get_device_info(cam_idx, &cap))) + return ret; + + if (0 != (ret = kmdw_camera_set_frame_format(cam_idx, &_cams_fmt[cam_idx]))) + return ret; + + if (0 != (ret = kmdw_camera_get_frame_format(cam_idx, &_cams_fmt[cam_idx]))) + return ret; + + memset(fmtstr, 0, 8); + memcpy(fmtstr, &_cams_fmt[cam_idx].pixelformat, 4); + + int buf_size; + uint32_t mipi_buf_addr[NUM_MIPI_INIT_BUFS] = {0}; + kmdw_printf("%s kmdw_fifoq_manager_image_get_free_buffer\n", __FUNCTION__); + // mipi needs some buffers at initialization + for (int i = 0; i < NUM_MIPI_INIT_BUFS; i++) + { + uint32_t head_buf; + // retrieve free hico buffer + kmdw_fifoq_manager_image_get_free_buffer(&head_buf, &buf_size, osWaitForever, false); + // and use its img buffer part for MIPI input + mipi_buf_addr[i] = head_buf + BUF_HEADER_SIZE; + } + kmdw_printf("%s kmdw_camera_buffer_init\n", __FUNCTION__); + if (0 != (ret = kmdw_camera_buffer_init(cam_idx, mipi_buf_addr[0], mipi_buf_addr[1]))) + return ret; + kmdw_printf("%s kmdw_camera_start\n", __FUNCTION__); + if (0 != (ret = kmdw_camera_start(cam_idx, image_coming_callback))) + return ret; + + return 0; +} + +// this thread receive the command from host SW +void kdp2_host_recv_cmd_thread(void *arg) +{ + dbg_log("[%s] start !\n", __FUNCTION__); + kmdw_printf("[%s] start !\n", __FUNCTION__); + _usb_cmd_tid = osThreadGetId(); + if (_usb_cmd_tid == NULL) + kmdw_printf("%s creation failed !\n", __FUNCTION__); + // wait until usb connection is established + osThreadFlagsWait(FLAG_WAIT_USB_CONNECTION, osFlagsWaitAny, osWaitForever); + kmdw_printf("[%s] FLAG_WAIT_USB_CONNECTION OK !\n", __FUNCTION__); + uint32_t cmd_buf = kmdw_ddr_reserve(CMD_BUF_SIZE); + + while (1) + { + uint32_t txLen = CMD_BUF_SIZE; + kdrv_status_t usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (void *)cmd_buf, &txLen, osWaitForever); + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + { + dbg_log("[%s] bulk receive is terminated, sts %d\n", __FUNCTION__, usb_sts); + continue; + } + + dbg_log("[%s] usb recv addr 0x%x len %d\n", __FUNCTION__, (void *)cmd_buf, txLen); + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)cmd_buf; + + if (header_stamp->magic_type == KDP2_MAGIC_TYPE_COMMAND) // standard KDP2 commands + { + // borrow image fifo to handle KDP2 commands as well + dbg_log("[%s] handle kdp2 command = 0x%x\n", __FUNCTION__, header_stamp->job_id); + // handle kdp2 commands ... + kdp2_cmd_handle_kp_command(cmd_buf); + continue; + } + else if (header_stamp->magic_type == KDP2_MAGIC_TYPE_CUSTOMIZED) // customized commands + { + dbg_log("[%s] configuration command received\n", __FUNCTION__); + + start_camera_cmd_t *scCmd = (start_camera_cmd_t *)cmd_buf; + + if (scCmd->cmd_id == COMMAND_START_CAMERA) + { + // start mipi cameras + + _cam_settings[0].img_width = IMGSRC_0_WIDTH; + _cam_settings[0].img_height = IMGSRC_0_HEIGHT; + _cam_settings[0].img_format = KP_IMAGE_FORMAT_RGB565; + _cam_settings[0].img_channel = 3; + _cam_settings[0].img_buf_size = IMGSRC_0_WIDTH * IMGSRC_0_HEIGHT * 2; + + if (0 != camera_start(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT)) + kmdw_printf("error !! camera_start 0 failed\n"); + + _cam_settings[1].img_width = IMGSRC_1_WIDTH; + _cam_settings[1].img_height = IMGSRC_1_HEIGHT; + _cam_settings[1].img_format = KP_IMAGE_FORMAT_RAW8; + _cam_settings[1].img_channel = 1; + _cam_settings[1].img_buf_size = IMGSRC_1_WIDTH * IMGSRC_1_HEIGHT * 1; + + if (0 != camera_start(1, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, IMGSRC_1_FORMAT)) + kmdw_printf("error !! camera_start 1 failed\n"); + + start_camera_resp_t scResp; + + scResp.header_stamp.magic_type = KDP2_MAGIC_TYPE_CUSTOMIZED; + scResp.header_stamp.status_code = KP_SUCCESS; + scResp.header_stamp.total_size = sizeof(scResp); + scResp.num_cam_sensors = NUM_HOST_SENSOR; + + for (int i = 0; i < NUM_HOST_SENSOR; i++) + memcpy(&scResp.cam_set[i], &_cam_settings[i], sizeof(camera_settings_t)); + + // send command-response back to user + usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&scResp, sizeof(scResp), 1000); + } + else if (scCmd->cmd_id == COMMAND_SELECT_CAMERA) + { + select_camera_cmd_t *cmd = (select_camera_cmd_t *)cmd_buf; + kmdw_printf("select camera %d\n", cmd->sel_camera); + _display_cam = cmd->sel_camera; + } + } + else if ((header_stamp->magic_type & 0xFFFF) == KDP_MSG_HDR_CMD) // very speical case for old arch. fw update + { + // handle legendary kdp commands, should be as few as possible + dbg_log("handle legendary kdp command = 0x%x\n", header_stamp->job_id); + kdp2_cmd_handle_legend_kdp_command(cmd_buf); + } + else + { + dbg_log("error ! buffer begin with incorrect magic_type 0x%x, txLen %d\n", __FUNCTION__, header_stamp->magic_type, txLen); + } + } +} +//TINY_YOLO_V3_224_224_3;//KNERON_YOLOV5S_COCO80_640_640_3;// +enum { + UART_CMD_START_TINY_YOLO_V3_INF_RGB = 1, + UART_CMD_START_TINY_YOLO_V3_INF_NIR, + UART_CMD_START_TINY_YOLO_V3_INF_RGB_NIR, + UART_CMD_STOP_TINY_YOLO_V3_INF, + UART_CMD_QUIT, + UART_CMD_SET_SNAPSHOT, + UART_CMD_SET_REVIEW_SNAPSHOT, + UART_CMD_NUM +}; + +// this thread receive the command from UART or power button ? + +void kdp2_host_recv_uart_cmd_thread(void *arg) +{ + int id = 0; + char buf[64]; + bool cam_started[2] = {false}; + bool quit_thread = false; + + kmdw_printf("[%s] start !\n", __FUNCTION__); + // Implement it if needed ? Press power button to toggle inference + // power_button_register(power_btn_handler); + //kmdw_console_echo_gets(buf, sizeof(buf)); + memset(buf, 0, sizeof(buf)); + kmdw_printf("[%s] clear uart buf !\n", __FUNCTION__); + + while(1) + { + //kmdw_printf("\n === Menu === id=%d\n",id); + if (id) + goto cmd_prompt; + + kmdw_printf("\n === Menu === \n"); + kmdw_printf("( 1) Start Tiny YoloV3 Inference with RGB camera\n"); + kmdw_printf("( 2) Start Tiny YoloV3 Inference with NIR camera\n"); + kmdw_printf("( 3) Start Tiny YoloV3 Inference with RGB and NIR camera\n"); + kmdw_printf("( 4) Stop Inference\n"); + kmdw_printf("( 5) Quit\n"); +cmd_prompt: + DSG_NOLF(" command >> "); + kmdw_console_echo_gets(buf, sizeof(buf)); + + id = atoi(strtok(buf, " \r\n\t")); + + if (id > 0 && id <= UART_CMD_NUM) + { + // FIXME: add mechanism of releasing buffers used by mipi driver to mipi driver and kmdw_camera levels + // following code is just a workaround + if (UART_CMD_START_TINY_YOLO_V3_INF_RGB <= id && id <= UART_CMD_START_TINY_YOLO_V3_INF_RGB_NIR) + { + if (true == cam_started[0] || true == cam_started[1]) + { + DSG("Please stop the current running camera first"); + goto cmd_prompt; + } + #if 1 + kmdw_printf("[%s] Wait until all image buffers are not used, cmd id=%d\n", __FUNCTION__,id); + // Wait until all image buffers are not used + while (osThreadBlocked != osThreadGetState(_update_display_tid)) + osDelay(1); + + uint32_t temp_buf_addr; + int temp_buf_size; + + kmdw_printf("[%s] clean up image buffers, cmd id=%d\n", __FUNCTION__,id); + // clean up image buffers + while (osErrorResource != kmdw_fifoq_manager_image_get_free_buffer(&temp_buf_addr, &temp_buf_size, 0, true)); + + uint32_t img_buf_addr = _img_buf_start_addr_backup; + + // requeue buffers into image free-queue + for (uint32_t i = 0; i < NUM_IMG_BUF; i++) + { + buf_header_t *bufHdr = (buf_header_t *)(img_buf_addr); + bufHdr->read_ref_count = 0; + + kmdw_fifoq_manager_image_put_free_buffer((uint32_t)&bufHdr->inf_header, IMG_BUF_SIZE, osWaitForever); + img_buf_addr += IMG_BUF_SIZE; // next one + } + #endif + } + + switch(id) + { + case UART_CMD_START_TINY_YOLO_V3_INF_RGB: + _display_cam = CAM_RGB_IDX; + if (0 != camera_start(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT)) + { + DSG("Error ! RGB camera start failed !"); + } + else + cam_started[0] = true; + + display_init(V2K_PIX_FMT_RGB565, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, _display_cam); + break; + case UART_CMD_START_TINY_YOLO_V3_INF_NIR: + _display_cam = CAM_NIR_IDX; + if (0 != camera_start(1, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, IMGSRC_1_FORMAT)) + { + DSG("Error ! NIR camera start failed !"); + } + else + cam_started[1] = true; + + display_init(V2K_PIX_FMT_RAW8, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, _display_cam); + break; + case UART_CMD_START_TINY_YOLO_V3_INF_RGB_NIR: + _display_cam = CAM_RGB_IDX; + if (0 != camera_start(0, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, IMGSRC_0_FORMAT) || 0 != camera_start(1, IMGSRC_1_WIDTH, IMGSRC_1_HEIGHT, IMGSRC_1_FORMAT)) + { + DSG("Error ! RGB or NIR camera start failed !"); + } + else + cam_started[0] = cam_started[1] = true; + + display_init(V2K_PIX_FMT_RGB565, IMGSRC_0_WIDTH, IMGSRC_0_HEIGHT, _display_cam); + kmdw_printf("LCD:default show RGB camera\n"); + break; + case UART_CMD_STOP_TINY_YOLO_V3_INF: + case UART_CMD_QUIT: + if (true == cam_started[0]) + { + kmdw_printf("kmdw_camera_stop 0\n"); + if (KMDW_STATUS_OK != kmdw_camera_stop(0)) + { + DSG("Error ! RGB camera stop failed !"); + } + kmdw_printf("kmdw_camera_close 0\n"); + if (KMDW_STATUS_OK != kmdw_camera_close(0)) + { + DSG("Error ! RGB camera close failed !"); + } + cam_started[0] = false; + //kdrv_gpio_write_pin(RGB_LED, false); // switch off the LED + } + if (true == cam_started[1]) + { + if (KMDW_STATUS_OK != kmdw_camera_stop(1)) + { + DSG("Error ! NIR camera stop failed !"); + } + if (KMDW_STATUS_OK != kmdw_camera_close(1)) + { + DSG("Error ! NIR camera close failed !"); + } + cam_started[1] = false; + } + display_exit(); + if (id == UART_CMD_QUIT) + { + DSG("Quit"); + quit_thread = true; + } + break; + } + } + else { + if (id) + err_msg("Invalid command: %d\n", id); + continue; + } + + if (quit_thread) + { + kmdw_power_manager_shutdown(); + break; + } + + } +} + +void kdp2_host_update_display_thread(void *arg) +{ + dbg_log("[%s] start !\n", __FUNCTION__); + kmdw_printf("start kdp2_host_update_display_thread\n"); + kimg_buf_object_t bufobj; + + _update_display_tid = osThreadGetId(); + + uint32_t display_buf[2];//PingPong buffer for display + static int display_idx = 0; + + for(int i = 0; i < 2; i++) + { + display_buf[i] = kmdw_ddr_reserve(IMG_BUF_SIZE); + if (display_buf[i] == 0) + kmdw_printf("error !! display_buf[%d] memory allocation failed\n",i); + } + + while (1) + { + // waiting for image from ISR though internal image queue + osMessageQueueGet(_display_img_queue, (void *)&bufobj, NULL, osWaitForever); + + int buf_size = bufobj.buf_size; + +#if 0 // this make HW crash whatever GDMA or GDMA3 !! FIXME FIXME !! + kdrv_status_t dma_sts = kdrv_gdma_memcpy(display_buf, bufobj.buf_address, buf_size, NULL, NULL); + if (dma_sts != KDRV_STATUS_OK) + { + kmdw_printf("error !! kdrv_gdma_memcpy() failed, err = %d\n", dma_sts); + break; + } +#else + //display_idx++; + //display_idx&=1; + lcdc_kdp2_get_disp_idx(&display_idx); + memcpy((void *)display_buf[display_idx], (void *)bufobj.buf_address, buf_size); +#endif + buf_header_t *bufHdr = (buf_header_t *)(bufobj.buf_address); + int cam_idx = bufHdr->cam_index; + // FIXME: need mutex + bufHdr->read_ref_count--; + + int img_width = _cam_settings[cam_idx].img_width; + int img_bpp = (cam_idx == CAM_RGB_IDX) ? 2 : 1; + + // drawing bounding box + osMutexAcquire(_mutex_result, osWaitForever); + { + kp_app_yolo_result_t *yd = _p_yolo_data[cam_idx]; + + char *img_begin_addr = (char *)(display_buf[display_idx] + BUF_HEADER_SIZE); + //char *img_begin_addr = (char *)(display_buf + BUF_HEADER_SIZE); + //char *img_begin_addr = (char *)(bufobj.buf_address + BUF_HEADER_SIZE); + + #ifdef SHOW_INF_RESULT//inference result + if(yd->box_count >= 1) + { + if (cam_idx == 0) + kmdw_printf("RGB image inference result :\n"); + else if (cam_idx == 1) + kmdw_printf("NIR image inference result :\n"); + kmdw_printf("box count : %d\n", yd->box_count); + for (int i = 0; i < yd->box_count; i++) + { + kmdw_printf("Box %d (x1, y1, x2, y2, score, class) = %.1f, %.1f, %.1f, %.1f, %f, %d\n", + i, + yd->boxes[i].x1, yd->boxes[i].y1, + yd->boxes[i].x2, yd->boxes[i].y2, + yd->boxes[i].score, yd->boxes[i].class_num); + + kmdw_printf("%s \n", classmap[yd->boxes[i].class_num]); + } + } + //DSG("kdp2_host_update_display_thread,box_count=%d",yd->box_count); + #endif + for (int i = 0; i < yd->box_count; i++) + { + int px1 = (int)yd->boxes[i].x1; + int py1 = (int)yd->boxes[i].y1; + int px2 = (int)yd->boxes[i].x2 - 1; + int py2 = (int)yd->boxes[i].y2 - 1; + + int tl_pos = img_bpp * (py1 * img_width + px1); // top-left pos + int bl_pos = img_bpp * (py2 * img_width + px1); // bottom-left pos + int tr_pos = img_bpp * (py1 * img_width + px2); // top-right pos + int x_diff = px2 - px1 + 1; + int y_diff = py2 - py1 + 1; + + char *draw_pos; + + if (cam_idx == CAM_RGB_IDX) // RGB565 + { + uint16_t box_color = 0x7E0; // green + + draw_pos = img_begin_addr + tl_pos; + for (int j = 0; j < x_diff; j++) + { + *(uint16_t *)draw_pos = box_color; + *(uint16_t *)(draw_pos+img_bpp*img_width) = box_color; + *(uint16_t *)(draw_pos+2*img_bpp*img_width) = box_color; + *(uint16_t *)(draw_pos+3*img_bpp*img_width) = box_color; + + draw_pos += img_bpp; + } + + draw_pos = img_begin_addr + bl_pos; + for (int j = 0; j < x_diff; j++) + { + *(uint16_t *)draw_pos = box_color; + *(uint16_t *)(draw_pos-img_bpp*img_width) = box_color; + *(uint16_t *)(draw_pos-2*img_bpp*img_width) = box_color; + *(uint16_t *)(draw_pos-3*img_bpp*img_width) = box_color; + + draw_pos += img_bpp; + } + + draw_pos = img_begin_addr + tl_pos; + for (int j = 0; j < y_diff; j++) + { + *(uint16_t *)draw_pos = box_color; + *(uint16_t *)(draw_pos+2) = box_color; + *(uint16_t *)(draw_pos+4) = box_color; + *(uint16_t *)(draw_pos+6) = box_color; + + draw_pos += (img_width * img_bpp); + } + + draw_pos = img_begin_addr + tr_pos; + for (int j = 0; j < y_diff; j++) + { + *(uint16_t *)draw_pos = box_color; + *(uint16_t *)(draw_pos-2) = box_color; + *(uint16_t *)(draw_pos-4) = box_color; + *(uint16_t *)(draw_pos-6) = box_color; + + draw_pos += (img_width * img_bpp); + } + } + else if (cam_idx == CAM_NIR_IDX) // grayscale + { + uint8_t box_color = 0xFF; // white + + draw_pos = img_begin_addr + tl_pos; + for (int j = 0; j < x_diff; j++) + { + *(uint8_t *)draw_pos = box_color; + draw_pos += img_bpp; + } + + draw_pos = img_begin_addr + bl_pos; + for (int j = 0; j < x_diff; j++) + { + *(uint8_t *)draw_pos = box_color; + draw_pos += img_bpp; + } + + draw_pos = img_begin_addr + tl_pos; + for (int j = 0; j < y_diff; j++) + { + *(uint8_t *)draw_pos = box_color; + draw_pos += (img_width * img_bpp); + } + + draw_pos = img_begin_addr + tr_pos; + for (int j = 0; j < y_diff; j++) + { + *(uint8_t *)draw_pos = box_color; + draw_pos += (img_width * img_bpp); + } + } + } + } + osMutexRelease(_mutex_result); + // FIXME, this is just a simulation via remote display + // replace code to send to a local display !! + #if 0 + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)display_buf, buf_size, osWaitForever); + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + kmdw_printf("[usb_image] error ! usbd_hal_bulk_send() ret = %d\n", usb_sts); + #else + lcdc_kdp2_set_disp_buf((uint32_t)(display_buf[display_idx] + BUF_HEADER_SIZE),display_idx); + //kmdw_printf("[%s] display=0x%x\n", __FUNCTION__,bufobj.buf_address); + //display_addr = bufobj.buf_address + BUF_HEADER_SIZE;//bufobj.buf_address: from image queue directly + #endif + } +} +// this thread sends inference result to host +void kdp2_host_update_result_thread(void *arg) +{ + dbg_log("[%s] start !\n", __FUNCTION__); + kmdw_printf("start kdp2_host_update_result_thread\n"); + while (1) + { + uint32_t result_buf_addr; + int result_buf_length; + + // get result data from result fifo queue, blocking wait + kmdw_fifoq_manager_result_dequeue(&result_buf_addr, &result_buf_length, osWaitForever); + //kmdw_printf("[%s] result_buf_addr=0x%x result_buf_length = %d\n",__FUNCTION__,result_buf_addr,result_buf_length); + // then send inference result + kdp2_ipc_app_yolo_result_t *yolo_result = (kdp2_ipc_app_yolo_result_t *)result_buf_addr; + + osMutexAcquire(_mutex_result, osWaitForever); + { + // copy needed size + int copy_size = 8 + (yolo_result->yolo_data.box_count * sizeof(kp_bounding_box_t)); + //kmdw_printf("[%s] copy_size = %d\n",__FUNCTION__,copy_size); + //kmdw_printf("[%s] box_count = %d\n",__FUNCTION__,yolo_result->yolo_data.box_count); + + memcpy(_p_yolo_data[yolo_result->inf_number], &yolo_result->yolo_data, copy_size); + + } + osMutexRelease(_mutex_result); + + // return free buf back to queue + kmdw_fifoq_manager_result_put_free_buffer(result_buf_addr, result_buf_length, osWaitForever); + } +} + +//////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////// + +int kdp2_host_mipi_init() +{ + // retrieve real serial number here from efuse + // then convert it to hex string format + + uint32_t uid = 0; + + uid = kdp_sys_get_kn_number(); + + int32_t sidx = 0; + uint8_t kn_num_string[32] = {0}; + for (int i = 7; i >= 0; i--) + { + uint32_t hex = (uid >> i * 4) & 0xF; + kn_num_string[sidx] = (hex < 10) ? '0' + hex : 'A' + (hex - 10); + sidx += 2; + } + + // Host Mode + uint16_t bcdDevice = KP_KDP2_FW_HOST_MODE; + + kmdw_printf("%s\n",__FUNCTION__); +#if 0//KL720_Scott + if (*((uint32_t *)JTAG_MAGIC_ADDRESS) == JTAG_MAGIC_VALUE) + { + kmdw_printf("FW is running in JTAG mode\n"); + bcdDevice |= KP_KDP2_FW_JTAG_TYPE; + } + else + { + uint32_t magic_lb, magic_hb; + magic_lb = (*(uint32_t *)(DDR_MAGIC_BASE)); + magic_hb = (*(uint32_t *)(DDR_MAGIC_BASE + 0x04)); + + if ((magic_lb == USB_BOOT_MAGIC_LB) && (magic_hb == USB_BOOT_MAGIC_HB)) + { + kmdw_printf("KDP2 FW is running in usb-boot mode\n"); + bcdDevice |= KP_KDP2_FW_USB_TYPE; + } + else + { + kmdw_printf("KDP2 FW is running in flash-boot mode\n"); + bcdDevice |= KP_KDP2_FW_FLASH_TYPE; + } + } + usbd_hal_initialize(kn_num_string, bcdDevice, usb_user_link_status_callback, usb_user_control_callback); +#else/* + if (*((uint32_t *)JTAG_MAGIC_ADDRESS) == JTAG_MAGIC_VALUE) + { + kmdw_printf("FW is running in JTAG mode\n"); + bcdDevice |= KP_KDP2_FW_JTAG_TYPE; + } + else*/ + { + kdp2_boot_config_t *bConfig = (kdp2_boot_config_t *)KDP2_BOOT_CONFIG_ADDRESS; + if (bConfig->boot_type == BOOT_FROM_FLASH) + { + kmdw_printf("KDP2 FW is running in flash-boot mode\n"); + bcdDevice |= KP_KDP2_FW_FLASH_TYPE; + + kmdw_printf("boot ncpu fw from flash\n"); + SCU_EXTREG_CM4_NCPU_CTRL_SET_wakeup(1); // run ncpu + } + else + { + kmdw_printf("KDP2 FW is running in usb-boot mode\n"); + bcdDevice |= KP_KDP2_FW_USB_TYPE; + } + } + //usbd_hal_initialize(kn_num_string, bcdDevice, usb_user_control_callback); + usbd_hal_initialize(kn_num_string, bcdDevice, usb_user_link_status_callback, usb_user_control_callback); +#endif + // this is about recovery mode +// *(uint32_t *)RECOVERY_MARK_POS = 0; + + //usbd_hal_initialize(kn_num_string, bcdDevice, usb_user_control_callback); + usbd_hal_initialize(kn_num_string, bcdDevice, usb_user_link_status_callback, usb_user_control_callback); + usbd_hal_set_enable(true); + + // wow ! fifoq can also handle command + kdp2_cmd_handler_initialize(); + + + + /* Allocate memory for image and result buffers */ + uint32_t img_buf_addr = kmdw_ddr_reserve(NUM_IMG_BUF * IMG_BUF_SIZE); + if (img_buf_addr == 0) + { + dbg_log("error !!! kmdw_ddr_reserve() failed for image/result buffers\n"); + return -1; + } + + // back up image buffer start address for reopening the camera + // FIXME: this is just a workaround + // temporary sync with 720 code base + _img_buf_start_addr_backup = img_buf_addr; + // queue buffers into image free-queue + for (uint32_t i = 0; i < NUM_IMG_BUF; i++) + { + buf_header_t *bufHdr = (buf_header_t *)(img_buf_addr); + bufHdr->read_ref_count = 0; + + kmdw_fifoq_manager_image_put_free_buffer((uint32_t)&bufHdr->inf_header, IMG_BUF_SIZE, osWaitForever); + img_buf_addr += IMG_BUF_SIZE; // next one + } + + uint32_t result_buf_addr = kmdw_ddr_reserve(NUM_RESULT_BUF * RESULT_BUF_SIZE); + + kmdw_printf("result_buf_addr = 0x%x\n", result_buf_addr); + + // queue buffers into result free-queue + for (uint32_t i = 0; i < NUM_RESULT_BUF; i++) + { + kmdw_fifoq_manager_result_put_free_buffer(result_buf_addr, RESULT_BUF_SIZE, osWaitForever); + result_buf_addr += RESULT_BUF_SIZE; + } + + _mutex_result = osMutexNew(NULL); + if (_mutex_result == NULL) + kmdw_printf("error !! _mutex_result creation failed\n"); + + for (int i = 0; i < NUM_HOST_SENSOR; i++) + { + _p_yolo_data[i] = (kp_app_yolo_result_t *)kmdw_ddr_reserve(sizeof(kp_app_yolo_result_t)); + if (_p_yolo_data[i] == NULL) + kmdw_printf("error !! _p_yolo_data memory allocation failed\n"); + + _p_yolo_data[i]->box_count = 0; + } + + _display_img_queue = osMessageQueueNew(NUM_DISPLAY_QUEUE_DEPTH, sizeof(kimg_buf_object_t), NULL); + if (_display_img_queue == NULL) + kmdw_printf("error !! _display_img_queue creation failed\n"); + + int32_t load_model_sts = kmdw_model_load_model(-1);//load_model from flash, -1:means to load all models + //return 0: failes; 1: OK(means 1 model is loaded) + kmdw_printf("%s: load_model_sts=%d\n",__FUNCTION__,load_model_sts); + + return 0; +} diff --git a/build/solution_kdp2_host_mipi/main_scpu/main.c b/build/solution_kdp2_host_mipi/main_scpu/main.c new file mode 100644 index 0000000..8496b5d --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/main.c @@ -0,0 +1,57 @@ +/* + * Kneron Main Entry driver + * + * Copyright (C) 2020 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +#include "project.h" +#include "version.h" + +// Customized configration and implementation +#include "system_init.h" +#include "driver_init.h" +#include "device_init.h" +#include "middleware_init.h" +#include "application_init.h" + +#include "kmdw_console.h" + +extern void task_initialize(void); + +/** + * @brief main, main function + */ +int main(void) +{ + osKernelInitialize(); // Initialize CMSIS-RTOS + sys_initialize(); + drv_initialize(); /* customize driver initialization, see driver_init.c */ + dev_initialize(); /* customize device initialization, see device_init.c */ + mdw_initialize(); /* customize middleware initialization, see middlewre_init.c */ + + + printf("SDK v%u.%u.%u-:build.%03u\n", + (uint8_t)(IMG_FW_MAJOR), + (uint8_t)(IMG_FW_MINOR), + (uint8_t)(IMG_FW_UPDATE), + (uint32_t)(IMG_FW_BUILD)); + + app_initialize(); /* customize application initialization, see application_init.c */ + + /* New task threads */ + task_initialize(); + + /* Start RTOS Kernel */ + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/solution_kdp2_host_mipi/main_scpu/middleware_init.c b/build/solution_kdp2_host_mipi/main_scpu/middleware_init.c new file mode 100644 index 0000000..1efb332 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/middleware_init.c @@ -0,0 +1,41 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kmdw_memory.h" +#include "kmdw_model.h" +#include "kmdw_dfu.h" +#include "kmdw_camera.h" +#include "kmdw_display.h" +#include "kmdw_console.h" + +/* config PROJ_NOT_USE_FW_LOADER in project.h */ +#if (defined(PROJ_NOT_USE_FW_LOADER) && (PROJ_NOT_USE_FW_LOADER != 0)) +#include "kmdw_system.h" /* for load_ncpu_fw */ +#endif + +void mdw_initialize(void) +{ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kmdw_ddr_store_system_reserve(DDR_SYSTEM_RESERVED_BEGIN, DDR_SYSTEM_RESERVED_END); + kmdw_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE); // uart console + kmdw_dfu_init(NULL, NULL); + kmdw_model_init(); + +#if (defined(PROJ_NOT_USE_FW_LOADER) && (PROJ_NOT_USE_FW_LOADER != 0)) + load_ncpu_fw(1/*reset_flag*/); // (kmdw_system.h) load ncpu fw from flash +#endif + kmdw_camera_init(); // init cameras + kmdw_display_initialize(); // init display +} + diff --git a/build/solution_kdp2_host_mipi/main_scpu/system_init.c b/build/solution_kdp2_host_mipi/main_scpu/system_init.c new file mode 100644 index 0000000..a89c8f3 --- /dev/null +++ b/build/solution_kdp2_host_mipi/main_scpu/system_init.c @@ -0,0 +1,23 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +//#include "project.h" +#include "kdrv_system.h" + + + //Function +void sys_initialize(void) +{ + /* SDK main init for companion mode */ + kdrv_system_init(); + kdrv_system_init_ncpu(); +} diff --git a/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.sct b/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.sct new file mode 100644 index 0000000..7e4a57e --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.sct @@ -0,0 +1,19 @@ +#!armcc -E +#define DRAM_START 0x0FFF0000 +#define DRAM_SIZE 0x00010000 + +LR_IROM1 0x00000000 0x00010000 { ; load region size_region + ER_IROM1 0x00000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } +} + diff --git a/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.uvoptx b/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.uvoptx new file mode 100644 index 0000000..5f40fd7 --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.uvoptx @@ -0,0 +1,552 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ncpu + 0x4 + ARM-ADS + + 250000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ULP2CM3 + -UAny -O905 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO3 -FD20000000 -FC1000 -FN0 + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U63610859 -O1 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO1 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 169 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + D:\3_code\mozart_sw_kdp2.git\scpu\project\companion_kdp2\main\main.c + + + + + + + 1 + 2 + 0x30ff0140 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\model_ftr_table.c + model_ftr_table.c + 0 + 0 + + + + + libs + 0 + 0 + 0 + 0 + + 2 + 3 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + kdp2_ncpu_sdk.lib + 0 + 0 + + + 2 + 4 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + kdp2_ncpu_model_ppp.lib + 0 + 0 + + + + + rtx + 0 + 0 + 0 + 0 + + 3 + 5 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + irq_cm4f.s + 0 + 0 + + + 3 + 6 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + os_systick.c + 0 + 0 + + + 3 + 7 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + RTX_Config.c + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + rtx_delay.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + rtx_evflags.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + rtx_evr.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + rtx_kernel.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + rtx_lib.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + rtx_memory.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + rtx_mempool.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + rtx_msgqueue.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + rtx_mutex.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + rtx_semaphore.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + rtx_system.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + rtx_thread.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 4 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + startup.c + 0 + 0 + + + 4 + 22 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + diff --git a/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.uvprojx b/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.uvprojx new file mode 100644 index 0000000..e2b41a1 --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/ncpu.uvprojx @@ -0,0 +1,547 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ncpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Mozart_ncpu + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_ncpu.bin" + post_build.bat fw_ncpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0xfff0000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + ARM_MATH_CM4, TARGET_NCPU, LOG_ENABLE, KL520 + + ..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\ncpu\drv\include;..\..\..\..\platform\kl520\ncpu\model_ppp\include;..\..\..\..\platform\kl520\ncpu\rtos\rtx\include;..\..\..\..\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\..\..\include + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x00000000 + 0x20000000 + + ..\..\..\..\platform\kl520\ncpu\mozart_ncpu.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_ncpu\main.c + + + model_ftr_table.c + 1 + ..\..\main_ncpu\model_ftr_table.c + + + + + libs + + + kdp2_ncpu_sdk.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + + + kdp2_ncpu_model_ppp.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/post_build.bat b/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/post_build.bat new file mode 100644 index 0000000..1ac5a9c --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/ncpu_keil/post_build.bat @@ -0,0 +1,10 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_ncpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ diff --git a/build/solution_kdp2_host_mipi/sn52096/proj.uvmpw b/build/solution_kdp2_host_mipi/sn52096/proj.uvmpw new file mode 100644 index 0000000..c1b2c26 --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/proj.uvmpw @@ -0,0 +1,22 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + + .\scpu_keil\scpu.uvprojx + 1 + + + + + + .\ncpu_keil\ncpu.uvprojx + + + diff --git a/build/solution_kdp2_host_mipi/sn52096/project.h b/build/solution_kdp2_host_mipi/sn52096/project.h new file mode 100644 index 0000000..f1a41ca --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/project.h @@ -0,0 +1,187 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +CAM setting +=============================================================================*/ +//project.h +#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 + +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +#define PROJ_NOT_USE_FW_LOADER 0 /**< not use fw_loader.bin to compose in fw image + if set as 1, must rebuild with corresponding scatter, kdp.sct */ + +/* Flash table for PROJ_NOT_USE_FW_LOADER = 1*/ +#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +#define FLASH_FW_NCPU0_ADDR 0x00018000 /**< fw_ncpu.bin */ +#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +#define FLASH_MODEL_ALL_ADDR 0x00301000 /**< all_models.bin */ +#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/solution_kdp2_host_mipi/sn52096/scpu_keil/kdp2_scpu_jlink.ini b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/kdp2_scpu_jlink.ini new file mode 100644 index 0000000..d4099c3 --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/kdp2_scpu_jlink.ini @@ -0,0 +1,13 @@ +MEMSET(0x10200000, 0x18000, 0) +MEMSET(0x10210000, 0x08000, 0) + +// to let USB know this is running in JTAG mode +MEMSET(0x10100000, 1, 0x01) +MEMSET(0x10100001, 1, 0xBA) +MEMSET(0x10100002, 1, 0xDC) +MEMSET(0x10100003, 1, 0xFE) + +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10104000) // Set Stack Pointer +PC=_RDWORD(0x10104004) // Set Program Counter = Reset_Handler +BS main \ No newline at end of file diff --git a/build/solution_kdp2_host_mipi/sn52096/scpu_keil/post_build.bat b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/post_build.bat new file mode 100644 index 0000000..f839167 --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/post_build.bat @@ -0,0 +1,12 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_scpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ + + diff --git a/build/solution_kdp2_host_mipi/sn52096/scpu_keil/pre_build.bat b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/pre_build.bat new file mode 100644 index 0000000..dba1dc6 --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/pre_build.bat @@ -0,0 +1 @@ +REM "prebuild script" diff --git a/build/solution_kdp2_host_mipi/sn52096/scpu_keil/scpu.uvoptx b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..22f76bc --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,1230 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + dev + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\kdp2_scpu_jlink.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + 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..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + task_handler.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 8 + 75 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + startup.c + 0 + 0 + + + 8 + 76 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + + libs + 0 + 0 + 0 + 0 + + 9 + 77 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\system_520.lib + system_520.lib + 0 + 0 + + + + diff --git a/build/solution_kdp2_host_mipi/sn52096/scpu_keil/scpu.uvprojx b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..fa38d98 --- /dev/null +++ b/build/solution_kdp2_host_mipi/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,847 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + dev + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + scpu_fw + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + pre_build.bat + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_scpu.bin" + post_build.bat fw_scpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE, BOARD_96 + + ..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\platform\kl520\scpu\rtos\rtx\include;..\..\..\..\platform\board\board_sn52096;..\..\..\..\platform\dev\include;..\..\..\..\mdw\include;..\..\..\..\mdw\inference;..\..\..\..\app;..\..\main_scpu\include;..\;..\..\..\lib\system_520\main_scpu\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\sn52096;..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\board\board_sn52096 + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + ..\..\..\..\platform\kl520\scpu\scatter_load.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_scpu\main.c + + + project.h + 5 + ..\project.h + + + task_handler.h + 5 + ..\..\main_scpu\include\task_handler.h + + + application_init.c + 1 + ..\..\main_scpu\application_init.c + + + device_init.c + 1 + ..\..\main_scpu\device_init.c + + + driver_init.c + 1 + ..\..\main_scpu\driver_init.c + + + middleware_init.c + 1 + ..\..\main_scpu\middleware_init.c + + + system_init.c + 1 + ..\..\main_scpu\system_init.c + + + display_init.c + 1 + ..\..\main_scpu\display_init.c + + + + + inf_app + + + demo_customize_inf_single_model.c + 1 + ..\..\..\..\app\demo_customize_inf_single_model.c + + + demo_customize_inf_multiple_models.c + 1 + ..\..\..\..\app\demo_customize_inf_multiple_models.c + + + kdp2_inf_app_yolo.c + 1 + ..\..\..\..\app\kdp2_inf_app_yolo.c + + + + + inf_client + + + kdp2_cmd_handler_520.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_cmd_handler_520.c + + + usbd_hal_520.c + 1 + ..\..\..\..\mdw\usb_companion\usbd_hal_520.c + + + kdp2_usb_log.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_usb_log.c + + + kdp2_host_mipi.c + 1 + ..\..\main_scpu\kdp2_host_mipi.c + + + + + middleware + + + kmdw_memory.c + 1 + ..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_memxfer.c + 1 + ..\..\..\..\mdw\flash\kmdw_memxfer.c + + + kmdw_console.c + 1 + ..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_power_manager.c + 1 + ..\..\..\..\mdw\power\kmdw_power_manager.c + + + kmdw_dfu.c + 1 + ..\..\..\..\mdw\dfu\kmdw_dfu.c + + + kdp_crc.c + 1 + ..\..\..\..\mdw\utils\kmdw_utils_crc.c + + + kmdw_system.c + 1 + ..\..\..\..\mdw\system\kmdw_system.c + + + kmdw_ipc.c + 1 + ..\..\..\..\mdw\ipc\kmdw_ipc.c + + + kmdw_model.c + 1 + ..\..\..\..\mdw\model\kmdw_model.c + + + dual_fifo2.c + 1 + ..\..\..\..\mdw\inference\dual_fifo2.c + + + kdp2_inf_generic_raw.c + 1 + ..\..\..\..\mdw\inference\kdp2_inf_generic_raw.c + + + kmdw_inference_520.c + 1 + ..\..\..\..\mdw\inference\kmdw_inference_520.c + + + kmdw_camera.c + 1 + ..\..\..\..\mdw\camera\kmdw_camera.c + + + kmdw_camera_kl520.c + 1 + ..\..\..\..\mdw\camera\kmdw_camera_kl520.c + + + kmdw_sensor.c + 1 + ..\..\..\..\mdw\camera\kmdw_sensor.c + + + kmdw_display.c + 1 + ..\..\..\..\mdw\display\kmdw_display.c + + + kmdw_fifoq_manager.c + 1 + ..\..\..\..\mdw\inference\kmdw_fifoq_manager.c + + + + + device + + + kdev_flash_winbond.c + 1 + ..\..\..\..\platform\dev\flash\kdev_flash_winbond.c + + + kdev_sensor_gc2145.c + 1 + ..\..\..\..\platform\dev\sensor\kdev_sensor_gc2145.c + + + kdev_sensor_sc132gs.c + 1 + ..\..\..\..\platform\dev\sensor\kdev_sensor_sc132gs.c + + + kdev_mzt_480x272.c + 1 + ..\..\..\..\platform\dev\panel\kdev_mzt_480x272.c + + + + + driver + + + kdrv_pinmux.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_gpio.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + + + kdrv_spif.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_spif.c + + + kdrv_uart.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_ipc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ipc.c + + + kdrv_usbd2.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2.c + + + kdrv_usbd2v.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2v.c + + + kdrv_clock.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_mpu.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mpu.c + + + kdrv_ddr.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_power.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_system.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_wdt.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_wdt.c + + + kdrv_gdma.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + + + rtc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\rtc.c + + + kdrv_pwm.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + kdrv_lcdc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_lcdc.c + + + kdrv_i2c.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + + + kdrv_mipicsirx.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mipicsirx.c + + + kdrv_dpi2ahb.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_dpi2ahb.c + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + + + task_handler.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + + + + + libs + + + system_520.lib + 4 + ..\..\..\..\lib\system_520.lib + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/build/solution_kdp2_user_ex/main_ncpu/main.c b/build/solution_kdp2_user_ex/main_ncpu/main.c new file mode 100644 index 0000000..fb0021a --- /dev/null +++ b/build/solution_kdp2_user_ex/main_ncpu/main.c @@ -0,0 +1,33 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2019 Kneron Inc. All rights reserved. + * + * Name: main.c + * Purpose: Kneron NCPU + * + *---------------------------------------------------------------------------*/ + + +#include "cmsis_os2.h" +#include "kdpio.h" + +extern void SystemCoreClockUpdate(void); + +/*---------------------------------------------------------------------------- + * Main: Initialize OS Kernel and NCPU SDK + *---------------------------------------------------------------------------*/ +int main(void) +{ + SystemCoreClockUpdate(); + osKernelInitialize(); + + /* init NCPU */ + kdpio_sdk_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + ; +} diff --git a/build/solution_kdp2_user_ex/main_ncpu/model_ftr_table.c b/build/solution_kdp2_user_ex/main_ncpu/model_ftr_table.c new file mode 100644 index 0000000..18a3d31 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_ncpu/model_ftr_table.c @@ -0,0 +1,58 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2020 Kneron Inc. All rights reserved. + * + * Name: ncpu_extend_ftr.c + * Purpose: Extend new features implementation + * + *---------------------------------------------------------------------------*/ + +#include "kdpio.h" +#include "model_type.h" +#include "model_ppp.h" + +extern int user_pre_yolo(struct kdp_image_s *image_p); +extern int user_post_yolo(struct kdp_image_s *image_p); + +/********************************************************************************* + Registered model pre-process features list + +only need to register functions for models that default builtin pre-proc can't support +*********************************************************************************/ +model_pre_post_func_t model_pre_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < pre-process function > */ + /* -------------------------------------------------------------------------- */ + 0 // no pre-process function is specified + + /* Put customized pre-process functions below: */ + //demo only + //{ TINY_YOLO_V3_224_224_3, user_pre_yolo }, + + /* + { CUSTOMER_MODEL_1, preproc_customer_model_1 }, + { CUSTOMER_MODEL_2, preproc_customer_model_2 }, + { CUSTOMER_MODEL_3, preproc_customer_model_3 }, + */ +}; + +/********************************************************************************* + Registered model post-process features list +*********************************************************************************/ +model_pre_post_func_t model_post_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < post-process function > */ + /* -------------------------------------------------------------------------- */ + + /* user post-process function example*/ + { TINY_YOLO_V3_224_224_3, user_post_yolo }, + + /* use builtin post-process function example*/ + //for face_detection and landmark here using Kneron app functions + { KNERON_FD_MASK_MBSSD_200_200_3, post_ssd_face_detection }, + { KNERON_LM_5PTS_ONET_56_56_3, post_face_landmark_onet_5p }, + + + /* Put customized post-process functions below:*/ + //{ CUSTOMER_MODEL_1, post_customer_model_1 }, + //{ CUSTOMER_MODEL_2, post_customer_model_2 }, + //{ CUSTOMER_MODEL_3, post_customer_model_3 }, +}; + diff --git a/build/solution_kdp2_user_ex/main_ncpu/user_post_process.c b/build/solution_kdp2_user_ex/main_ncpu/user_post_process.c new file mode 100644 index 0000000..6af9bb0 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_ncpu/user_post_process.c @@ -0,0 +1,466 @@ +/* + * Kneron Example Post-Processing driver + * + * Copyright (C) 2018-2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include "base.h" +#include "model_res.h" +#include "post_processing.h" + +#define YOLO_CLASS_MAX 80 /* max result box number per class */ +#define YOLO_GOOD_BOX_MAX 80 /* max result box number for one time inference */ +#define YOLO_BOX_FIX_CH 5 /* x, y, w, h, confidence score */ + +#define YOLO_V3_GRID_W 14 /* max output feature map width */ +#define YOLO_V3_GRID_H 14 /* max output feature map higheit */ +#define YOLO_V3_GRID_MAX (YOLO_V3_GRID_W * YOLO_V3_GRID_H) /* max predict box number per channel */ +#define YOLO_V3_CELL_BOX_NUM 3 /* number of anchors on each output node */ +#define YOLO_V3_MAX_BOX_NUM MIN(500, YOLO_V3_GRID_MAX * YOLO_V3_CELL_BOX_NUM) + +#define KDP_COL_MIN 16 /* hardware 16 bytes alignment, i.e. 128 bits */ + +/* YOLO default parameters */ +const float ex_unpass_score = -999.0; // used as box filter + +const float ex_anchors_v0[3][2] = {{116 ,90}, {156, 198}, {373, 326}}; +const float ex_anchors_v1[3][2] = {{30, 61}, {62, 45}, {59, 119}}; +const float ex_anchors_v2[3][2] = {{10, 13}, {16, 30}, {33, 23}}; + +/* Output node layout */ +struct ex_output_node { + int8_t *base_ptr; + uint32_t ch; + uint32_t row; + uint32_t col; + uint32_t col_len; + uint32_t radix; + uint32_t scale; +}; + +/* Shared global variable area among models */ +struct ex_yolo_v3_post_globals_s { + float box_class_probs[YOLO_CLASS_MAX]; + struct bounding_box_s bboxes_v3[YOLO_V3_GRID_MAX * YOLO_V3_CELL_BOX_NUM]; + struct bounding_box_s result_tmp_s[YOLO_V3_MAX_BOX_NUM]; +}; + +/* Model globals */ +static struct ex_yolo_v3_post_globals_s *ex_yolov3_gp; + +void *get_gp(void **gp, size_t len); + +static inline struct ex_yolo_v3_post_globals_s *get_yolov3_gp(void) { + return (struct ex_yolo_v3_post_globals_s *)get_gp((void **)&ex_yolov3_gp, sizeof(struct ex_yolo_v3_post_globals_s)); +} + +/* Post-Processing utils functions */ +float ex_do_div_scale_optim(float v, float scale) { + return (v * scale); +} + +uint32_t ex_round_up(uint32_t num) { + return ((num + (KDP_COL_MIN - 1)) & ~(KDP_COL_MIN - 1)); +} + +float ex_sigmoid(float x) { + float exp_value; + float return_value; + + exp_value = expf(-x); + + return_value = 1 / (1 + exp_value); + + return return_value; +} + +int ex_float_comparator(float a, float b) { + float diff = a - b; + + if (diff < 0) + return 1; + else if (diff > 0) + return -1; + return 0; +} + +int ex_box_score_comparator(const void *pa, const void *pb) { + float a, b; + + a = ((struct bounding_box_s *) pa)->score; + b = ((struct bounding_box_s *) pb)->score; + + return ex_float_comparator(a, b); +} + +float ex_overlap(float l1, float r1, float l2, float r2) { + float left = l1 > l2 ? l1 : l2; + float right = r1 < r2 ? r1 : r2; + return right - left; +} + +float ex_box_intersection(struct bounding_box_s *a, struct bounding_box_s *b) { + float w, h, area; + + w = ex_overlap(a->x1, a->x2, b->x1, b->x2); + h = ex_overlap(a->y1, a->y2, b->y1, b->y2); + + if (w < 0 || h < 0) + return 0; + + area = w * h; + return area; +} + +float ex_box_union(struct bounding_box_s *a, struct bounding_box_s *b) { + float i, u; + + i = ex_box_intersection(a, b); + u = (a->y2 - a->y1) * (a->x2 - a->x1) + (b->y2 - b->y1) * (b->x2 - b->x1) - i; + + return u; +} + +float ex_box_iou(struct bounding_box_s *a, struct bounding_box_s *b) { + /* origin iou */ + + float c; + float intersection_a_b = ex_box_intersection(a, b); + float union_a_b = ex_box_union(a, b); + + c = intersection_a_b / union_a_b; + + return c; +} + +/* Get the output node information */ +void ex_get_output_node(struct ex_output_node *out_node, struct kdp_image_s *image_p, int node_num) { + struct out_node_s *out_p; + out_p = (struct out_node_s *)((kdp_size_t)POSTPROC_OUT_NODE(image_p) + node_num * sizeof(struct out_node_s)); + + out_node->base_ptr = (int8_t *)OUT_NODE_ADDR(out_p); + out_node->ch = OUT_NODE_CH(out_p); + out_node->row = OUT_NODE_ROW(out_p); + out_node->col = OUT_NODE_COL(out_p); + out_node->col_len = ex_round_up(out_node->col); + out_node->radix = OUT_NODE_RADIX(out_p); + out_node->scale = OUT_NODE_SCALE(out_p); +} + +/* Get the index corresponding to given channel, row, and column indices */ +uint32_t ex_get_index(struct ex_output_node node, uint32_t ch_idx, uint32_t row_idx, uint32_t col_idx) { + uint32_t index = row_idx * node.ch * node.col_len + ch_idx * node.col_len + col_idx; + return index; +} + +/* Get the data pointer corresponding to given channel, row, and column indices */ +int8_t *ex_get_data(struct ex_output_node node, uint32_t ch_idx, uint32_t row_idx, uint32_t col_idx) { + uint32_t index = ex_get_index(node, ch_idx, row_idx, col_idx); + return node.base_ptr + index; +} + +/* Performs NMS on the potential boxes */ +static int ex_nms_bbox_for_post_yolov3_no_sigmoid(struct bounding_box_s *potential_boxes, + struct bounding_box_s *temp_results, + int class_num, + int good_box_count, + int max_boxes, + int single_class_max_boxes, + struct bounding_box_s *results, + float score_thresh, + float iou_thresh) { + int good_result_count = 0; + + // check overlap between only boxes from same class + for (int i = 0; i < class_num; i++) { + int class_good_result_count = 0; + if (good_result_count == max_boxes) // break out of outer loop as well for future classes + break; + + int class_good_box_count = 0; + + // find all boxes of a specific class + for (int j = 0; j < good_box_count; j++) { + if (potential_boxes[j].class_num == i) { + memcpy(&temp_results[class_good_box_count], &potential_boxes[j], sizeof(struct bounding_box_s)); + class_good_box_count++; + } + } + + if (class_good_box_count == 1) { + memcpy(&results[good_result_count], temp_results, sizeof(struct bounding_box_s)); + good_result_count++; + } else if (class_good_box_count >= 2) { + // sort boxes based on the score + qsort(temp_results, class_good_box_count, sizeof(struct bounding_box_s), ex_box_score_comparator); + for (int j = 0; j < class_good_box_count; j++) { + // if the box score is too low or is already filtered by previous box + if (temp_results[j].score < score_thresh) + continue; + + // filter out overlapping, lower score boxes + for (int k = j + 1; k < class_good_box_count; k++) + if (ex_box_iou(&temp_results[j], &temp_results[k]) > iou_thresh) + temp_results[k].score = ex_unpass_score; + + // keep boxes with highest scores, up to a certain amount + if ((good_result_count == max_boxes) || (class_good_result_count == single_class_max_boxes)) + break; + memcpy(&results[good_result_count], &temp_results[j], sizeof(struct bounding_box_s)); + good_result_count++; + class_good_result_count++; + } + } + } + + return good_result_count; +} + +/** + * Update candidate bbox list, reserve top max_candidate_num candidate bbox. + */ +static int ex_update_candidate_bbox_list(struct bounding_box_s *new_candidate_bbox, + int max_candidate_num, + struct bounding_box_s *candidate_bbox_list, + int *candidate_bbox_num, + int *max_candidate_idx, + int *min_candidate_idx) { + + if ((NULL == new_candidate_bbox) || (NULL == candidate_bbox_list)) + return -1; + + int update_idx = -1; + + if (0 == *candidate_bbox_num) { + /** add 1-th bbox */ + *max_candidate_idx = 0; + *min_candidate_idx = 0; + update_idx = 0; + (*candidate_bbox_num)++; + memcpy(&candidate_bbox_list[update_idx], new_candidate_bbox, sizeof(struct bounding_box_s)); + } else { + if (max_candidate_num > *candidate_bbox_num) { + /** directly add bbox when the candidate bbox list is not filled */ + update_idx = *candidate_bbox_num; + + if (new_candidate_bbox->score > candidate_bbox_list[*max_candidate_idx].score) + *max_candidate_idx = update_idx; + else if (new_candidate_bbox->score < candidate_bbox_list[*min_candidate_idx].score) + *min_candidate_idx = update_idx; + + (*candidate_bbox_num)++; + + if (0 <= update_idx) + memcpy(&candidate_bbox_list[update_idx], new_candidate_bbox, sizeof(struct bounding_box_s)); + } else { + /** update candidate bbox list when candidate bbox list is filled */ + if (new_candidate_bbox->score >= candidate_bbox_list[*max_candidate_idx].score) { + /** update the largest score candidate index */ + update_idx = *min_candidate_idx; + *max_candidate_idx = *min_candidate_idx; + } else if (new_candidate_bbox->score > candidate_bbox_list[*min_candidate_idx].score) { + update_idx = *min_candidate_idx; + } + + if (0 <= update_idx) { + memcpy(&candidate_bbox_list[update_idx], new_candidate_bbox, sizeof(struct bounding_box_s)); + + for (int i = 0; i < *candidate_bbox_num; i++) { + /** update the smallest score candidate index */ + if (candidate_bbox_list[i].score < candidate_bbox_list[*min_candidate_idx].score) + *min_candidate_idx = i; + } + } + } + } + + return 0; +} + +/* Remap one bounding box to original image coordinates */ +void ex_remap_bbox(struct kdp_image_s *image_p, struct bounding_box_s *box, int need_scale) { + // original box values are percentages, scale to model sizes + if (need_scale) { + box->x1 *= DIM_INPUT_COL(image_p); + box->y1 *= DIM_INPUT_ROW(image_p); + box->x2 *= DIM_INPUT_COL(image_p); + box->y2 *= DIM_INPUT_ROW(image_p); + } + + // scale from model sizes to original input sizes + box->x1 = (box->x1 - RAW_PAD_LEFT(image_p)) * RAW_SCALE_WIDTH(image_p) + RAW_CROP_LEFT(image_p); + box->y1 = (box->y1 - RAW_PAD_TOP(image_p)) * RAW_SCALE_HEIGHT(image_p) + RAW_CROP_TOP(image_p); + box->x2 = (box->x2 - RAW_PAD_LEFT(image_p)) * RAW_SCALE_WIDTH(image_p) + RAW_CROP_LEFT(image_p); + box->y2 = (box->y2 - RAW_PAD_TOP(image_p)) * RAW_SCALE_HEIGHT(image_p) + RAW_CROP_TOP(image_p); + + // clip to boundaries of image + box->x1 = (int)((box->x1 < 0 ? 0 : box->x1) + (float)0.5); + box->y1 = (int)((box->y1 < 0 ? 0 : box->y1) + (float)0.5); + box->x2 = (int)((box->x2 > RAW_INPUT_COL(image_p) ? RAW_INPUT_COL(image_p) : box->x2) + (float)0.5); + box->y2 = (int)((box->y2 > RAW_INPUT_ROW(image_p) ? RAW_INPUT_ROW(image_p) : box->y2) + (float)0.5); +} + +/* YOLO parameters */ +static float iou_threshold = 0.45; +static float score_threshold = 0.6; +static uint32_t max_detection_box_num = YOLO_V3_MAX_BOX_NUM; +static uint32_t anchors[3][3][2] = {{{0}}}; + +/* User YOLO post processing */ +int user_post_yolo(struct kdp_image_s *image_p) +{ + /************************* Input parameters ******************************/ + host_od_post_params_t *pHostParam = (host_od_post_params_t *)POSTPROC_PARAMS_P(image_p); + + if (pHostParam->prob_thresh > 0) + score_threshold = pHostParam->prob_thresh; + + if (pHostParam->nms_thresh > 0) + iou_threshold = pHostParam->nms_thresh; + + if (pHostParam->max_detection_per_class > 0) + { + max_detection_box_num = pHostParam->max_detection_per_class; + if (max_detection_box_num > YOLO_V3_MAX_BOX_NUM) + max_detection_box_num = YOLO_V3_MAX_BOX_NUM; + } + + // use passed anchor table + uint32_t *p_anchors = (uint32_t *)pHostParam->data; + if (pHostParam->anchor_row * pHostParam->anchor_col > 0 && pHostParam->anchor_row <= 3 && pHostParam->anchor_col <= 6) + { + for (int i = 0; i < pHostParam->anchor_row; i++) + { + for (int j = 0; j < (pHostParam->anchor_col / 2); j++) + { + anchors[i][j][0] = *p_anchors++; + anchors[i][j][1] = *p_anchors++; + } + } + } + else + { + memcpy(anchors[0], ex_anchors_v0, sizeof(float) * 6); + memcpy(anchors[1], ex_anchors_v1, sizeof(float) * 6); + memcpy(anchors[2], ex_anchors_v2, sizeof(float) * 6); + } + + /*************************************************************************/ + + // get result buffer + struct yolo_result_s *result = (struct yolo_result_s *)(POSTPROC_RESULT_MEM_ADDR(image_p)); + struct ex_yolo_v3_post_globals_s *gp = get_yolov3_gp(); + struct bounding_box_s *bbox = gp->bboxes_v3; + struct ex_output_node node_yolo; + int good_box_count = 0; + int max_candidate_idx = 0; + int min_candidate_idx = 0; + + ex_get_output_node(&node_yolo, image_p, 0); + int class_num = node_yolo.ch / YOLO_V3_CELL_BOX_NUM - YOLO_BOX_FIX_CH; + result->class_count = class_num; + + for (int idx = 0; idx < POSTPROC_OUTPUT_NUM(image_p); idx++) { + // get output node parameters + ex_get_output_node(&node_yolo, image_p, idx); + + // get radix and scale for floating conversion + float div = pow(2, node_yolo.radix); + float scale = *(float *)&node_yolo.scale; + + // convert threshold to fp for fast comparison + int prob_thresh_yolov3_fp = floor(-log(1.f / score_threshold - 1.f) * div * scale); + scale = 1.0f / (div * scale); + + for (int ch = 0; ch < YOLO_V3_CELL_BOX_NUM; ch++) { + for (int row = 0; row < node_yolo.row; row++) { + for (int col = 0; col < node_yolo.col; col++) { + // check if the score (4th channel) better than threshold + int8_t box_confidence_fp = *ex_get_data(node_yolo, ch * (class_num + 5) + 4, row, col); + + // filter out small box score + if (box_confidence_fp <= prob_thresh_yolov3_fp) + continue; + + // find maximum score among all classes + // get the predicted class and score in fixed + int max_score_class = 0; + int8_t max_score_int = *ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 5, row, col); + for (int i = 1; i < class_num; i++) { + int8_t cur_score = *ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 5 + i, row, col); + if (cur_score > max_score_int) { + max_score_int = cur_score; + max_score_class = i; + } + } + + // filter out small class number + if (max_score_int <= prob_thresh_yolov3_fp) + continue; + + // get the confidence score in floating + float box_confidence = ex_sigmoid(ex_do_div_scale_optim(box_confidence_fp, scale)); + float max_score = ex_sigmoid(ex_do_div_scale_optim(max_score_int, scale)); + float score = max_score * box_confidence; + + // check if score is larger than threshold we set in floating + if (score > score_threshold) { + if ((YOLO_V3_MAX_BOX_NUM == good_box_count) && (score <= bbox[min_candidate_idx].score)) + continue; + float box_x = (float)*ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH), row, col); + float box_y = (float)*ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 1, row, col); + float box_w = (float)*ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 2, row, col); + float box_h = (float)*ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 3, row, col); + + box_x = ex_do_div_scale_optim(box_x, scale); + box_y = ex_do_div_scale_optim(box_y, scale); + box_w = ex_do_div_scale_optim(box_w, scale); + box_h = ex_do_div_scale_optim(box_h, scale); + + box_x = (ex_sigmoid(box_x) + col) * (DIM_INPUT_COL(image_p) / node_yolo.col); + box_y = (ex_sigmoid(box_y) + row) * (DIM_INPUT_ROW(image_p) / node_yolo.row); + box_w = expf(box_w) * anchors[idx][ch][0]; + box_h = expf(box_h) * anchors[idx][ch][1]; + + struct bounding_box_s new_candidate_bbox = {0}; + new_candidate_bbox.x1 = (box_x - (box_w / 2)); + new_candidate_bbox.y1 = (box_y - (box_h / 2)); + new_candidate_bbox.x2 = (box_x + (box_w / 2)); + new_candidate_bbox.y2 = (box_y + (box_h / 2)); + + new_candidate_bbox.score = score; + new_candidate_bbox.class_num = max_score_class; + + ex_update_candidate_bbox_list(&new_candidate_bbox, + YOLO_V3_MAX_BOX_NUM, + bbox, + &good_box_count, + &max_candidate_idx, + &min_candidate_idx); + } + } + } + } + } + + // do NMS + result->box_count = ex_nms_bbox_for_post_yolov3_no_sigmoid(gp->bboxes_v3, + gp->result_tmp_s, + class_num, + good_box_count, + max_detection_box_num, + max_detection_box_num, + result->boxes, + 0, + iou_threshold); + + // remap boxes to original coordinates + for (int i = 0; i < result->box_count; i++) + ex_remap_bbox(image_p, &result->boxes[i], 0); + + return result->box_count; +} diff --git a/build/solution_kdp2_user_ex/main_ncpu/user_pre_process.c b/build/solution_kdp2_user_ex/main_ncpu/user_pre_process.c new file mode 100644 index 0000000..8e2ea1d --- /dev/null +++ b/build/solution_kdp2_user_ex/main_ncpu/user_pre_process.c @@ -0,0 +1,52 @@ +/* + * Kneron Example Pre-Processing driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include "base.h" +#include "kdpio.h" +#include "ipc.h" + +inline static int pad_up_16(int a) +{ + return ceil((float)a / 16) * 16; +} + +static void pre_proc_unsign_right_shift(uint8_t *src_p, uint8_t *dst_p, int row, int col, int bit_shift) +{ + int unit = 4; + unsigned int r; + int pad_col = pad_up_16(col); + + int len = pad_col * row * unit; + for (r = 0; r < len; r++) { + *(dst_p + r) = (*(src_p + r)) >> bit_shift; + } + return; +} + +// This function is to right-shift the input RGBA image (HeightxWidthxChannel: 224x224x4) for 1 bit +int user_pre_yolo(struct kdp_image_s *image_p) +{ + int out_row, out_col; + int input_radix, bit_shift; + uint8_t *src_p, *dst_p; + + out_row = DIM_INPUT_ROW(image_p); + out_col = DIM_INPUT_COL(image_p); + + input_radix = PREPROC_INPUT_RADIX(image_p); + bit_shift = 8 - input_radix; // 1 byte (8 bits) for every R/G/B/A data + + src_p = (uint8_t *)RAW_IMAGE_MEM_ADDR(image_p); + dst_p = (uint8_t *)PREPROC_INPUT_MEM_ADDR(image_p); + pre_proc_unsign_right_shift(src_p, dst_p, out_row, out_col, bit_shift); + + return 0; +} + diff --git a/build/solution_kdp2_user_ex/main_scpu/application_init.c b/build/solution_kdp2_user_ex/main_scpu/application_init.c new file mode 100644 index 0000000..866ec20 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/application_init.c @@ -0,0 +1,89 @@ +/* + * Kneron Application initialization + * + * Copyright (C) 2022 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" + +// power manager +#include "kmdw_power_manager.h" + +// inference core +#include "kp_struct.h" +#include "kmdw_console.h" +#include "kmdw_inference_app.h" + +// inference app +#include "kdp2_inf_app_yolo.h" +#include "demo_customize_inf_single_model.h" +#include "demo_customize_inf_multiple_models.h" + +// inference client +#include "kdp2_usb_companion.h" + +#define MAX_IMAGE_COUNT 10 /**< MAX inference input queue slot count */ +#define MAX_RESULT_COUNT 10 /**< MAX inference output queue slot count */ + + +/** + * @brief To register AI applications + * @param[in] num_input_buf number of data inputs in list + * @param[in] inf_input_buf_list list of data input for inference task + * @return N/A + * @note Add a switch case item for a new inf_app application + */ +static void _app_func(int num_input_buf, void** inf_input_buf_list); + + +void _app_func(int num_input_buf, void** inf_input_buf_list) +{ + // check header stamp + if (0 >= num_input_buf) { + kmdw_printf("No input buffer for app function\n"); + return; + } + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)inf_input_buf_list[0]; + uint32_t job_id = header_stamp->job_id; + + switch (job_id) + { + case KDP2_INF_ID_APP_YOLO: + kdp2_app_yolo_inference(job_id, num_input_buf, inf_input_buf_list); + break; + case KDP2_JOB_ID_APP_YOLO_CONFIG_POST_PROC: + kdp2_app_yolo_config_post_process_parameters(job_id, num_input_buf, inf_input_buf_list); + break; + case DEMO_KL520_CUSTOMIZE_INF_SINGLE_MODEL_JOB_ID: // a demo code implementation in SCPU for user-defined/customized infernece from one model + demo_customize_inf_single_model(job_id, num_input_buf, inf_input_buf_list); + break; + case DEMO_KL520_CUSTOMIZE_INF_MULTIPLE_MODEL_JOB_ID: // a demo code implementation in SCPU for user-defined/customized infernece from two models + demo_customize_inf_multiple_models(job_id, num_input_buf, inf_input_buf_list); + break; + default: + kmdw_inference_app_send_status_code(job_id, KP_FW_ERROR_UNKNOWN_APP); + break; + } +} + + +void app_initialize(void) +{ + info_msg(">> Start running KL520 KDP2 companion mode ...\n"); + + /* for shutdown command */ + kmdw_power_manager_init(); + + /* initialize inference app */ + /* register APP functions */ + /* specify depth of inference queues */ + kmdw_inference_app_init(_app_func, MAX_IMAGE_COUNT, MAX_RESULT_COUNT); + + /* companion mode init */ + kdp2_usb_companion_init(); + + return; +} diff --git a/build/solution_kdp2_user_ex/main_scpu/device_init.c b/build/solution_kdp2_user_ex/main_scpu/device_init.c new file mode 100644 index 0000000..bbfa991 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/device_init.c @@ -0,0 +1,25 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +#include "project.h" +#if defined(FLASH_TYPE) && (FLASH_TYPE == FLASH_TYPE_NULL) +#include "kdev_flash_null.h" +#else +#include "kdev_flash.h" +#endif + +//Function +void dev_initialize(void) +{ + kdev_flash_initialize(); +} + diff --git a/build/solution_kdp2_user_ex/main_scpu/driver_init.c b/build/solution_kdp2_user_ex/main_scpu/driver_init.c new file mode 100644 index 0000000..481a97b --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/driver_init.c @@ -0,0 +1,28 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kdrv_uart.h" +#include "kdrv_ddr.h" +#include "kdrv_pinmux.h" +//#include "kdrv_power.h" + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; + +void drv_initialize(void) +{ + kdrv_uart_initialize(); + kdrv_pinmux_initialize(PIN_NUM, pinmux_array); + kdrv_ddr_system_init(DDR_INIT_ALL); // TODO, not 720 style +} + diff --git a/build/solution_kdp2_user_ex/main_scpu/include/application_init.h b/build/solution_kdp2_user_ex/main_scpu/include/application_init.h new file mode 100644 index 0000000..980f71b --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/include/application_init.h @@ -0,0 +1,31 @@ +/******************************************************************** + * Copyright (c) 2022 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup APPLICATION_INIT + * @{ + * @brief Kneron application init + * @copyright Copyright (C) 2022 Kneron, Inc. All rights reserved. + */ +#ifndef __APPLICATION_INIT_H__ +#define __APPLICATION_INIT_H__ + +/** + * @brief app_initialize + * + * Add application layer initialization code + * + * @return void + */ +void app_initialize(void); +#endif + + diff --git a/build/solution_kdp2_user_ex/main_scpu/include/device_init.h b/build/solution_kdp2_user_ex/main_scpu/include/device_init.h new file mode 100644 index 0000000..9b1ae22 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/include/device_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup DEVICE_INIT + * @{ + * @brief Kneron device init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __DEVICE_INIT_H__ +#define __DEVICE_INIT_H__ + +/** + * @brief dev_initialize + * + * @return void + */ +void dev_initialize(void); +#endif + + diff --git a/build/solution_kdp2_user_ex/main_scpu/include/driver_init.h b/build/solution_kdp2_user_ex/main_scpu/include/driver_init.h new file mode 100644 index 0000000..d564484 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/include/driver_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup SYSTEM_INIT + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __DRIVER_INIT_H__ +#define __DRIVER_INIT_H__ + +/** + * @brief drv_initialize + * + * @return void + */ +void drv_initialize(void); +#endif + + diff --git a/build/solution_kdp2_user_ex/main_scpu/include/middleware_init.h b/build/solution_kdp2_user_ex/main_scpu/include/middleware_init.h new file mode 100644 index 0000000..f86a89e --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/include/middleware_init.h @@ -0,0 +1,29 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup MIDDLEWARE_INIT + * @{ + * @brief Kneron middleware init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __MIDDLEWARE_INIT_H__ +#define __MIDDLEWARE_INIT_H__ + +/** + * @brief mdw_initialize + * + * @return void + */ +void mdw_initialize(void); +#endif + + diff --git a/build/solution_kdp2_user_ex/main_scpu/include/system_init.h b/build/solution_kdp2_user_ex/main_scpu/include/system_init.h new file mode 100644 index 0000000..32fe0c2 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/include/system_init.h @@ -0,0 +1,28 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup SYSTEM_INIT + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __SYSTEM_INIT_H__ +#define __SYSTEM_INIT_H__ + +/** + * @brief sys_initialize + * + * @return void + */ +void sys_initialize(void); +#endif + diff --git a/build/solution_kdp2_user_ex/main_scpu/include/task_handler.h b/build/solution_kdp2_user_ex/main_scpu/include/task_handler.h new file mode 100644 index 0000000..e9c5b76 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/include/task_handler.h @@ -0,0 +1,86 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +/**@addtogroup TASK_HANDLER + * @{ + * @brief Kneron System init + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef _TASK_HANDLER_H +#define _TASK_HANDLER_H +#include "cmsis_os2.h" +// #include "project.h" +#define USB_HOST +/****************************************************************************** +Declaration of data structure +******************************************************************************/ +// Sec 5: structure, uniou, enum, linked list +typedef struct +{ + //parameters for creating tasks + const char caName[8]; //now, len=8 + + osThreadId_t *tTaskHandle; + osThreadFunc_t fpEntry; + const uint32_t dwStackSize; + osPriority_t dwPriority; + + //parameters for creating queue + osMessageQueueId_t *tQueueHandle; + const uint32_t tQmsg_count; + const uint32_t tQmsg_size; +}T_S_KneronTask; + +osThreadId_t task_log_handle; +osThreadId_t task_infdata_handle; +osThreadId_t task_infcb_handle; +osThreadId_t task_usb_recv_handle; +osThreadId_t task_usb_send_handle; +osThreadId_t task_buf_mgr_handle; + +// put osMessageQueueId_t objects here for setting tQueueHandle + +extern void logger_thread(void *arg); +extern void kmdw_inference_image_dispatcher_thread(void *argument); +extern void kmdw_inference_result_handler_callback_thread(void *argument); +extern void kdp2_usb_companion_image_thread(void *arg); +extern void kdp2_usb_companion_result_thread(void *arg); +extern void kdp2_fifoq_manager_enqueue_image_thread(void *arg); + +/****************************************************************************** +Declaration of Global Variables & Functions +******************************************************************************/ +// Sec 6: declaration of global variable +T_S_KneronTask g_atKneronTaskPool[]= +{ +// TaskName TaskHandle TaskFuncEntry TaskStack TaskPriority QueueHandle QueueMsgCount QueueMsgSize +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + {"LogTask", &task_log_handle, logger_thread, 1024, osPriorityBelowNormal, NULL, 0, 0 }, + {"Infdata", &task_infdata_handle, kmdw_inference_image_dispatcher_thread, 2048, osPriorityNormal, NULL, 0, 0 }, + {"Infcb", &task_infcb_handle, kmdw_inference_result_handler_callback_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"usbrecv", &task_usb_recv_handle, kdp2_usb_companion_image_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"usbsend", &task_usb_send_handle, kdp2_usb_companion_result_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + {"buf_mgr", &task_buf_mgr_handle, kdp2_fifoq_manager_enqueue_image_thread, 1024, osPriorityNormal, NULL, 0, 0 }, + +// +//Follow above format to add your TASK here +// + + +//end of table, don't remove it +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + {NULL,NULL,NULL,0,0,NULL,0,0} +//------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ +}; + +#endif + diff --git a/build/solution_kdp2_user_ex/main_scpu/main.c b/build/solution_kdp2_user_ex/main_scpu/main.c new file mode 100644 index 0000000..60e1db3 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/main.c @@ -0,0 +1,57 @@ +/* + * Kneron Main Entry driver + * + * Copyright (C) 2020 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +#include "project.h" +#include "version.h" + +// Customized configration and implimentation +#include "system_init.h" +#include "driver_init.h" +#include "device_init.h" +#include "middleware_init.h" +#include "application_init.h" + +#include "kmdw_console.h" + +extern void task_initialize(void); + +/** + * @brief main, main function + */ +int main(void) +{ + osKernelInitialize(); // Initialize CMSIS-RTOS + sys_initialize(); + drv_initialize(); /* customize driver initialization, see driver_init.c */ + dev_initialize(); /* customize device initialization, see device_init.c */ + mdw_initialize(); /* customize middleware initialization, see middlewre_init.c */ + + + printf("SDK v%u.%u.%u-:build.%03u\n", + (uint8_t)(IMG_FW_MAJOR), + (uint8_t)(IMG_FW_MINOR), + (uint8_t)(IMG_FW_UPDATE), + (uint32_t)(IMG_FW_BUILD)); + + app_initialize(); /* customize application initialization, see application_init.c */ + + /* New task threads */ + task_initialize(); + + /* Start RTOS Kernel */ + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/solution_kdp2_user_ex/main_scpu/middleware_init.c b/build/solution_kdp2_user_ex/main_scpu/middleware_init.c new file mode 100644 index 0000000..fcdb7b3 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/middleware_init.c @@ -0,0 +1,31 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kmdw_memory.h" +#include "kmdw_model.h" +#include "kmdw_dfu.h" +#include "kmdw_console.h" + +void mdw_initialize(void) +{ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kmdw_ddr_store_system_reserve(DDR_SYSTEM_RESERVED_BEGIN, DDR_SYSTEM_RESERVED_END); + kmdw_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE); // uart console + kmdw_dfu_init(NULL, NULL); + kmdw_model_init(); + + // FW is loaded by fw_loader + //load_ncpu_fw(1/*reset_flag*/); // (kmdw_system.h) load ncpu fw from flash +} + diff --git a/build/solution_kdp2_user_ex/main_scpu/system_init.c b/build/solution_kdp2_user_ex/main_scpu/system_init.c new file mode 100644 index 0000000..a89c8f3 --- /dev/null +++ b/build/solution_kdp2_user_ex/main_scpu/system_init.c @@ -0,0 +1,23 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +//#include "project.h" +#include "kdrv_system.h" + + + //Function +void sys_initialize(void) +{ + /* SDK main init for companion mode */ + kdrv_system_init(); + kdrv_system_init_ncpu(); +} diff --git a/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.sct b/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.sct new file mode 100644 index 0000000..0260f1e --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.sct @@ -0,0 +1,19 @@ +#!armcc -E +#define DRAM_START 0x0FFF0000 +#define DRAM_SIZE 0x00010000 + +LR_IROM1 0x00000000 0x00010000 { ; load region size_region + ER_IROM1 0x00000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } +} + diff --git a/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.uvoptx b/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.uvoptx new file mode 100644 index 0000000..1ad4186 --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.uvoptx @@ -0,0 +1,576 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ncpu + 0x4 + ARM-ADS + + 250000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ULP2CM3 + -UAny -O905 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO3 -FD20000000 -FC1000 -FN0 + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U63610859 -O1 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO1 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 169 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + D:\3_code\mozart_sw_kdp2.git\scpu\project\companion_kdp2\main\main.c + + + + + + + 1 + 2 + 0x30ff0140 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\user_pre_process.c + user_pre_process.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\user_post_process.c + user_post_process.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\model_ftr_table.c + model_ftr_table.c + 0 + 0 + + + + + libs + 1 + 0 + 0 + 0 + + 2 + 5 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + kdp2_ncpu_sdk.lib + 0 + 0 + + + 2 + 6 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + kdp2_ncpu_model_ppp.lib + 0 + 0 + + + + + rtx + 0 + 0 + 0 + 0 + + 3 + 7 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + irq_cm4f.s + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + os_systick.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + RTX_Config.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + rtx_delay.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + rtx_evflags.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + rtx_evr.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + rtx_kernel.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + rtx_lib.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + rtx_memory.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + rtx_mempool.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + rtx_msgqueue.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + rtx_mutex.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + rtx_semaphore.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + rtx_system.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + rtx_thread.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + + + startup + 1 + 0 + 0 + 0 + + 4 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + startup.c + 0 + 0 + + + 4 + 24 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + diff --git a/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.uvprojx b/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.uvprojx new file mode 100644 index 0000000..dad3df7 --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/ncpu_keil/ncpu.uvprojx @@ -0,0 +1,557 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ncpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Mozart_ncpu + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_ncpu.bin" + post_build.bat fw_ncpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0xfff0000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + ARM_MATH_CM4, TARGET_NCPU, LOG_ENABLE, KL520 + + ..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\ncpu\rtos\rtx\include;..\..\..\..\platform\kl520\ncpu\drv\include;..\..\..\..\platform\kl520\ncpu\model_ppp\include;..\..\..\..\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\..\..\include + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x00000000 + 0x20000000 + + ..\..\..\..\platform\kl520\ncpu\mozart_ncpu.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_ncpu\main.c + + + user_pre_process.c + 1 + ..\..\main_ncpu\user_pre_process.c + + + user_post_process.c + 1 + ..\..\main_ncpu\user_post_process.c + + + model_ftr_table.c + 1 + ..\..\main_ncpu\model_ftr_table.c + + + + + libs + + + kdp2_ncpu_sdk.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + + + kdp2_ncpu_model_ppp.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/build/solution_kdp2_user_ex/sn52096/ncpu_keil/post_build.bat b/build/solution_kdp2_user_ex/sn52096/ncpu_keil/post_build.bat new file mode 100644 index 0000000..1ac5a9c --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/ncpu_keil/post_build.bat @@ -0,0 +1,10 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_ncpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ diff --git a/build/solution_kdp2_user_ex/sn52096/proj.uvmpw b/build/solution_kdp2_user_ex/sn52096/proj.uvmpw new file mode 100644 index 0000000..c38cafd --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/proj.uvmpw @@ -0,0 +1,20 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + + .\scpu_keil\scpu.uvprojx + 1 + + + + .\ncpu_keil\ncpu.uvprojx + + + diff --git a/build/solution_kdp2_user_ex/sn52096/project.h b/build/solution_kdp2_user_ex/sn52096/project.h new file mode 100644 index 0000000..b677458 --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +#define FLASH_FW_NCPU0_ADDR 0x00018000 /**< fw_ncpu.bin */ +#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +#define FLASH_MODEL_ALL_ADDR 0x00301000 /**< all_models.bin */ +#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/solution_kdp2_user_ex/sn52096/scpu_keil/kdp2_scpu_jlink.ini b/build/solution_kdp2_user_ex/sn52096/scpu_keil/kdp2_scpu_jlink.ini new file mode 100644 index 0000000..d4099c3 --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/scpu_keil/kdp2_scpu_jlink.ini @@ -0,0 +1,13 @@ +MEMSET(0x10200000, 0x18000, 0) +MEMSET(0x10210000, 0x08000, 0) + +// to let USB know this is running in JTAG mode +MEMSET(0x10100000, 1, 0x01) +MEMSET(0x10100001, 1, 0xBA) +MEMSET(0x10100002, 1, 0xDC) +MEMSET(0x10100003, 1, 0xFE) + +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10104000) // Set Stack Pointer +PC=_RDWORD(0x10104004) // Set Program Counter = Reset_Handler +BS main \ No newline at end of file diff --git a/build/solution_kdp2_user_ex/sn52096/scpu_keil/post_build.bat b/build/solution_kdp2_user_ex/sn52096/scpu_keil/post_build.bat new file mode 100644 index 0000000..f839167 --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/scpu_keil/post_build.bat @@ -0,0 +1,12 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_scpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ + + diff --git a/build/solution_kdp2_user_ex/sn52096/scpu_keil/pre_build.bat b/build/solution_kdp2_user_ex/sn52096/scpu_keil/pre_build.bat new file mode 100644 index 0000000..dba1dc6 --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/scpu_keil/pre_build.bat @@ -0,0 +1 @@ +REM "prebuild script" diff --git a/build/solution_kdp2_user_ex/sn52096/scpu_keil/scpu.uvoptx b/build/solution_kdp2_user_ex/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..88ec4a6 --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,1093 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + dev + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\kdp2_scpu_jlink.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + + 1 + 2 + 0 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + 0 + + + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_scpu\main.c + main.c + 0 + 0 + + + 1 + 2 + 5 + 0 + 0 + 0 + ..\project.h + project.h + 0 + 0 + + + 1 + 3 + 5 + 0 + 0 + 0 + ..\..\main_scpu\include\task_handler.h + task_handler.h + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\main_scpu\application_init.c + application_init.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\..\main_scpu\system_init.c + system_init.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + ..\..\main_scpu\device_init.c + device_init.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + ..\..\main_scpu\driver_init.c + driver_init.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + ..\..\main_scpu\middleware_init.c + middleware_init.c + 0 + 0 + + + + + inf_app + 1 + 0 + 0 + 0 + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\app\demo_customize_inf_single_model.c + demo_customize_inf_single_model.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\app\demo_customize_inf_multiple_models.c + demo_customize_inf_multiple_models.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\app\kdp2_inf_app_yolo.c + kdp2_inf_app_yolo.c + 0 + 0 + + + + + inf_client + 1 + 0 + 0 + 0 + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\mdw\usb_companion\kdp2_cmd_handler_520.c + kdp2_cmd_handler_520.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\mdw\usb_companion\kdp2_usb_companion.c + kdp2_usb_companion.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\mdw\usb_companion\usbd_hal_520.c + usbd_hal_520.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\mdw\usb_companion\kdp2_usb_log.c + kdp2_usb_log.c + 0 + 0 + + + + + middleware + 1 + 0 + 0 + 0 + + 4 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\mdw\memory\kmdw_memory.c + kmdw_memory.c + 0 + 0 + + + 4 + 17 + 1 + 0 + 0 + 0 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kmdw_inference_520.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + ..\..\..\..\mdw\inference\kmdw_fifoq_manager.c + kmdw_fifoq_manager.c + 0 + 0 + + + + + device + 0 + 0 + 0 + 0 + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\dev\flash\kdev_flash_winbond.c + kdev_flash_winbond.c + 0 + 0 + + + + + driver + 0 + 0 + 0 + 0 + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + kdrv_pinmux.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + kdrv_gpio.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_spif.c + kdrv_spif.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + kdrv_uart.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ipc.c + kdrv_ipc.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ncpu.c + kdrv_ncpu.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2.c + kdrv_usbd2.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2v.c + kdrv_usbd2v.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + kdrv_clock.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mpu.c + kdrv_mpu.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + kdrv_ddr.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + kdrv_power.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + kdrv_system.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_wdt.c + kdrv_wdt.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + kdrv_gdma.c + 0 + 0 + + + 6 + 45 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\rtc.c + rtc.c + 0 + 0 + + + 6 + 46 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + kdrv_pwm.c + 0 + 0 + + + + + rtx + 1 + 0 + 0 + 0 + + 7 + 47 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\irq_cm4f.s + irq_cm4f.s + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\os_systick.c + os_systick.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\RTX_Config.c + RTX_Config.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_delay.c + rtx_delay.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evflags.c + rtx_evflags.c + 0 + 0 + + + 7 + 52 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evr.c + rtx_evr.c + 0 + 0 + + + 7 + 53 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_kernel.c + rtx_kernel.c + 0 + 0 + + + 7 + 54 + 1 + 1 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_lib.c + rtx_lib.c + 0 + 0 + + + 7 + 55 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_memory.c + rtx_memory.c + 0 + 0 + + + 7 + 56 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mempool.c + rtx_mempool.c + 0 + 0 + + + 7 + 57 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_msgqueue.c + rtx_msgqueue.c + 0 + 0 + + + 7 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mutex.c + rtx_mutex.c + 0 + 0 + + + 7 + 59 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_semaphore.c + rtx_semaphore.c + 0 + 0 + + + 7 + 60 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_system.c + rtx_system.c + 0 + 0 + + + 7 + 61 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_thread.c + rtx_thread.c + 0 + 0 + + + 7 + 62 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + 7 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + task_handler.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 8 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + startup.c + 0 + 0 + + + 8 + 65 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + + libs + 1 + 0 + 0 + 0 + + 9 + 66 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\system_520.lib + system_520.lib + 0 + 0 + + + + diff --git a/build/solution_kdp2_user_ex/sn52096/scpu_keil/scpu.uvprojx b/build/solution_kdp2_user_ex/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..2388b3f --- /dev/null +++ b/build/solution_kdp2_user_ex/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,843 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + dev + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.5.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + scpu_fw + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + pre_build.bat + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_scpu.bin" + post_build.bat fw_scpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE + + ..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\platform\kl520\scpu\rtos\rtx\include;..\..\..\..\platform\board\board_sn52096;..\..\..\..\platform\dev\include;..\..\..\..\mdw\include;..\..\..\..\mdw\inference;..\..\..\..\app;..\..\main_scpu\include;..\;..\..\..\lib\system_520\main_scpu\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\sn52096;..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\board\board_sn52096 + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + ..\..\..\..\platform\kl520\scpu\scatter_load.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_scpu\main.c + + + project.h + 5 + ..\project.h + + + task_handler.h + 5 + ..\..\main_scpu\include\task_handler.h + + + application_init.c + 1 + ..\..\main_scpu\application_init.c + + + system_init.c + 1 + ..\..\main_scpu\system_init.c + + + device_init.c + 1 + ..\..\main_scpu\device_init.c + + + driver_init.c + 1 + ..\..\main_scpu\driver_init.c + + + middleware_init.c + 1 + ..\..\main_scpu\middleware_init.c + + + + + inf_app + + + demo_customize_inf_single_model.c + 1 + ..\..\..\..\app\demo_customize_inf_single_model.c + + + demo_customize_inf_multiple_models.c + 1 + ..\..\..\..\app\demo_customize_inf_multiple_models.c + + + kdp2_inf_app_yolo.c + 1 + ..\..\..\..\app\kdp2_inf_app_yolo.c + + + + + inf_client + + + kdp2_cmd_handler_520.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_cmd_handler_520.c + + + kdp2_usb_companion.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_usb_companion.c + + + usbd_hal_520.c + 1 + ..\..\..\..\mdw\usb_companion\usbd_hal_520.c + + + kdp2_usb_log.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_usb_log.c + + + + + middleware + + + kmdw_memory.c + 1 + ..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_memxfer.c + 1 + ..\..\..\..\mdw\flash\kmdw_memxfer.c + + + kmdw_console.c + 1 + ..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_power_manager.c + 1 + ..\..\..\..\mdw\power\kmdw_power_manager.c + + + kmdw_dfu.c + 1 + ..\..\..\..\mdw\dfu\kmdw_dfu.c + + + kdp_crc.c + 1 + ..\..\..\..\mdw\utils\kmdw_utils_crc.c + + + kmdw_system.c + 1 + ..\..\..\..\mdw\system\kmdw_system.c + + + kmdw_ipc.c + 1 + ..\..\..\..\mdw\ipc\kmdw_ipc.c + + + kmdw_model.c + 1 + ..\..\..\..\mdw\model\kmdw_model.c + + + dual_fifo2.c + 1 + ..\..\..\..\mdw\inference\dual_fifo2.c + + + kdp2_inf_generic_raw.c + 1 + ..\..\..\..\mdw\inference\kdp2_inf_generic_raw.c + + + kmdw_inference_520.c + 1 + ..\..\..\..\mdw\inference\kmdw_inference_520.c + + + kmdw_fifoq_manager.c + 1 + ..\..\..\..\mdw\inference\kmdw_fifoq_manager.c + + + + + device + + + kdev_flash_winbond.c + 1 + ..\..\..\..\platform\dev\flash\kdev_flash_winbond.c + + + + + driver + + + kdrv_pinmux.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_gpio.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + + + kdrv_spif.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_spif.c + + + kdrv_uart.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_ipc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ipc.c + + + kdrv_ncpu.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ncpu.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + kdrv_usbd2.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2.c + + + kdrv_usbd2v.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2v.c + + + kdrv_clock.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_mpu.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mpu.c + + + kdrv_ddr.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_power.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_system.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_wdt.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_wdt.c + + + kdrv_gdma.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + + + rtc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\rtc.c + + + kdrv_pwm.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + + + task_handler.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + + + + + libs + + + system_520.lib + 4 + ..\..\..\..\lib\system_520.lib + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/include/base.h b/include/base.h new file mode 100644 index 0000000..5051f8a --- /dev/null +++ b/include/base.h @@ -0,0 +1,121 @@ +/** + * @file base.h + * @brief Basic utils & struct + * @copyright (c) 2018 Kneron Inc. All right reserved. + */ + +#ifndef __BASE_H__ +#define __BASE_H__ + +#include +#include + +#define EPSILON_FLT ((float)0.000001) /**< a loose value than FLT_FPSILON */ +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +typedef uint8_t u8_t; +typedef uint16_t u16_t; +typedef uint32_t u32_t; +typedef uint64_t u64_t; + +typedef int8_t s8; +typedef int16_t s16; +typedef int32_t s32; +typedef int64_t s64; + + +#define BIT(x) (0x01U << (x)) + +#define BIT0 0x00000001 +#define BIT1 0x00000002 +#define BIT2 0x00000004 +#define BIT3 0x00000008 +#define BIT4 0x00000010 +#define BIT5 0x00000020 +#define BIT6 0x00000040 +#define BIT7 0x00000080 +#define BIT8 0x00000100 +#define BIT9 0x00000200 +#define BIT10 0x00000400 +#define BIT11 0x00000800 +#define BIT12 0x00001000 +#define BIT13 0x00002000 +#define BIT14 0x00004000 +#define BIT15 0x00008000 +#define BIT16 0x00010000 +#define BIT17 0x00020000 +#define BIT18 0x00040000 +#define BIT19 0x00080000 +#define BIT20 0x00100000 +#define BIT21 0x00200000 +#define BIT22 0x00400000 +#define BIT23 0x00800000 +#define BIT24 0x01000000 +#define BIT25 0x02000000 +#define BIT26 0x04000000 +#define BIT27 0x08000000 +#define BIT28 0x10000000 +#define BIT29 0x20000000 +#define BIT30 0x40000000 +#define BIT31 0x80000000 + +#ifndef NULL +#define NULL 0 +#endif + +#ifndef ENABLE +#define ENABLE 1 +#endif + +#ifndef DISABLE +#define DISABLE 0 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef MIN +#define MIN(a,b) (((a)<(b))?(a):(b)) +#endif + +#ifndef MAX +#define MAX(a,b) (((a)>(b))?(a):(b)) +#endif + +#ifndef ABS +#define ABS(a) (((a)>=0)?(a):(-(a))) +#endif + +#ifndef ABSDIFF +#define ABSDIFF(x, y) (x > y) ? (x-y) : (y-x) +#endif + +#ifndef FLOOR +#define FLOOR(val) ((int)(val) - ((int)(val) > val)) +#endif + +#ifndef ROUND +#define ROUND(x) ((x)>=0?(int)((x)+0.5):(int)((x)-0.5)) +#endif + +#define STS_OK 0 +#define STS_ERR_NORMAL 1 +#define STS_ERR_CRC 2 + +#define vLib_LeWrite8(x,y) *(volatile u8 *)((u8* )x)=(y) +#define vLib_LeWrite32(x,y) *(volatile u32*)((u8* )x)=(y) //bessel:add (u8* ) +#define u32lib_leread32(x) *((volatile u32*)((u8* )x)) //bessel:add (u8* ) +#define u32Lib_LeRead32(x) *((volatile u32*)((u8* )x)) //bessel:add (u8* ) + + +#endif + + diff --git a/include/io.h b/include/io.h new file mode 100644 index 0000000..532b5e9 --- /dev/null +++ b/include/io.h @@ -0,0 +1,41 @@ +#ifndef IO_H +#define IO_H + + +#define readl(addr) (*(volatile unsigned int *)(addr)) +#define writel(val, addr) (*(volatile unsigned int *)(addr) = (val)) + +#define readw(addr) (*(volatile unsigned short *)(addr)) +#define writew(val, addr) (*(volatile unsigned short *)(addr) = (val)) + +#define readb(addr) (*(volatile unsigned char *)(addr)) +#define writeb(val, addr) (*(volatile unsigned char *)(addr) = (val)) + +#define inw(port) readl(port) +#define outw(port, val) writel(val, port) + +#define inb(port) readb(port) +#define outb(port, val) writeb(val, port) + +#define inhw(port) readw(port) +#define outhw(port, val) writew(val, port) + +#define masked_outw(port, val, mask) outw(port, (inw(port) & ~mask) | (val & mask)) + +#define GET_BIT(port, __bit) \ + ((inw(port) & BIT##__bit) >> __bit) + +#define GET_BITS(port, __s_bit, __e_bit) \ + ((inw(port) & (BIT##__e_bit | (BIT##__e_bit - BIT##__s_bit))) >> __s_bit) + +#define SET_BIT(port, __bit) \ + outw(port, BIT##__bit) + +#define SET_MASKED_BIT(port, val, __bit) \ + outw(port, (inw(port) & ~BIT##__bit) | ((val << __bit) & BIT##__bit)) + +#define SET_MASKED_BITS(port, val, __s_bit, __e_bit) \ + outw(port, ((inw(port) & ~(BIT##__e_bit | (BIT##__e_bit - BIT##__s_bit))) | (val << __s_bit))); + + +#endif // IO_H diff --git a/include/scu_ipc.h b/include/scu_ipc.h new file mode 100644 index 0000000..729dd5e --- /dev/null +++ b/include/scu_ipc.h @@ -0,0 +1,32 @@ +/** + * @file scu_ipc.h + * @brief Kneron Header for KL520 SCU IPC + * @version 0.1 + * @date 2021-03-22 + * + * @copyright Copyright (c) 2018-2021 Kneron Inc. All rights reserved. + */ + + +#ifndef SCU_IPC_H +#define SCU_IPC_H + +#if defined(TARGET_SCPU) +/* To NCPU */ +void scu_ipc_enable_to_ncpu_int(void); +void scu_ipc_trigger_to_ncpu_int(void); + +/* From NCPU */ +void scu_ipc_clear_from_ncpu_int(void); +#endif + +#if defined(TARGET_NCPU) +/* To SCPU */ +void scu_ipc_enable_to_scpu_int(void); +void scu_ipc_trigger_to_scpu_int(void); + +/* From SCPU */ +void scu_ipc_clear_from_scpu_int(void); +#endif + +#endif diff --git a/include/version.h b/include/version.h new file mode 100644 index 0000000..d8cb087 --- /dev/null +++ b/include/version.h @@ -0,0 +1,17 @@ +#ifndef __VERSION_H__ +#define __VERSION_H__ + +//Image FW version format: 0xAABBCCDD, AA=major, BB=minor, CC=update, DD=RD reserve version +#define IMG_FW_MAJOR 0x02 +#define IMG_FW_MINOR 0x02 +#define IMG_FW_UPDATE 0x00 +#define IMG_FW_RD_VER 0x00 +#define IMG_FW_BUILD 1226 + +#define IMG_ID "SCPU" //must be 4 bytes +#define IMG_FW_VERSION ((IMG_FW_MAJOR<<24)+(IMG_FW_MINOR<<16)+(IMG_FW_UPDATE<<8)+(IMG_FW_RD_VER)) +#define IMG_FLAG 0xFFFFFFFF + +#endif //__VERSION_H__ + + diff --git a/lib/kdp2_ncpu_model_ppp.lib b/lib/kdp2_ncpu_model_ppp.lib new file mode 100644 index 0000000..946eb50 Binary files /dev/null and b/lib/kdp2_ncpu_model_ppp.lib differ diff --git a/lib/kdp2_ncpu_sdk.lib b/lib/kdp2_ncpu_sdk.lib new file mode 100644 index 0000000..e7ffc35 Binary files /dev/null and b/lib/kdp2_ncpu_sdk.lib differ diff --git a/lib/system_520.lib b/lib/system_520.lib new file mode 100644 index 0000000..303e027 Binary files /dev/null and b/lib/system_520.lib differ diff --git a/mdw/camera/kmdw_camera.c b/mdw/camera/kmdw_camera.c new file mode 100644 index 0000000..614b2df --- /dev/null +++ b/mdw/camera/kmdw_camera.c @@ -0,0 +1,299 @@ +/* + * KDP Camera driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include "board.h" +#include +#include +#include +#include +#include "kmdw_camera.h" +#ifdef KDP_UVC +#include "uvc_dev.h" +#endif + +struct kmdw_camera_s { + uint32_t inuse; + struct cam_ops *ops; +} camera_s[IMGSRC_NUM]; + +#ifdef KL520 +extern kmdw_status_t kmdw_cam_kl520_init(void); +#endif + +kmdw_status_t kmdw_camera_init(void) +{ +#ifdef KDP_UVC + kmdw_cam_uvc_init(); +#else +#ifdef KL520 + kmdw_cam_kl520_init(); +#endif +#endif + return KMDW_STATUS_OK; +} + +kmdw_status_t kmdw_camera_open(uint32_t cam_idx) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->open == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->open(cam_idx); +} + +kmdw_status_t kmdw_camera_close(uint32_t cam_idx) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->close == NULL) + return KMDW_STATUS_ERROR; + + camera_s[cam_idx].ops->close(cam_idx); + return KMDW_STATUS_OK; +} + +kmdw_status_t kmdw_camera_get_device_info(uint32_t cam_idx, struct cam_capability *cap) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->query_capability == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->query_capability(cam_idx, cap); +} + +kmdw_status_t kmdw_camera_set_frame_format(uint32_t cam_idx, struct cam_format *format) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->set_format == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->set_format(cam_idx, format); +} + +kmdw_status_t kmdw_camera_get_frame_format(uint32_t cam_idx, struct cam_format *format) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->get_format == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->get_format(cam_idx, format); +} + +kmdw_status_t kmdw_camera_buffer_init(uint32_t cam_idx, uint32_t buf_addr_0, uint32_t buf_addr_1) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->buffer_init == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->buffer_init(cam_idx, buf_addr_0, buf_addr_1); +} + +kmdw_status_t kmdw_camera_start(uint32_t cam_idx, kmdw_camera_callback_t img_cb) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->start_capture == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->start_capture(cam_idx, img_cb); +} + +kmdw_status_t kmdw_camera_stop(uint32_t cam_idx) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->stop_capture == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->stop_capture(cam_idx); +} + +kmdw_status_t kmdw_camera_buffer_prepare(uint32_t cam_idx) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->buffer_prepare == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->buffer_prepare(cam_idx); +} + +kmdw_status_t kmdw_camera_buffer_capture(uint32_t cam_idx, uint32_t *addr, uint32_t *size) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->buffer_capture == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->buffer_capture(cam_idx, addr, size); +} + +kmdw_status_t kmdw_camera_stream_on(uint32_t cam_idx) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->stream_on == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->stream_on(cam_idx); +} + +kmdw_status_t kmdw_camera_stream_off(uint32_t cam_idx) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->stream_off == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->stream_off(cam_idx); +} + +kmdw_status_t kmdw_camera_set_gain(uint32_t cam_idx, uint32_t gain1, uint32_t gain2) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->set_gain == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->set_gain(cam_idx, gain1, gain2); +} + +kmdw_status_t kmdw_camera_set_aec(uint32_t cam_idx, struct cam_sensor_aec *aec_p) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->set_aec == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->set_aec(cam_idx, aec_p); +} + +kmdw_status_t kmdw_camera_set_exp_time(uint32_t cam_idx, uint32_t gain1, uint32_t gain2) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->set_exp_time == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->set_exp_time(cam_idx, gain1, gain2); +} + +kmdw_status_t kmdw_camera_get_lux(uint32_t cam_idx, uint16_t *expo, uint8_t *pre_gain, uint8_t *post_gain, uint8_t *global_gain, uint8_t *y_average) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->get_lux == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->get_lux(cam_idx, expo, pre_gain, post_gain, global_gain, y_average); +} + +kmdw_status_t kmdw_camera_led_switch(uint32_t cam_idx, uint32_t on) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->led_switch == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->led_switch(cam_idx, on); +} + +kmdw_status_t kmdw_camera_set_mirror(uint32_t cam_idx, uint32_t enable) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->set_mirror == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->set_mirror(cam_idx, enable); +} + +kmdw_status_t kmdw_camera_set_flip(uint32_t cam_idx, uint32_t enable) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->set_flip == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->set_flip(cam_idx, enable); +} + +uint32_t kmdw_camera_get_device_id(uint32_t cam_idx) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->get_device_id == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->get_device_id(cam_idx); +} + +kmdw_status_t kmdw_camera_ioctl(uint32_t cam_idx, uint32_t cid, void *data, uint16_t len) +{ + if (cam_idx >= IMGSRC_NUM) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].ops->ioctl == NULL) + return KMDW_STATUS_ERROR; + + return camera_s[cam_idx].ops->ioctl(cam_idx, cid, data, len); +} + +kmdw_status_t kmdw_camera_controller_register(uint32_t cam_idx, struct cam_ops *cam_ops_p) +{ + if (cam_idx >= IMGSRC_NUM || cam_ops_p == NULL) + return KMDW_STATUS_ERROR; + + if (camera_s[cam_idx].inuse) + return KMDW_STATUS_ERROR; + + camera_s[cam_idx].ops = cam_ops_p; + camera_s[cam_idx].inuse = 1; + + return KMDW_STATUS_OK; +} + +kmdw_status_t kmdw_camera_controller_unregister(uint32_t cam_idx, struct cam_ops *cam_ops_p) +{ + if (cam_idx >= IMGSRC_NUM || cam_ops_p == NULL) + return KMDW_STATUS_ERROR; + + if (!camera_s[cam_idx].inuse) + return KMDW_STATUS_ERROR; + + camera_s[cam_idx].ops = NULL; + camera_s[cam_idx].inuse = 0; + + return KMDW_STATUS_OK; +} + + diff --git a/mdw/camera/kmdw_camera_kl520.c b/mdw/camera/kmdw_camera_kl520.c new file mode 100644 index 0000000..a2dde0a --- /dev/null +++ b/mdw/camera/kmdw_camera_kl520.c @@ -0,0 +1,309 @@ +/* + * KDP Camera driver for KL520 + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "kmdw_camera.h" +#include "kmdw_sensor.h" +#include "kmdw_console.h" +#include "kdrv_clock.h" +#include "kdrv_dpi2ahb.h" +#include "kdrv_mipicsirx.h" + +#define CAM_DEBUG + +#ifdef CAM_DEBUG +#define cam_msg(fmt, ...) err_msg("[%s] " fmt, __func__, ##__VA_ARGS__) +#else +#define cam_msg(fmt, ...) +#endif + +struct kmdw_cam_context { + uint32_t id; + uint32_t sensor_id; + uint32_t cam_input_type; + uint32_t capabilities; + struct cam_format fmt; +}; + +struct kmdw_cam_context cam_ctx[KDP_CAM_NUM]; + +/* API */ +static kmdw_status_t kmdw_cam_open(uint32_t cam_idx) +{ + struct kmdw_cam_context *ctx = &cam_ctx[cam_idx]; + + if(ctx->cam_input_type != IMGSRC_IN_PORT_MIPI) + return KMDW_STATUS_OK; + cam_msg("cam: %d\n", cam_idx); + kdrv_clock_set_csiclk(cam_idx, 1); + kdrv_csi2rx_set_power(cam_idx, 1); + kdrv_csi2rx_reset(cam_idx, ctx->sensor_id); + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_close(uint32_t cam_idx) +{ + struct kmdw_cam_context *ctx = &cam_ctx[cam_idx]; + if(ctx->cam_input_type != IMGSRC_IN_PORT_MIPI) + return KMDW_STATUS_OK; + cam_msg("cam: %d\n", cam_idx); + kdrv_csi2rx_set_power(cam_idx, 0); + kdrv_clock_set_csiclk(cam_idx, 0); + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_query_capability(uint32_t cam_idx, struct cam_capability *cap) +{ + struct kmdw_cam_context *ctx = &cam_ctx[cam_idx]; + + cam_msg("cam: %d\n", cam_idx); + + ctx->capabilities = CAP_VIDEO_CAPTURE | CAP_STREAMING | CAP_DEVICE_CAPS; + + strcpy(cap->driver, "kl520_camera"); + strcpy(cap->desc, "kl520_camera"); + cap->version = 0x00010001; + cap->capabilities = ctx->capabilities; + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_set_format(uint32_t cam_idx, struct cam_format *format) +{ + struct kmdw_cam_context *ctx = &cam_ctx[cam_idx]; + uint32_t bpp; + + ctx->fmt = *format; + + if (format->pixelformat == IMG_FORMAT_RGB565) + bpp = 2; + else if (format->pixelformat == IMG_FORMAT_RAW8) + { + if(cam_ctx[cam_idx].cam_input_type == IMGSRC_IN_PORT_DPI) + bpp = 2; + else + bpp = 1; + } + + ctx->fmt.sizeimage = format->width * format->height * bpp; + + cam_msg("cam %d: w=%d h=%d p=0x%x f=%d b=%d s=%d c=%d\n", cam_idx, + ctx->fmt.width, ctx->fmt.height, ctx->fmt.pixelformat, ctx->fmt.field, + ctx->fmt.bytesperline, ctx->fmt.sizeimage, ctx->fmt.colorspace); + + kdrv_dpi2ahb_enable(ctx->id, format); + kdrv_csi2rx_enable(ctx->cam_input_type, ctx->id, ctx->sensor_id, format); + kmdw_sensor_set_fmt(cam_idx, &ctx->fmt); + + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_get_format(uint32_t cam_idx, struct cam_format *format) +{ + struct kmdw_cam_context *ctx = &cam_ctx[cam_idx]; + + cam_msg("cam: %d\n", cam_idx); + + *format = ctx->fmt; + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_buffer_init(uint32_t cam_idx, uint32_t buf_addr_0, uint32_t buf_addr_1) +{ + struct kmdw_cam_context *ctx = &cam_ctx[cam_idx]; + + cam_msg("cam %d: size=%d\n", cam_idx, ctx->fmt.sizeimage); + + kdrv_dpi2ahb_buf_init(cam_idx, buf_addr_0, buf_addr_1); + + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_start_capture(uint32_t cam_idx, kmdw_camera_callback_t img_cb) +{ + cam_msg("cam: %d\n", cam_idx); + kdrv_csi2rx_start(cam_ctx[cam_idx].cam_input_type, cam_idx); + kdrv_dpi2ahb_start((uint32_t)cam_idx, img_cb); + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_stop_capture(uint32_t cam_idx) +{ + cam_msg("cam: %d\n", cam_idx); + kdrv_dpi2ahb_stop((uint32_t)cam_idx); + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_buffer_prepare(uint32_t cam_idx) +{ + cam_msg("cam: %d\n", cam_idx); + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_buffer_capture(uint32_t cam_idx, uint32_t *addr, uint32_t *size) +{ + cam_msg("cam: %d\n", cam_idx); + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_stream_on(uint32_t cam_idx) +{ + cam_msg("cam: %d\n", cam_idx); + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_stream_off(uint32_t cam_idx) +{ + cam_msg("cam: %d\n", cam_idx); + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_set_gain(uint32_t cam_idx, uint32_t gain1, uint32_t gain2) +{ + cam_msg("cam: %d: gain1 %d, gain2 %d\n", cam_idx, gain1, gain2); + + return kmdw_sensor_set_gain(cam_idx, gain1, gain2); +} + +static kmdw_status_t kmdw_cam_set_aec(uint32_t cam_idx, struct cam_sensor_aec *aec_p) +{ + cam_msg("cam: %d\n", cam_idx); + + return kmdw_sensor_set_aec(cam_idx, aec_p); +} + +static kmdw_status_t kmdw_cam_set_exp_time(uint32_t cam_idx, uint32_t gain1, uint32_t gain2) +{ + cam_msg("cam: %d: gain1 %d, gain2 %d\n", cam_idx, gain1, gain2); + + return kmdw_sensor_set_exp_time(cam_idx, gain1, gain2); +} + +static kmdw_status_t kmdw_cam_get_lux(uint32_t cam_idx, uint16_t *expo, uint8_t *pre_gain, uint8_t *post_gain, uint8_t *global_gain, uint8_t *y_average) +{ + cam_msg("cam: %d\n", cam_idx); + + return kmdw_sensor_get_lux(cam_idx, expo, pre_gain, post_gain, global_gain, y_average); +} + +static kmdw_status_t kmdw_cam_led_switch(uint32_t cam_idx, uint32_t on) +{ + cam_msg("cam: %d\n", cam_idx); + + return kmdw_sensor_led_switch(cam_idx, on); +} + +static kmdw_status_t kmdw_cam_set_mirror(uint32_t cam_idx, uint32_t enable) +{ + cam_msg("[%s] cam: %d\n", __func__, cam_idx); + + kmdw_sensor_set_mirror(cam_idx, enable); + + return KMDW_STATUS_OK; +} + +static kmdw_status_t kmdw_cam_set_flip(uint32_t cam_idx, uint32_t enable) +{ + cam_msg("[%s] cam: %d\n", __func__, cam_idx); + + kmdw_sensor_set_flip(cam_idx, enable); + + return KMDW_STATUS_OK; +} + +static uint32_t kmdw_cam_get_device_id(uint32_t cam_idx) +{ + cam_msg("[%s] cam: %d\n", __func__, cam_idx); + + return kmdw_sensor_get_dev_id(cam_idx); +} + +static struct cam_ops kdp520_camera_ops = { + .open = kmdw_cam_open, + .close = kmdw_cam_close, + .query_capability = kmdw_cam_query_capability, + .set_format = kmdw_cam_set_format, + .get_format = kmdw_cam_get_format, + .buffer_init = kmdw_cam_buffer_init, + .start_capture = kmdw_cam_start_capture, + .stop_capture = kmdw_cam_stop_capture, + .buffer_prepare = kmdw_cam_buffer_prepare, + .buffer_capture = kmdw_cam_buffer_capture, + .stream_on = kmdw_cam_stream_on, + .stream_off = kmdw_cam_stream_off, + .set_gain = kmdw_cam_set_gain, + .set_aec = kmdw_cam_set_aec, + .set_exp_time = kmdw_cam_set_exp_time, + .get_lux = kmdw_cam_get_lux, + .led_switch = kmdw_cam_led_switch, + .set_mirror = kmdw_cam_set_mirror, + .set_flip = kmdw_cam_set_flip, + .get_device_id = kmdw_cam_get_device_id, +}; + +static void kmdw_cam_clock_init() +{ + kdrv_clock_enable(CLK_PLL3); + kdrv_clock_mgr_change_pll3_clock(/* mnp */ CAM_CLK_MS, CAM_CLK_NS, CAM_CLK_PS, + /* csi0 */ CSI0_TXESC, CSI0_CSI, CSI0_VC0, + /* csi1 */ CSI1_TXESC, CSI1_CSI, CSI1_VC0); + + kdrv_delay_us(10 * 5); + kdrv_clock_enable(CLK_PLL3_OUT1); + kdrv_clock_enable(CLK_PLL3_OUT2); +} +void kmdw_cam_mipi_init(uint32_t cam_idx) +{ + critical_msg("[%s] init %d\n", __func__,cam_idx); + kdrv_csi2rx_initialize(cam_idx); +} + +void kmdw_cam_dpi_init(uint32_t cam_idx) +{ + critical_msg("[%s] init %d\n", __func__); + if(cam_idx == KDP_CAM_0) + { + SCU_EXTREG_MISC_SET_DPI_MUX_0_sel(1); + } + else if(cam_idx == KDP_CAM_1) + { + SCU_EXTREG_MISC_SET_DPI_MUX_1_sel(1); + } +} + +void kmdw_cam_port_init(uint32_t cam_idx) +{ + if(cam_ctx[cam_idx].cam_input_type == IMGSRC_IN_PORT_MIPI) + { + kmdw_cam_mipi_init(cam_idx); + } + else if(cam_ctx[cam_idx].cam_input_type == IMGSRC_IN_PORT_DPI) + { + kmdw_cam_dpi_init(cam_idx); + } +} + +kmdw_status_t kmdw_cam_kl520_init(void) +{ + uint32_t cam_id; + cam_msg("init\n"); + for(cam_id = 0; cam_id < CAM_ID_MAX ; cam_id++) + { + cam_ctx[cam_id].cam_input_type= (cam_id)? IMGSRC_IN_1_PORT : IMGSRC_IN_0_PORT; + if(cam_ctx[cam_id].cam_input_type != IMGSRC_IN_PORT_NONE) + { + cam_ctx[cam_id].id = cam_id; + cam_ctx[cam_id].sensor_id = (cam_id)?IMGSRC_1_SENSORID: IMGSRC_0_SENSORID; + kmdw_camera_controller_register(cam_id, &kdp520_camera_ops); + kmdw_sensor_register(cam_id, cam_ctx[cam_id].sensor_id); + kmdw_cam_port_init(cam_id); + kdrv_dpi2ahb_initialize(cam_id); + } + } + kmdw_cam_clock_init(); + + return KMDW_STATUS_OK; +} diff --git a/mdw/camera/kmdw_sensor.c b/mdw/camera/kmdw_sensor.c new file mode 100644 index 0000000..443bd55 --- /dev/null +++ b/mdw/camera/kmdw_sensor.c @@ -0,0 +1,232 @@ +/* + * KDP Sensor driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include "board.h" +#include +#include +#include +#include "kmdw_sensor.h" + +#if defined(BOARD_96) || defined(BOARD_DVP_EXAMPLE) +extern struct sensor_ops* kdev_sensor_gc2145_get_ops(void); +extern struct sensor_ops* kdev_sensor_sc132gs_get_ops(void); +#endif + +struct kmdw_sensor_s { + uint32_t inuse; + struct sensor_ops *ops; +} sensor_s[CAM_ID_MAX]; + + +kmdw_status_t kmdw_sensor_s_power(uint32_t cam_idx, uint32_t on) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->s_power == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->s_power(on); +} + +kmdw_status_t kmdw_sensor_reset(uint32_t cam_idx) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->reset == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->reset(); +} + +kmdw_status_t kmdw_sensor_s_stream(uint32_t cam_idx, uint32_t enable) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->s_stream == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->s_stream(enable); +} + +kmdw_status_t kmdw_sensor_enum_fmt(uint32_t cam_idx, uint32_t index, uint32_t *fourcc) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->enum_fmt == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->enum_fmt(index, fourcc); +} + +kmdw_status_t kmdw_sensor_set_fmt(uint32_t cam_idx, struct cam_format *format) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + if (sensor_s[cam_idx].ops->set_fmt == NULL) + return KMDW_STATUS_ERROR; + if (sensor_s[cam_idx].inuse == 0) + return KMDW_STATUS_ERROR; + return (kmdw_status_t)sensor_s[cam_idx].ops->set_fmt(format); +} + +kmdw_status_t kmdw_sensor_get_fmt(uint32_t cam_idx, struct cam_format *format) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->get_fmt == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->get_fmt(format); +} +kmdw_status_t kmdw_sensor_set_gain(uint32_t cam_idx, uint32_t gain1, uint32_t gain2) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->set_gain == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->set_gain(gain1, gain2); +} + +kmdw_status_t kmdw_sensor_set_aec(uint32_t cam_idx, struct cam_sensor_aec *aec_p) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->set_aec == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->set_aec(aec_p); +} + +kmdw_status_t kmdw_sensor_set_exp_time(uint32_t cam_idx, uint32_t gain1, uint32_t gain2) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->set_exp_time == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->set_exp_time(gain1, gain2); +} + +kmdw_status_t kmdw_sensor_get_lux(uint32_t cam_idx, uint16_t *expo, uint8_t *pre_gain, uint8_t *post_gain, uint8_t *global_gain, uint8_t *y_average) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->get_lux == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->get_lux(expo, pre_gain, post_gain, global_gain, y_average); +} + +kmdw_status_t kmdw_sensor_led_switch(uint32_t cam_idx, uint32_t on) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->led_switch == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->led_switch(on); +} + +kmdw_status_t kmdw_sensor_set_mirror(uint32_t cam_idx, uint32_t enable) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->set_mirror == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->set_mirror(enable); +} + +kmdw_status_t kmdw_sensor_set_flip(uint32_t cam_idx, uint32_t enable) +{ + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + + if (sensor_s[cam_idx].ops->set_flip == NULL) + return KMDW_STATUS_ERROR; + + return (kmdw_status_t)sensor_s[cam_idx].ops->set_flip(enable); +} + +uint32_t kmdw_sensor_get_dev_id(uint32_t cam_idx) +{ + if (cam_idx >= CAM_ID_MAX) + return 1; + + if (sensor_s[cam_idx].ops->get_dev_id == NULL) + return 1; + + return sensor_s[cam_idx].ops->get_dev_id(); +} +struct sensor_ops * kmdw_sensor_get_ops(uint32_t sensor_idx) +{ + struct sensor_ops *pops = NULL; + if (sensor_idx >= SENSOR_ID_MAX) + return NULL; + switch(sensor_idx) + { + case SENSOR_ID_HMX2056: + break; + case SENSOR_ID_OV9286: + break; + case SENSOR_ID_HMXRICA: + break; + case SENSOR_ID_GC2145: + pops = kdev_sensor_gc2145_get_ops(); + break; + case SENSOR_ID_SC132GS: + pops = kdev_sensor_sc132gs_get_ops(); + break; + default: + break; + } + return pops; +} +kmdw_status_t kmdw_sensor_register(uint32_t cam_idx, uint32_t sensor_idx) +{ + struct sensor_ops *pops; + if (cam_idx >= CAM_ID_MAX) + return KMDW_STATUS_ERROR; + if (sensor_idx >= SENSOR_ID_MAX) + return KMDW_STATUS_ERROR; + pops = kmdw_sensor_get_ops(sensor_idx); + if(pops == NULL) + return KMDW_STATUS_ERROR; + if (sensor_s[cam_idx].inuse) + return KMDW_STATUS_ERROR; + + sensor_s[cam_idx].ops = pops; + sensor_s[cam_idx].inuse = 1; + + return KMDW_STATUS_OK; +} + +kmdw_status_t kmdw_sensor_unregister(uint32_t cam_idx, struct sensor_ops *sensor_ops_p) +{ + if (cam_idx >= CAM_ID_MAX || sensor_ops_p == NULL) + return KMDW_STATUS_ERROR; + + if (!sensor_s[cam_idx].inuse) + return KMDW_STATUS_ERROR; + + sensor_s[cam_idx].ops = NULL; + sensor_s[cam_idx].inuse = 0; + + return KMDW_STATUS_OK; +} diff --git a/mdw/console/kmdw_console.c b/mdw/console/kmdw_console.c new file mode 100644 index 0000000..4a47767 --- /dev/null +++ b/mdw/console/kmdw_console.c @@ -0,0 +1,377 @@ +#include +#include +#include +#include "kmdw_console.h" +#include "project.h" + +#include "cmsis_os2.h" +#include "kdrv_cmsis_core.h" + +#define UART_RX_ECHO_GET_DBG 0 + +#define BACKSP_KEY 0x08 +#define RETURN_KEY 0x0D +#define DELETE_KEY 0x7F +#define BELL 0x07 + +#define MAX_LOG_LENGTH (256) //14bytes are necessary amount structure information "sizeof(os_message_t)" for each msg element in rtx_msgqueue.c +#define MAX_LOG_LENGTH_MSGQ (MAX_LOG_LENGTH+14) +#define DDR_LOG_BUFFER_SIZE (1 * 1024 * 1024) +#define DDR_MAX_LOG_COUNT (DDR_LOG_BUFFER_SIZE/MAX_LOG_LENGTH_MSGQ)// if using DDR +static uint32_t scpu_debug_flags = 0; + +static kdrv_uart_handle_t handle0 = MSG_PORT; +static osMessageQueueId_t log_msgq = NULL; + +print_callback _print_callback = NULL; + +#if (defined(UART_RX_ECHO_GET_DBG) && UART_RX_ECHO_GET_DBG == 1) +uint32_t buf_tmp[1024]; +char buf_tmp_char[1024]; +uint32_t uart_rx_cnt = 0; +uint32_t uart_rx_cnt_tmp = 0; +#endif + +osEventFlagsId_t uart_console_evid; +osSemaphoreId_t uart_send_mutex; + +__weak uint32_t osKernelIrqStatus(void) +{ + return false; +} + +static void _print_to_uart(const char *str) +{ + osMutexAcquire(uart_send_mutex, osWaitForever); + kdrv_uart_write(handle0, (uint8_t *)str, strlen(str)); + osMutexRelease(uart_send_mutex); +} + +kmdw_status_t kmdw_printf(const char *fmt, ...) +{ + va_list arg_ptr; + static char *buffer_s = NULL; + + if (NULL == buffer_s) + buffer_s = (char *)malloc(sizeof(char) * MAX_LOG_LENGTH); + + sprintf(buffer_s, "[%.03f] ", (float)osKernelGetTickCount() / osKernelGetTickFreq()); + int pre_len = strlen(buffer_s); + + va_start(arg_ptr, fmt); + vsnprintf(buffer_s + pre_len, MAX_LOG_LENGTH - 1, fmt, arg_ptr); + va_end(arg_ptr); + + buffer_s[MAX_LOG_LENGTH - 1] = 0; // just in case + + if (log_msgq == NULL || osThreadGetId() == NULL) + _print_to_uart(buffer_s); + else + { + osStatus_t oss = osMessageQueuePut(log_msgq, buffer_s, NULL, 0); + if (oss != osOK) + { + //_print_to_uart("[logger] enqueue log1 failed\n"); + return KMDW_STATUS_ERROR; + } + } + + return KMDW_STATUS_OK; +} + +kmdw_status_t kmdw_level_printf(int level, const char *fmt, ...) +{ + static char *buffer_s = NULL; + uint32_t lvl = kmdw_console_get_log_level_scpu(); + lvl >>= 16; + + if ((level == LOG_PROFILE && level == lvl) || (level > 0 && level <= lvl)) + { + va_list arg_ptr; + + if (NULL == buffer_s) + buffer_s = (char *)malloc(sizeof(char) * MAX_LOG_LENGTH); + + sprintf(buffer_s, "[%.03f] ", (float)osKernelGetTickCount() / osKernelGetTickFreq()); + int pre_len = strlen(buffer_s); + + va_start(arg_ptr, fmt); + vsnprintf(buffer_s + pre_len, MAX_LOG_LENGTH - 1, fmt, arg_ptr); + va_end(arg_ptr); + + buffer_s[MAX_LOG_LENGTH - 1] = 0; // just in case + + if (log_msgq == NULL || osThreadGetId() == NULL) + _print_to_uart(buffer_s); + else + { + osStatus_t oss = osMessageQueuePut(log_msgq, buffer_s, NULL, 0); + if (oss != osOK) + { + //_print_to_uart("[logger] enqueue log failed\n"); + return KMDW_STATUS_ERROR; + } + } + } + + return KMDW_STATUS_OK; +} + +void logger_thread(void *arg) +{ + uint8_t log[MAX_LOG_LENGTH]; + + void *log_pool = (void *)kmdw_ddr_reserve(DDR_LOG_BUFFER_SIZE); + + if (log_pool) + { + osMessageQueueAttr_t msgq_attr; + memset(&msgq_attr, 0, sizeof(msgq_attr)); + msgq_attr.mq_mem = log_pool; + msgq_attr.mq_size = DDR_LOG_BUFFER_SIZE; + memset(log_pool, 0, DDR_LOG_BUFFER_SIZE); + + log_msgq = osMessageQueueNew(DDR_MAX_LOG_COUNT, MAX_LOG_LENGTH, &msgq_attr); + if (log_msgq == NULL) + { + printf("[logger] osMessageQueueNew failed\n"); + } + } + while (1) + { + osStatus_t oss = osMessageQueueGet(log_msgq, &log[0], NULL, osWaitForever); + if (oss != osOK) + { + _print_to_uart("[logger] dequeue log failed\n"); + // if (_print_callback) + // _print_callback("[logger] dequeue log failed\n"); + continue; + } + + _print_to_uart((const char *)log); + + if (_print_callback) + _print_callback((const char *)log); + } +} + +__weak uint32_t kmdw_ddr_reserve(uint32_t numbyte) +{ + return 0; +} + +void kmdw_console_hook_callback(print_callback print_cb) +{ + _print_callback = print_cb; +} + +char kmdw_console_getc(void) +{ + char c; + kdrv_uart_read(handle0, (uint8_t *)&c, 1); + return c; +} + +void kmdw_console_putc(char Ch) +{ + char cc; + + if (Ch != '\0') + { + cc = Ch; + kdrv_uart_write(handle0, (uint8_t *)&cc, 1); + } + + if (Ch == '\n') + { + cc = '\r'; + kdrv_uart_write(handle0, (uint8_t *)&cc, 1); + } +} + +void kmdw_console_puts(char *str) +{ + char *cp; + for (cp = str; *cp != 0; cp++) + kmdw_console_putc(*cp); +} + +int kmdw_console_echo_gets(char *buf, int len) +{ + char *cp; + char data[MAX_FIFO_RX]; + uint32_t count; + uint32_t exit_while = 0; + count = 0; + cp = buf; + len = 1024; + #if (defined(UART_RX_ECHO_GET_DBG) && UART_RX_ECHO_GET_DBG == 1) + uart_rx_cnt=0; + memset(buf_tmp, 0, sizeof(buf_tmp)); + memset(buf_tmp_char, 0xff, sizeof(buf_tmp_char)); + #endif + do + { + memset(data, 0, MAX_FIFO_RX); + kdrv_uart_get_char(handle0, data); + //kdrv_uart_read(handle0, (uint8_t*)data, 1); + for(uint32_t i = 0; i< gDrvCtx.uart_dev[handle0]->info.xfer.rx_cnt; i++) + { + + #if (defined(UART_RX_ECHO_GET_DBG) && UART_RX_ECHO_GET_DBG == 1) + buf_tmp[uart_rx_cnt] = uart_rx_cnt; + buf_tmp_char[uart_rx_cnt] = data[i]; + uart_rx_cnt++; + #endif + if(data[i] == BACKSP_KEY || data[i] == DELETE_KEY) + { + if ((count > 0) && (count < len)) + { + count--; + *(--cp) = '\0'; + //kmdw_console_puts("\b \b"); + } + break; + } + if(data[i] == RETURN_KEY) + { + if (count < len) + { + *cp = '\0'; + kmdw_console_putc('\n'); + } + exit_while = 1; + break; + } + else + { + if(count < len) + { + *cp = (char)data[i]; + cp++; + count++; + kmdw_console_putc(data[i]); + } + } + } + } while (exit_while == 0); + #if (defined(UART_RX_ECHO_GET_DBG) && UART_RX_ECHO_GET_DBG == 1) + uart_rx_cnt_tmp = uart_rx_cnt; + #endif + return (count); +} + +__weak void kdrv_ncpu_set_scpu_debug_lvl(uint32_t lvl) +{ +} + +__weak void kdrv_ncpu_set_ncpu_debug_lvl(uint32_t lvl) +{ +} + +void kmdw_console_set_log_level_scpu(uint32_t level) +{ + scpu_debug_flags = (scpu_debug_flags & ~0x000F0000) | (((level) << 16) & 0x000F0000); + kdrv_ncpu_set_scpu_debug_lvl(level); +} + +uint32_t kmdw_console_get_log_level_scpu(void) +{ + return scpu_debug_flags; +} + +void kmdw_console_set_log_level_ncpu(uint32_t level) +{ + kdrv_ncpu_set_ncpu_debug_lvl(level); +} + +void kmdw_console_callback(uint32_t event) +{ + + if(osKernelGetState() == osKernelRunning && uart_console_evid != NULL) + { + if (event & UART_RX_DONE) + { + osEventFlagsSet(uart_console_evid, UART_RX_DONE); + } + if (event & UART_TX_DONE) + { + osEventFlagsSet(uart_console_evid, UART_TX_DONE); + } + if (event & UART_RX_TIMEOUT) + { + osEventFlagsSet(uart_console_evid, UART_RX_DONE); + } + } + if (event & UART_REVEIVE_COMPLETE) + { + kmdw_console_wait_rx_done(MSG_PORT); + }; + if (event & UART_TRANSFER_COMPLETE) + { + kmdw_console_wait_tx_done(MSG_PORT); + }; +} + +void kmdw_console_wait_rx_done(kdrv_uart_handle_t handle) +{ + if(osKernelGetState() == osKernelRunning && uart_console_evid != NULL) + { + int32_t evt_flg = osEventFlagsWait(uart_console_evid, UART_RX_DONE, osFlagsWaitAny , osWaitForever); + } + else + { + while((uart_get_status((DRVUART_PORT)handle) & SERIAL_LSR_DR) != SERIAL_LSR_DR) + { + if(osKernelIrqStatus() == false) + __WFI(); + else + __NOP(); + } + } +} + +void kmdw_console_wait_tx_done(kdrv_uart_handle_t handle) +{ + if(osKernelIrqStatus() == true) + { + while((uart_get_status((DRVUART_PORT)handle) & SERIAL_LSR_THRE) != SERIAL_LSR_THRE) + { + __NOP(); + } + gDrvCtx.uart_dev[handle0]->info.status.tx_busy = 0; + } + else if(osKernelGetState() == osKernelRunning && uart_console_evid != NULL) + { + int32_t evt_flg = osEventFlagsWait(uart_console_evid, UART_TX_DONE, osFlagsWaitAny , osWaitForever); + } + else + { + while((uart_get_status((DRVUART_PORT)handle) & SERIAL_LSR_THRE) != SERIAL_LSR_THRE) + { + __WFI(); + } + } +} + +kmdw_status_t kmdw_uart_console_init(uint8_t uart_dev, uint32_t baudrate) +{ + kdrv_status_t sts = kdrv_uart_console_init(uart_dev, baudrate, kmdw_console_callback);//NULL);// + + if (sts != KDRV_STATUS_OK) + return KMDW_STATUS_ERROR; + + uart_send_mutex = osMutexNew(NULL); // for uart send usage + uart_console_evid = osEventFlagsNew(0); + + if(uart_console_evid == NULL) + return KMDW_STATUS_ERROR; + + return KMDW_STATUS_OK; +} + + +kmdw_status_t kmdw_uart_uninitialize(void) +{ + return KMDW_STATUS_OK; +} diff --git a/mdw/dfu/kmdw_dfu.c b/mdw/dfu/kmdw_dfu.c new file mode 100644 index 0000000..2c92d4b --- /dev/null +++ b/mdw/dfu/kmdw_dfu.c @@ -0,0 +1,987 @@ +#include +#include "project.h" +#include "base.h" +#include "kmdw_dfu.h" +#include "kmdw_utils_crc.h" +#include "kdev_flash.h" +#include "kmdw_model.h" +#include "kmdw_console.h" +#include "kdrv_clock.h" +#include "kmdw_power_manager.h" +#include "kdp_system.h" +#include "kdrv_cmsis_core.h" + +#define VERIFY_BLK_SZ FLASH_MINI_BLOCK_SIZE //0x1000 + +#define MODEL_INFO_FLASH_ADDR FLASH_MODEL_FW_INFO_ADDR +#define MODEL_ALL_BIN_FLASH_ADDR FLASH_MODEL_ALL_ADDR + +#define BOOT_STATE_CONFIRMED 0x1 +#define BOOT_STATE_FIRST_BOOT 0x2 +#define BOOT_STATE_POST_FIRST_BOOT 0x4 +#define BOOT_STATE_NOT_CONFIRMED 0x8 + +#define MAX_BOOT_SEQ 0x7ffffff0 + +typedef struct { + u32 partition_id; + u32 seq; + u32 flag; +} dfu_boot_cfg_item_t; + +typedef struct { + dfu_boot_cfg_item_t scpu_cfg; + dfu_boot_cfg_item_t ncpu_cfg; +} dfu_boot_cfg_t; + +// Initial buffer for boot configuration +static u8 init_ver_buf[0x40 + sizeof(dfu_boot_cfg_t)]; + +/* tmp buffer for content verification + * passed by caller, length should be at least VERIFY_BLK_SZ */ +static u8 *tmp_ver_buf = init_ver_buf; +static FnReadData fn_read_data = NULL; + +/* ############################ + * ## static functions ## + * ############################ */ + +static dfu_boot_cfg_t boot_cfg_0, boot_cfg_1; + +int flashing; + +static int flash_wait_ready(int timeout_ms) +{ + kdev_flash_status_t flash_status; + int i; + + for (i = 0; i < timeout_ms; i++) { + flash_status = kdev_flash_get_status(); + if (flash_status.busy == 0) break; + kdrv_delay_us(1*1000); + } + if (i == timeout_ms) i = -1; // we have timed out + return i; +} + +static int dfu_update_sleep(enum kmdw_power_manager_device_id dev_id) +{ + while (flashing == 1) { + err_msg("dfu_update_sleep: stop for flashing.\n"); + osThreadFlagsWait(BIT27, osFlagsWaitAll, osWaitForever); + } + err_msg("dfu_update_sleep: ok\n"); + + return 0; +} + +static int dfu_update_deep_sleep(enum kmdw_power_manager_device_id dev_id) +{ + while (flashing == 1) { + err_msg("dfu_update_deep_sleep: stop for flashing.\n"); + osThreadFlagsWait(BIT27, osFlagsWaitAll, osWaitForever); + } + err_msg("dfu_update_deep_sleep: ok\n"); + + return 0; +} + +/* +Compare flash content with buffer content, the size shall be more than 4k, + because small block (<4k) was verified already, here is to verify the + consistency/integrity among 4k blocks +Return: + 0 - success + -1 - fail +*/ + +static int dfu_post_flash_verify_4kblock(u32 flash_addr, u32 size, u8 *pbuf) +{ + int remainder, loop, i, ret, len; + + loop = size / VERIFY_BLK_SZ; + if (size % VERIFY_BLK_SZ) + loop += 1; + remainder = size; + u8* flash_sector_check = tmp_ver_buf + 0x40; + + for (i = 0; i < loop; i++) { + len = remainder > VERIFY_BLK_SZ ? VERIFY_BLK_SZ : remainder; + kdev_flash_readdata((flash_addr + i * VERIFY_BLK_SZ) & 0xFFFFF000, + flash_sector_check, len); // read the new sector + ret = flash_wait_ready(300); + if (ret == -1) + { + err_msg("Flash read failure, timeout\n"); + return -1; + } + + ret = memcmp(flash_sector_check, pbuf + i * VERIFY_BLK_SZ, len); + if (ret != 0) + { + err_msg("Found diff, flash failed\n"); + return -1; + } + remainder -= len; + } + + return 0; +} + +/* +Write memory data to flash, the size is 4k blocks (i.e. n*4k) + +Return: + 0 - success + -1 - fail +*/ +static int dfu_mem_to_flash_4k_blocks(u32 mem_addr, u32 flash_addr, u32 size) +{ + int ret; + + if (mem_addr & 0x1f != 0) + { + err_msg("memory address does not align to 32bit boundary"); + return -1; + } + + if (flash_addr & 0x1f != 0) + { + err_msg("flash address does not align to 32bit boundary"); + return -1; + } + + /* erase flash sectors firstly */ + + u16 sect_num = size / VERIFY_BLK_SZ; /* sector size = 4K */ + if (size % VERIFY_BLK_SZ) + sect_num += 1; + u32 offset = 0; + u32 length = size; + u32 len = 0; + for (int sect = 0; sect < sect_num; sect++) + { + len = length > VERIFY_BLK_SZ ? VERIFY_BLK_SZ : length; + kdev_flash_erase_sector(flash_addr + offset); + ret = flash_wait_ready(300); // wait for the erase operation to complete + if (ret < 0) { + dbg_msg("Erase Flash Sector Timeout\n"); + } + + kdev_flash_programdata((uint32_t)(flash_addr + offset), (void *)(mem_addr + offset), len); + + offset += len; + length -= len; + } + + kdrv_delay_us(500 * 1000); + return 0; +} + +/* +Write memory data to flash, the size is less than 4k + +Return: + 0 - success + -1 - fail +*/ +static int dfu_mem_to_flash_small_block(u32 mem_addr, u32 flash_addr, u32 size) +{ + int ret; + + /* validate parameters */ + if (size >= VERIFY_BLK_SZ) + { + err_msg("Wrong size, bigger than 4K"); + return -1; + } + + if (mem_addr & 0x1f != 0) + { + err_msg("memory address does not align to 32bit boundary"); + return -1; + } + + if (flash_addr & 0x1f != 0) + { + err_msg("flash address does not align to 32bit boundary"); + return -1; + } + + /* erase flash sectors firstly */ + + kdev_flash_erase_sector(flash_addr); + ret = flash_wait_ready(300); // wait for the erase operation to complete + if (ret < 0) { + dbg_msg("Erase Flash Sector Timeout\n"); + } + + kdev_flash_programdata(flash_addr, (void *)mem_addr, size); + flash_wait_ready(500); + + /* read back for confirmation*/ + u8* flash_sector_check = tmp_ver_buf + 0x40; + kdev_flash_readdata(flash_addr, flash_sector_check, size); + ret = flash_wait_ready(300); + if (memcmp((void *)mem_addr, (void *)flash_sector_check, size)) { + err_msg("Flash readback verification fail at flash addr=%x\n", flash_addr); + return -1; + } + + kdrv_delay_us(200 * 1000); + + return 0; +} + +static void dfu_init_partition_boot_cfg() +{ + int ret; + boot_cfg_0.scpu_cfg.partition_id = 0; + boot_cfg_0.scpu_cfg.seq = 1; + boot_cfg_0.scpu_cfg.flag = BOOT_STATE_CONFIRMED; + + boot_cfg_0.ncpu_cfg.partition_id = 0; + boot_cfg_0.ncpu_cfg.seq = 1; + boot_cfg_0.ncpu_cfg.flag = BOOT_STATE_CONFIRMED; + + boot_cfg_1.scpu_cfg.partition_id = 1; + boot_cfg_1.scpu_cfg.seq = 0; + boot_cfg_1.scpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + + boot_cfg_1.ncpu_cfg.partition_id = 1; + boot_cfg_1.ncpu_cfg.seq = 0; + boot_cfg_1.ncpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + + kdev_flash_erase_sector(PARTITION_0_CFG_START_IN_FLASH); + + ret = flash_wait_ready(200); + if (ret < 0) { + err_msg("Error: Erase Flash Sector Timeout\n"); + } + + kdev_flash_erase_sector(PARTITION_1_CFG_START_IN_FLASH); + + ret = flash_wait_ready(200); + if (ret < 0) { + err_msg("Error: Erase Flash Sector Timeout\n"); + } + + kdev_flash_programdata(PARTITION_0_CFG_START_IN_FLASH, &boot_cfg_0, 32); + ret = flash_wait_ready(200); + if (ret < 0) { + err_msg("Error: Flash partition 0 config Timeout\n"); + } + + kdev_flash_programdata(PARTITION_1_CFG_START_IN_FLASH, &boot_cfg_1, 32); + ret = flash_wait_ready(200); + if (ret < 0) { + err_msg("Error: Flash partition 1 config Timeout\n"); + } + +} + +static void dfu_pre_update() +{ + NVIC_DisableIRQ(UART_FTUART010_0_IRQ); //UART0 + NVIC_DisableIRQ(UART_FTUART010_1_IRQ); //UART1 + NVIC_DisableIRQ(UART_FTUART010_1_1_IRQ); //UART2 + NVIC_DisableIRQ(UART_FTUART010_1_2_IRQ); //UART3 + NVIC_DisableIRQ(UART_FTUART010_1_3_IRQ); //UART4 + NVIC_DisableIRQ(NPU_NPU_IRQ); //NPU +} + +static void dfu_update_abort(u32 reload_flag) +{ + if (reload_flag) + kmdw_model_refresh_models(); // reload all the models again + NVIC_EnableIRQ(UART_FTUART010_0_IRQ); //UART0 + NVIC_EnableIRQ(UART_FTUART010_1_IRQ); //UART1 + NVIC_EnableIRQ(UART_FTUART010_1_1_IRQ); //UART2 + NVIC_EnableIRQ(UART_FTUART010_1_2_IRQ); //UART3 + NVIC_EnableIRQ(UART_FTUART010_1_3_IRQ); //UART4 + NVIC_EnableIRQ(NPU_NPU_IRQ); //NPU +} + +/* ############################ + * ## public functions ## + * ############################ */ + +int kmdw_dfu_init(u8 *tmp_buf, FnReadData fn_read) +{ + static int flash_checked = 0; + int ret; + + if (tmp_buf) + tmp_ver_buf = tmp_buf; + if (fn_read) + fn_read_data = fn_read; + + if (flash_checked) + return 0; + flash_checked = 1; + + struct kmdw_power_manager_s pms = { + .sleep = dfu_update_sleep, + .deep_sleep = dfu_update_deep_sleep, + }; + + /* read flash to mem */ + + kdev_flash_readdata(PARTITION_0_CFG_START_IN_FLASH, &boot_cfg_0, sizeof(boot_cfg_0)); + flash_wait_ready(300); + + kdev_flash_readdata(PARTITION_1_CFG_START_IN_FLASH, &boot_cfg_1, sizeof(boot_cfg_1)); + flash_wait_ready(300); + + if ((boot_cfg_0.scpu_cfg.flag == 0xffffffff) && (boot_cfg_1.scpu_cfg.flag == 0xffffffff)) { + ret = -1; + goto exit; + } + + if ((boot_cfg_0.scpu_cfg.flag == BOOT_STATE_FIRST_BOOT) || + (boot_cfg_0.ncpu_cfg.flag == BOOT_STATE_FIRST_BOOT) || + (boot_cfg_1.scpu_cfg.flag == BOOT_STATE_FIRST_BOOT) || + (boot_cfg_1.ncpu_cfg.flag == BOOT_STATE_FIRST_BOOT)) { + err_msg("Error: wrong state, BOOT_STATE_FIRST_BOOT shall not be here\n"); + ret = -1; + goto exit; + } + + /* determine if necessary to read flash */ + + if ((boot_cfg_0.scpu_cfg.flag != BOOT_STATE_POST_FIRST_BOOT) && + (boot_cfg_0.ncpu_cfg.flag != BOOT_STATE_POST_FIRST_BOOT) && + (boot_cfg_1.scpu_cfg.flag != BOOT_STATE_POST_FIRST_BOOT) && + (boot_cfg_1.ncpu_cfg.flag != BOOT_STATE_POST_FIRST_BOOT)) { + + ret = 0; + goto exit; + } + + if (boot_cfg_0.scpu_cfg.flag == BOOT_STATE_POST_FIRST_BOOT) { + boot_cfg_0.scpu_cfg.flag = BOOT_STATE_CONFIRMED; + if(boot_cfg_1.scpu_cfg.flag == BOOT_STATE_CONFIRMED) { + boot_cfg_1.scpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + } + err_msg("SCPU partition 0 was confirmed\n"); + + } + + if (boot_cfg_0.ncpu_cfg.flag == BOOT_STATE_POST_FIRST_BOOT) { + boot_cfg_0.ncpu_cfg.flag = BOOT_STATE_CONFIRMED; + if(boot_cfg_1.ncpu_cfg.flag == BOOT_STATE_CONFIRMED) { + boot_cfg_1.ncpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + } + err_msg("NCPU partition 0 was confirmed\n"); + } + + if (boot_cfg_1.scpu_cfg.flag == BOOT_STATE_POST_FIRST_BOOT) { + boot_cfg_1.scpu_cfg.flag = BOOT_STATE_CONFIRMED; + if(boot_cfg_0.scpu_cfg.flag == BOOT_STATE_CONFIRMED) { + boot_cfg_0.scpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + } + err_msg("SCPU partition 1 was confirmed\n"); + } + + if (boot_cfg_1.ncpu_cfg.flag == BOOT_STATE_POST_FIRST_BOOT) { + boot_cfg_1.ncpu_cfg.flag = BOOT_STATE_CONFIRMED; + if(boot_cfg_0.ncpu_cfg.flag == BOOT_STATE_CONFIRMED) { + boot_cfg_0.ncpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + } + err_msg("NCPU partition 1 was confirmed\n"); + } + + /* write back to flash */ + ret = dfu_mem_to_flash_small_block((u32)&boot_cfg_0, PARTITION_0_CFG_START_IN_FLASH, sizeof(boot_cfg_0)); + if (ret == -1) + { + err_msg("Flash write fail on %x\n", PARTITION_0_CFG_START_IN_FLASH); + ret = MSG_FLASH_FAIL; + goto exit; + } + + ret = dfu_mem_to_flash_small_block((u32)&boot_cfg_1, PARTITION_1_CFG_START_IN_FLASH, sizeof(boot_cfg_1)); + if (ret == -1) + { + err_msg("Flash write fail on %x\n", PARTITION_1_CFG_START_IN_FLASH); + ret = MSG_FLASH_FAIL; + } else { + ret = 0; + } + +exit: + kmdw_power_manager_register(KMDW_POWER_MANAGER_DEVICE_DFU_UPDATE, &pms); + + return ret; +} + +int kmdw_dfu_get_active_scpu_partition() +{ + kdev_flash_readdata(PARTITION_0_CFG_START_IN_FLASH, &boot_cfg_0, sizeof(boot_cfg_0)); + flash_wait_ready(300); + kdev_flash_readdata(PARTITION_1_CFG_START_IN_FLASH, &boot_cfg_1, sizeof(boot_cfg_1)); + flash_wait_ready(300); + + if ((boot_cfg_0.scpu_cfg.flag == 0xffffffff) && (boot_cfg_1.scpu_cfg.flag == 0xffffffff)) { + // no config data is there, need to create them for partition 0/1 + dfu_init_partition_boot_cfg(); + return 0; + } + + if (boot_cfg_0.scpu_cfg.flag & boot_cfg_1.scpu_cfg.flag & BOOT_STATE_CONFIRMED) + { + err_msg("Critical Error: 2 active SCPU boot config\n"); + return -1; + } + + if ((boot_cfg_0.scpu_cfg.partition_id == boot_cfg_1.scpu_cfg.partition_id) + && (boot_cfg_0.scpu_cfg.seq == boot_cfg_1.scpu_cfg.seq)) + { + // no config data is there, need to create them for partition 0/1 + dfu_init_partition_boot_cfg(); + return 0; + } + + if ((boot_cfg_0.scpu_cfg.flag & BOOT_STATE_CONFIRMED) == BOOT_STATE_CONFIRMED) + return 0; + + if ((boot_cfg_1.scpu_cfg.flag & BOOT_STATE_CONFIRMED) == BOOT_STATE_CONFIRMED) + return 1; + return 0; +} + +int kmdw_dfu_get_active_ncpu_partition() +{ + kdev_flash_readdata(PARTITION_0_CFG_START_IN_FLASH, &boot_cfg_0, sizeof(boot_cfg_0)); + flash_wait_ready(300); + + kdev_flash_readdata(PARTITION_1_CFG_START_IN_FLASH, &boot_cfg_1, sizeof(boot_cfg_1)); + flash_wait_ready(300); + + if ((boot_cfg_0.ncpu_cfg.flag == 0xffffffff) && (boot_cfg_1.ncpu_cfg.flag == 0xffffffff)) { + // no config data is there, need to create them for partition 0/1 + dfu_init_partition_boot_cfg(); + return 0; + } + + if (boot_cfg_0.ncpu_cfg.flag & boot_cfg_1.ncpu_cfg.flag & BOOT_STATE_CONFIRMED) + { + err_msg("Critical Error: 2 active NCPU boot config\n"); + return -1; + } + + if ((boot_cfg_0.ncpu_cfg.partition_id == boot_cfg_1.ncpu_cfg.partition_id) && + (boot_cfg_0.ncpu_cfg.seq == boot_cfg_1.ncpu_cfg.seq)) + { + // no config data is there, need to create them for partition 0/1 + dfu_init_partition_boot_cfg(); + return 0; + } + + if ((boot_cfg_0.ncpu_cfg.flag & BOOT_STATE_CONFIRMED) == BOOT_STATE_CONFIRMED) + return 0; + + if ((boot_cfg_1.ncpu_cfg.flag & BOOT_STATE_CONFIRMED) == BOOT_STATE_CONFIRMED) + return 1; + return 0; +} + +int kmdw_dfu_update_scpu() +{ + int ret; + u8 *pBase; + u32 local_sum32, remote_sum32; + u8 pre_active_partition; + u32 flash_cfg_addr, flash_data_addr; + dfu_boot_cfg_t dfu_cfg; + u32 seq; + + flashing = 1; + err_msg("kmdw_dfu_update_scpu: flashing ...\n"); + + dfu_pre_update(); + + pBase = (u8 *)DDR_BEGIN; + memset(pBase, 0, SCPU_IMAGE_SIZE); + ret = fn_read_data((u32)pBase, SCPU_IMAGE_SIZE); + if (ret == SCPU_IMAGE_SIZE) + { + local_sum32 = kmdw_utils_crc_gen_sum32(pBase, SCPU_IMAGE_SIZE - 4); + remote_sum32 = *(u32 *)(pBase + SCPU_IMAGE_SIZE - 4); + if (local_sum32 != remote_sum32) { + ret = MSG_AUTH_FAIL; + goto exit; + } + + } + else { + ret = MSG_DATA_ERROR; + goto exit; + } + + pre_active_partition = kmdw_dfu_get_active_scpu_partition(); + if (pre_active_partition == 0) { + // active partition is 0, flash to partition 1 + flash_cfg_addr = PARTITION_1_CFG_START_IN_FLASH; + flash_data_addr = SCPU_PARTITION1_START_IN_FLASH; + } + else if(pre_active_partition == 1){ + // active partition is 1, flash to partition 0 + flash_cfg_addr = PARTITION_0_CFG_START_IN_FLASH; + flash_data_addr = SCPU_PARTITION0_START_IN_FLASH; + } else { + ret = MSG_FLASH_FAIL; + goto exit; + } + + // flash data + ret = dfu_mem_to_flash_4k_blocks((u32)pBase, (u32)flash_data_addr, SCPU_IMAGE_SIZE); + if (ret == -1) + { + ret = MSG_FLASH_FAIL; + goto exit; + } + + ret = dfu_post_flash_verify_4kblock(flash_data_addr, SCPU_IMAGE_SIZE, pBase); + if (ret != 0) { + err_msg("Error: post flash verification failed\n"); + ret = MSG_FLASH_FAIL; + goto exit; + } + + // update boot cfg + + if (pre_active_partition == 0) { + seq = MAX(boot_cfg_0.scpu_cfg.seq, boot_cfg_1.scpu_cfg.seq); + + if(seq > MAX_BOOT_SEQ){ + boot_cfg_0.scpu_cfg.seq = 0; + boot_cfg_1.scpu_cfg.seq = 1; + } else { + boot_cfg_1.scpu_cfg.seq = seq + 1; + } + boot_cfg_1.scpu_cfg.flag = BOOT_STATE_FIRST_BOOT; + dfu_cfg = boot_cfg_1; + } + else { + seq = MAX(boot_cfg_0.scpu_cfg.seq, boot_cfg_1.scpu_cfg.seq); + + if(seq > MAX_BOOT_SEQ){ + boot_cfg_0.scpu_cfg.seq = 1; + boot_cfg_1.scpu_cfg.seq = 0; + } else { + boot_cfg_0.scpu_cfg.seq = seq + 1; + } + boot_cfg_0.scpu_cfg.flag = BOOT_STATE_FIRST_BOOT; + dfu_cfg = boot_cfg_0; + } + + ret = dfu_mem_to_flash_small_block((u32)&dfu_cfg, flash_cfg_addr, sizeof(dfu_cfg)); + + kdev_flash_readdata(PARTITION_0_CFG_START_IN_FLASH, &boot_cfg_0, sizeof(boot_cfg_0)); + flash_wait_ready(300); + + kdev_flash_readdata(PARTITION_1_CFG_START_IN_FLASH, &boot_cfg_1, sizeof(boot_cfg_1)); + flash_wait_ready(300); + + if (pre_active_partition == 0) { + ret = memcmp(&boot_cfg_1, &dfu_cfg, sizeof(dfu_cfg)); + } + else { + ret = memcmp(&boot_cfg_0, &dfu_cfg, sizeof(dfu_cfg)); + } + + if (ret == -1) + ret = MSG_FLASH_FAIL; + else + ret = SUCCESS; + +exit: + err_msg("kmdw_dfu_update_scpu: flashing done\n"); + flashing = 0; + return ret; +} + +int kmdw_dfu_update_ncpu() +{ + int ret; + u8 *pBase; + u32 local_sum32, remote_sum32; + u8 pre_active_partition; + u32 flash_cfg_addr, flash_data_addr; + dfu_boot_cfg_t dfu_cfg; + u32 seq; + + flashing = 1; + err_msg("kmdw_dfu_update_ncpu: flashing ...\n"); + + dfu_pre_update(); + + pBase = (u8 *)DDR_BEGIN; + memset(pBase, 0, NCPU_IMAGE_SIZE); + ret = fn_read_data((u32)pBase, (u32)NCPU_IMAGE_SIZE); + if (ret == NCPU_IMAGE_SIZE) + { + local_sum32 = kmdw_utils_crc_gen_sum32(pBase, NCPU_IMAGE_SIZE - 4); + remote_sum32 = *(u32 *)(pBase + NCPU_IMAGE_SIZE - 4); + if (local_sum32 != remote_sum32) { + ret = MSG_AUTH_FAIL; + goto exit; + } + + } + else { + ret = MSG_DATA_ERROR; + goto exit; + } + + pre_active_partition = kmdw_dfu_get_active_ncpu_partition(); + if (pre_active_partition == 0) { + // active partition is 0, flash to partition 1 + flash_cfg_addr = PARTITION_1_CFG_START_IN_FLASH; + flash_data_addr = NCPU_PARTITION1_START_IN_FLASH; + } + else if (pre_active_partition == 1){ + // active partition is 1, flash to partition 0 + flash_cfg_addr = PARTITION_0_CFG_START_IN_FLASH; + flash_data_addr = NCPU_PARTITION0_START_IN_FLASH; + } else { + ret = MSG_FLASH_FAIL; + goto exit; + } + + // flash data + ret = dfu_mem_to_flash_4k_blocks((u32)pBase, (u32)flash_data_addr, NCPU_IMAGE_SIZE); + if (ret == -1) + { + ret = MSG_FLASH_FAIL; + goto exit; + } + + ret = dfu_post_flash_verify_4kblock(flash_data_addr, NCPU_IMAGE_SIZE, pBase); + if (ret != 0) { + err_msg("Error: post flash verification failed\n"); + ret = MSG_FLASH_FAIL; + goto exit; + } + + // update boot cfg + + if (pre_active_partition == 0) { + seq = MAX(boot_cfg_0.ncpu_cfg.seq, boot_cfg_1.ncpu_cfg.seq); + + if(seq > MAX_BOOT_SEQ){ + boot_cfg_0.ncpu_cfg.seq = 0; + boot_cfg_1.ncpu_cfg.seq = 1; + } else { + boot_cfg_1.ncpu_cfg.seq = seq + 1; + } + + boot_cfg_1.ncpu_cfg.flag = BOOT_STATE_FIRST_BOOT; + dfu_cfg = boot_cfg_1; + } + else { + seq = MAX(boot_cfg_0.ncpu_cfg.seq, boot_cfg_1.ncpu_cfg.seq); + + if(seq > MAX_BOOT_SEQ){ + boot_cfg_0.ncpu_cfg.seq = 1; + boot_cfg_1.ncpu_cfg.seq = 0; + } else { + boot_cfg_0.ncpu_cfg.seq = seq + 1; + } + + boot_cfg_0.ncpu_cfg.flag = BOOT_STATE_FIRST_BOOT; + dfu_cfg = boot_cfg_0; + } + + ret = dfu_mem_to_flash_small_block((u32)&dfu_cfg, flash_cfg_addr, sizeof(dfu_cfg)); + if (ret == -1) + { + ret = MSG_FLASH_FAIL; + goto exit; + } + + kdev_flash_readdata(PARTITION_0_CFG_START_IN_FLASH, &boot_cfg_0, sizeof(boot_cfg_0)); + flash_wait_ready(300); + + kdev_flash_readdata(PARTITION_1_CFG_START_IN_FLASH, &boot_cfg_1, sizeof(boot_cfg_1)); + flash_wait_ready(300); + + if (pre_active_partition == 0) { + ret = memcmp(&boot_cfg_1, &dfu_cfg, sizeof(dfu_cfg)); + } + else { + ret = memcmp(&boot_cfg_0, &dfu_cfg, sizeof(dfu_cfg)); + } + + if (ret != 0) { + err_msg("Error: partition config read back compare fail\n"); + ret = MSG_FLASH_FAIL; + } else { + ret = SUCCESS; + } + +exit: + err_msg("kmdw_dfu_update_ncpu: flashing done\n"); + flashing = 0; + return ret; +} + +int kmdw_dfu_update_model(u32 info_size, u32 model_size) +{ + u32 sum32_download, sum32_embedded; + u32 ddr_buf; + int ret; + u32 size; + + info_size >>= 16; + + if (info_size == 0) { + // non NEF + size = model_size; + } else { + // NEF + size = info_size + model_size; + } + + err_msg("kmdw_dfu_update_model: flashing ...\n"); + dbg_msg("kmdw_dfu_update_model: size: %d %d\n", info_size, model_size); + dfu_pre_update(); + + ddr_buf = DDR_BEGIN; + ret = fn_read_data(ddr_buf, size); + if (ret == size) { + if (info_size == 0) { + // non NEF + sum32_embedded = *(u32 *)(ddr_buf + size - 4); + sum32_download = kmdw_utils_crc_gen_sum32((u8 *)ddr_buf, size - 4); + } else { + // NEF + u32 model_count; + kmdw_model_fw_info_t *info_p = (kmdw_model_fw_info_t *)ddr_buf; + kmdw_model_fw_info_ext_t *info2_p; + + model_count = info_p->model_count; + dbg_msg("kmdw_dfu_update_model: model count is %d\n", model_count); + info2_p = (kmdw_model_fw_info_ext_t *)(ddr_buf + sizeof(uint32_t) + model_count * sizeof(struct kdp_model_s)); + sum32_embedded = info2_p->model_checksum; + sum32_download = sum32_embedded; // TODO: use crc32 algorithm + dbg_msg("kmdw_dfu_update_model: checksum 0x%X\n", sum32_download); + } + + if (sum32_embedded != sum32_download) { + err_msg("kmdw_dfu_update_model: checksum error 0x%X : 0x%X\n", sum32_embedded, sum32_download); + dfu_update_abort(1); + return MSG_AUTH_FAIL; + } + } else { + dfu_update_abort(1); + return MSG_DATA_ERROR; + } + + if (info_size == 0) { + // flash model_dfu.bin + ret = dfu_mem_to_flash_4k_blocks(ddr_buf, MODEL_INFO_FLASH_ADDR, size); + if (ret == -1) { + err_msg("Error: flash model_dfu.bin failed %d\n", ret); + return MSG_FLASH_FAIL; + } + + ret = dfu_post_flash_verify_4kblock((u32)MODEL_INFO_FLASH_ADDR, size, + (u8 *)ddr_buf); + if (ret != 0) { + err_msg("Error: verify model_dfu.bin failed %d\n", ret); + return MSG_FLASH_FAIL; + } + } else { + // check flash space + if ( model_size > (FLASH_END_ADDR - MODEL_ALL_BIN_FLASH_ADDR) ) { + err_msg("Error: Not enough flash space\n"); + return MSG_FLASH_NO_SPACE; + } + + // flash fw_info.bin + ret = dfu_mem_to_flash_4k_blocks(ddr_buf, MODEL_INFO_FLASH_ADDR, info_size); + if (ret == -1) { + err_msg("Error: flash fw_info.bin failed %d\n", ret); + return MSG_FLASH_FAIL; + } + + ret = dfu_post_flash_verify_4kblock((u32)MODEL_INFO_FLASH_ADDR, info_size, + (u8 *)ddr_buf); + if (ret != 0) { + err_msg("Error: verify fw_info.bin failed %d\n", ret); + return MSG_FLASH_FAIL; + } + + // flash all_models.bin + ret = dfu_mem_to_flash_4k_blocks(ddr_buf+info_size, MODEL_ALL_BIN_FLASH_ADDR, model_size); + if (ret == -1) { + err_msg("Error: flash all_models.bin failed %d\n", ret); + return MSG_FLASH_FAIL; + } + + ret = dfu_post_flash_verify_4kblock((u32)MODEL_ALL_BIN_FLASH_ADDR, model_size, + (u8 *)(ddr_buf+info_size)); + if (ret != 0) { + err_msg("Error: verify all_models.bin failed %d\n", ret); + return MSG_FLASH_FAIL; + } + } + + err_msg("kmdw_dfu_update_model: flashing done\n"); + return SUCCESS; + +} + +int kmdw_dfu_update_spl(u32 file_size) +{ + u32 ddr_buf, size = file_size; + int ret; + u16 tmp; + + dbg_msg("kmdw_dfu_spl: flashing ...\n"); + dfu_pre_update(); + + ddr_buf = DDR_BEGIN; + ret = fn_read_data(ddr_buf, size); + if (ret != size) { // spl has no checksum + dfu_update_abort(0); + return MSG_DATA_ERROR; + } + + if ((size % VERIFY_BLK_SZ) != 0) { + tmp = (size + VERIFY_BLK_SZ - 1) / VERIFY_BLK_SZ; + size = tmp * VERIFY_BLK_SZ; + } + + // flash data + ret = dfu_mem_to_flash_4k_blocks(ddr_buf, 0, size); + if (ret == -1) { + dfu_update_abort(0); + return MSG_FLASH_FAIL; + } + + ret = dfu_post_flash_verify_4kblock(0, size, (u8 *)ddr_buf); + dfu_update_abort(0); + if (ret != 0) { + err_msg("Error: post flash verification failed\n"); + return MSG_FLASH_FAIL; + } + + dbg_msg("kmdw_dfu_update_spl: flashing done\n"); + kdp_sys_update_spl_image(ddr_buf, file_size); + return SUCCESS; + +} + +int kmdw_dfu_switch_active_partition(u32 partition) +{ + u32 seq; + int ret; + + if((partition != 1) && (partition != 2)) { + err_msg("Error: wrong partition number\n"); + return -1; + } + + kdev_flash_readdata(PARTITION_0_CFG_START_IN_FLASH, &boot_cfg_0, sizeof(boot_cfg_0)); + flash_wait_ready(300); + + kdev_flash_readdata(PARTITION_1_CFG_START_IN_FLASH, &boot_cfg_1, sizeof(boot_cfg_1)); + flash_wait_ready(300); + + if ((boot_cfg_0.scpu_cfg.flag == 0xffffffff) && (boot_cfg_1.scpu_cfg.flag == 0xffffffff)) { + // no config data is there, need to create them for partition 0/1 + dfu_init_partition_boot_cfg(); + return 0; + } + + if (boot_cfg_0.ncpu_cfg.flag & boot_cfg_1.ncpu_cfg.flag & BOOT_STATE_CONFIRMED) + { + err_msg("Critical Error: 2 active NCPU boot config\n"); + return -1; + } + + if ((boot_cfg_0.ncpu_cfg.partition_id == boot_cfg_1.ncpu_cfg.partition_id) + && (boot_cfg_0.ncpu_cfg.seq == boot_cfg_1.ncpu_cfg.seq)) + { + // no config data is there, need to create them for partition 0/1 + dfu_init_partition_boot_cfg(); + err_msg("only one partition, cannot switch\n"); + return -1; + } + + if (partition == 1) //switch SCPU + { + /* determine if any update ever happened, if not, just return */ + if ((boot_cfg_0.scpu_cfg.flag == BOOT_STATE_CONFIRMED) && + (boot_cfg_0.scpu_cfg.seq == 1) && + (boot_cfg_1.scpu_cfg.flag == BOOT_STATE_NOT_CONFIRMED) && + (boot_cfg_1.scpu_cfg.seq == 0)) + { + err_msg("Never have SCPU firmware updated, cannot switch\n"); + return -1; + } + + if (boot_cfg_0.scpu_cfg.flag == BOOT_STATE_CONFIRMED) + { + boot_cfg_1.scpu_cfg.flag = BOOT_STATE_CONFIRMED; + seq = MAX(boot_cfg_0.scpu_cfg.seq, boot_cfg_1.scpu_cfg.seq); + boot_cfg_1.scpu_cfg.seq = seq + 1; + boot_cfg_0.scpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + + } else if (boot_cfg_1.scpu_cfg.flag == BOOT_STATE_CONFIRMED) + { + boot_cfg_0.scpu_cfg.flag = BOOT_STATE_CONFIRMED; + seq = MAX(boot_cfg_0.scpu_cfg.seq, boot_cfg_1.scpu_cfg.seq); + boot_cfg_0.scpu_cfg.seq = seq + 1; + boot_cfg_1.scpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + } + } + + if (partition == 2) //switch NCPU + { + + /* determine if any update ever happened, if not, just return */ + if ((boot_cfg_0.ncpu_cfg.flag == BOOT_STATE_CONFIRMED) && + (boot_cfg_0.ncpu_cfg.seq == 1) && + (boot_cfg_1.ncpu_cfg.flag == BOOT_STATE_NOT_CONFIRMED) && + (boot_cfg_1.ncpu_cfg.seq == 0)) + { + err_msg("Never have NCPU firmware updated, cannot switch\n"); + return -1; + } + + if (boot_cfg_0.ncpu_cfg.flag == BOOT_STATE_CONFIRMED) + { + boot_cfg_1.ncpu_cfg.flag = BOOT_STATE_CONFIRMED; + seq = MAX(boot_cfg_0.ncpu_cfg.seq, boot_cfg_1.ncpu_cfg.seq); + boot_cfg_1.ncpu_cfg.seq = seq + 1; + boot_cfg_0.ncpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + + } else if (boot_cfg_1.ncpu_cfg.flag == BOOT_STATE_CONFIRMED) + { + boot_cfg_0.ncpu_cfg.flag = BOOT_STATE_CONFIRMED; + seq = MAX(boot_cfg_0.ncpu_cfg.seq, boot_cfg_1.ncpu_cfg.seq); + boot_cfg_0.ncpu_cfg.seq = seq + 1; + boot_cfg_1.ncpu_cfg.flag = BOOT_STATE_NOT_CONFIRMED; + } + + } + + ret = dfu_mem_to_flash_small_block((u32)&boot_cfg_0, PARTITION_0_CFG_START_IN_FLASH, sizeof(boot_cfg_0)); + if (ret == -1) + { + err_msg("Flash write fail on %x\n", PARTITION_0_CFG_START_IN_FLASH); + return MSG_FLASH_FAIL; + } + + ret = dfu_mem_to_flash_small_block((u32)&boot_cfg_1, PARTITION_1_CFG_START_IN_FLASH, sizeof(boot_cfg_1)); + if (ret == -1) + { + err_msg("Flash write fail on %x\n", PARTITION_1_CFG_START_IN_FLASH); + return MSG_FLASH_FAIL; + } + return SUCCESS; +} diff --git a/mdw/display/kmdw_display.c b/mdw/display/kmdw_display.c new file mode 100644 index 0000000..6793c8c --- /dev/null +++ b/mdw/display/kmdw_display.c @@ -0,0 +1,160 @@ +/* + * Kneron Display driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include "board.h" +#include +#include "kmdw_display.h" +#include "kdev_panel.h" + +kdrv_display_t *p_display_drv; + +int kmdw_video_renderer_buffer_initialize(struct video_input_params *dp_params) +{ + if(p_display_drv != NULL) { + return kdrv_display_buffer_initialize(dp_params); + } + return -1; +} + +uint32_t kmdw_video_renderer_get_buffer_addr(void) +{ + if(p_display_drv != NULL) { + return kdrv_display_get_buffer(); + } + return 0; +} + +int kmdw_display_get_params(struct video_input_params *dp_params) +{ + if(p_display_drv != NULL) { + return kdrv_display_get_params(p_display_drv, dp_params); + } + return -1; +} + +int kmdw_display_get_device_id(void) +{ + if(p_display_drv != NULL) { + return kdev_panel_read_display_id(p_display_drv); + } + return -1; +} + +int kmdw_video_renderer_open(struct video_input_params *params) +{ + if(p_display_drv != NULL) { + kdrv_display_set_params(p_display_drv, params); + kdev_panel_initialize(p_display_drv); + return 0; + } + return -1; +} + +int kmdw_video_renderer_set_camera(uint8_t cam_idx) +{ + if(p_display_drv != NULL) { + return kdrv_display_set_camera(p_display_drv, cam_idx); + } + return -1; +} + +int kmdw_video_renderer_start(void) +{ + if(p_display_drv != NULL) { + return kdrv_display_start(p_display_drv); + } + return -1; +} + +int kmdw_video_renderer_stop(void) +{ + if(p_display_drv != NULL) { + return kdrv_display_stop(p_display_drv); + } + return -1; +} + +int kmdw_display_set_pen_rgb565(uint16_t color, uint16_t pen_width) +{ + if(p_display_drv != NULL) { + return kdrv_display_set_pen(p_display_drv, color, pen_width); + } + return -1; +} + +int kmdw_display_draw_rect(uint32_t x, uint32_t y, uint32_t width, uint32_t height, uint8_t draw_mode) +{ + if(p_display_drv != NULL) { + if(draw_mode == DRAW_HINT_BOUNDINGBOX) + return kdrv_display_draw_static_rect(p_display_drv, x, y, width, height); + else if(draw_mode == DRAW_FDR_RESULT_BOUNDINGBOX) + return kdrv_display_draw_rect(p_display_drv, x, y, width, height); + } + return -1; +} + +int kmdw_display_draw_line(uint32_t xs, uint32_t ys, uint32_t xe, uint32_t ye) +{ + if(p_display_drv != NULL) { + return kdrv_display_draw_line(p_display_drv, xs, ys, xe, ye); + } + return -1; +} + +int kmdw_display_fill_rect(uint32_t x, uint32_t y, uint32_t width, uint32_t height) +{ + if(p_display_drv != NULL) { + return kdrv_display_fill_rect(p_display_drv, x, y, width, height); + } + return -1; +} + +int kmdw_display_draw_bitmap(uint32_t x, uint32_t y, uint32_t width, uint32_t height, void *buf) +{ + if(p_display_drv != NULL) { + return kdrv_display_draw_bitmap(p_display_drv, x, y, width, height, buf); + } + return -1; +} + +int kmdw_display_update_draw_fb(uint32_t addr, uint8_t cam_idx) +{ + if(p_display_drv != NULL) { + return kdrv_display_update_draw_fb(p_display_drv, addr, cam_idx); + } + return -1; +} + +int kmdw_display_refresh(void) +{ + if(p_display_drv != NULL) { + return kdev_panel_refresh(p_display_drv); + } + return -1; +} + +int kmdw_display_test_pattern_gen(bool pat_gen) +{ + return kdrv_display_test_pattern_gen(p_display_drv, pat_gen); +} + +int kmdw_display_set_backlight(int duty) +{ + if(p_display_drv != NULL) { + return kdrv_display_set_backlight(p_display_drv, duty); + } + return -1; +} + +int kmdw_display_initialize(void) +{ + p_display_drv = NULL; + if((p_display_drv = kdrv_display_initialize()) != NULL) { + return 0; + } + return -1; +} diff --git a/mdw/flash/kmdw_memxfer.c b/mdw/flash/kmdw_memxfer.c new file mode 100644 index 0000000..d7e1a41 --- /dev/null +++ b/mdw/flash/kmdw_memxfer.c @@ -0,0 +1,275 @@ +#include +#include "io.h" +#include "project.h" + +#include "kdrv_spif.h" +#include "kdev_flash.h" +#include "kmdw_memxfer.h" +#include "kmdw_dfu.h" +#include "kmdw_console.h" + +#define MEMXFER_INITED 0x10 +#define SPI_QUAD_MODE + + +#if FLASH_4BYTES_CMD_EN +extern void kdev_flash_4Bytes_ctrl(uint8_t enable); +#endif + +#define _get_min(x,y) ( x < y ? x: y ) + +static uint8_t _flash_mode = MEMXFER_OPS_NONE; +static uint8_t _mem_mode = MEMXFER_OPS_NONE; + +static uint8_t flash_device_id = 0; + +extern void kdrv_spif_set_commands(uint32_t cmd0, uint32_t cmd1, uint32_t cmd2, uint32_t cmd3); +extern void kdrv_spif_wait_command_complete(void); +extern void kdev_flash_write_control(uint8_t enable); +extern void kdrv_spif_check_quad_status_till_ready(void); +extern void kdev_flash_64kErase(uint32_t offset); +extern void kdev_flash_read_flash_id(void); + +static +int _kdp_memxfer_flash_to_ddr(uint32_t dst, uint32_t src, size_t bytes) +{ + int32_t total_lens; + int32_t access_byte; + uint32_t write_addr; + uint32_t read_data; + int32_t rx_fifo_depth; + + if ((bytes & 0x3) > 0) return -1; + + total_lens = bytes; + write_addr = dst; + rx_fifo_depth = (int32_t)kdrv_spif_rxfifo_depth(); + //read from flash + //write to ddr + +#if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(src)) + { + kdev_flash_4Bytes_ctrl(1); + #ifdef SPI_QUAD_MODE + kdrv_spif_set_commands(src, SPI020_EC_CMD1, total_lens, SPI020_EC_CMD3); + #else + kdrv_spif_set_commands(src, SPI020_13_CMD1, total_lens, SPI020_13_CMD3); + #endif + } + else +#endif + { + #ifdef SPI_QUAD_MODE + kdrv_spif_set_commands(src, SPI020_EB_CMD1, total_lens, SPI020_EB_CMD3); + #else + #if defined(SPI_BUS_SPEED) && (SPI_BUS_SPEED == SPI_BUS_SPEED_100MHZ) + kdrv_spif_set_commands(src, SPI020_0B_CMD1, total_lens, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(src, SPI020_03_CMD1, total_lens, SPI020_03_CMD3); + #endif + #endif + } + + while (total_lens > 0) + { + kdrv_spif_wait_rx_full(); + + access_byte = _get_min(total_lens, rx_fifo_depth); + total_lens -= access_byte; + + while (access_byte > 0) + { + read_data = regSPIF_data->dw.kdrv_spif_dp; + outw(write_addr, read_data); + write_addr += 4; + access_byte -= 4; + } + } +#ifndef MIXING_MODE_OPEN_RENDERER + kdrv_spif_wait_command_complete();/* wait for command complete */ +#endif + +#if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(src)) + kdev_flash_4Bytes_ctrl(0); +#endif + + return 0; +} + + + + +static +int _kdp_memxfer_ddr_to_flash(uint32_t dst, uint32_t src, size_t bytes) +{ +#define BLOCK_SIZE FLASH_PAGE_SIZE //256 +#define SECTOR_ERASE_SIZE SPI020_SECTOR_SIZE //4096 +#define SECTOR64_ERASE_SIZE SPI020_BLOCK_64SIZE //0x10000 + + int32_t total_lens; + uint32_t erase_dst_addr; + uint32_t write_dst_addr; + int32_t write_len, write_len2; + int32_t access_byte; + uint32_t read_addr; + uint32_t write_data; + int32_t tx_fifo_depth; + + if ((dst & 0x00000FFF) > 0) return -1; + if ((src & 0x3) > 0) return -1; + if ((bytes & 0x3) > 0) return -1; + + //erase flash + total_lens = bytes; + erase_dst_addr = dst; + + while (total_lens > 0) + { + if ((total_lens >= SECTOR64_ERASE_SIZE) && ((erase_dst_addr & 0x0FFFF) == 0)) { // use 64KB erase if possible + kdev_flash_64kErase(erase_dst_addr); + total_lens -= SECTOR64_ERASE_SIZE; + erase_dst_addr += SECTOR64_ERASE_SIZE; + } + else { // use 4K erase + kdev_flash_write_control(1); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(erase_dst_addr)) + { + kdev_flash_4Bytes_ctrl(1); + kdrv_spif_set_commands(erase_dst_addr, SPI020_21_CMD1, SPI020_21_CMD2, SPI020_21_CMD3); + } + else + kdrv_spif_set_commands(erase_dst_addr, SPI020_20_CMD1, SPI020_20_CMD2, SPI020_20_CMD3); + #else + kdrv_spif_set_commands(erase_dst_addr, SPI020_20_CMD1, SPI020_20_CMD2, SPI020_20_CMD3); + #endif + + kdrv_spif_check_quad_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(erase_dst_addr)) + kdev_flash_4Bytes_ctrl(0); + #endif + total_lens -= SECTOR_ERASE_SIZE; + erase_dst_addr += SECTOR_ERASE_SIZE; + } + if (total_lens <= 0) + break; + } + + total_lens = bytes; + write_dst_addr = dst; + read_addr = src; + tx_fifo_depth = (int32_t)kdrv_spif_txfifo_depth(); + + while (total_lens > 0) { + kdev_flash_write_control(1); + + write_len = _get_min(total_lens, BLOCK_SIZE); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(write_dst_addr)) + { + kdev_flash_4Bytes_ctrl(1); + kdrv_spif_set_commands(write_dst_addr, SPI020_12_CMD1, write_len, SPI020_12_CMD3); + } + else + kdrv_spif_set_commands(write_dst_addr, SPI020_02_CMD1, write_len, SPI020_02_CMD3); + #else + kdrv_spif_set_commands(write_dst_addr, SPI020_02_CMD1, write_len, SPI020_02_CMD3); + #endif + + write_dst_addr += write_len; + write_len2 = write_len; + + while(write_len2 > 0) + { + kdrv_spif_wait_tx_empty(); + access_byte = _get_min(write_len2, tx_fifo_depth); + write_len2 -= access_byte; + while(access_byte > 0) + { + write_data = inw(read_addr); + regSPIF_data->dw.kdrv_spif_dp = write_data; + read_addr += 4; + access_byte -= 4; + } + } + + kdrv_spif_check_quad_status_till_ready(); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(write_dst_addr)) + kdev_flash_4Bytes_ctrl(0); + #endif + total_lens -= write_len; + } + + return 0; +} + +int kdp_memxfer_init(uint8_t flash_mode, uint8_t mem_mode) +{ + int ret = -1; + + _flash_mode = (_flash_mode & (~MEMXFER_OPS_MASK&0xFF)) | flash_mode; + _mem_mode = (_mem_mode & (~MEMXFER_OPS_MASK&0xFF)) | mem_mode; + kdrv_spif_memxfer_initialize(_flash_mode, _mem_mode); + if (!(_flash_mode & MEMXFER_INITED)) { + kdev_flash_read_flash_id(); + _flash_mode |= MEMXFER_INITED; + } + + return ret; +} + +int kdp_memxfer_flash_to_ddr(uint32_t dst, uint32_t src, size_t bytes) +{ + return _kdp_memxfer_flash_to_ddr(dst, src, bytes); +} + +int kdp_memxfer_ddr_to_flash(uint32_t dst, uint32_t src, size_t bytes) +{ + return _kdp_memxfer_ddr_to_flash(dst, src, bytes); +} + +/** + * @brief flash 64k sector erase + */ +int kdp_memxfer_flash_sector_erase64k(uint32_t addr) +{ + kdev_flash_64kErase(addr); + return 0; +} + +/** + * @brief load ncpu firmware code from flash to niram + */ +int kdp_memxfer_flash_to_niram(int part_idx) + +{ + /* stop ncpu, then load code from flash to NiRAM */ + if (part_idx == 0) { + kdp_memxfer_flash_to_ddr((uint32_t)NCPU_START_ADDRESS, + NCPU_PARTITION0_START_IN_FLASH, NCPU_IMAGE_SIZE); + } else { + kdp_memxfer_flash_to_ddr((uint32_t)NCPU_START_ADDRESS, + NCPU_PARTITION1_START_IN_FLASH, NCPU_IMAGE_SIZE); + } + return 0; +} + +uint8_t kdp_memxfer_get_flash_device_id(void) +{ + return flash_device_id; +} + +const struct s_kdp_memxfer kdp_memxfer_module = { + kdp_memxfer_init, + kdp_memxfer_flash_to_ddr, + kdp_memxfer_ddr_to_flash, + kdp_memxfer_flash_sector_erase64k, + kdp_memxfer_flash_to_niram, + kdp_memxfer_get_flash_device_id, +}; + diff --git a/mdw/include/buffer_object.h b/mdw/include/buffer_object.h new file mode 100644 index 0000000..3c61c97 --- /dev/null +++ b/mdw/include/buffer_object.h @@ -0,0 +1,10 @@ +#pragma once + +#include "ipc.h" + +typedef struct +{ + int num_of_buffer; + uint32_t buffer_addr[MAX_INPUT_NODE_COUNT]; + int length[MAX_INPUT_NODE_COUNT]; +} buffer_object_t; diff --git a/mdw/include/kdp2_ipc_cmd.h b/mdw/include/kdp2_ipc_cmd.h new file mode 100644 index 0000000..fad0651 --- /dev/null +++ b/mdw/include/kdp2_ipc_cmd.h @@ -0,0 +1,406 @@ +/** + * @file kdp2_ipc_cmd.h + * @brief system/model commands + * @version 0.1 + * @date 2021-03-22 + * + * @copyright Copyright (c) 2021 Kneron Inc. All rights reserved. + */ + +#pragma once + +#include + +#include "kp_struct.h" + +// below are for usb control trasnfer +enum +{ + KDP2_CONTROL_REBOOT = 0xFF, // chip reboot + KDP2_CONTROL_SHUTDOWN = 0xFE, // chip shut down + KDP2_CONTROL_FIFOQ_RESET = 0x80, // make fifo queue clean and start-over + KDP2_CONTROL_FIFOQ_GET_STATUS = 0x81, // make firmware print fifoq status (debug only) + KDP2_CONTROL_FIFOQ_CONFIGURE = 0x82, // configure FIFO Queue buffer size and queue depth + KDP2_CONTROL_FIFOQ_ENABLE_DROPPABLE = 0x83, // enable/disable droppable inference image attribute (default : disabled) + KDP2_CONTROL_DDR_HEAP_BOUNDARY_ADJUST = 0x84, // adjust the boundary address of the ddr heap + KDP2_CONTROL_REBOOT_SYSTEM = 0x85, // reboot the entire system (KL630 only) +}; + +// below are for usb bulk command transfer +enum kdp2_command_id +{ + KDP2_COMMAND_LOAD_MODEL = 0xA01, + KDP2_COMMAND_MEMORY_READ = 0xA02, + KDP2_COMMAND_MEMORY_WRITE = 0xA03, + KDP2_COMMAND_GET_SYSTEM_INFO = 0xA04, + KDP2_COMMAND_GET_MODEL_INFO = 0xA05, + KDP2_COMMAND_LOAD_FIRMWARE = 0xA06, + KDP2_COMMAND_LOAD_MODEL_FROM_FLASH = 0xA07, + KDP2_COMMAND_SET_CKEY = 0xA08, + KDP2_COMMAND_SET_SBT_KEY = 0xA09, + KDP2_COMMAND_SET_GPIO = 0xA0A, + KDP2_COMMAND_SET_DBG_CHECKPOINT = 0xA0B, + KDP2_COMMAND_SET_PROFILE_ENABLE = 0xA0C, + KDP2_COMMAND_GET_PROFILE_STATISTICS = 0xA0D, + KDP2_COMMAND_GET_DDR_CONFIG = 0xA0E, + KDP2_COMMAND_LOAD_NEF = 0xA0F, // not supported + KDP2_COMMAND_UPDATE_FIRMWARE = 0xA10, // not supported + KDP2_COMMAND_SWITCH_BOOT_MODE = 0xA11, // not supported + KDP2_COMMAND_UPDATE_LOADER = 0xA12, // not supported + KDP2_COMMAND_GET_FIFOQ_CONFIG = 0xA13, + KDP2_COMMAND_READ_FLASH = 0xA98, + KDP2_COMMAND_WRITE_FLASH = 0xA99, +}; + +// below are for firmware serial number +enum kp_firmware_serial_t +{ + KP_KDP_FW = 0x01, /**< 00000001 */ + + /* ======================= Kdp2 Legacy ========================== */ + + KP_KDP2_FW = 0x80, /**< 1******* */ + + KP_KDP2_FW_USB_TYPE = 0x80, /**< 1*****00 */ + KP_KDP2_FW_FLASH_TYPE = 0x81, /**< 1*****01 */ + KP_KDP2_FW_JTAG_TYPE = 0x82, /**< 1*****10 */ + KP_KDP2_FW_LOADER = 0x83, /**< 1*****11 */ + KP_KDP2_FW_FIND_TYPE_MASK = 0x83, /**< 10000011 */ + + KP_KDP2_FW_KL720_USB_DFU = 0x101, /**< 000100000001 Special Case */ + KP_KDP2_FW_KL720_LOADER = 0xBA, /**< 10111010 Special Case */ + + KP_KDP2_FW_HOST_MODE = 0x90, /**< 1001**** */ + KP_KDP2_FW_HICO_MODE = 0xA0, /**< 1010**** */ + KP_KDP2_FW_COMPANION_MODE = 0xB0, /**< 1011**** */ + KP_KDP2_FW_FIND_MODE_MASK = 0xF0, /**< 11110000 */ + + /* ============================================================== */ + + KP_KDP2_FW_V2 = 0x400, /**< 01********** */ + + KP_KDP2_FW_USB_TYPE_V2 = 0x400, /**< 01*******000 */ + KP_KDP2_FW_FLASH_TYPE_V2 = 0x401, /**< 01*******001 */ + KP_KDP2_FW_JTAG_TYPE_V2 = 0x402, /**< 01*******010 */ + KP_KDP2_FW_LOADER_V2 = 0x403, /**< 01*******011 */ + KP_KDP2_FW_FIND_TYPE_MASK_V2 = 0x407, /**< 010000000111 */ + + KP_KDP2_FW_HOST_MODE_V2 = 0x410, /**< 01***001**** */ + KP_KDP2_FW_HICO_MODE_V2 = 0x420, /**< 01***010**** */ + KP_KDP2_FW_COMPANION_MODE_V2 = 0x430, /**< 01***011**** */ + KP_KDP2_FW_FIND_MODE_MASK_V2 = 0x470, /**< 010001110000 */ + + KP_KDP2_FW_RTOS_OS_V2 = 0x500, /**< 0101******** */ + KP_KDP2_FW_LINUX_OS_V2 = 0x600, /**< 0110******** */ + KP_KDP2_FW_FIND_OS_MASK_V2 = 0x700, /**< 011100000000 */ +}; + +#define FW_TYPE_SCPU 0x1 +#define FW_TYPE_NCPU 0x2 + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_LOAD_FIRMWARE' + + uint32_t fw_type; // FW_TYPE_SCPU or FW_TYPE_NCPU + uint32_t fw_start; // FW code start address + uint32_t fw_size; // should equal to following data trasnfer size + uint32_t fw_bypass[16]; // 64 bytes for future use, used to bypass control settings while uploading fw +} __attribute__((aligned(4))) kdp2_ipc_cmd_upload_firmware_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_LOAD_MODEL' + + uint32_t model_size; + uint32_t fw_info_size; + uint8_t fw_info[]; +} __attribute__((aligned(4))) kdp2_ipc_cmd_load_model_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_LOAD_NEF' + + uint32_t nef_size; +} __attribute__((aligned(4))) kdp2_ipc_cmd_load_nef_t; + +// KDP2_COMMAND_MEMORY_READ and KDP2_COMMAND_MEMORY_WRITE use the same cmd struct +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_MEMORY_READ' or 'KDP2_COMMAND_MEMORY_WRITE' + + uint32_t start_address; + uint32_t length; +} __attribute__((aligned(4))) kdp2_ipc_cmd_memory_read_write_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_GET_SYSTEM_INFO' + +} __attribute__((aligned(4))) kdp2_ipc_cmd_get_system_info_t; + +typedef struct +{ + uint32_t return_code; // KP_API_RETURN_CODE + + kp_system_info_t system_info; +} __attribute__((aligned(4))) kdp2_ipc_response_get_system_info_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_READ_FLASH' + + uint32_t flash_offset; + uint32_t length; + +} __attribute__((aligned(4))) kdp2_ipc_cmd_read_flash_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_WRITE_FLASH' + + uint32_t flash_offset; // 4KB alignment + uint32_t length; + +} __attribute__((aligned(4))) kdp2_ipc_cmd_write_flash_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_GET_MODEL_INFO' + + uint32_t from_ddr; // 0 = from flash, 1 = from ddr not working when value = 0, fix it if needed +} __attribute__((aligned(4))) kdp2_ipc_cmd_get_model_info_t; + +typedef struct +{ + uint32_t return_code; // KP_API_RETURN_CODE + uint32_t fw_info_size; + uint32_t target_chip; // 1: KL520, 2: KL720 (Ref: kp_model_target_chip_t) +} __attribute__((aligned(4))) kdp2_ipc_response_get_model_info_fw_info_t; + +typedef struct +{ + uint32_t return_code; // KP_API_RETURN_CODE + uint32_t setup_size; +} __attribute__((aligned(4))) kdp2_ipc_response_get_model_info_setup_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_UPDATE_FIRMWARE' + + uint32_t firmware_id; // 1 = scpu, 2 = ncpu + uint32_t firmware_size; + uint8_t firmware_content[]; +} __attribute__((aligned(4))) kdp2_ipc_cmd_update_firmware_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_UPDATE_LOADER' + + uint32_t loader_size; +} __attribute__((aligned(4))) kdp2_ipc_cmd_update_loader_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_LOAD_MODEL_FROM_FLASH' +} __attribute__((aligned(4))) kdp2_ipc_cmd_load_model_from_flash_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_SET_CKEY' + uint32_t ckey; +} __attribute__((aligned(4))) kdp2_ipc_cmd_set_ckey_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_SET_SBT_KEY' + uint32_t entry; + uint32_t key; +} __attribute__((aligned(4))) kdp2_ipc_cmd_set_sbt_key_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_SET_GPIO' + uint32_t pin; + uint32_t value; +} __attribute__((aligned(4))) kdp2_ipc_cmd_set_gpio_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_SET_DBG_CHECKPOINT' + uint32_t checkpoint_flags; + bool enable; +} __attribute__((aligned(4))) kdp2_ipc_cmd_set_dbg_checkpoint_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_SET_PROFILE_ENABLE' + bool enable; +} __attribute__((aligned(4))) kdp2_ipc_cmd_set_profile_enable_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_GET_PROFILE_STATISTICS' +} __attribute__((aligned(4))) kdp2_ipc_cmd_get_profile_statics_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_GET_DDR_CONFIG' +} __attribute__((aligned(4))) kdp2_ipc_cmd_get_available_ddr_config_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_GET_FIFOQ_CONFIG' +} __attribute__((aligned(4))) kdp2_ipc_cmd_get_fifo_queue_config_t; + +typedef struct +{ + uint32_t magic_type; // should be 'KDP2_MAGIC_TYPE_COMMAND' + uint32_t total_size; // size of this data struct + uint32_t command_id; // should be 'KDP2_COMMAND_SWITCH_BOOT_MODE' + uint32_t boot_mode; +} __attribute__((aligned(4))) kdp2_ipc_cmd_switch_boot_mode_t; + +// below section is for old KDP firmware update, system status and get kn number commands +////////////////////////////////////////////////////////////////// + +#define KDP_MSG_HDR_CMD 0xA583 +#define KDP_MSG_HDR_RSP 0x8A35 + +#define KDP_CMD_SYSTEM_STATUS 0x21 +#define KDP_CMD_SYSTEM_STATUS_RESPONSE 0x8021 +#define KDP_CMD_UPDATE_FW 0x22 +#define KDP_CMD_UPDATE_FW_RESPONSE 0x8022 +#define KDP_CMD_UPDATE_MODEL 0x23 +#define KDP_CMD_UPDATE_MODEL_RESPONSE 0x8023 +#define KDP_CMD_GET_KN_NUM 0x25 +#define KDP_CMD_GET_KN_NUM_RESPONSE 0x8025 + +// allowed to connect through passing this value as error_code parameter to kp_connect_devices() +#define KDP_MAGIC_CONNECTION_PASS 536173391 + +#define KDP_UPDATE_MODULE_SCPU 1 +#define KDP_UPDATE_MODULE_NCPU 2 + +typedef struct +{ + uint16_t preamble; + uint16_t ctrl; /* payload_len & ctrl info */ + uint16_t cmd; + uint16_t msg_len; + uint32_t fw_id; + uint32_t auto_reboot; +} __attribute__((aligned(4))) kdp_firmware_update_cmd_t; + +typedef struct +{ + uint16_t preamble; + uint16_t ctrl; /* payload_len & ctrl info */ + uint16_t cmd; + uint16_t msg_len; + uint32_t rsp_code; + uint32_t fw_id; +} __attribute__((aligned(4))) kdp_firmware_update_response_t; + +typedef struct +{ + uint16_t preamble; + uint16_t ctrl; /* payload_len & ctrl info */ + uint16_t cmd; + uint16_t msg_len; + uint32_t crc; +} __attribute__((aligned(4))) kdp_get_kn_number_cmd_t; + +typedef struct +{ + uint16_t preamble; + uint16_t ctrl; /* payload_len & ctrl info */ + uint16_t cmd; + uint16_t msg_len; + uint32_t kn_number; + uint32_t dummy; // Seems not used +} __attribute__((aligned(4))) kdp_get_kn_number_response_t; + +typedef struct +{ + uint16_t preamble; + uint16_t ctrl; /* payload_len & ctrl info */ + uint16_t cmd; + uint16_t msg_len; + uint32_t crc; +} __attribute__((aligned(4))) kdp_system_status_cmd_t; + +typedef struct +{ + uint16_t preamble; + uint16_t ctrl; /* payload_len & ctrl info */ + uint16_t cmd; + uint16_t msg_len; + uint32_t sfirmware_id; + uint32_t sbuild_id; + uint16_t sys_status; + uint16_t app_status; + uint32_t nfirmware_id; + uint32_t nbuild_id; +} __attribute__((aligned(4))) kdp_system_status_response_t; + +typedef struct +{ + uint16_t preamble; + uint16_t ctrl; /* payload_len & ctrl info */ + uint16_t cmd; + uint16_t msg_len; + uint32_t fw_info_size; + uint32_t all_models_size; + uint32_t auto_reboot; +} __attribute__((aligned(4))) kdp_model_update_cmd_t; + +typedef struct +{ + uint16_t preamble; + uint16_t ctrl; /* payload_len & ctrl info */ + uint16_t cmd; + uint16_t msg_len; + uint32_t rsp_code; + uint32_t model_id; +} __attribute__((aligned(4))) kdp_model_update_response_t; + +////////////////////////////////////////////////////////////////// diff --git a/mdw/include/kdp2_usb_companion.h b/mdw/include/kdp2_usb_companion.h new file mode 100644 index 0000000..1a5a0ea --- /dev/null +++ b/mdw/include/kdp2_usb_companion.h @@ -0,0 +1,9 @@ +#pragma once + +int kdp2_usb_companion_init(void); + +int kdp2_cmd_handler_initialize(void); +int kdp2_cmd_handle_kp_command(uint32_t command_header_buf); // for new KDP2 commands +int kdp2_cmd_handle_legend_kdp_command(uint32_t command_buffer); // for old KDP commands + +int kdp2_usb_log_initialize(void); diff --git a/mdw/include/kmdw_camera.h b/mdw/include/kmdw_camera.h new file mode 100644 index 0000000..bcd02cc --- /dev/null +++ b/mdw/include/kmdw_camera.h @@ -0,0 +1,308 @@ +/** + * @file kmdw_camera.h + * @brief Kneron camera middleware for camera driver + * + * @copyright Copyright (c) 2020 Kneron Inc. All rights reserved. + */ + + +#ifndef __KMDW_CAMERA_H__ +#define __KMDW_CAMERA_H__ + +#include "kmdw_status.h" +#include "kdrv_camera.h" +#include + +#define CAP_VIDEO_CAPTURE 0x00000001 /**< Is a video capture device */ +#define CAP_STREAMING 0x00000002 /**< can stream on/off */ +#define CAP_DEVICE_CAPS 0x00000004 /**< can query capabilities */ + +enum { + CID_SCANNING_MODE = 0x1, + CID_AUTO_EXPOSURE_MODE, + CID_AUTO_EXPOSURE_PRIORITY, + CID_EXPOSURE_TIME_ABSOLUTE, + CID_EXPOSURE_TIME_RELATIVE, + CID_FOCUS_ABSOLUTE, + CID_FOCUS_RELATIVE, + CID_IRIS_ABSOLUTE, + CID_IRIS_RELATIVE, + CID_ZOOM_ABSOLUTE, + CID_ZOOM_RELATIVE, + CID_PANTILT_ABSOLUTE, + CID_PANTILT_RELATIVE, + CID_ROLL_ABSOLUTE, + CID_ROLL_RELATIVE, + CID_FOCUS_AUTO, + CID_PRIVACY, + CID_FOCUS_SIMPLE, + CID_DIGITAL_WINDOW, + CID_REGION_OF_INTEREST, + CID_BRIGHTNESS, + CID_CONTRAST, + CID_HUE, + CID_SATURATION, + CID_SHARPNESS, + CID_GAMMA, + CID_WHITE_BALANCE_TEMPERATURE, + CID_WHITE_BALANCE_COMPONENT, + CID_BACKLIGHT_COMPENSATION, + CID_GAIN, + CID_POWER_LINE_FREQUENCY, + CID_HUE_AUTO, + CID_WHITE_BALANCE_TEMPERATURE_AUTO, + CID_WHITE_BALANCE_COMPONENT_AUTO, + CID_DIGITAL_MULTIPLIER, + CID_DIGITAL_MULTIPLIER_LIMIT, + CID_CONTRAST_AUTO, + CID_LIST_ALL = 0xFF, +}; + +enum { + KDP_CAM_0, + KDP_CAM_1, + KDP_CAM_NUM, // = IMGSRC_NUM +}; + +enum camera_state { + CAMERA_STATE_IDLE = 0, + CAMERA_STATE_INITED, + CAMERA_STATE_RUNNING, + CAMERA_STATE_IN_FDR_INFERENCE, + CAMERA_STATE_IN_FDR_REGISTRATION, + CAMERA_STATE_IN_FDR_AUTO_REGISTRATION, + CAMERA_STATE_IN_FDR_REGISTRATION_CONFIRM, + CAMERA_STATE_IN_FDR_BOTH_REGISTRATION, + CAMERA_STATE_IN_FDR_BOTH_REGISTRATION_CONFIRM, + CAMERA_STATE_IN_FDR_BOTH_INFERENCE, + CAMERA_STATE_IN_FDR_REGISTRATION_POSE_JUSTIFY, +}; + +typedef struct cam_capability { + char driver[16]; + char desc[16]; + uint32_t version; + uint32_t capabilities; +}cam_capability; + +typedef struct cam_sensor_aec { + uint8_t x1; + uint8_t x2; + uint8_t y1; + uint8_t y2; + uint8_t center_x1; + uint8_t center_x2; + uint8_t center_y1; + uint8_t center_y2; +}cam_sensor_aec; + +typedef void (*kmdw_camera_callback_t)(uint32_t cam_idx, uint32_t img_buf, uint32_t *p_new_img); + +typedef struct cam_ops { + kmdw_status_t (*open)(uint32_t cam_idx); + kmdw_status_t (*close)(uint32_t cam_idx); + kmdw_status_t (*set_format)(uint32_t cam_idx, cam_format *format); + kmdw_status_t (*get_format)(uint32_t cam_idx, cam_format *format); + kmdw_status_t (*buffer_init)(uint32_t cam_idx, uint32_t buf_addr_0, uint32_t buf_addr_1); + kmdw_status_t (*start_capture)(uint32_t cam_idx, kmdw_camera_callback_t img_cb); + kmdw_status_t (*stop_capture)(uint32_t cam_idx); + kmdw_status_t (*buffer_prepare)(uint32_t cam_idx); + kmdw_status_t (*buffer_capture)(uint32_t cam_idx, uint32_t *addr, uint32_t *size); + kmdw_status_t (*stream_on)(uint32_t cam_idx); + kmdw_status_t (*stream_off)(uint32_t cam_idx); + kmdw_status_t (*query_capability)(uint32_t cam_idx, struct cam_capability *cap); + kmdw_status_t (*set_gain)(uint32_t cam_idx, uint32_t gain1, uint32_t gain2); + kmdw_status_t (*set_aec)(uint32_t cam_idx, struct cam_sensor_aec *aec_p); + kmdw_status_t (*set_exp_time)(uint32_t cam_idx, uint32_t gain1, uint32_t gain2); + kmdw_status_t (*get_lux)(uint32_t cam_idx, uint16_t *expo, uint8_t *pre_gain, uint8_t *post_gain, uint8_t *global_gain, uint8_t *y_average); + kmdw_status_t (*led_switch)(uint32_t cam_idx, uint32_t on); + kmdw_status_t (*set_mirror)(uint32_t cam_idx, uint32_t enable); + kmdw_status_t (*set_flip)(uint32_t cam_idx, uint32_t enable); + uint32_t (*get_device_id)(uint32_t cam_idx); + kmdw_status_t (*ioctl)(uint32_t cam_idx, uint32_t cid, void *data, uint16_t len); +}cam_ops; + +/** + * @brief Initializes camera setting + * + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_init(void); + +/** + * @brief camera open function + * + * @param[in] cam_idx camera id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_open(uint32_t cam_idx); + +/** + * @brief camera close function + * + * @param[in] cam_idx camera id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_close(uint32_t cam_idx); + +/** + * @brief camera get device information function + * + * @param[in] cam_idx camera id + * @param[out] cap point of camera capability information. + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_get_device_info(uint32_t cam_idx, struct cam_capability *cap); + +/** + * @brief camera set frame format function + * + * @param[in] cam_idx camera id + * @param[in] cap point of format information. + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_set_frame_format(uint32_t cam_idx, cam_format *format); + +/** + * @brief camera get frame format function + * + * @param[in] cam_idx camera id + * @param[out] cap point of format information. + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_get_frame_format(uint32_t cam_idx, cam_format *format); + +/** + * @brief camera buffer init function + * + * @param[in] cam_idx camera id + * @param[in] buf_addr_0 buffer address 0 + * @param[in] buf_addr_1 buffer address 1 + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_buffer_init(uint32_t cam_idx, uint32_t buf_addr_0, uint32_t buf_addr_1); + +/** + * @brief camera start function + * + * @param[in] cam_idx camera id + * @param[in] img_cb image complete callback function + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_start(uint32_t cam_idx, kmdw_camera_callback_t img_cb); + +/** + * @brief camera stop function + * + * @param[in] cam_idx camera id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_stop(uint32_t cam_idx); + +/** + * @brief camera buffer prepare function + * + * @param[in] cam_idx camera id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_buffer_prepare(uint32_t cam_idx); + +/** + * @brief camera buffer capture function + * + * @param[in] cam_idx camera id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_buffer_capture(uint32_t cam_idx, uint32_t *addr, uint32_t *size); + +/** + * @brief camera streaming on function + * + * @param[in] cam_idx camera id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_stream_on(uint32_t cam_idx); + +/** + * @brief camera streaming off function + * + * @param[in] cam_idx camera id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_stream_off(uint32_t cam_idx); + +/** + * @brief camera set gain function + * + * @param[in] cam_idx camera id + * @param[in] gain1 gain parameter 1 + * @param[in] gain2 gain parameter 2 + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_set_gain(uint32_t cam_idx, uint32_t gain1, uint32_t gain2); + +/** + * @brief camera set ae controller ROI area function + * + * @param[in] cam_idx camera id + * @param[in] aec_p point of cam_sensor_aec + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_set_aec(uint32_t cam_idx, struct cam_sensor_aec *aec_p); + +/** + * @brief camera set exposure time function + * + * @param[in] cam_idx camera id + * @param[in] gain1 exposure time parameter 1 + * @param[in] gain2 exposure time parameter 2 + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_set_exp_time(uint32_t cam_idx, uint32_t gain1, uint32_t gain2); + +/** + * @brief camera get lum and other parameter function + * + * @param[in] cam_idx camera id + * @param[out] expo exposure time parameter + * @param[out] pre_gain exposure time parameter + * @param[out] post_gain exposure time parameter + * @param[out] global_gain exposure time parameter + * @param[in] y_average exposure time parameter 2 + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_get_lux(uint32_t cam_idx, uint16_t *expo, uint8_t *pre_gain, uint8_t *post_gain, uint8_t *global_gain, uint8_t *y_average); + +/** + * @brief camera set nir led on/off function + * + * @param[in] cam_idx camera id + * @param[in] on LED on/off cmd, 1: on, 0:off + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_led_switch(uint32_t cam_idx, uint32_t on); + +/** + * @brief camera ioctl function + * + * @param[in] cam_idx camera id + * @param[in] cid control command id + * @param[in|out] *data poniter to the parameter structure, a control command specific + * @param[in] len structure length + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_ioctl(uint32_t cam_idx, uint32_t cid, void *data, uint16_t len); + + +kmdw_status_t kmdw_camera_controller_register(uint32_t cam_idx, struct cam_ops *cam_ops_p); + +/** + * @brief unregister specific cam ops with cam_idx + * + * @param[in] cam_idx camera id + * @param[in] cam_ops_p incidence for each cam_idx + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_camera_controller_unregister(uint32_t cam_idx, struct cam_ops *cam_ops_p); + +#endif // __KMDW_CAMERA_H__ diff --git a/mdw/include/kmdw_console.h b/mdw/include/kmdw_console.h new file mode 100644 index 0000000..c9bec58 --- /dev/null +++ b/mdw/include/kmdw_console.h @@ -0,0 +1,88 @@ +/** + * @file kmdw_console.h + * @brief log message to console APIs + * + * @copyright Copyright (c) 2020 Kneron Inc. All rights reserved. + */ + +#ifndef __KMDW_CONSOLE_H__ +#define __KMDW_CONSOLE_H__ + +#include +#include "kmdw_status.h" +#include "kdrv_uart.h" +#include "kmdw_memory.h" + +#define LOG_NONE 0 /**< log level for none */ +#define LOG_CRITICAL 1 /**< log level for critical */ +#define LOG_ERROR 2 /**< log level for error */ +#define LOG_USER 3 /**< log level for user */ + +#define LOG_INFO 4 /**< log level for info */ +#define LOG_TRACE 5 /**< log level for trace */ +#define LOG_DBG 6 /**< log level for dbg */ + +#define LOG_PROFILE 9 /**< log level for profile */ + +typedef void (*print_callback)(const char *log); + +extern void kmdw_console_set_log_level_scpu(uint32_t level); +extern void kmdw_console_set_log_level_ncpu(uint32_t level); +extern char kmdw_console_getc(void); +extern void kmdw_console_putc(char Ch); +extern void kmdw_console_puts(char *str); +extern int kmdw_console_echo_gets(char *buf, int len); +extern void kmdw_console_hook_callback(print_callback print_cb); +extern void kmdw_console_wait_rx_done(kdrv_uart_handle_t handle); +extern void kmdw_console_wait_tx_done(kdrv_uart_handle_t handle); +extern kmdw_status_t kmdw_uart_console_init(uint8_t uart_dev, uint32_t baudrate); +extern kmdw_status_t kmdw_uart_uninitialize(void); +extern uint32_t kmdw_console_get_log_level_scpu(void); + +extern kmdw_status_t kmdw_printf(const char *fmt, ...); + +extern kmdw_status_t kmdw_level_printf(int level, const char *fmt, ...); + +extern bool ModelFromDDR; //check model is from flash or ddr + +#ifdef LOG_ENABLE + +#define DSG(__format__, ...) \ + { \ + kmdw_printf(__format__ "\n", ##__VA_ARGS__); \ + } + +#define DSG_NOLF(__format__, ...) \ + { \ + kmdw_printf(__format__, ##__VA_ARGS__); \ + } + +#define dbg_msg(fmt, ...) kmdw_level_printf(LOG_DBG, fmt, ##__VA_ARGS__) +#define trace_msg(fmt, ...) kmdw_level_printf(LOG_TRACE, fmt, ##__VA_ARGS__) +#define info_msg(fmt, ...) kmdw_level_printf(LOG_INFO, fmt, ##__VA_ARGS__) +#define err_msg(fmt, ...) kmdw_level_printf(LOG_ERROR, fmt, ##__VA_ARGS__) +#define critical_msg(fmt, ...) kmdw_level_printf(LOG_CRITICAL, fmt, ##__VA_ARGS__) +#define profile_msg(fmt, ...) kmdw_level_printf(LOG_PROFILE, fmt, ##__VA_ARGS__) + +#define dlog(fmt, ...) kmdw_level_printf(LOG_DBG, "[%s][%s] " fmt "\r\n", DEF_LOG_CATEG, __func__, ##__VA_ARGS__) + +#else ////////////////////////////////////////////////////////////////////// + +#define DSG_NOLF(__format__, ...) +#define DSG(__format__, ...) +#define dbg_msg(fmt, ...) +#define trace_msg(fmt, ...) +#define info_msg(fmt, ...) +#define err_msg(fmt, ...) +#define critical_msg(fmt, ...) +#define dlog(fmt, ...) + +#endif // LOG_ENABLE /////////////////////////////////////////////////////// + +#define dbg_msg_api(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) +#define dbg_msg_app(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__) +#define dbg_msg_algo(fmt, ...) critical_msg(fmt, ##__VA_ARGS__) +#define dbg_msg_console(fmt, ...) critical_msg(fmt "\n", ##__VA_ARGS__) +#define dbg_msg_user(fmt, ...) kmdw_level_printf(LOG_USER, fmt, ##__VA_ARGS__) + +#endif // __KMDW_CONSOLE_H__ diff --git a/mdw/include/kmdw_dfu.h b/mdw/include/kmdw_dfu.h new file mode 100644 index 0000000..147ff3e --- /dev/null +++ b/mdw/include/kmdw_dfu.h @@ -0,0 +1,94 @@ +/** + * @file kmdw_dfu.h + * @brief APIs for device firmware update + * + * @copyright Copyright (c) 2020 Kneron Inc. All rights reserved. + */ + +#ifndef __KMDW_DFU_H__ +#define __KMDW_DFU_H__ + +#include "base.h" +#include "cmsis_os2.h" + +#define SCPU_PARTITION0_START_IN_FLASH FLASH_FW_SCPU0_ADDR /**< 0x2000 */ +#define NCPU_PARTITION0_START_IN_FLASH FLASH_FW_NCPU0_ADDR /**< 0x18000 */ +#define PARTITION_0_CFG_START_IN_FLASH FLASH_FW_CFG0_ADDR /**< 0X28000 */ +#define SCPU_PARTITION1_START_IN_FLASH FLASH_FW_SCPU1_ADDR /**< 0x41000 */ +#define NCPU_PARTITION1_START_IN_FLASH FLASH_FW_NCPU1_ADDR /**< 0x57000 */ +#define PARTITION_1_CFG_START_IN_FLASH FLASH_FW_CFG1_ADDR /**< 0X67000 */ + +#define SCPU_START_ADDRESS (SiRAM_MEM_BASE + 0x2000 ) /**< - */ +#define NCPU_START_ADDRESS NiRAM_MEM_BASE /**< - */ + +#define PARTITION_CFG_SIZE 32 /**< size of cfg partition */ + +#define SUCCESS 0 /**< return code: success */ +#define MSG_AUTH_FAIL 251 /**< return code: auth fail */ +#define MSG_FLASH_FAIL 252 /**< return code: falshing fail */ +#define MSG_DATA_ERROR 253 /**< return code: data check fail */ +#define MSG_FLASH_NO_SPACE 254 /**< return code: flash no space fail */ + +/* function used to read DFU content */ +typedef uint32_t (*FnReadData)(uint32_t addr, uint32_t img_size); + +/* @brief Init DFU function + * @param tmp_buf temp buffer: size should be >= VERIFY_BLK_SZ + * @param fn_read_data function to read data + * @return 0 on success + */ +int kmdw_dfu_init(uint8_t* tmp_buf, FnReadData fn_read_data); + +/** + * @brief Update SCPU firmware + * @return 0 on success + */ +int kmdw_dfu_update_scpu(void); + +/** + * @brief Update NCPU firmware + * @return 0 on success + */ +int kmdw_dfu_update_ncpu(void); + +/** + * @brief Update model + * @param[in] info_size fw_info.bin size + * @param[in] model_size all_models.bin size + * @return 0 on success + */ +int kmdw_dfu_update_model(uint32_t info_size, uint32_t model_size); + +/** + * @brief Update spl + * @param[in] size spl size + * @return 0 on success + */ +int kmdw_dfu_update_spl(uint32_t size); + +/** + * @brief Switch active partition + * @param[in] partition active partition + * @return 0 on success + */ +int kmdw_dfu_switch_active_partition(uint32_t partition); + +/** + * @brief get active SCPU partition ID + * @return + * 0 - partition 0 + * 1 - partition 1 + * -1 - error condition (2 active partitions) + */ +int kmdw_dfu_get_active_scpu_partition(void); + +/** + * @brief get active NCPU partition ID + * @return + * 0 - partition 0 + * 1 - partition 1 + * -1 - error condition (2 active partitions) + */ +int kmdw_dfu_get_active_ncpu_partition(void); + +#endif diff --git a/mdw/include/kmdw_display.h b/mdw/include/kmdw_display.h new file mode 100644 index 0000000..d823ad4 --- /dev/null +++ b/mdw/include/kmdw_display.h @@ -0,0 +1,286 @@ +/** + * @file kmdw_display.h + * @brief Kneron display middleware + * + * @copyright Copyright (c) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __KMDW_DISPLAY_H__ +#define __KMDW_DISPLAY_H__ + +#include "kdrv_display.h" + +/* Method of draw boundingbox */ +#define DRAW_HINT_BOUNDINGBOX (0x01) /**< Only display 4-corner hint boundingbox on LDC preview*/ +#define DRAW_FDR_RESULT_BOUNDINGBOX (0x02) /**< Only display face boundingbox on LDC preview*/ +#define ALL_DRAW_BOUNDINGBOX_MODE (DRAW_HINT_BOUNDINGBOX | DRAW_FDR_RESULT_BOUNDINGBOX) /**< Display hint 4-corner and face boundingbox on LDC preview*/ + +/** + * @brief Structure of representing display and panel driver compatibility + */ +struct kmdw_display_panel_drv { + struct video_input_params vi_params; /**< - */ + uint32_t fb_size; /**< - */ + uint32_t type; /**< - */ + uint32_t base; /**< - */ + uint16_t display_id; /**< - */ +}; + +/** + * @brief Initialize display and panel driver + * + * @return N/A + */ +int kmdw_display_initialize(void); + +/** + * @brief Open a video renderer to display frame buffer + * + * @param[in] params see @ref video_input_params + * @return 0, Open a video renderer to display frame buffer successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * struct video_input_params params;\n + * params.input_fmt = V2K_PIX_FMT_RGB565;\n + * params.input_xres = LCD_WIDTH;\n + * params.input_yres = LCD_HEIGHT;\n + * kmdw_video_renderer_open(¶ms); + */ +int kmdw_video_renderer_open(struct video_input_params *params); + +/** + * @brief Set camera source index which be displayed on LCD + * + * @param[in] cam_idx Camera source index + * @return 0, Set camera source index which be displayed on LCD successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * struct video_input_params params;\n + * params.input_fmt = V2K_PIX_FMT_RGB565;\n + * params.input_xres = LCD_WIDTH;\n + * params.input_yres = LCD_HEIGHT;\n + * kmdw_video_renderer_open(¶ms);\n + * kmdw_video_renderer_set_camera(CAMERA_RGB_IDX); + */ +int kmdw_video_renderer_set_camera(uint8_t cam_idx); + +/** + * @brief Initilize display frame buffer + * + * @param[in] params see @ref video_input_params + * @return 0, Initilize display frame buffer successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * struct video_input_params params;\n + * params.input_fmt = V2K_PIX_FMT_RGB565;\n + * params.input_xres = LCD_WIDTH;\n + * params.input_yres = LCD_HEIGHT;\n + * kmdw_video_renderer_open(¶ms);\n + * kmdw_video_renderer_set_camera(CAMERA_RGB_IDX);\n + * kmdw_video_renderer_buffer_initialize(¶ms); + */ +int kmdw_video_renderer_buffer_initialize(struct video_input_params *params); + +/** + * @brief Turn on display preview + * + * @return 0, Turn on display preview successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * struct video_input_params params;\n + * params.input_fmt = V2K_PIX_FMT_RGB565;\n + * params.input_xres = LCD_WIDTH;\n + * params.input_yres = LCD_HEIGHT;\n + * kmdw_video_renderer_open(¶ms);\n + * kmdw_video_renderer_set_camera(CAMERA_RGB_IDX);\n + * kmdw_video_renderer_buffer_initialize(¶ms);\n + * kmdw_video_renderer_start(); + */ +int kmdw_video_renderer_start(void); + +/** + * @brief Turn off display preview + * + * @return 0, Turn off display preview successfully\n + * -1, Empty or wrong lcd driver or other errors + */ +int kmdw_video_renderer_stop(void); + +/** + * @brief Get display snapshot frame buffer + * + * @return >0, Return snapshot frame buffer successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * uint32_t buf_addr;\n + * buf_addr = kmdw_video_renderer_get_buffer_addr(); + */ +uint32_t kmdw_video_renderer_get_buffer_addr(void); + +/** + * @brief Get the input parameters of display + * + * @param[in] dp_params see @ref video_input_params + * @return 0, Update frame buffer successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * uint32_t buf_idx, buf_addr;\n + * buf_addr = kdp_fb_mgr_next_read(CAMERA_RGB_IDX, &buf_idx);\n + * kmdw_display_update_draw_fb(buf_addr, CAMERA_RGB_IDX)\n + * kmdw_display_draw_xxx(); + */ +int kmdw_display_get_params(struct video_input_params *dp_params); + +/** + * @brief Get display panel id + * + * @return [id], display panel id + * + * @note Exmpale:\n + * int dev_id;\n + * dev_id = kmdw_display_get_device_id()\n + */ +int kmdw_display_get_device_id(void); + +/** + * @brief Update frame buffer which be used to draw something on display + * + * @param[in] addr Frame buffer address + * @param[in] cam_idx Camera source index + * @return 0, Update frame buffer successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * uint32_t buf_idx, buf_addr;\n + * buf_addr = kdp_fb_mgr_next_read(CAMERA_RGB_IDX, &buf_idx);\n + * kmdw_display_update_draw_fb(buf_addr, CAMERA_RGB_IDX)\n + * kmdw_display_draw_xxx(); + */ +int kmdw_display_update_draw_fb(uint32_t addr, uint8_t cam_idx); + +/** + * @brief Set pen width and color + * + * @param[in] color Color of pen + * @param[in] pen_width Width of pen + * @return 0, Set pen width and color successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * kmdw_display_set_pen_rgb565(BLUE, 8); + */ +int kmdw_display_set_pen_rgb565(uint16_t color, uint16_t pen_width); + +/** + * @brief Draw rectangle without filling color on display + * + * @param[in] x Start x-axis of rectangle on display to draw + * @param[in] y Start y-axis of rectangle on display to draw + * @param[in] width Width of rectangle + * @param[in] height Height of rectangle + * @param[in] draw_mode see @ref KDP_BOUNDINGBOX_MODE + * @return 0, Draw rectangle on display successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * uint32_t buf_idx, buf_addr;\n + * buf_addr = kdp_fb_mgr_next_read(CAMERA_RGB_IDX, &buf_idx);\n + * kmdw_display_update_draw_fb(buf_addr, CAMERA_RGB_IDX);\n + * kmdw_display_set_pen_rgb565(BLUE, 8);\n + * kmdw_display_draw_rect(50, 55, 120, 100, DRAW_FDR_RESULT_BOUNDINGBOX); + */ +int kmdw_display_draw_rect(uint32_t x, uint32_t y, uint32_t width, uint32_t height, uint8_t draw_mode); + +/** + * @brief Draw line on display + * + * @param[in] xs Start x-axis of line on display to draw + * @param[in] xe End x-axis of line on display to draw + * @param[in] ys Start y-axis of line on display to draw + * @param[in] ye End y-axis of line on display to draw + * @return 0, Draw line on display successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * uint32_t buf_idx, buf_addr;\n + * buf_addr = kdp_fb_mgr_next_read(CAMERA_RGB_IDX, &buf_idx);\n + * kmdw_display_update_draw_fb(buf_addr, CAMERA_RGB_IDX);\n + * kmdw_display_set_pen_rgb565(BLACK, 4);\n + * kmdw_display_draw_line(50, 400, 50, 300); + */ +int kmdw_display_draw_line(uint32_t xs, uint32_t ys, uint32_t xe, uint32_t ye); + +/** + * @brief Draw rectangle with filling color on display + * + * @param[in] x Start x-axis of rectangle on display to draw + * @param[in] y Start y-axis of rectangle on display to draw + * @param[in] width Width of rectangle + * @param[in] height Height of rectangle + * @return 0, Draw rectangle on display successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * uint32_t buf_idx, buf_addr;\n + * buf_addr = kdp_fb_mgr_next_read(CAMERA_RGB_IDX, &buf_idx);\n + * kmdw_display_update_draw_fb(buf_addr, CAMERA_RGB_IDX);\n + * kmdw_display_set_pen_rgb565(BLACK, 8);\n + * kmdw_display_fill_rect(0, 0, 640, 480); + */ +int kmdw_display_fill_rect(uint32_t x, uint32_t y, uint32_t width, uint32_t height); + +/** + * @brief Draw bitmap on display + * + * @param[in] x Start x-axis of bitmap on display to draw + * @param[in] y Start y-axis of bitmap on display to draw + * @param[in] width Width of bitmap + * @param[in] height Height of bitmap + * @param[in] buf Bitmap of target + * @return 0, Draw bitmap on display successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * uint32_t buf_idx, buf_addr;\n + * buf_addr = kdp_fb_mgr_next_read(CAMERA_RGB_IDX, &buf_idx);\n + * kmdw_display_update_draw_fb(buf_addr, CAMERA_RGB_IDX);\n + * kmdw_display_draw_bitmap(0, 450, 100, 50, (void *)USER_IMG_ICON_ADDR); + */ +int kmdw_display_draw_bitmap(uint32_t x, uint32_t y, uint32_t width, uint32_t height, void *buf); + +/** + * @brief Generate display test image display + * + * @param[in] pat_gen TRUE or FALSE to generate test pattern + * @return 0, Draw rectangle on display successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * kmdw_display_test_pattern_gen(TRUE);\n + * kmdw_display_initialize(); + * kmdw_video_renderer_open(¶ms); + */ +int kmdw_display_test_pattern_gen(bool pat_gen); + + +int kmdw_display_refresh(void); + +/** + * @brief Set display backlight + * + * @param[in] duty see @ref kdrv_display_backlight_t + * @return 0, Set display backlight successfully\n + * -1, Empty or wrong lcd driver or other errors + * + * @note Exmpale:\n + * kkmdw_display_set_backlight(KDRV_DISPLAY_BACKLIGHT_ON); + */ +int kmdw_display_set_backlight(int duty); + + +#endif diff --git a/mdw/include/kmdw_fifoq_manager.h b/mdw/include/kmdw_fifoq_manager.h new file mode 100644 index 0000000..bd4612e --- /dev/null +++ b/mdw/include/kmdw_fifoq_manager.h @@ -0,0 +1,164 @@ +/** + * @file kmdw_fifoq_manager.h + * @brief for kdp2 fw only - inference structures and functions + * + * @copyright Copyright (c) 2022 Kneron Inc. All rights reserved. + */ + +#pragma once + +#include +#include + +#include "kp_struct.h" +#include "dual_fifo2.h" + +/** + * @brief Init the fifo queue manager + * + * @param image_count[in] the capacity of buffers in image queue + * @param result_count[in] the capacity of buffers in result queue + * @return int 0: success, -1: failed + */ +int kmdw_fifoq_manager_init(uint32_t image_count, uint32_t result_count); + +/** + * @brief enqueue one inference object containing one or more images to the "inference-waiting buffer queue" + * + * return immediately if queue is not full + * blocking wait (unless timeout) if queue if full + * If 1 < total_num_buf, the image buffers will be enqueued after index 0 ~ (total_num_buf - 1) has been stored. + * + * @param total_num_buf[in] the total number of buffers should be contain in the list + * @param index[in] index of the buffer in the list + * @param buf_addr[in] address of the buffer + * @param buf_size[in] size of the buffer + * @param timeout[in] CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. + * @param preempt[in] preempt this result data + * @return osStatus_t Status code values returned by CMSIS-RTOS functions. + */ +osStatus_t kmdw_fifoq_manager_image_enqueue(uint32_t total_num_buf, uint32_t index, uint32_t buf_addr, int buf_size, uint32_t timeout, bool preempt); + +/** + * @brief request one inference object from the "inference-waiting buffer queue" + * + * return immediately if queue has inference objects + * blocking wait (unless timeout) if no inference object is available yet + * + * @param bobj[out] buffer object containing one or more buffers to be inference + * @param timeout[int] CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. + * @return osStatus_t Status code values returned by CMSIS-RTOS functions. + */ +osStatus_t kmdw_fifoq_manager_image_dequeue(buffer_object_t *bobj, uint32_t timeout); + +/** + * @brief retrieve one free-to-use image buffer from the "inference-done image queue" + * + * return immediately if queue has free buffers + * blocking wait (unless timeout) if no free buffer is available + * if force_grab, and no free buffer is available, it will force grab the earliest-queued buffer from the "inference-waiting buffer queue" + * + * @param buf_addr[in] address of the buffer + * @param buf_size[in] size of the buffer + * @param timeout[in] CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. + * @param force_grab[int] whether force grab one buffer from data queue when no free buffer is available + * @return osStatus_t Status code values returned by CMSIS-RTOS functions. + */ +osStatus_t kmdw_fifoq_manager_image_get_free_buffer(uint32_t *buf_addr, int *buf_size, uint32_t timeout, bool force_grab); + +/** + * @brief put one free buffer to the "inference-done image queue" + * + * return immediately if queue is not full + * blocking wait (unless timeout) if no free buffer is available + * + * @param buf_addr[in] address of the buffer + * @param buf_size[in] size of the buffer + * @param timeout[in] CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. + * @return osStatus_t Status code values returned by CMSIS-RTOS functions. + */ +osStatus_t kmdw_fifoq_manager_image_put_free_buffer(uint32_t buf_addr, int buf_size, uint32_t timeout); + +/** + * @brief enqueue one result data to the "inference-complete result queue" + * + * return immediately if queue is not full + * blocking wait (unless timeout) if queue if full + * + * @param result_buf[in] address of the buffer + * @param result_buf_size[in] size of the buffer + * @param preempt[in] preempt this result data + * @return osStatus_t Status code values returned by CMSIS-RTOS functions. + */ +osStatus_t kmdw_fifoq_manager_result_enqueue(void *result_buf, int result_buf_size, bool preempt); + +/** + * @brief request one inference result from the "inference-complete result queue" + * + * return immediately if queue has resutls + * blocking wait (unless timeout) if no result is available yet + * + * @param buf_addr[in] address of the buffer + * @param buf_size[in] size of the buffer + * @param timeout[in] CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. + * @return osStatus_t Status code values returned by CMSIS-RTOS functions. + */ +osStatus_t kmdw_fifoq_manager_result_dequeue(uint32_t *buf_addr, int *buf_size, uint32_t timeout); + +/** + * @brief retrieve one free-to-use result buffer from the "free result queue" + * + * return immediately if queue has free buffers + * blocking wait (unless timeout) if no free buffer is available + * if force_grab, and no free buffer is available, it will force grab the earliest-queued buffer from the "inference-complete result queue" + * + * @param buf_size[in] size of the buffer + * @return void* address of the buffer + */ +void *kmdw_fifoq_manager_result_get_free_buffer(int *buf_size); + +/** + * @brief put one free buffer to the "free result queue" (which will be used by inference APP) + * + * return immediately if queue is not full + * blocking wait (unless timeout) if no free buffer is available + * + * @param buf_addr[in] address of the buffer + * @param buf_size[in] size of the buffer + * @param timeout[in] CMSIS_RTOS_TimeOutValue or 0 in case of no time-out. + * @return osStatus_t Status code values returned by CMSIS-RTOS functions. + */ +osStatus_t kmdw_fifoq_manager_result_put_free_buffer(uint32_t buf_addr, int buf_size, uint32_t timeout); + +/** + * @brief Clear the data queues and put buffer back to free queues + */ +void kmdw_fifoq_manager_clean_queues(void); + +/** + * @brief Set the status of the fifo queue buffer has been allocated + * + * @param input_buf_countp[in] Input buffer count for FIFO queue + * @param input_buf_size[in] Input buffer size for FIFO queue + * @param result_buf_count[in] Result buffer count for FIFO queue + * @param result_buf_size[in] Result buffer size for FIFO queue + */ +void kmdw_fifoq_manager_store_fifoq_config(uint32_t input_buf_count, uint32_t input_buf_size, uint32_t result_buf_count, uint32_t result_buf_size); + +/** + * @brief Get the status of whether the fifo queue buffer has been allocated + * + * @return true the fifo queue buffer has been allocated + * @return false the fifo queue buffer has NOT been allocated + */ +bool kmdw_fifoq_manager_get_fifoq_allocated(void); + +/** + * @brief Get the configuration of FIFO queue buffer + * + * @param input_buf_count[out] Input buffer count for FIFO queue + * @param input_buf_size[out] Input buffer size for FIFO queue + * @param result_buf_count[out] Result buffer count for FIFO queue + * @param result_buf_size[out] Result buffer size for FIFO queue + */ +void kmdw_fifoq_manager_get_fifoq_config(uint32_t *input_buf_count, uint32_t *input_buf_size, uint32_t *result_buf_count, uint32_t *result_buf_size); diff --git a/mdw/include/kmdw_inference_app.h b/mdw/include/kmdw_inference_app.h new file mode 100644 index 0000000..b3deebf --- /dev/null +++ b/mdw/include/kmdw_inference_app.h @@ -0,0 +1,152 @@ +/** + * @file kmdw_inference_app.h + * @brief for kdp2 fw only - inference structures and functions + * + * @copyright Copyright (c) 2021 Kneron Inc. All rights reserved. + */ + +#pragma once + +#include +#include + +#include "kp_struct.h" +#include "buffer_object.h" + +/** + * @brief prototype for inference entry callback function + * + * @param[in] num_input_buf number of input buffer in list + * @param[in] inf_input_buf_list transmitted from host SW = list of (header + image, input buffer for inference) + * + */ +typedef void (*kmdw_inference_app_callback_t)(int num_input_buf, void **inf_input_buf_list); + +/** + * @brief prototype for inference result callback function + * + * @param[out] status used to indicate exeuction status, refer to KP_API_RETURN_CODE. + * @param[out] inf_result_buf used to carry inference result back to host SW = header + inferernce result (from ncpu/npu) + * @param[out] ncpu_result_buf post-processing result buffer done by ncpu + * + */ +typedef void (*kmdw_inference_app_result_callback_t)(int status, void *inf_result_buf, int inf_result_buf_size, void *ncpu_result_buf); + +/** + * @brief padding values of image for ncpu/npu pre-processing + */ +typedef struct +{ + int32_t pad_top; /**< padding pixel number at the top of image */ + int32_t pad_bottom; /**< padding pixel number at the bottom of image */ + int32_t pad_left; /**< padding pixel number at the left of image */ + int32_t pad_right; /**< padding pixel number at the right of image */ +} kp_pad_value_t; + +/** + * @brief structure of image and pre process info + */ +typedef struct +{ + void *image_buf; /**< image buffer address */ + uint32_t image_width; /**< width in pixel */ + uint32_t image_height; /**< height in pixel */ + uint32_t image_channel; /**< channel count */ + uint32_t image_resize; /**< for resize image, part of pre-process, kp_resize_mode_t */ + uint32_t image_padding; /**< for padding image, part of pre-process, kp_padding_mode_t */ + uint32_t image_format; /**< for color space conversion, part of pre-process, kp_image_format_t */ + uint32_t image_norm; /**< for data normalization, part of pre-process, kp_normalize_mode_t */ + bool enable_crop; /**< if true then 'crop_area' should be set */ + kp_inf_crop_box_t crop_area; /**< inference cropping area */ + kp_pad_value_t *pad_value; /**< pad_value for ncpu/npu pre-processing */ + + bool bypass_pre_proc; /**< if true, then all pre-process will be ignored */ + uint32_t image_buf_size; /**< only used for bypass pre-process */ +} kp_img_pre_proc_t; + +/** + * @brief inference configuration + */ +typedef struct +{ + /* input */ + int num_image; /**< number of available images in image_list */ + kp_img_pre_proc_t image_list[MAX_INPUT_NODE_COUNT]; /**< list of images and pre process info */ + + int model_id; /**< target inference model ID */ + bool enable_raw_output; /**< should be true if ncpu does not do post-process */ + bool enable_parallel; /**< only works for single model and post-process in ncpu */ + kmdw_inference_app_result_callback_t result_callback; /**< callback function for parallel mode */ + void *inf_result_buf; /**< works for enable_parallel=true to carry it back to user callback function */ + int inf_result_buf_size; /**< size of inf_result_buf */ + void *ncpu_result_buf; /**< for ncpu/npu to output, if enable_parallel=true, it will be passed to 'kmdw_inference_app_result_callback_t' */ + void *user_define_data; /**< user define data for ncpu/npu pre-processing */ +} kmdw_inference_app_config_t; + +/** + * @brief initialize all components for inference + * + * @param[in] app_entry entry function for application + * @param[in] image_count number of queue size for image buffers. MIN val is 1. + * @param[in] result_count number of queue size for result buffers. MIN val is 1. + * + */ +int kmdw_inference_app_init(kmdw_inference_app_callback_t app_entry, uint32_t image_count, uint32_t result_count); + +/** + * @brief request a result buffer for inference output + * + * @param[out] buf_size buffer size requested + * + * @return the buffer address + */ +void *kmdw_inference_app_result_get_free_buffer(int *buf_size); + +/** + * @brief send result back to host SW + * + * @param[in] result_buf result buffer address + * @param[out] result_buf_size result buffer size + * @param[out] preempt preempt this result data + * + * @return osStatus_t + */ +osStatus_t kmdw_inference_app_result_enqueue(void *result_buf, int result_buf_size, bool preempt); + +/** + * @brief send error/status result back to host SW + * + * @param[in] job_id user-defind ID to synchronize with host SW side + * @param[in] error_code error code that needs to send back + * + */ +void kmdw_inference_app_send_status_code(int job_id, int error_code); + +/** + * @brief do one inference, result_callback works only while enable_parallel = true + * + * @param[in] inf_config desired inference configuration + * + * @return refer to KP_API_RETURN_CODE in kp_struct.h + */ +int kmdw_inference_app_execute(kmdw_inference_app_config_t *inf_config); + +/** + * @brief get model raw output size with specified model id + * + * @param[in] model_id specified model id + * + * @return model raw output size + */ +uint32_t kmdw_inference_app_get_model_raw_output_size(uint32_t model_id); + +/** + * @brief get model input width and height + * + * @param model_id specified model id + * @param input_index specified input node index + * @param model_input_width [output] model input width + * @param model_input_height [output] model input height + * @return refer to KP_API_RETURN_CODE in kp_struct.h + */ +int kmdw_inference_get_model_input_image_size(uint32_t model_id, uint32_t input_index, uint32_t *model_input_width, uint32_t *model_input_height); diff --git a/mdw/include/kmdw_inference_client.h b/mdw/include/kmdw_inference_client.h new file mode 100644 index 0000000..f838dc7 --- /dev/null +++ b/mdw/include/kmdw_inference_client.h @@ -0,0 +1,45 @@ +/** + * @file kmdw_inference_client.h + * @brief for kdp2 fw only - inference structures and functions + * + * @copyright Copyright (c) 2021 Kneron Inc. All rights reserved. + */ + +#pragma once + +#include +#include + +#include "kp_struct.h" + +// enqueue one image to the "inference-waiting buffer queue" +// return immediately if queue is not full +// blocking wait (unless timeout) if queue if full +osStatus_t kmdw_inference_client_image_enqueue(uint32_t buf_addr, int buf_size, uint32_t timeout, bool preempt); + +// retrieve one free-to-use image buffer from the "inference-done image queue" +// return immediately if queue has free buffers +// blocking wait (unless timeout) if no free buffer is available +// if force_grab, and no free buffer is available, it will forcely grab the earliest-queued buffer from the "inference-waiting buffer queue" +osStatus_t kmdw_inference_client_image_get_free_buffer(uint32_t *buf_addr, int *buf_size, uint32_t timeout, bool force_grab); + +// put one free buffer to the "inference-done image queue" +// return immediately if queue is not full +// blocking wait (unless timeout) if no free buffer is available +osStatus_t kmdw_inference_client_image_put_free_buffer(uint32_t buf_addr, int buf_size, uint32_t timeout); + +// reqeust one inference result from the "inference-complete result queue" +// return immediately if queue has resutls +// blocking wait (unless timeout) if no result is available yet +osStatus_t kmdw_inference_client_result_request(uint32_t *buf_addr, int *buf_size, uint32_t timeout); + +// put one free buffer to the "free result queue" (which will be used by inference APP) +// return immediately if queue is not full +// blocking wait (unless timeout) if no free buffer is available +osStatus_t kmdw_inference_client_result_put_free_buffer(uint32_t buf_addr, int buf_size, uint32_t timeout); + +void kmdw_inference_client_clean_queues(void); + +void kmdw_inference_client_set_fifoq_allocated(bool blAllocated); + +bool kmdw_inference_client_get_fifoq_allocated(void); diff --git a/mdw/include/kmdw_ipc.h b/mdw/include/kmdw_ipc.h new file mode 100644 index 0000000..ce978f1 --- /dev/null +++ b/mdw/include/kmdw_ipc.h @@ -0,0 +1,73 @@ +/** + * @file kmdw_ipc.h + * @brief IPC APIs + * + * @copyright Copyright (c) 2022 Kneron Inc. All rights reserved. + */ + +#ifndef __KMDW_IPC_H_ +#define __KMDW_IPC_H_ + +#include "cmsis_os2.h" +#include "ipc.h" + +typedef void (*ipc_handler_t)(struct kdp_img_raw_s *p_raw_image, int state); + +/** + * @brief Initialize NPU functionality + * @param ipc_handler IPC callback + */ +void kmdw_ipc_initialize(ipc_handler_t ipc_handler); + +/** + * @brief Set model information + * @param model_info_addr model information address + * @param info_idx information index + * @param slot_idx slot index + */ +void kmdw_ipc_set_model(struct kdp_model_s *model_info_addr, uint32_t info_idx, int32_t slot_idx); + +/** + * @brief Set active model index + * @param index model slot index + */ +void kmdw_ipc_set_model_active(uint32_t index); + +/** + * @brief Set active image index + * @param index image index + */ +void kmdw_ipc_set_image_active(uint32_t index); + +/** + * @brief Set SCPU debug level + * @param lvl level + */ +void kdrv_ncpu_set_scpu_debug_lvl(uint32_t lvl); + +/** + * @brief Set NCPU debug level + * @param lvl level + */ +void kdrv_ncpu_set_ncpu_debug_lvl(uint32_t lvl); + +/** + * @brief Trigger NCPU interrupt + * @param ipc_idx IPC channel to trigger + */ +void kmdw_ipc_trigger_int(int ipc_cmd); + +/** + * @brief Get scpu_to_ncpu_t point + * @return IPC struct + */ +scpu_to_ncpu_t* kmdw_ipc_get_output(void); + +/** + * @brief Get ncpu_to_scpu_result_t point + * @return IPC struct + */ +ncpu_to_scpu_result_t* kmdw_ipc_get_input(void); + + +#endif diff --git a/mdw/include/kmdw_memory.h b/mdw/include/kmdw_memory.h new file mode 100644 index 0000000..857ed1b --- /dev/null +++ b/mdw/include/kmdw_memory.h @@ -0,0 +1,72 @@ +/** + * @file kmdw_memory.h + * @brief ddr memory access APIs + * + * @copyright Copyright (c) 2019 Kneron Inc. All rights reserved. + */ + +#ifndef __KMDW_MEMORY_H_ +#define __KMDW_MEMORY_H_ + +#include + +#define ALIGN_16BYTE 16 /**< 16 byte alignment annotation */ +#define ALIGN_64BYTE 64 /**< 64 byte aligement annotation */ + +#define ALIGN16(n) ((n + ALIGN_16BYTE - 1) & ~( ALIGN_16BYTE - 1)) +#define ALIGN16_FLOOR(n) ((n) & ~(ALIGN_16BYTE - 1)) + +#define ALIGN64(n) ((n + ALIGN_64BYTE - 1) & ~(ALIGN_64BYTE - 1)) +#define ALIGN64_FLOOR(n) ((n) & ~(ALIGN_64BYTE - 1)) + + +/** + * @brief To initialize available DDR block + * @param[in] start_addr the start address of DDR block(bigger address) + * @param[in] end_addr the end address of DDR block(smaller address) + */ +void kmdw_ddr_init(uint32_t start_addr, uint32_t end_addr); + + +/** + * @brief to set ddr boundary address(smaller address) + * @param[in] boundary the address of boundary + * @return 0: ok, -1: failed(cross available boundary) + * @notes + * once boundary address is updated, all reserved blocks + * might become invalid with the new boundary + * !!warning!! be sure you well know the boundary is safe to update + */ +int kmdw_ddr_set_ddr_boundary(uint32_t boundary); + + +/** + * @brief to allocate DDR memory + * @param[in] numbtye size in byte + * @return the address of allocated block + */ +uint32_t kmdw_ddr_reserve(uint32_t numbyte); + +/** + * @brief to get available DDR block tail address + * @return uint32_t + */ +uint32_t kmdw_ddr_get_heap_tail(void); + +/** + * @brief To store DDR block for system reserve + * + * @param[in] start_addr the start address of system reserve + * @param[in] end_addr the end address of system reserve + */ +void kmdw_ddr_store_system_reserve(uint32_t start_addr, uint32_t end_addr); + +/** + * @brief To get DDR block and size of the system reserve + * @param[in] start_addr [output] the start address of the system reserve + * @param[in] end_addr [output] the size of the system reserve + */ +void kmdw_ddr_get_system_reserve(uint32_t *start_addr, uint32_t *ddr_size); + +#endif + diff --git a/mdw/include/kmdw_memxfer.h b/mdw/include/kmdw_memxfer.h new file mode 100644 index 0000000..79dd71c --- /dev/null +++ b/mdw/include/kmdw_memxfer.h @@ -0,0 +1,29 @@ +/** + * @file kmdw_memxfer.h + * @brief memory operation between fash/ddr + * + * @copyright Copyright (c) 2019 Kneron Inc. All rights reserved. + */ +#ifndef __MEMXFER_H__ +#define __MEMXFER_H__ + + +#include "base.h" +#include "cmsis_os2.h" + +#define MEMXFER_OPS_NONE 0x00 /**< default op */ +#define MEMXFER_OPS_CPU 0x01 /**< transfer by CPU */ +#define MEMXFER_OPS_DMA 0x02 /**< transfer by DMA */ + +extern const struct s_kdp_memxfer kdp_memxfer_module; + +struct s_kdp_memxfer { + int (*init)(uint8_t flash_mode, uint8_t mem_mode); + int (*flash_to_ddr)(uint32_t dst, uint32_t src, size_t bytes); + int (*ddr_to_flash)(uint32_t dst, uint32_t src, size_t bytes); + int (*flash_sector_erase64k)(uint32_t addr); + int (*flash_to_niram)(int part_idx); + uint8_t (*flash_get_device_id)(void); +} ; + +#endif diff --git a/mdw/include/kmdw_model.h b/mdw/include/kmdw_model.h new file mode 100644 index 0000000..3fbf66c --- /dev/null +++ b/mdw/include/kmdw_model.h @@ -0,0 +1,314 @@ +/** + * @file kmdw_model.h + * @brief model manager APIs + * + * @copyright Copyright (c) 2019 Kneron Inc. All rights reserved. + */ +#ifndef __KMDW_MODEL_H__ +#define __KMDW_MODEL_H__ + +#include "cmsis_os2.h" +#include "base.h" +#include "ipc.h" /* for MULTI_MODEL_MAX */ +#include "model_type.h" + + +#define KMDW_MODEL_ALL_MODELS -1 /**< A term means ALL_MODELS */ +#define KMDW_MODEL_MAX_MODEL_COUNT MULTI_MODEL_MAX /**< MAX model count for DME and flash */ + +/* These crc values will ONLY change if model is changed in FLASH */ +#define MODEL_INFO_SUM32_VALUE 0x00eee074 /**< SUM32 value */ + +#define MODEL_IN_DDR 1 /**< - */ +#define MODEL_IN_FLASH 0 /**< - */ + +/** + * @brief npu data format + */ +enum kmdw_model_data_layout { + DATA_FMT_UNKNOWN = -1, + DATA_FMT_4W4C8B = 16, + DATA_FMT_16W1C8B = 8 +}; + +/** + * @brief return code of kmdw_model_run() + */ +enum kmdw_model_rc { + // 0 - 9 is reserved for ncpu return + // defined in ipc.h + // IMAGE_STATE_INACTIVE == 0 + // IMAGE_STATE_ACTIVE == 1 + // IMAGE_STATE_NPU_DONE == 2 + // IMAGE_STATE_DONE == 3 + KMDW_MODEL_RUN_RC_ABORT = 10, /**< return code: abort */ + KMDW_MODEL_RUN_RC_ERROR = 11, /**< return code: error */ + KMDW_MODEL_RUN_RC_END /**< dummy item for enum table end */ +}; + +/** + * @brief data structure of model run time + */ +typedef struct kmdw_model_img_run_time_s { + uint32_t round_trip_time; /**< round trip time */ + uint32_t pre_proc_time; /**< pre process time */ + uint32_t npu_proc_time; /**< npu process time */ + uint32_t post_proc_time; /**< post process time */ +} kmdw_model_run_time_t; + +/** + * @brief a mask for easy read fw_info data + */ +typedef struct kmdw_model_fw_info_s { + uint32_t model_count; /**< model count */ + struct kdp_model_s models[1]; /**< the address of dynamical count of models */ +} kmdw_model_fw_info_t; + +/** + * @brief a mask for easy read fw_info_ext data + */ +typedef struct kmdw_model_fw_info_ext_s { + uint32_t model_dram_addr_end; /**< model end address */ + uint32_t model_total_size; /**< model total size */ + uint32_t model_checksum; /**< checksum */ +} kmdw_model_fw_info_ext_t; + +/** + * @brief a basic descriptor for a input/output node in model + */ +typedef struct +{ + uint32_t index; /**< index of node */ + uint32_t shape_npu_len; /**< length of npu shape */ + uint32_t shape_npu[4]; /**< npu shape BxCxHxW (Compatable with KL720 NEFv1 4-dims shape interface) */ + uint32_t data_layout; /**< npu memory layout */ + float scale; /**< scale of node (KL520 only support layer wised quantization param) */ + int32_t radix; /**< radix of node (KL520 only support layer wised quantization param) */ +} kmdw_model_tensor_descriptor_t; + +/* ############################ + * ## Public Functions ## + * ############################ */ + +/** + * @brief Init model functionality + */ +void kmdw_model_init(void); + +/** + * @brief A wrapper of load_model from flash + * @param model_index_p: model info index, + * 0-n: info_index of model to load + * -1 means to load all models + * @return 0: failes; 1: OK(means 1 model is loaded) + */ +int32_t kmdw_model_load_model(int8_t model_info_index_p); + + +/** + * @brief A wrapper of load_model_info + * @param [in] is_model_from_ddr: if model is from ddr/host command + * @return reloaded model count; 0 means failed + */ +int32_t kmdw_model_reload_model_info(bool from_ddr); + + +/** + * @brief Refresh all models + * @return refreshed model count; 0 means failed + */ +int32_t kmdw_model_refresh_models(void); + + +/** + * @brief Output model_info of specified index + * @param[in] idx_p the index of programmed models + * @return model_info defined in ipc.h + */ +struct kdp_model_s* kmdw_model_get_model_info(int idx_p); + + +/** + * @brief Output total number of models and all model IDs + * @param[in] trust_ddr_data if true, no need to check validness of ddr data + * @return a list of model count, id0, id1, id2 + * @note only obtain data from ddr space + * model must be loaded from file or flash to ddr first + */ +uint32_t *kmdw_model_get_all_model_info(bool trust_ddr_data); + +/** + * @brief Output model end address defined in model file + * @param[in] trust_ddr_data if true, no need to check validness of ddr data + * @return model end address when loaded + * @note only obtain data from ddr space + * model must be loaded from file or flash to ddr first + */ +uint32_t kmdw_model_get_model_end_addr(bool trust_ddr_data); + +/** + * @brief Output crc value + * @param[in] trust_ddr_data if true, no need to check validness of ddr data + * @return crc value + * @note only obtain data from ddr space + * model must be loaded from file or flash to ddr first + */ +uint32_t kmdw_model_get_crc(bool trust_ddr_data); + +/** + * @brief Get the buffer address of fw_info + * @param[in] trust_ddr_data if true, no need to check validness of ddr data + * @return the buffer address of fw_info or NULL when model is not loaded + */ +kmdw_model_fw_info_t* kmdw_model_get_fw_info(bool trust_ddr_data); + + +/** + * @brief Check if a model is in flash + * @param[in] model_type model type + * @return 1 - the model is in flash; 0 - not in flash + */ +int kmdw_model_is_model_in_flash(uint32_t model_type); + + +/** + * @brief Specify output address for model run in ncpu/npu + * @return always 0 + * @note must be called after kmdw_model_config_model() + */ +int32_t kmdw_model_config_result(osEventFlagsId_t result_evt, uint32_t result_evt_flag); + + +/** + * @brief Config model image + * @param img_cfg image config + * @param ext_param extra param + */ +void kmdw_model_config_img(struct kdp_img_cfg *img_cfg, void *ext_param); + + +/** + * @brief Get raw image config + * @param idx image index + * @return raw image config + */ +struct kdp_img_raw_s* kmdw_model_get_raw_img(int idx); + + +/** + * @brief Run model + * @param tag model tag + * @param output model output + * @param model_type model type + * @param dme DME mode + * @return kmdw_model_rc + */ +int kmdw_model_run(const char *tag, void *output, uint32_t model_type, bool dme); + + +/** + * @brief Abort model execution + */ +void kmdw_model_abort(void); + + +/** + * @brief Get round-trip/pre/npu/post times + * @param [in] img_idx raw image index + * @param [out] run_time run time of pre/npu/post/ + * @return void + */ +void kmdw_model_get_run_time(int img_idx, kmdw_model_run_time_t *run_time); + + +/** + * @brief Check if a model is loaded in memory + * @param[in] model_type model type + * @return 1 - loaded in memory; 0 - not loaded + */ +int kmdw_model_is_model_loaded(uint32_t model_type); + + +/** + * @brief Set model storage location + * @param[in] model_inddr // model is from flash : false, ddr : true + */ +void kmdw_model_set_location(bool model_inddr); + + +/** + * @brief Get model storage location + * @return 1 - DDR; 0 - Flash + */ +bool kmdw_model_get_location(void); + + +/** + * @brief Get model input tensor/node number + * @param[in] model_type model type + * @return input tensor/node number, 0 means failed + */ +int kmdw_model_get_input_tensor_num(uint32_t model_type); + + +/** + * @brief Get model input tensor/node information + * @param[in] model_type model type + * @param[in] tensor_idx input tensor index + * @param[out] tensor_info input tensor information + * @return 1: success; 0: fail + */ +int kmdw_model_get_input_tensor_info(uint32_t model_type, uint32_t tensor_idx, kmdw_model_tensor_descriptor_t *tensor_info); + + +/** + * @brief Get model output tensor/node number + * @param[in] model_type model type + * @return output tensor/node number, 0 means failed + */ +int kmdw_model_get_output_tensor_num(uint32_t model_type); + + +/** + * @brief Check if a model is loaded in memory + * @param[in] model_type model type + * @param[in] tensor_idx output tensor index + * @param[out] tensor_info output tensor information + * @return 1: success; 0: fail + */ +int kmdw_model_get_output_tensor_info(uint32_t model_type, uint32_t tensor_idx, kmdw_model_tensor_descriptor_t *tensor_info); + +#ifdef EMBED_CMP_NPU +/** + * @brief A wrapper of adding or update specific model configuration + * @param model_type model type + * @param cmd_len model command length + * @param wt_len model weight length + * @param input_len input data length + * @param output_len output data length + * @param setup_len setup data length + * @param cmd_mem_addr model command memory address + * @param wt_mem_addr model weight memory address + * @param input_mem_addr input data memory address + * @param output_mem_addr output data memory address + * @param setup_mem_addr setup data memory address + * @return int8_t 0: config ok + * -1: model not found + */ +int8_t kmdw_model_add_update_model(uint32_t model_type, + int cmd_len, int wt_len, int input_len, int output_len, int setup_len, + uint32_t cmd_mem_addr, uint32_t wt_mem_addr, + uint32_t input_mem_addr, uint32_t output_mem_addr, uint32_t setup_mem_addr); + +#endif // EMBED_CMP_NPU + +#if DEBUG + +/** + * @brief Dump model debug info + */ +void kmdw_model_dump_model_info(void); + +#endif + +#endif diff --git a/mdw/include/kmdw_power_manager.h b/mdw/include/kmdw_power_manager.h new file mode 100644 index 0000000..7662550 --- /dev/null +++ b/mdw/include/kmdw_power_manager.h @@ -0,0 +1,64 @@ +/** + * @file kmdw_power_manager.h + * @brief Power Manager driver + * + * @copyright Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#ifndef __KMDW_POWER_MANAGER_H__ +#define __KMDW_POWER_MANAGER_H__ + +enum kmdw_power_manager_device_id { + KMDW_POWER_MANAGER_DEVICE_NONE = 0, + KMDW_POWER_MANAGER_DEVICE_CAMERA1, + KMDW_POWER_MANAGER_DEVICE_CAMERA2, + KMDW_POWER_MANAGER_DEVICE_DISPLAY1, + KMDW_POWER_MANAGER_DEVICE_DISPLAY2, + KMDW_POWER_MANAGER_DEVICE_HOST_COM, + KMDW_POWER_MANAGER_DEVICE_DFU_UPDATE, + KMDW_POWER_MANAGER_DEVICE_NCPU_INFERENCE, + KMDW_POWER_MANAGER_DEVICE_UNUSED4, + KMDW_POWER_MANAGER_DEVICE_UNUSED5, + KMDW_POWER_MANAGER_DEVICE_UNUSED6, + KMDW_POWER_MANAGER_DEVICE_UNUSED7, + KMDW_POWER_MANAGER_DEVICE_UNUSED8, + KMDW_POWER_MANAGER_DEVICE_MAX, +}; + +/* Prototypes for callback functions */ +typedef int (*kmdw_power_manager_call)(enum kmdw_power_manager_device_id dev_id); +typedef void (*kmdw_power_manager_ptn_handler)(int released); + +struct kmdw_power_manager_s { + kmdw_power_manager_call nap; + kmdw_power_manager_call wakeup_nap; + kmdw_power_manager_call deep_nap; + kmdw_power_manager_call wakeup_deep_nap; + kmdw_power_manager_call sleep; + kmdw_power_manager_call wakeup_sleep; + kmdw_power_manager_call deep_sleep; + kmdw_power_manager_call wakeup_deep_sleep; +}; + +/* PM APIs */ +__NO_RETURN void kmdw_power_manager_cpu_idle(void); +void kmdw_power_manager_init(void); +void kmdw_power_manager_error_notify(uint32_t code, void *object_id); +void kmdw_power_manager_reset(void); +void kmdw_power_manager_sleep(void); +void kmdw_power_manager_deep_sleep(void); +void kmdw_power_manager_shutdown(void); + +/* Registration APIs */ +int kmdw_power_manager_register( + enum kmdw_power_manager_device_id dev_id, + struct kmdw_power_manager_s *pm_p); + +void kmdw_power_manager_unregister( + enum kmdw_power_manager_device_id dev_id, + struct kmdw_power_manager_s *pm_p); + +void kmdw_power_manager_power_button_register(kmdw_power_manager_ptn_handler button_handler); + +#endif diff --git a/mdw/include/kmdw_sensor.h b/mdw/include/kmdw_sensor.h new file mode 100644 index 0000000..0ff5c43 --- /dev/null +++ b/mdw/include/kmdw_sensor.h @@ -0,0 +1,188 @@ +/** + * @file kmdw_sensor.h +* @brief middleware for sensor device + * + * @copyright Copyright (c) 2020 Kneron Inc. All rights reserved. + */ + +#ifndef __KMDW_SENSOR_H__ +#define __KMDW_SENSOR_H__ + +#include +#include "base.h" +#include "kmdw_camera.h" +#include "kdev_sensor.h" + +#define fourcc(a, b, c, d) \ + ((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) + +#define PIX_FMT_YCBCR fourcc('Y', 'B', 'Y', 'R') /**< fourcc YBYR */ +#define PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /**< fourcc RGBP */ +#define PIX_FMT_RAW10 fourcc('R', 'A', '1', '0') /**< fourcc ra10 */ +#define PIX_FMT_RAW8 fourcc('R', 'A', 'W', '8') /**< fourcc raw8 */ + +enum colorspace { + COLORSPACE_RGB = 0, + COLORSPACE_YUV = 1, + COLORSPACE_RAW = 2, +}; + +struct sensor_device { + uint16_t addr; /* chip address - NOTE: 7bit */ +}; + +struct sensor_init_seq { + uint16_t addr; + uint8_t value; +}__attribute__((packed)); + +struct sensor_datafmt_info { + uint32_t fourcc; + enum colorspace colorspace; +}; + +struct sensor_win_size { + uint32_t width; + uint32_t height; +}; + +/** + * @brief set sensor power function + * + * @param[in] cam_idx camera id + * @param[in] on power on/off, 1:on, 0:off + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_s_power(uint32_t cam_idx, uint32_t on); + +/** + * @brief sensor reset function + * + * @param[in] cam_idx camera id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_reset(uint32_t cam_idx); + +/** + * @brief set sensor stream function + * + * @param[in] cam_idx camera id + * @param[in] enable stream enable/disable, 1:enable, 0:disable + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_s_stream(uint32_t cam_idx, uint32_t enable); + +/** + * @brief set sensor enum function + * + * @param[in] cam_idx camera id + * @param[in] index index + * @param[out] fourcc point of fourcc + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_enum_fmt(uint32_t cam_idx, uint32_t index, uint32_t *fourcc); + +/** + * @brief set sensor format function + * + * @param[in] cam_idx camera id + * @param[in] format point of cam_format + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_set_fmt(uint32_t cam_idx, struct cam_format *format); + +/** + * @brief get sensor format function + * + * @param[in] cam_idx camera id + * @param[out] format point of cam_format + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_get_fmt(uint32_t cam_idx, struct cam_format *format); + +/** + * @brief get sensor gain function + * + * @param[in] cam_idx camera id + * @param[in] gain1 aec gain parameter 1 + * @param[in] gain2 aec gain parameter 2 + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_set_gain(uint32_t cam_idx, uint32_t gain1, uint32_t gain2); + +/** + * @brief sensor set ae controller ROI area function + * + * @param[in] cam_idx camera id + * @param[in] aec_p point of cam_sensor_aec + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_set_aec(uint32_t cam_idx, struct cam_sensor_aec *aec_p); + +/** + * @brief sensor set exposure time function + * + * @param[in] cam_idx camera id + * @param[in] gain1 exposure time parameter 1 + * @param[in] gain2 exposure time parameter 2 + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_set_exp_time(uint32_t cam_idx, uint32_t gain1, uint32_t gain2); + +/** + * @brief sensor get lum and other parameter function + * + * @param[in] cam_idx camera id + * @param[out] expo exposure time parameter + * @param[out] pre_gain exposure time parameter + * @param[out] post_gain exposure time parameter + * @param[out] global_gain exposure time parameter + * @param[in] y_average exposure time parameter 2 + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_get_lux(uint32_t cam_idx, uint16_t *expo, uint8_t *pre_gain, uint8_t *post_gain, uint8_t *global_gain, uint8_t *y_average); + +/** + * @brief sensor set nir led on/off function + * + * @param[in] cam_idx camera id + * @param[in] on LED on/off cmd, 1: on, 0:off + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_led_switch(uint32_t cam_idx, uint32_t on); + +/** + * @brief sensor set image mirror on/off function + * + * @param[in] cam_idx camera id + * @param[in] enable enable/disable cmd, 1: enable, 0:disable + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_set_mirror(uint32_t cam_idx, uint32_t enable); + +/** + * @brief sensor set image flip on/off function + * + * @param[in] cam_idx camera id + * @param[in] enable enable/disable cmd, 1: enable, 0:disable + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_set_flip(uint32_t cam_idx, uint32_t enable); + +/** + * @brief sensor get device ID function + * + * @param[in] cam_idx camera id + * @return sensor id + */ +uint32_t kmdw_sensor_get_dev_id(uint32_t cam_idx); + +/** + * @brief register sensor + * + * @param[in] cam_idx camera id + * @param[in] sensor_idx sensor id + * @return kmdw_status_t see @ref kmdw_status_t + */ +kmdw_status_t kmdw_sensor_register(uint32_t cam_idx, uint32_t sensor_idx); +#endif // __KMDW_SENSOR_H__ diff --git a/mdw/include/kmdw_status.h b/mdw/include/kmdw_status.h new file mode 100644 index 0000000..59b1478 --- /dev/null +++ b/mdw/include/kmdw_status.h @@ -0,0 +1,21 @@ + +/** + * @file kmdw_status.h + * @brief status code + * + * @copyright Copyright (c) 2020 Kneron Inc. All rights reserved. + */ + +#ifndef __KMDW_STATUS_H__ +#define __KMDW_STATUS_H__ + +/** + * @brief enum for status code + */ +typedef enum +{ + KMDW_STATUS_OK = 0, /**< mdw status OK */ + KMDW_STATUS_ERROR, /**< mdw status error */ +} kmdw_status_t; + +#endif /* __KMDW_STATUS_H__ */ diff --git a/mdw/include/kmdw_system.h b/mdw/include/kmdw_system.h new file mode 100644 index 0000000..652cef0 --- /dev/null +++ b/mdw/include/kmdw_system.h @@ -0,0 +1,52 @@ +/** + * @file kmdw_memory.h + * @brief ddr memory access APIs + * + * @copyright Copyright (c) 2019 Kneron Inc. All rights reserved. + */ + +#ifndef __KMDW_SYSTEM_H__ +#define __KMDW_SYSTEM_H__ + +#include "base.h" + +/** + * @brief Wakeup ncpu + * + * @param[in] boot_loader_flag bootloader flag, 0: none, 1: add 200ms delay + * @param[in] wakeup_all wakeup_all, 0: none, 1: wake up all ncpu clock + * @return N/A + */ +void system_wakeup_ncpu(int32_t boot_loader_flag, uint8_t wakeup_all); + + +/** + * @brief Reload ncpu firmware from flash + * + * @return N/A + */ +void reload_ncpu_fw(void); + + +/** + * @brief System initialize + * + * @param[in] reset_flag = 0, just launch ncpu + * <>0, load and launch ncpu + * < 0, not using mpu + * @return kdrv_status_t 0: KDRV_STATUS_OK, otherwise: wrong checksum + */ +uint32_t load_ncpu_fw(int32_t reset_flag); + + +/** + * @brief check fw image via sum32 method + * @details Calculate sum32 of scpu/ncpu fw and compare to the value which + * resides at the end of flash + * + * @param[in] fw_type SCPU_FW, NCPU_FW + * @return kdrv_status_t 0: KDRV_STATUS_OK, otherwise: wrong calculated value + */ +uint32_t system_check_fw_image(int32_t fw_type); + +#endif diff --git a/mdw/include/kmdw_usbh.h b/mdw/include/kmdw_usbh.h new file mode 100644 index 0000000..86e01b4 --- /dev/null +++ b/mdw/include/kmdw_usbh.h @@ -0,0 +1,368 @@ +/** + * @file kmdw_usbh.h + * @brief usbh 2.0 APIs + * + * @copyright Copyright (c) 2019 Kneron Inc. All rights reserved. + */ + +#ifndef __KMDW_USBH_H__ +#define __KMDW_USBH_H__ + +#include +#include + +#include "usb_def.h" + +/// ==== USB Constants and Defines ==== + +/// Status code values returned by USB library functions. +typedef enum +{ + usbOK = 0U, ///< Function completed with no error + + usbTimeout, ///< Function completed; time-out occurred + usbInvalidParameter, ///< Invalid Parameter error: a mandatory parameter was missing or specified an incorrect object + + usbThreadError = 0x10U, ///< CMSIS-RTOS Thread creation/termination failed + usbTimerError, ///< CMSIS-RTOS Timer creation/deletion failed + usbSemaphoreError, ///< CMSIS-RTOS Semaphore creation failed + usbMutexError, ///< CMSIS-RTOS Mutex creation failed + + usbControllerError = 0x20U, ///< Controller does not exist + usbDeviceError, ///< Device does not exist + usbDriverError, ///< Driver function produced error + usbDriverBusy, ///< Driver function is busy + usbMemoryError, ///< Memory management function produced error + usbNotConfigured, ///< Device is not configured (is connected) + usbClassErrorADC, ///< Audio Device Class (ADC) error (no device or device produced error) + usbClassErrorCDC, ///< Communication Device Class (CDC) error (no device or device produced error) + usbClassErrorHID, ///< Human Interface Device (HID) error (no device or device produced error) + usbClassErrorMSC, ///< Mass Storage Device (MSC) error (no device or device produced error) + usbClassErrorCustom, ///< Custom device Class (Class) error (no device or device produced error) + usbUnsupportedClass, ///< Unsupported Class + + usbTransferStall = 0x40U, ///< Transfer handshake was stall + usbTransferError, ///< Transfer error + + usbUnknownError = 0xFFU ///< Unspecified USB error +} usbStatus; + +/* USB Host Constants and Defines */ + +/// USB Host Notification enumerated constants +typedef enum +{ + USBH_NOTIFY_CONNECT = 0U, ///< Port connection happened + USBH_NOTIFY_DISCONNECT, ///< Port disconnection happened + USBH_NOTIFY_OVERCURRENT, ///< Port overcurrent happened + USBH_NOTIFY_REMOTE_WAKEUP, ///< Port remote wakeup signaling happened + USBH_NOTIFY_READY, ///< Device was successfully enumerated, initialized and is ready for communication + USBH_NOTIFY_UNKNOWN_DEVICE, ///< Device was successfully enumerated but there is no driver for it + USBH_NOTIFY_INSUFFICIENT_POWER, ///< Device requires more power consumption than available + USBH_NOTIFY_CONFIGURATION_FAILED, ///< Device was not successfully configured (not enough resources) + USBH_NOTIFY_INITIALIZATION_FAILED ///< Device was not successfully initialized +} USBH_NOTIFY; + +/* USB Host Pipe handle type */ +typedef uint32_t USBH_PIPE_HANDLE; + +// ==== USB Host Functions ==== + +/// \brief Get version of USB Host stack +/// \return version (major.minor.revision : mmnnnrrrr decimal) +extern uint32_t USBH_GetVersion(void); + +/// \brief Initialize USB Host stack and controller +/// \param[in] ctrl index of USB Host controller. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_Initialize(uint8_t ctrl); + +/// \brief De-initialize USB Host stack and controller +/// \param[in] ctrl index of USB Host controller. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_Uninitialize(uint8_t ctrl); + +/// \brief Suspend a root HUB port on specified controller +/// \param[in] ctrl index of USB Host controller. +/// \param[in] port root HUB port. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_Port_Suspend(uint8_t ctrl, uint8_t port); + +/// \brief Resume a root HUB port on specified controller +/// \param[in] ctrl index of USB Host controller. +/// \param[in] port root HUB port. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_Port_Resume(uint8_t ctrl, uint8_t port); + +/// \brief Get index of USB Host controller to which USB Device is connected +/// \param[in] device index of USB Device. +/// \return index of USB Host controller or non-existing USB Host controller : +/// - value != 255 : index of USB Host controller +/// - value 255 : non-existing USB Host controller +extern uint8_t USBH_Device_GetController(uint8_t device); + +/// \brief Get index of USB Host Root HUB port to which USB Device is connected +/// \param[in] device index of USB Device. +/// \return index of USB Host Root HUB port or non-existing USB Host Root HUB port : +/// - value <= 15 : index of USB Host Root HUB port +/// - value 255 : non-existing USB Host Root HUB port +extern uint8_t USBH_Device_GetPort(uint8_t device); + +/// \brief Get status of USB Device +/// \param[in] device index of USB Device. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_Device_GetStatus(uint8_t device); + +/// \brief Get communication speed of USB Device +/// \param[in] device index of USB Device. +/// \return communication speed : +/// - USB_SPEED_LOW = low speed +/// - USB_SPEED_FULL = full speed +/// - USB_SPEED_HIGH = high speed +extern int32_t USBH_Device_GetSpeed(uint8_t device); + +/// \brief Get communication address of USB Device +/// \param[in] device index of USB Device. +/// \return enumerated address or invalid address : +/// - value <= 127 : enumerated address +/// - value 255 : invalid address +extern uint8_t USBH_Device_GetAddress(uint8_t device); + +/// \brief Get Vendor ID (VID) of USB Device +/// \param[in] device index of USB Device. +/// \return Vendor ID. +extern uint16_t USBH_Device_GetVID(uint8_t device); + +/// \brief Get Product ID (PID) of USB Device +/// \param[in] device index of USB Device. +/// \return Product ID. +extern uint16_t USBH_Device_GetPID(uint8_t device); + +/// \brief Get String Descriptor of USB Device +/// \param[in] device index of USB Device. +/// \param[in] index index of string descriptor. +/// \param[in] language_id language ID. +/// \param[out] descriptor_data pointer to where descriptor data will be read. +/// \param[in] descriptor_length maximum descriptor length. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_Device_GetStringDescriptor(uint8_t device, uint8_t index, uint16_t language_id, uint8_t *descriptor_data, uint16_t descriptor_length); + +/// \brief Callback function called when some event has happened on corresponding controller and port +/// \param[in] ctrl index of USB Host controller. +/// \param[in] port index of Root HUB port. +/// \param[in] device index of USB Device : +/// - value <= 127: index of of USB Device for device notifications +/// - value 255: no device information for port notifications +/// \param[in] notify notification : +/// - USBH_NOTIFY_CONNECT = Port connection happened +/// - USBH_NOTIFY_DISCONNECT = Port disconnection happened +/// - USBH_NOTIFY_OVERCURRENT = Port overcurrent happened +/// - USBH_NOTIFY_REMOTE_WAKEUP = Port remote wakeup signaling happened +/// - USBH_NOTIFY_READY = Device was successfully enumerated, initialized and is ready for communication +/// - USBH_NOTIFY_UNKNOWN_DEVICE = Device was successfully enumerated but there is no driver for it +/// - USBH_NOTIFY_INSUFFICIENT_POWER = Device requires more power consumption than available +/// - USBH_NOTIFY_CONFIGURATION_FAILED = Device was not successfully configured (not enough resources) +/// - USBH_NOTIFY_INITIALIZATION_FAILED = Device was not successfully initialized +extern void USBH_Notify(uint8_t ctrl, uint8_t port, uint8_t device, USBH_NOTIFY notify); + +// ==== USB Host Custom Class Functions ==== + +/// \brief Get Device instance of Custom Class Device +/// \param[in] instance instance of Custom Class Device. +/// \return instance of Device or non-existing Device instance : +/// - value <= 127 : instance of Device +/// - value 255 : non-existing Device instance +extern uint8_t USBH_CustomClass_GetDevice(uint8_t instance); + +/// \brief Get status of Custom Class Device +/// \param[in] instance instance of Custom Class Device. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_CustomClass_GetStatus(uint8_t instance); + +/// \brief Callback function called when custom class device is connected and needs +/// to configure resources used by custom class device instance +/// \param[in] device index of USB Device. +/// \param[in] ptr_dev_desc pointer to device descriptor. +/// \param[in] ptr_cfg_desc pointer to configuration descriptor. +/// \return index of configured custom class device instance or configuration failed : +/// - value <= 127 : index of configured custom class device instance +/// - value 255 : configuration failed +extern uint8_t USBH_CustomClass_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc); + +/// \brief Callback function called when custom class device is disconnected and needs +/// to de-configure resources used by custom class device instance +/// \param[in] instance index of custom class device instance. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_CustomClass_Unconfigure(uint8_t instance); + +/// \brief Callback function called when custom class device is connected and needs +/// to initialize custom class device instance +/// \param[in] instance index of custom class device instance. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_CustomClass_Initialize(uint8_t instance); + +/// \brief Callback function called when custom class device is disconnected and needs +/// to de-initialize custom class device instance +/// \param[in] instance index of custom class device instance. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_CustomClass_Uninitialize(uint8_t instance); + +/// \brief Create Pipe +/// \param[in] device index of USB Device. +/// \param[in] ep_addr endpoint address : +/// - ep_addr.0..3 : address +/// - ep_addr.7 : direction +/// \param[in] ep_type endpoint type. +/// \param[in] ep_max_packet_size endpoint maximum packet size. +/// \param[in] ep_interval endpoint polling interval. +/// \return pipe handle or pipe creation failed : +/// - value > 0 : pipe handle +/// - value 0 : pipe creation failed +extern USBH_PIPE_HANDLE USBH_PipeCreate(uint8_t device, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size, uint8_t ep_interval); + +/// \brief Update Pipe +/// \param[in] pipe_hndl pipe handle. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_PipeUpdate(USBH_PIPE_HANDLE pipe_hndl); + +/// \brief Delete Pipe +/// \param[in] pipe_hndl pipe handle. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_PipeDelete(USBH_PIPE_HANDLE pipe_hndl); + +/// \brief Reset Pipe (reset data toggle) +/// \param[in] pipe_hndl pipe handle. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_PipeReset(USBH_PIPE_HANDLE pipe_hndl); + +/// \brief Receive data on Pipe +/// \param[in] pipe_hndl pipe handle. +/// \param[out] buf buffer that receives data. +/// \param[in] len maximum number of bytes to receive. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_PipeReceive(USBH_PIPE_HANDLE pipe_hndl, uint8_t *buf, uint32_t len); + +/// \brief Get result of receive data operation on Pipe +/// \param[in] pipe_hndl pipe handle. +/// \return number of successfully received data bytes. +extern uint32_t USBH_PipeReceiveGetResult(USBH_PIPE_HANDLE pipe_hndl); + +/// \brief Send data on Pipe +/// \param[in] pipe_hndl pipe handle. +/// \param[in] buf buffer containing data bytes to send. +/// \param[in] len number of bytes to send. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_PipeSend(USBH_PIPE_HANDLE pipe_hndl, const uint8_t *buf, uint32_t len); + +/// \brief Get result of send data operation on Pipe +/// \param[in] pipe_hndl pipe handle. +/// \return number of successfully sent data bytes. +extern uint32_t USBH_PipeSendGetResult(USBH_PIPE_HANDLE pipe_hndl); + +/// \brief Abort send/receive operation on Pipe +/// \param[in] pipe_hndl pipe handle. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_PipeAbort(USBH_PIPE_HANDLE pipe_hndl); + +/// \brief Do a Control Transfer on Default Pipe +/// \param[in] device index of USB Device. +/// \param[in] setup_packet pointer to setup packet. +/// \param[in,out] data buffer containing data bytes to send or where data should be received in data stage of Control Transfer. +/// \param[in] len number of bytes to send or receive in data stage of Control Transfer. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_ControlTransfer(uint8_t device, const USB_SETUP_PACKET *setup_packet, uint8_t *data, uint32_t len); + +/// \brief Standard Device Request on Default Pipe - GET_STATUS +/// \param[in] device index of USB Device. +/// \param[in] recipient recipient. +/// \param[in] index interface or endpoint index. +/// \param[out] ptr_stat_dat pointer to where status data should be received. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_GetStatus(uint8_t device, uint8_t recipient, uint8_t index, uint8_t *ptr_stat_dat); + +/// \brief Standard Device Request on Default Pipe - CLEAR_FEATURE +/// \param[in] device index of USB Device. +/// \param[in] recipient recipient. +/// \param[in] index interface or endpoint index. +/// \param[in] feature_selector feature selector. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_ClearFeature(uint8_t device, uint8_t recipient, uint8_t index, uint8_t feature_selector); + +/// \brief Standard Device Request on Default Pipe - SET_FEATURE +/// \param[in] device index of USB Device. +/// \param[in] recipient recipient. +/// \param[in] index interface or endpoint index. +/// \param[in] feature_selector feature selector. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_SetFeature(uint8_t device, uint8_t recipient, uint8_t index, uint8_t feature_selector); + +/// \brief Standard Device Request on Default Pipe - SET_ADDRESS +/// \param[in] device index of USB Device. +/// \param[in] device_address device address. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_SetAddress(uint8_t device, uint8_t device_address); + +/// \brief Standard Device Request on Default Pipe - GET_DESCRIPTOR +/// \param[in] device index of USB Device. +/// \param[in] recipient recipient. +/// \param[in] descriptor_type descriptor type. +/// \param[in] descriptor_index descriptor index. +/// \param[in] language_id language ID. +/// \param[out] descriptor_data pointer to where descriptor data will be read. +/// \param[in] descriptor_length maximum descriptor length. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_GetDescriptor(uint8_t device, uint8_t recipient, uint8_t descriptor_type, uint8_t descriptor_index, uint16_t language_id, uint8_t *descriptor_data, uint16_t descriptor_length); + +/// \brief Standard Device Request on Default Pipe - SET_DESCRIPTOR +/// \param[in] device index of USB Device. +/// \param[in] recipient recipient. +/// \param[in] descriptor_type descriptor type. +/// \param[in] descriptor_index descriptor index. +/// \param[in] language_id language ID. +/// \param[in] descriptor_data pointer to descriptor data to be written. +/// \param[in] descriptor_length descriptor length. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_SetDescriptor(uint8_t device, uint8_t recipient, uint8_t descriptor_type, uint8_t descriptor_index, uint16_t language_id, const uint8_t *descriptor_data, uint16_t descriptor_length); + +/// \brief Standard Device Request on Default Pipe - GET_CONFIGURATION +/// \param[in] device index of USB Device. +/// \param[out] ptr_configuration pointer to where configuration will be read. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_GetConfiguration(uint8_t device, uint8_t *ptr_configuration); + +/// \brief Standard Device Request on Default Pipe - SET_CONFIGURATION +/// \param[in] device index of USB Device. +/// \param[in] configuration configuration. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_SetConfiguration(uint8_t device, uint8_t configuration); + +/// \brief Standard Device Request on Default Pipe - GET_INTERFACE +/// \param[in] device index of USB Device. +/// \param[in] index interface index. +/// \param[out] ptr_alternate pointer to where alternate setting data will be read. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_GetInterface(uint8_t device, uint8_t index, uint8_t *ptr_alternate); + +/// \brief Standard Device Request on Default Pipe - SET_INTERFACE +/// \param[in] device index of USB Device. +/// \param[in] index interface index. +/// \param[in] alternate alternate setting. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_SetInterface(uint8_t device, uint8_t index, uint8_t alternate); + +/// \brief Standard Device Request on Default Pipe - SYNCH_FRAME +/// \param[in] device index of USB Device. +/// \param[in] index interface or endpoint index. +/// \param[out] ptr_frame_number pointer to where frame number data will be read. +/// \return status code that indicates the execution status of the function as defined with \ref usbStatus. +extern usbStatus USBH_DeviceRequest_SynchFrame(uint8_t device, uint8_t index, uint8_t *ptr_frame_number); + +// below is a set of extended functions for isochronous transfer +typedef void (*USBH_CB_ISR_Isoch_transfer)(uint32_t *payload, uint32_t length); + +extern USBH_PIPE_HANDLE USBH_Pipe_ISOCH_PipeDelete(USBH_PIPE_HANDLE pipe_hndl); +extern USBH_PIPE_HANDLE USBH_Pipe_ISOCH_PipeCreate(uint8_t device, uint8_t ep_addr, uint32_t wMaxPacketSize, uint8_t bInterval, uint8_t *buf, uint32_t buf_size); +extern usbStatus USBH_Pipe_ISOCH_Start(USBH_PIPE_HANDLE pipe_hndl, USBH_CB_ISR_Isoch_transfer isoch_cb); +extern usbStatus USBH_Pipe_ISOCH_Stop(USBH_PIPE_HANDLE pipe_hndl); + +#endif diff --git a/mdw/include/kmdw_utils_crc.h b/mdw/include/kmdw_utils_crc.h new file mode 100644 index 0000000..10d6354 --- /dev/null +++ b/mdw/include/kmdw_utils_crc.h @@ -0,0 +1,44 @@ +/** + * @file kmdw_utils_crc.h + * @brief Kneron crc driver header + * + * @copyright Copyright (c) 2018 Kneron, Inc. All rights reserved. + */ + +#ifndef __KMDW_UTILS_CRC_H__ +#define __KMDW_UTILS_CRC_H__ + +#include "base.h" + +#define CRC16_CONSTANT 0x8005 /**< crc16 constant value */ +#define ENABLE_CRC32 0 /**< enable CRC32 check or not */ + +/** + * @brief generate crc16 code + * @param[in] data data for calculation + * @param[in] size data size + */ +uint16_t kmdw_utils_crc_gen_crc16(uint8_t *data, uint32_t size); + +/** + * @brief generate sha32 + * @param[in] data data for calculation + * @param[in] size data size + */ +uint32_t kmdw_utils_crc_gen_sha32(uint8_t *data, uint32_t size); + +/** + * @brief generate sum32 + * @param[in] data data for calculation + * @param[in] size data size + */ +uint32_t kmdw_utils_crc_gen_sum32(uint8_t *data, uint32_t size); + +/** + * @brief generate crc32 code + * @param[in] data data for calculation + * @param[in] size data size + */ +uint32_t kmdw_utils_crc_gen_crc32(uint8_t *data, uint32_t size); + +#endif diff --git a/mdw/include/kmdw_uvc.h b/mdw/include/kmdw_uvc.h new file mode 100644 index 0000000..596760a --- /dev/null +++ b/mdw/include/kmdw_uvc.h @@ -0,0 +1,64 @@ +/** + * @file kmdw_uvc.h + * @brief Kneron usbh uvc control APIs + * + * @copyright Copyright (c) 2022 Kneron Inc. All rights reserved. + */ + +#ifndef __USBH_UVC_H__ +#define __USBH_UVC_H__ + +typedef enum +{ + SET_CUR = 0x01, + GET_CUR = 0x81, + GET_MIN = 0x82, + GET_MAX = 0x83, + // others +} UVC_VS_Request_t; + +typedef enum +{ + VS_PROBE_CONTROL = 0x100, + VS_COMMIT_CONTROL = 0x200, + // others +} UVC_VS_ControlSelector_t; + +typedef struct __attribute__((__packed__)) +{ + uint16_t bmHint; + uint8_t bFormatIndex; + uint8_t bFrameIndex; + uint32_t dwFrameInterval; + uint16_t wKeyFrameRate; + uint16_t wPFrameRate; + uint16_t wCompQuality; + uint16_t wCompWindowSize; + uint16_t wDelay; + uint32_t dwMaxVideoFrameSize; + uint32_t dwMaxPayloadTransferSize; +} UVC_PROBE_COMMIT_CONTROL; + +// Callback function called when UVC class device is connected and +extern uint8_t USBH_UVC_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc); + +extern USBH_PIPE_HANDLE USBH_UVC_PipeCreate_Isoch(uint8_t device, uint8_t ep_addr, uint32_t wMaxPacketSize, uint8_t bInterval); + +extern usbStatus USBH_UVC_PipeStart_Isoch(USBH_PIPE_HANDLE pipe_hndl); + +extern usbStatus USBH_UVC_PipeStop_Isoch(USBH_PIPE_HANDLE pipe_hndl); + +// Callback function called when custom class device is connected +extern usbStatus USBH_UVC_Initialize(uint8_t instance); + +extern usbStatus USBH_UVC_VS_Control(uint8_t device, UVC_VS_Request_t vs_req, UVC_VS_ControlSelector_t cs, UVC_PROBE_COMMIT_CONTROL *upc_ctrl); + +extern usbStatus USBH_UVC_Queue_Frame(USBH_PIPE_HANDLE pipe, uint32_t *frame_ptr, uint32_t size); + +// Callback function called when a frame is complete +#ifdef KDP_UVC +extern void USBH_UVC_Get_Frame(uint32_t *frame_ptr, uint32_t *frame_size, int *index); +#else +void USBH_UVC_Get_Frame(uint32_t *frame_ptr, uint32_t frame_size); +#endif +#endif diff --git a/mdw/include/usb_def.h b/mdw/include/usb_def.h new file mode 100644 index 0000000..e231abc --- /dev/null +++ b/mdw/include/usb_def.h @@ -0,0 +1,243 @@ +/*------------------------------------------------------------------------------ + * MDK Middleware - Component ::USB + * Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved. + *------------------------------------------------------------------------------ + * Name: usb_def.h + * Purpose: USB Definitions + *----------------------------------------------------------------------------*/ + +#ifndef __USB_DEF_H +#define __USB_DEF_H + +#include "cmsis_os2.h" + + +// USB Speed +#define USB_SPEED_LOW 0U +#define USB_SPEED_FULL 1U +#define USB_SPEED_HIGH 2U + +// USB PID Types +#define USB_PID_RESERVED 0U +#define USB_PID_OUT 1U +#define USB_PID_ACK 2U +#define USB_PID_DATA0 3U +#define USB_PID_PING 4U +#define USB_PID_SOF 5U +#define USB_PID_DATA2 7U +#define USB_PID_NYET 6U +#define USB_PID_SPLIT 8U +#define USB_PID_IN 9U +#define USB_PID_NAK 10U +#define USB_PID_DATA1 11U +#define USB_PID_PRE 12U +#define USB_PID_ERR 12U +#define USB_PID_SETUP 13U +#define USB_PID_STALL 14U +#define USB_PID_MDATA 15U + +// bmRequestType.Dir +#define USB_REQUEST_HOST_TO_DEVICE 0U +#define USB_REQUEST_DEVICE_TO_HOST 1U + +// bmRequestType.Type +#define USB_REQUEST_STANDARD 0U +#define USB_REQUEST_CLASS 1U +#define USB_REQUEST_VENDOR 2U +#define USB_REQUEST_RESERVED 3U + +// bmRequestType.Recipient +#define USB_REQUEST_TO_DEVICE 0U +#define USB_REQUEST_TO_INTERFACE 1U +#define USB_REQUEST_TO_ENDPOINT 2U +#define USB_REQUEST_TO_OTHER 3U + +/// bmRequestType Definition +typedef struct { + uint8_t Recipient : 5; ///< D4..0: Recipient + uint8_t Type : 2; ///< D6..5: Type + uint8_t Dir : 1; ///< D7: Data Transfer Direction +} USB_REQUEST_TYPE; + +// USB Standard Request Codes +#define USB_REQUEST_GET_STATUS 0U +#define USB_REQUEST_CLEAR_FEATURE 1U +#define USB_REQUEST_SET_FEATURE 3U +#define USB_REQUEST_SET_ADDRESS 5U +#define USB_REQUEST_GET_DESCRIPTOR 6U +#define USB_REQUEST_SET_DESCRIPTOR 7U +#define USB_REQUEST_GET_CONFIGURATION 8U +#define USB_REQUEST_SET_CONFIGURATION 9U +#define USB_REQUEST_GET_INTERFACE 10U +#define USB_REQUEST_SET_INTERFACE 11U +#define USB_REQUEST_SYNC_FRAME 12U + +// USB GET_STATUS Bit Values +#define USB_GETSTATUS_SELF_POWERED 0x01U +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02U +#define USB_GETSTATUS_ENDPOINT_STALL 0x01U + +// USB Standard Feature selectors +#define USB_FEATURE_ENDPOINT_STALL 0U +#define USB_FEATURE_REMOTE_WAKEUP 1U + +/// USB Default Control Pipe Setup Packet +typedef struct { + USB_REQUEST_TYPE bmRequestType; ///< Characteristics of request + uint8_t bRequest; ///< Specific request + uint16_t wValue; ///< Value according to request + uint16_t wIndex; ///< Index or Offset according to request + uint16_t wLength; ///< Number of bytes to transfer if there is a Data stage +} USB_SETUP_PACKET; + + +// USB Descriptor Types +#define USB_DEVICE_DESCRIPTOR_TYPE 1U +#define USB_CONFIGURATION_DESCRIPTOR_TYPE 2U +#define USB_STRING_DESCRIPTOR_TYPE 3U +#define USB_INTERFACE_DESCRIPTOR_TYPE 4U +#define USB_ENDPOINT_DESCRIPTOR_TYPE 5U +#define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 6U +#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_TYPE 7U +#define USB_INTERFACE_POWER_DESCRIPTOR_TYPE 8U +#define USB_OTG_DESCRIPTOR_TYPE 9U +#define USB_DEBUG_DESCRIPTOR_TYPE 10U +#define USB_INTERFACE_ASSOCIATION_DESCRIPTOR_TYPE 11U + +// USB Device Classes +#define USB_DEVICE_CLASS_RESERVED 0x00U +#define USB_DEVICE_CLASS_AUDIO 0x01U +#define USB_DEVICE_CLASS_COMMUNICATIONS 0x02U +#define USB_DEVICE_CLASS_HUMAN_INTERFACE 0x03U +#define USB_DEVICE_CLASS_MONITOR 0x04U +#define USB_DEVICE_CLASS_PHYSICAL_INTERFACE 0x05U +#define USB_DEVICE_CLASS_POWER 0x06U +#define USB_DEVICE_CLASS_PRINTER 0x07U +#define USB_DEVICE_CLASS_STORAGE 0x08U +#define USB_DEVICE_CLASS_HUB 0x09U +#define USB_DEVICE_CLASS_MISCELLANEOUS 0xEFU +#define USB_DEVICE_CLASS_VENDOR_SPECIFIC 0xFFU + +// bmAttributes in Configuration Descriptor +#define USB_CONFIG_POWERED_MASK 0x40U +#define USB_CONFIG_BUS_POWERED 0x80U +#define USB_CONFIG_SELF_POWERED 0xC0U +#define USB_CONFIG_REMOTE_WAKEUP 0x20U + +// bMaxPower in Configuration Descriptor +#define USB_CONFIG_POWER_MA(mA) ((mA)/2) + +// bEndpointAddress in Endpoint Descriptor +#define USB_ENDPOINT_DIRECTION_MASK 0x80U +#define USB_ENDPOINT_OUT(addr) ( addr ) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80U) + +// bmAttributes in Endpoint Descriptor +#define USB_ENDPOINT_TYPE_MASK 0x03U +#define USB_ENDPOINT_TYPE_CONTROL 0x00U +#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01U +#define USB_ENDPOINT_TYPE_BULK 0x02U +#define USB_ENDPOINT_TYPE_INTERRUPT 0x03U +#define USB_ENDPOINT_SYNC_MASK 0x0CU +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION 0x00U +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS 0x04U +#define USB_ENDPOINT_SYNC_ADAPTIVE 0x08U +#define USB_ENDPOINT_SYNC_SYNCHRONOUS 0x0CU +#define USB_ENDPOINT_USAGE_MASK 0x30U +#define USB_ENDPOINT_USAGE_DATA 0x00U +#define USB_ENDPOINT_USAGE_FEEDBACK 0x10U +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK 0x20U +#define USB_ENDPOINT_USAGE_RESERVED 0x30U + +/// USB Standard Device Descriptor +typedef struct __attribute__((__packed__)) { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEVICE_DESCRIPTOR; + +/// USB 2.0 Device Qualifier Descriptor +typedef struct __attribute__((__packed__)) { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bReserved; +} USB_DEVICE_QUALIFIER_DESCRIPTOR; + +/// USB Standard Configuration Descriptor +typedef struct __attribute__((__packed__)) { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} USB_CONFIGURATION_DESCRIPTOR; + +/// USB Standard Interface Descriptor +typedef struct __attribute__((__packed__)) { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_INTERFACE_DESCRIPTOR; + +/// USB Standard Endpoint Descriptor +typedef struct __attribute__((__packed__)) { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; +} USB_ENDPOINT_DESCRIPTOR; + +/// USB String Descriptor +typedef struct __attribute__((__packed__)) { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString; +} USB_STRING_DESCRIPTOR; + +/// USB Common Descriptor +typedef struct __attribute__((__packed__)) { + uint8_t bLength; + uint8_t bDescriptorType; +} USB_COMMON_DESCRIPTOR; + +/// USB Interface Association Descriptor +typedef struct __attribute__((__packed__)) { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubclass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} USB_INTERFACE_ASSOCIATION_DESCRIPTOR; + +#endif // __USB_DEF_H diff --git a/mdw/include/usbd_hal.h b/mdw/include/usbd_hal.h new file mode 100644 index 0000000..a089850 --- /dev/null +++ b/mdw/include/usbd_hal.h @@ -0,0 +1,51 @@ +#pragma once + +#include +#include + +#include "kdrv_status.h" + +#define KDP2_USB_ENDPOINT_DATA_IN 0x81 // endpoint for command input +#define KDP2_USB_ENDPOINT_DATA_OUT 0x02 // endpoint for inference image input or command input + +#ifdef FIFIOQ_LOG_VIA_USB +#define KDP2_USB_ENDPOINT_LOG_IN 0x83 // endpoint for log input +#endif + +typedef enum +{ + USBD_STATUS_DISCONNECTED = 0x1, + USBD_STATUS_CONFIGURED, // connected +} usbd_hal_link_status_t; + +typedef struct __attribute__((__packed__)) +{ + uint8_t bmRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} usbd_hal_setup_packet_t; + +typedef void (*usbd_hal_user_link_status_callback_t)(usbd_hal_link_status_t link_status); +typedef bool (*usbd_hal_user_control_callback_t)(usbd_hal_setup_packet_t *setup); + +kdrv_status_t usbd_hal_initialize( + uint8_t *serial_string, + uint16_t bcdDevice, + usbd_hal_user_link_status_callback_t usr_link_isr_cb, + usbd_hal_user_control_callback_t usr_cx_isr_cb); + +kdrv_status_t usbd_hal_set_enable(bool enable); + +kdrv_status_t usbd_hal_bulk_send(uint32_t endpoint, uint32_t *buf, uint32_t txLen, uint32_t timeout_ms); + +kdrv_status_t usbd_hal_bulk_receive(uint32_t endpoint, uint32_t *buf, uint32_t *blen, uint32_t timeout_ms); + +bool usbd_hal_interrupt_send_check_buffer_empty(uint32_t endpoint); + +kdrv_status_t usbd_hal_interrupt_send(uint32_t endpoint, uint32_t *buf, uint32_t txLen, uint32_t timeout_ms); + +kdrv_status_t usbd_hal_terminate_all_endpoint(void); + +usbd_hal_link_status_t usbd_hal_get_link_status(void); diff --git a/mdw/inference/dual_fifo2.c b/mdw/inference/dual_fifo2.c new file mode 100644 index 0000000..ed35571 --- /dev/null +++ b/mdw/inference/dual_fifo2.c @@ -0,0 +1,94 @@ +#include "dual_fifo2.h" + +#include +#include "kmdw_memory.h" + +typedef struct +{ + osMessageQueueId_t free_msgq; // free buf queue + osMessageQueueId_t data_msgq; // data buf queue + uint32_t queue_count; +} _Dual_FIFO2_t; + +dual_fifo2_t dual_fifo2_create(uint32_t queue_count) +{ + _Dual_FIFO2_t *df_ptr = (_Dual_FIFO2_t *)malloc(sizeof(_Dual_FIFO2_t)); + if (df_ptr == NULL) + return (void *)DUAL_FIFO_MALLOC_FAILED; + + // fifo queues save only the pointer address + df_ptr->free_msgq = osMessageQueueNew(queue_count, sizeof(buffer_object_t), NULL); + if (df_ptr->free_msgq == NULL) { + free(df_ptr); + return (void *)DUAL_FIFO_MSGQ_NEW_FAILED; + } + + df_ptr->data_msgq = osMessageQueueNew(queue_count, sizeof(buffer_object_t), NULL); + if (df_ptr->data_msgq == NULL) { + osMessageQueueDelete(df_ptr->free_msgq); + free(df_ptr); + return (void *)DUAL_FIFO_MSGQ_NEW_FAILED; + } + + df_ptr->queue_count = queue_count; + + return (dual_fifo2_t)df_ptr; +} + +osStatus_t dual_fifo2_get_free_buffer(dual_fifo2_t df, buffer_object_t *bobj, uint32_t timeout, bool force_grab) +{ + // NOTE: timeout should be 0 for force_grab = true + + _Dual_FIFO2_t *df_ptr = (_Dual_FIFO2_t *)df; + + if (force_grab) + timeout = 0; + + osStatus_t sts = osMessageQueueGet(df_ptr->free_msgq, (void *)bobj, NULL, timeout); + + if (force_grab && sts == osErrorResource) + sts = osMessageQueueGet(df_ptr->data_msgq, (void *)bobj, NULL, 0); + + return sts; +} + +osStatus_t dual_fifo2_put_free_buffer(dual_fifo2_t df, buffer_object_t bobj, uint32_t timeout) +{ + _Dual_FIFO2_t *df_ptr = (_Dual_FIFO2_t *)df; + osStatus_t sts = osMessageQueuePut(df_ptr->free_msgq, (const void *)&bobj, 0U, timeout); + return sts; +} + +osStatus_t dual_fifo2_enqueue_data(dual_fifo2_t df, buffer_object_t bobj, uint32_t timeout, bool preempt) +{ + _Dual_FIFO2_t *df_ptr = (_Dual_FIFO2_t *)df; + osStatus_t sts = osMessageQueuePut(df_ptr->data_msgq, (const void *)&bobj, (preempt) ? (1U) : (0U), timeout); + return sts; +} + +osStatus_t dual_fifo2_dequeue_data(dual_fifo2_t df, buffer_object_t *bobj, uint32_t timeout) +{ + _Dual_FIFO2_t *df_ptr = (_Dual_FIFO2_t *)df; + osStatus_t sts = osMessageQueueGet(df_ptr->data_msgq, (void *)bobj, NULL, timeout); + return sts; +} + +uint32_t dual_fifo2_num_unconsumed_data(dual_fifo2_t df) +{ + _Dual_FIFO2_t *df_ptr = (_Dual_FIFO2_t *)df; + return osMessageQueueGetCount(df_ptr->data_msgq); +} + +uint32_t dual_fifo2_num_free_buffer(dual_fifo2_t df) +{ + _Dual_FIFO2_t *df_ptr = (_Dual_FIFO2_t *)df; + return osMessageQueueGetCount(df_ptr->free_msgq); +} + +void dual_fifo2_destroy(dual_fifo2_t df) +{ + _Dual_FIFO2_t *df_ptr = (_Dual_FIFO2_t *)df; + osMessageQueueDelete(df_ptr->free_msgq); + osMessageQueueDelete(df_ptr->data_msgq); + free(df_ptr); +} diff --git a/mdw/inference/dual_fifo2.h b/mdw/inference/dual_fifo2.h new file mode 100644 index 0000000..d0b5f1b --- /dev/null +++ b/mdw/inference/dual_fifo2.h @@ -0,0 +1,56 @@ +#pragma once + +#include +#include "cmsis_os2.h" + +#include "buffer_object.h" + +/* +'osStatus_t' : +osOK: the message has been put into the queue. +osErrorTimeout: the message could not be put into the queue in the given time (wait-timed semantics). +osErrorResource: not enough space in the queue (try semantics). +osErrorParameter: parameter mq_id is NULL or invalid, non-zero timeout specified in an ISR. +*/ + +/* +'timeout' : +when timeout is 0, the function returns instantly (i.e. try semantics). +when timeout is set to osWaitForever the function will wait for an infinite time until the message is delivered (i.e. wait semantics). +all other values specify a time in kernel ticks for a timeout (i.e. timed-wait semantics). +*/ + +// handle to a dual_fifo2_t +typedef void *dual_fifo2_t; + +#define DUAL_FIFO_VALID_ADDR 0x10 // value of 'dual_fifo2_t' should bigger than this +#define DUAL_FIFO_MALLOC_FAILED 0x1 +#define DUAL_FIFO_MSGQ_NEW_FAILED 0x2 + +// create a new dual fifo +dual_fifo2_t dual_fifo2_create(uint32_t queue_count); + +// producer: acquire a new free buffer +// NOTE: timeout should be 0 for force_grab = true +osStatus_t dual_fifo2_get_free_buffer(dual_fifo2_t df, buffer_object_t *bobj, uint32_t timeout, bool force_grab); + +// producer: put/enqueue data buffer +osStatus_t dual_fifo2_enqueue_data(dual_fifo2_t df, buffer_object_t bobj, uint32_t timeout, bool preempt); + +// consumer get/dequeue data buffer +osStatus_t dual_fifo2_dequeue_data(dual_fifo2_t df, buffer_object_t *bobj, uint32_t timeout); + +// consumer: return used data buffer +osStatus_t dual_fifo2_put_free_buffer(dual_fifo2_t df, buffer_object_t bobj, uint32_t timeout); + +// check the number of un-consumed data buffer +uint32_t dual_fifo2_num_unconsumed_data(dual_fifo2_t df); + +// check the number of free data buffer +uint32_t dual_fifo2_num_free_buffer(dual_fifo2_t df); + +// return the total contain buffer size of this dual fifo +uint32_t dual_fifo2_total_buffer_size(dual_fifo2_t df); + +// destroy a dual fifo +void dual_fifo2_destroy(dual_fifo2_t df); diff --git a/mdw/inference/kdp2_inf_generic_raw.c b/mdw/inference/kdp2_inf_generic_raw.c new file mode 100644 index 0000000..63fe490 --- /dev/null +++ b/mdw/inference/kdp2_inf_generic_raw.c @@ -0,0 +1,248 @@ +/* + * Kneron Application general functions + * + * Copyright (C) 2021 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include + +#include "kmdw_console.h" + +#include "kmdw_inference_app.h" +#include "kmdw_fifoq_manager.h" +#include "kdp2_inf_generic_raw.h" + +void kdp2_generic_raw_inference(int num_input_buf, void **inf_input_buf_list) +{ + // 'inf_input_buf' and 'result_buf' are provided by kdp2 middleware + // the content of 'inf_input_buf' is transmitted from host SW = header + image + // 'result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu) + + // config image preprocessing and model settings + kmdw_inference_app_config_t inf_config; + memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false' + + kdp2_ipc_generic_raw_inf_header_t *input_header = (kdp2_ipc_generic_raw_inf_header_t *)inf_input_buf_list[0]; + int crop_count = input_header->image_header.crop_count; + + inf_config.num_image = num_input_buf; + + kp_pad_value_t pad_value[num_input_buf]; + + for (int i = 0; i < num_input_buf; i++) { + input_header = (kdp2_ipc_generic_raw_inf_header_t *)inf_input_buf_list[i]; + + // image buffer address should be just after the header + inf_config.image_list[i].image_buf = (void *)((uint32_t)input_header + sizeof(kdp2_ipc_generic_raw_inf_header_t)); + inf_config.image_list[i].image_width = input_header->image_header.width; + inf_config.image_list[i].image_height = input_header->image_header.height; + inf_config.image_list[i].image_channel = (input_header->image_header.image_format == KP_IMAGE_FORMAT_RAW8) ? 1 : 3; + inf_config.image_list[i].image_format = input_header->image_header.image_format; + inf_config.image_list[i].image_norm = input_header->image_header.normalize_mode; + inf_config.image_list[i].enable_crop = (0 < input_header->image_header.crop_count); // use crop + inf_config.image_list[i].image_resize = input_header->image_header.resize_mode; // user's choice + inf_config.image_list[i].image_padding = input_header->image_header.padding_mode; // user's choice + + memset(&pad_value[i], 0, sizeof(kp_pad_value_t)); + inf_config.image_list[i].pad_value = &pad_value[i]; + } + + inf_config.model_id = input_header->model_id; + inf_config.enable_raw_output = true; // raw output no post-processing + inf_config.result_callback = NULL; + inf_config.user_define_data = NULL; + + // need to know model raw output size for result transfer size + uint32_t model_raw_out_size = kmdw_inference_app_get_model_raw_output_size(inf_config.model_id); + + if (0 == crop_count) { + int output_header_buf_size; + void *result_buf = kmdw_fifoq_manager_result_get_free_buffer(&output_header_buf_size); + void *ncpu_result_buf = (void *)((uint32_t)result_buf + sizeof(kdp2_ipc_generic_raw_result_t)); + + inf_config.ncpu_result_buf = ncpu_result_buf; // give result buffer for ncpu/npu + + // run preprocessing and inference, trigger ncpu/npu to do the work + int ret = kmdw_inference_app_execute(&inf_config); + + kdp2_ipc_generic_raw_result_t *output_header = (kdp2_ipc_generic_raw_result_t *)result_buf; + + // header_stamp is a must to correctly transfer result data back to host SW + output_header->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + output_header->header_stamp.job_id = KDP2_INF_ID_GENERIC_RAW; + output_header->product_id = KP_DEVICE_KL520; + output_header->inf_number = input_header->inference_number; // sync the inference number + output_header->crop_number = 0; // sync the crop number + output_header->is_last_crop = 1; + output_header->num_of_pre_proc_info = num_input_buf; + + for (int i = 0; i < num_input_buf; i++) { + uint32_t model_input_width = 0; + uint32_t model_input_height = 0; + + kmdw_inference_get_model_input_image_size(inf_config.model_id, i, &model_input_width, &model_input_height); + + output_header->pre_proc_info[i].img_width = inf_config.image_list[i].image_width; + output_header->pre_proc_info[i].img_height = inf_config.image_list[i].image_height; + output_header->pre_proc_info[i].pad_top = inf_config.image_list[i].pad_value->pad_top; + output_header->pre_proc_info[i].pad_bottom = inf_config.image_list[i].pad_value->pad_bottom; + output_header->pre_proc_info[i].pad_left = inf_config.image_list[i].pad_value->pad_left; + output_header->pre_proc_info[i].pad_right = inf_config.image_list[i].pad_value->pad_right; + output_header->pre_proc_info[i].resized_img_width = model_input_width - inf_config.image_list[i].pad_value->pad_left - inf_config.image_list[i].pad_value->pad_right; + output_header->pre_proc_info[i].resized_img_height = model_input_height - inf_config.image_list[i].pad_value->pad_top - inf_config.image_list[i].pad_value->pad_bottom; + output_header->pre_proc_info[i].model_input_width = model_input_width; + output_header->pre_proc_info[i].model_input_height = model_input_height; + + memset(&output_header->pre_proc_info[i].crop_area, 0, sizeof(kp_inf_crop_box_t)); + } + + if (ret == KP_SUCCESS) { + output_header->header_stamp.status_code = KP_SUCCESS; + output_header->header_stamp.total_size = sizeof(kdp2_ipc_generic_raw_result_t) + model_raw_out_size; + } else { + // some sort of inference error + output_header->header_stamp.status_code = ret; + output_header->header_stamp.total_size = sizeof(kdp2_ipc_generic_raw_result_t); + } + + kmdw_fifoq_manager_result_enqueue((void *)output_header, output_header_buf_size, false); + } else { + // remember: one crop, one inference result ! + for (int c = 0; c < crop_count; c++) + { + // now get an available free result buffer + // normally the begin part of result buffer should contain app-defined result header + // and the rest is for ncpu/npu inference output data + int output_header_buf_size; + void *result_buf = kmdw_fifoq_manager_result_get_free_buffer(&output_header_buf_size); + + // leave some space for result header + void *ncpu_result_buf = (void *)((uint32_t)result_buf + sizeof(kdp2_ipc_generic_raw_result_t)); + + for (int i = 0; i < num_input_buf; i++) { + input_header = (kdp2_ipc_generic_raw_inf_header_t *)inf_input_buf_list[i]; + inf_config.image_list[i].crop_area = input_header->image_header.inf_crop[c]; + + memset(inf_config.image_list[i].pad_value, 0, sizeof(kp_pad_value_t)); + } + + inf_config.ncpu_result_buf = ncpu_result_buf; // give result buffer for ncpu/npu + + // run preprocessing and inference, trigger ncpu/npu to do the work + int ret = kmdw_inference_app_execute(&inf_config); + + kdp2_ipc_generic_raw_result_t *output_header = (kdp2_ipc_generic_raw_result_t *)result_buf; + + // header_stamp is a must to correctly transfer result data back to host SW + output_header->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + output_header->header_stamp.job_id = KDP2_INF_ID_GENERIC_RAW; + output_header->product_id = KP_DEVICE_KL520; + output_header->inf_number = input_header->inference_number; // sync the inference number + output_header->crop_number = input_header->image_header.inf_crop[c].crop_number; // sync the crop number + output_header->is_last_crop = (c == crop_count - 1) ? 1 : 0; + output_header->num_of_pre_proc_info = num_input_buf; + + for (int i = 0; i < num_input_buf; i++) { + uint32_t model_input_width = 0; + uint32_t model_input_height = 0; + + kmdw_inference_get_model_input_image_size(inf_config.model_id, i, &model_input_width, &model_input_height); + + output_header->pre_proc_info[i].img_width = inf_config.image_list[i].crop_area.width; + output_header->pre_proc_info[i].img_height = inf_config.image_list[i].crop_area.height; + output_header->pre_proc_info[i].pad_top = inf_config.image_list[i].pad_value->pad_top; + output_header->pre_proc_info[i].pad_bottom = inf_config.image_list[i].pad_value->pad_bottom; + output_header->pre_proc_info[i].pad_left = inf_config.image_list[i].pad_value->pad_left; + output_header->pre_proc_info[i].pad_right = inf_config.image_list[i].pad_value->pad_right; + output_header->pre_proc_info[i].resized_img_width = model_input_width - inf_config.image_list[i].pad_value->pad_left - inf_config.image_list[i].pad_value->pad_right; + output_header->pre_proc_info[i].resized_img_height = model_input_height - inf_config.image_list[i].pad_value->pad_top - inf_config.image_list[i].pad_value->pad_bottom; + output_header->pre_proc_info[i].model_input_width = model_input_width; + output_header->pre_proc_info[i].model_input_height = model_input_height; + + memcpy(&output_header->pre_proc_info[i].crop_area, &inf_config.image_list[i].crop_area, sizeof(kp_inf_crop_box_t)); + } + + if (ret == KP_SUCCESS) { + output_header->header_stamp.status_code = KP_SUCCESS; + output_header->header_stamp.total_size = sizeof(kdp2_ipc_generic_raw_result_t) + model_raw_out_size; + } else { + // some sort of inference error + output_header->header_stamp.status_code = ret; + output_header->header_stamp.total_size = sizeof(kdp2_ipc_generic_raw_result_t); + } + + kmdw_fifoq_manager_result_enqueue((void *)output_header, output_header_buf_size, false); + } + } +} + +void kdp2_generic_raw_inference_bypass_pre_proc(int num_input_buf, void **inf_input_buf_list) +{ + // 'inf_input_buf' and 'result_buf' are provided by kdp2 middleware + // the content of 'inf_input_buf' is transmitted from host SW = header + image + // 'result_buf' is used to carry inference result back to host SW = header + inferernce result (from ncpu/npu) + + // config image preprocessing and model settings + kmdw_inference_app_config_t inf_config; + memset(&inf_config, 0, sizeof(kmdw_inference_app_config_t)); // for safety let default 'bool' to 'false' + + kdp2_ipc_generic_raw_inf_bypass_pre_proc_header_t *input_header; + + inf_config.num_image = num_input_buf; + + for (int i = 0; i < num_input_buf; i++) { + input_header = (kdp2_ipc_generic_raw_inf_bypass_pre_proc_header_t *)inf_input_buf_list[i]; + + // image buffer address should be just after the header + inf_config.image_list[i].image_buf = (void *)((uint32_t)input_header + sizeof(kdp2_ipc_generic_raw_inf_bypass_pre_proc_header_t)); + inf_config.image_list[i].image_buf_size = input_header->image_buffer_size; + inf_config.image_list[i].bypass_pre_proc = true; + inf_config.image_list[i].pad_value = NULL; + } + + // now get an available free result buffer + // normally the begin part of result buffer should contain app-defined result header + // and the rest is for ncpu/npu inference output data + int output_header_buf_size; + void *result_buf = kmdw_fifoq_manager_result_get_free_buffer(&output_header_buf_size); + + // leave some space for result header + void *ncpu_result_buf = (void *)((uint32_t)result_buf + sizeof(kdp2_ipc_generic_raw_bypass_pre_proc_result_t)); + + inf_config.model_id = input_header->model_id; + inf_config.enable_raw_output = true; // raw output no post-processing + inf_config.ncpu_result_buf = ncpu_result_buf; // give result buffer for ncpu/npu + inf_config.result_callback = NULL; + inf_config.user_define_data = NULL; + + // run preprocessing and inference, trigger ncpu/npu to do the work + int ret = kmdw_inference_app_execute(&inf_config); + + kdp2_ipc_generic_raw_bypass_pre_proc_result_t *output_header = (kdp2_ipc_generic_raw_bypass_pre_proc_result_t *)result_buf; + + // need to know model raw output size for result transfer size + uint32_t model_raw_out_size = kmdw_inference_app_get_model_raw_output_size(inf_config.model_id); + + // header_stamp is a must to correctly transfer result data back to host SW + output_header->header_stamp.magic_type = KDP2_MAGIC_TYPE_INFERENCE; + output_header->header_stamp.job_id = KDP2_INF_ID_GENERIC_RAW_BYPASS_PRE_PROC; + output_header->product_id = KP_DEVICE_KL520; + output_header->inf_number = input_header->inference_number; // sync the inference number + output_header->num_of_pre_proc_info = 0; + output_header->crop_number = 0; + output_header->is_last_crop = 1; + + if (ret == KP_SUCCESS) { + output_header->header_stamp.status_code = KP_SUCCESS; + output_header->header_stamp.total_size = sizeof(kdp2_ipc_generic_raw_bypass_pre_proc_result_t) + model_raw_out_size; + } else { + // some sort of inference error + output_header->header_stamp.status_code = ret; + output_header->header_stamp.total_size = sizeof(kdp2_ipc_generic_raw_bypass_pre_proc_result_t); + } + + kmdw_fifoq_manager_result_enqueue((void *)output_header, output_header_buf_size, false); +} diff --git a/mdw/inference/kdp2_inf_generic_raw.h b/mdw/inference/kdp2_inf_generic_raw.h new file mode 100644 index 0000000..fa42810 --- /dev/null +++ b/mdw/inference/kdp2_inf_generic_raw.h @@ -0,0 +1,60 @@ +#ifndef KDP2_INF_GENERIC_RAW_H +#define KDP2_INF_GENERIC_RAW_H + +#include +#include "kp_struct.h" +#include "buffer_object.h" + +#define KDP2_INF_ID_GENERIC_RAW 10 +#define KDP2_INF_ID_GENERIC_RAW_BYPASS_PRE_PROC 17 + +typedef struct +{ + uint32_t width; + uint32_t height; + uint32_t resize_mode; + uint32_t padding_mode; + uint32_t image_format; + uint32_t normalize_mode; + uint32_t crop_count; + kp_inf_crop_box_t inf_crop[MAX_CROP_BOX]; +} __attribute__((aligned(4))) kdp2_ipc_generic_raw_inf_image_header_t; + +// input header for 'Generic RAW inference' +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t inference_number; + uint32_t model_id; + kdp2_ipc_generic_raw_inf_image_header_t image_header; +} __attribute__((aligned(4))) kdp2_ipc_generic_raw_inf_header_t; + +// result header for 'Generic RAW inference' +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t num_of_pre_proc_info; + kp_hw_pre_proc_info_t pre_proc_info[MAX_INPUT_NODE_COUNT]; + uint32_t product_id; // enum kp_product_id_t. + uint32_t inf_number; + uint32_t crop_number; + uint32_t is_last_crop; // 0: not last crop box, 1: last crop box + uint8_t raw_data[]; // just imply following raw output data +} __attribute__((aligned(4))) kdp2_ipc_generic_raw_result_t; + +// input header for 'Generic RAW inference Bypass Pre-Process' +typedef struct +{ + /* header stamp is necessary for data transfer between host and device */ + kp_inference_header_stamp_t header_stamp; + uint32_t inference_number; + uint32_t model_id; + uint32_t image_buffer_size; +} __attribute__((aligned(4))) kdp2_ipc_generic_raw_inf_bypass_pre_proc_header_t; + +// result header for 'Generic RAW inference Bypass Pre-Process' +typedef kdp2_ipc_generic_raw_result_t kdp2_ipc_generic_raw_bypass_pre_proc_result_t; + +#endif diff --git a/mdw/inference/kmdw_fifoq_manager.c b/mdw/inference/kmdw_fifoq_manager.c new file mode 100644 index 0000000..d7e7e23 --- /dev/null +++ b/mdw/inference/kmdw_fifoq_manager.c @@ -0,0 +1,273 @@ +/* + * Kneron Application general functions + * + * Copyright (C) 2022 Kneron, Inc. All rights reserved. + * + */ + +// #define DEBUG_PRINT + +#include +#include +#include + +#include "kmdw_ipc.h" +#include "kmdw_memory.h" +#include "kmdw_model.h" +#include "kmdw_console.h" +#include "membase.h" + +#include "kp_struct.h" +#include "kmdw_fifoq_manager.h" + +#ifdef DEBUG_PRINT +#include "kmdw_console.h" +#define dbg_print(__format__, ...) kmdw_level_printf(LOG_CUSTOM, "[buf_mgr]"__format__, ##__VA_ARGS__) +#else +#define dbg_print(__format__, ...) +#endif + +#define INF_TIMEOUT 2000 // twice + +static dual_fifo2_t _image_fifioq = 0; +static dual_fifo2_t _result_fifoq = 0; +static osMessageQueueId_t _temp_image_queue; +static bool _fifoq_mem_allocated = false; +static uint32_t _fifoq_input_buf_count = 0; +static uint32_t _fifoq_input_buf_size = 0; +static uint32_t _fifoq_result_buf_count = 0; +static uint32_t _fifoq_result_buf_size = 0; + +typedef struct +{ + int total_num_buffer; + uint32_t buffer_addr; + int length; + int buffer_index; +} special_buffer_object_t; + +void kdp2_fifoq_manager_enqueue_image_thread(void *arg) +{ + special_buffer_object_t received_bobj; + buffer_object_t stored_bobj; + int num_received_img = 0; + + memset(&stored_bobj, 0, sizeof(buffer_object_t)); + + while (true) { + osStatus_t sts = osMessageQueueGet(_temp_image_queue, (void *)&received_bobj, NULL, osWaitForever); + + if (osOK != sts) { + continue; + } + + stored_bobj.num_of_buffer = received_bobj.total_num_buffer; + + if (NULL != stored_bobj.buffer_addr[received_bobj.buffer_index]) { + kmdw_fifoq_manager_image_put_free_buffer(stored_bobj.buffer_addr[received_bobj.buffer_index], + stored_bobj.length[received_bobj.buffer_index], osWaitForever); + } else { + num_received_img++; + } + + stored_bobj.buffer_addr[received_bobj.buffer_index] = received_bobj.buffer_addr; + stored_bobj.length[received_bobj.buffer_index] = received_bobj.length; + + if (num_received_img == stored_bobj.num_of_buffer) { + dual_fifo2_enqueue_data(_image_fifioq, stored_bobj, osWaitForever, false); + + num_received_img = 0; + memset(&stored_bobj, 0, sizeof(buffer_object_t)); + } + } +} + +int kmdw_fifoq_manager_init(uint32_t image_count, uint32_t result_count) +{ + kmdw_printf("creating image queue with size %d\n", image_count); + kmdw_printf("creating result queue with size %d\n", result_count); + + _image_fifioq = dual_fifo2_create(image_count); + if ((uint32_t)_image_fifioq < DUAL_FIFO_VALID_ADDR) + { + kmdw_printf("image queue creating failed !!\n"); + return -1; + } + + _result_fifoq = dual_fifo2_create(result_count); + if ((uint32_t)_result_fifoq < DUAL_FIFO_VALID_ADDR) + { + kmdw_printf("result queue creating failed !!\n"); + return -1; + } + + //the size of message queue is MAX at image count as one multiple-input + _temp_image_queue = osMessageQueueNew(image_count, sizeof(special_buffer_object_t), NULL); + + return 0; +} + +osStatus_t kmdw_fifoq_manager_image_enqueue(uint32_t total_num_buf, uint32_t index, uint32_t buf_addr, int buf_size, uint32_t timeout, bool preempt) +{ + if (0 == total_num_buf) { + return osErrorParameter; + } + + special_buffer_object_t special_obj; + + special_obj.total_num_buffer = total_num_buf; + special_obj.buffer_index = (1 == special_obj.total_num_buffer) ? 0 : index; + special_obj.buffer_addr = buf_addr; + special_obj.length = buf_size; + + return osMessageQueuePut(_temp_image_queue, (const void *)&special_obj, (preempt) ? (1U) : (0U), timeout); +} + +osStatus_t kmdw_fifoq_manager_image_dequeue(buffer_object_t *bobj, uint32_t timeout) +{ + return dual_fifo2_dequeue_data(_image_fifioq, bobj, timeout); +} + +osStatus_t kmdw_fifoq_manager_image_get_free_buffer(uint32_t *buf_addr, int *buf_size, uint32_t timeout, bool force_grab) +{ + buffer_object_t bobj; + osStatus_t sts = dual_fifo2_get_free_buffer(_image_fifioq, &bobj, timeout, force_grab); + + if (osOK != sts) { + return sts; + } + + //TODO: so far, just handle num_of_buffer > 1 in the future + if (1 < bobj.num_of_buffer) { + for (int i = 1; i < bobj.num_of_buffer; i++) { + kmdw_fifoq_manager_image_put_free_buffer(bobj.buffer_addr[i], bobj.length[i], timeout); + //TODO: need to handle return value + } + } + + *buf_addr = bobj.buffer_addr[0]; + *buf_size = bobj.length[0]; + + return sts; +} + +osStatus_t kmdw_fifoq_manager_image_put_free_buffer(uint32_t buf_addr, int buf_size, uint32_t timeout) +{ + buffer_object_t bobj; + + bobj.num_of_buffer = 1; + bobj.buffer_addr[0] = buf_addr; + bobj.length[0] = buf_size; + + return dual_fifo2_put_free_buffer(_image_fifioq, bobj, timeout); +} + +osStatus_t kmdw_fifoq_manager_result_enqueue(void *result_buf, int result_buf_size, bool preempt) +{ + buffer_object_t bobj; + + bobj.num_of_buffer = 1; + bobj.buffer_addr[0] = (uint32_t)result_buf; + bobj.length[0] = result_buf_size; + + return dual_fifo2_enqueue_data(_result_fifoq, bobj, 0, preempt); +} + +osStatus_t kmdw_fifoq_manager_result_dequeue(uint32_t *buf_addr, int *buf_size, uint32_t timeout) +{ + buffer_object_t bobj; + osStatus_t sts = dual_fifo2_dequeue_data(_result_fifoq, &bobj, timeout); + + if (osOK != sts) { + return sts; + } + + //TODO: so far, just handle num_of_buffer > 1 in the future + if (1 < bobj.num_of_buffer) { + for (int i = 1; i < bobj.num_of_buffer; i++) { + kmdw_fifoq_manager_result_put_free_buffer(bobj.buffer_addr[i], bobj.length[i], timeout); + //TODO: need to handle return value + } + } + + *buf_addr = bobj.buffer_addr[0]; + *buf_size = bobj.length[0]; + + return sts; +} + +void *kmdw_fifoq_manager_result_get_free_buffer(int *buf_size) +{ + buffer_object_t bobj; + osStatus_t sts = dual_fifo2_get_free_buffer(_result_fifoq, &bobj, osWaitForever, false); + + if (osOK != sts) { + return NULL; + } + + //TODO: so far, just handle num_of_buffer > 1 in the future + if (1 < bobj.num_of_buffer) { + for (int i = 1; i < bobj.num_of_buffer; i++) { + kmdw_fifoq_manager_result_put_free_buffer(bobj.buffer_addr[i], bobj.length[i], 0); + //TODO: need to handle return value + } + } + + *buf_size = bobj.length[0]; + + return (void *)bobj.buffer_addr[0]; +} + +osStatus_t kmdw_fifoq_manager_result_put_free_buffer(uint32_t buf_addr, int buf_size, uint32_t timeout) +{ + buffer_object_t bobj; + + bobj.num_of_buffer = 1; + bobj.buffer_addr[0] = buf_addr; + bobj.length[0] = buf_size; + + return dual_fifo2_put_free_buffer(_result_fifoq, bobj, timeout); +} + +void kmdw_fifoq_manager_clean_queues(void) +{ + buffer_object_t bobj; + + while (1) + { + if (dual_fifo2_dequeue_data(_image_fifioq, &bobj, 0) == osOK) + dual_fifo2_put_free_buffer(_image_fifioq, bobj, 0); + else + break; + } + + while (1) + { + if (dual_fifo2_dequeue_data(_result_fifoq, &bobj, 0) == osOK) + dual_fifo2_put_free_buffer(_result_fifoq, bobj, 0); + else + break; + } +} + +void kmdw_fifoq_manager_store_fifoq_config(uint32_t input_buf_count, uint32_t input_buf_size, uint32_t result_buf_count, uint32_t result_buf_size) +{ + _fifoq_mem_allocated = true; + _fifoq_input_buf_count = input_buf_count; + _fifoq_input_buf_size = input_buf_size; + _fifoq_result_buf_count = result_buf_count; + _fifoq_result_buf_size = result_buf_size; +} + +bool kmdw_fifoq_manager_get_fifoq_allocated() +{ + return _fifoq_mem_allocated; +} + +void kmdw_fifoq_manager_get_fifoq_config(uint32_t *input_buf_count, uint32_t *input_buf_size, uint32_t *result_buf_count, uint32_t *result_buf_size) +{ + *input_buf_count = _fifoq_input_buf_count; + *input_buf_size = _fifoq_input_buf_size; + *result_buf_count = _fifoq_result_buf_count; + *result_buf_size = _fifoq_result_buf_size; +} diff --git a/mdw/inference/kmdw_inference_520.c b/mdw/inference/kmdw_inference_520.c new file mode 100644 index 0000000..3ea5e8e --- /dev/null +++ b/mdw/inference/kmdw_inference_520.c @@ -0,0 +1,541 @@ +/* + * Kneron Application general functions + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +// #define DEBUG_PRINT + +#include +#include +#include + +#include "project.h" +#include "kp_struct.h" + +#include "kdrv_gdma.h" +#include "kmdw_ipc.h" +#include "kmdw_memory.h" +#include "kmdw_model.h" +#include "kmdw_console.h" + +#include "kmdw_inference_app.h" +#include "kmdw_fifoq_manager.h" +#include "kdp2_inf_generic_raw.h" + +#ifdef DEBUG_PRINT +#include "kmdw_console.h" +#define dbg_print(__format__, ...) kmdw_printf("[inf]"__format__, ##__VA_ARGS__) +#else +#define dbg_print(__format__, ...) +#endif + +#define IMG_PREPROC_UNIT_BYTES 4 // copied from ncpu fw +#define INF_TIMEOUT 2000 // twice + +/* Structure of CNN Header in setup.bin - copy from kdpio.h */ +struct cnn_header_s +{ + uint32_t crc; + uint32_t version; + uint32_t key_offset; + uint32_t model_type; + uint32_t app_type; + uint32_t dram_start; + uint32_t dram_size; + uint32_t input_row; + uint32_t input_col; + uint32_t input_channel; + uint32_t cmd_start; + uint32_t cmd_size; + uint32_t weight_start; + uint32_t weight_size; + uint32_t input_start; + uint32_t input_size; + uint32_t input_radix; + uint32_t output_nums; +}; + +static osEventFlagsId_t g_result_event; + +static kmdw_inference_app_callback_t _app_entry_func = NULL; + +static volatile int g_inf_index = 0; +static volatile uint32_t g_num_parallel_inf = 0; +static volatile uint32_t g_num_parallel_result = 0; + +typedef struct +{ + void *inf_result_buf; + int inf_result_buf_size; + void *ncpu_result_buf; + kmdw_inference_app_result_callback_t result_callback_func; +} result_context_t; + +#define MAX_OUTPUT_CONTEXT_NUM 5 +static result_context_t g_result_ctx[MAX_OUTPUT_CONTEXT_NUM] = {0}; + +extern void kdp2_generic_raw_inference(int num_input_buf, void **inf_input_buf_list); +extern void kdp2_generic_raw_inference_bypass_pre_proc(int num_input_buf, void **inf_input_buf_list); + +void kmdw_inference_image_dispatcher_thread(void *argument) +{ + dbg_print("[%s] start !\n", __FUNCTION__); + while (1) + { + buffer_object_t fifoq_obj; // fifoq buffer object + + osStatus_t sts = kmdw_fifoq_manager_image_dequeue(&fifoq_obj, osWaitForever); + + if (0 < fifoq_obj.num_of_buffer) { + void *inf_input_buf = (void *)fifoq_obj.buffer_addr[0]; // contains header + image + + dbg_print("got a image buffer for inference: buf 0x%x\n", inf_input_buf); + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)inf_input_buf; + + if (header_stamp->job_id == KDP2_INF_ID_GENERIC_RAW) + kdp2_generic_raw_inference(fifoq_obj.num_of_buffer, (void **)fifoq_obj.buffer_addr); + else if (header_stamp->job_id == KDP2_INF_ID_GENERIC_RAW_BYPASS_PRE_PROC) + kdp2_generic_raw_inference_bypass_pre_proc(fifoq_obj.num_of_buffer, (void **)fifoq_obj.buffer_addr); + else + _app_entry_func(fifoq_obj.num_of_buffer, (void **)fifoq_obj.buffer_addr); + } + + // return buffer back to fifoq + for (int i = 0; i < fifoq_obj.num_of_buffer; i++) { + kmdw_fifoq_manager_image_put_free_buffer(fifoq_obj.buffer_addr[i], fifoq_obj.length[i], osWaitForever); + } + } +} + +void kmdw_inference_result_handler_callback_thread(void *argument) +{ + uint32_t result_index = 0; // next result sequence index + uint32_t wait_result_flag; + int timeout_count = 0; + + dbg_print("[%s] start !\n", __FUNCTION__); + while (1) + { + wait_result_flag = (0x1 << result_index); + + uint32_t wait_timeout = (kmdw_ipc_get_output()->kp_dbg_checkpoinots == 0x0) ? INF_TIMEOUT : osWaitForever; + + uint32_t flags = osEventFlagsWait(g_result_event, wait_result_flag, osFlagsWaitAny, wait_timeout); + + dbg_print("result_get: osEventFlagsWait() return 0x%x\n", flags); + + // a tricky way to check if inf timeout + if (flags == (uint32_t)osFlagsErrorTimeout) + { + if (g_num_parallel_inf > g_num_parallel_result) + timeout_count++; + + if (timeout_count >= 2) + { + kmdw_printf("[inf] parallel inference timeout\n"); + kmdw_printf("inf req %d done %d timeout %d secs\n", g_num_parallel_inf, g_num_parallel_result, timeout_count); + + void *inf_result_buf = g_result_ctx[result_index].inf_result_buf; + int inf_result_buf_size = g_result_ctx[result_index].inf_result_buf_size; + void *ncpu_result_buf = g_result_ctx[result_index].ncpu_result_buf; + g_result_ctx[result_index].result_callback_func(KP_FW_INFERENCE_TIMEOUT_103, inf_result_buf, inf_result_buf_size, ncpu_result_buf); + + return; // FIXME, game over ? + } + } + else if (flags == wait_result_flag) + { + void *inf_result_buf = g_result_ctx[result_index].inf_result_buf; + int inf_result_buf_size = g_result_ctx[result_index].inf_result_buf_size; + void *ncpu_result_buf = g_result_ctx[result_index].ncpu_result_buf; + g_result_ctx[result_index].result_callback_func(KP_SUCCESS, inf_result_buf, inf_result_buf_size, ncpu_result_buf); + + g_num_parallel_result++; + + if (++result_index >= MAX_OUTPUT_CONTEXT_NUM) + result_index = 0; + + timeout_count = 0; + } + else + { + // should not be here + kmdw_printf("[inf] error flag 0x%x\n", flags); + } + } +} + +/* ############################ + * ## public functions ## + * ############################ */ + +int kmdw_inference_app_execute(kmdw_inference_app_config_t *inf_config) +{ + dbg_print("run image inference:\n"); + + struct kdp_img_cfg ncpu_img_config; + + // Check if image width, heigth > model width, height + uint32_t num_models = 0; + + uint32_t *p_all_model_info = + kmdw_model_get_all_model_info(false); + if (p_all_model_info) + num_models = p_all_model_info[0]; + else + return KP_ERROR_MODEL_NOT_LOADED_35; + + struct kdp_model_s *p_model_info = NULL; + struct cnn_header_s *p_cnn_header = NULL; + + for (int i = 0; i < num_models; i++) { + p_model_info = kmdw_model_get_model_info(i); + + if (p_model_info) { + if (p_model_info->model_type == inf_config->model_id) { + break; + } else { + p_model_info = NULL; + } + } + } + + if (NULL == p_model_info) { + return KP_ERROR_MODEL_NOT_LOADED_35; + } + + /* FIXME: Different between KL520 and KL70 */ + int num_input_node = 1; + + if (num_input_node != inf_config->num_image) { + return KP_FW_WRONG_INPUT_BUFFER_COUNT_110; + } + + ncpu_img_config.num_image = inf_config->num_image; + ncpu_img_config.image_buf_active_index = g_inf_index; + ncpu_img_config.inf_format = 0; + + // if no post-processing + if (inf_config->enable_raw_output) + ncpu_img_config.inf_format |= IMAGE_FORMAT_RAW_OUTPUT; + + // enable parallel post-processing + if (inf_config->enable_parallel) + ncpu_img_config.inf_format |= IMAGE_FORMAT_PARALLEL_PROC; + + for (int i = 0; i < num_input_node; i++) { + /* FIXME: Different between KL520 and KL70 */ + p_cnn_header = (struct cnn_header_s *)p_model_info->setup_mem_addr; + + uint32_t model_width = p_cnn_header->input_col; + uint32_t model_height = p_cnn_header->input_row; + uint32_t input_index = i; + + if ((0 == model_width) && (0 == model_height)) { + return KP_ERROR_MODEL_NOT_LOADED_35; + } + + ncpu_img_config.image_list[input_index].image_mem_addr = (uint32_t)inf_config->image_list[input_index].image_buf; + ncpu_img_config.image_list[input_index].image_mem_len = inf_config->image_list[input_index].image_buf_size; // FIXME ?? + ncpu_img_config.image_list[input_index].input_col = inf_config->image_list[input_index].image_width; + ncpu_img_config.image_list[input_index].input_row = inf_config->image_list[input_index].image_height; + ncpu_img_config.image_list[input_index].input_channel = inf_config->image_list[input_index].image_channel; + ncpu_img_config.image_list[input_index].format = 0; // sycn with 'ncpu_config' + + dbg_msg("[%d] image_mem_addr = 0x%x\n", input_index, ncpu_img_config.image_list[input_index].image_mem_addr); + dbg_msg("[%d] image_col = %d\n", input_index, ncpu_img_config.image_list[input_index].input_col); + dbg_msg("[%d] image_row = %d\n", input_index, ncpu_img_config.image_list[input_index].input_row); + dbg_msg("[%d] image_ch = %d\n", input_index, ncpu_img_config.image_list[input_index].input_channel); + + if (inf_config->image_list[input_index].bypass_pre_proc == false) // enable pre-processing + { + if (ncpu_img_config.image_list[input_index].input_col < model_width || ncpu_img_config.image_list[input_index].input_row < model_height) + return KP_ERROR_IMAGE_RESOLUTION_TOO_SMALL_22; + + int bytes_per_pixel = 0; + + switch (inf_config->image_list[input_index].image_format) + { + case KP_IMAGE_FORMAT_RGB565: + case KP_IMAGE_FORMAT_YCBCR422_CRY1CBY0: + case KP_IMAGE_FORMAT_YCBCR422_CBY1CRY0: + case KP_IMAGE_FORMAT_YCBCR422_Y1CRY0CB: + case KP_IMAGE_FORMAT_YCBCR422_Y1CBY0CR: + case KP_IMAGE_FORMAT_YCBCR422_CRY0CBY1: + case KP_IMAGE_FORMAT_YCBCR422_CBY0CRY1: + case KP_IMAGE_FORMAT_YCBCR422_Y0CRY1CB: + case KP_IMAGE_FORMAT_YCBCR422_Y0CBY1CR: + bytes_per_pixel = 2; + ncpu_img_config.image_list[input_index].format |= inf_config->image_list[input_index].image_format; + break; + case KP_IMAGE_FORMAT_YUYV: + bytes_per_pixel = 2; + ncpu_img_config.image_list[input_index].format |= NPU_FORMAT_YCBCR422_Y0CBY1CR; + break; + case KP_IMAGE_FORMAT_RGBA8888: + bytes_per_pixel = 4; + ncpu_img_config.image_list[input_index].format |= inf_config->image_list[input_index].image_format; + break; + case KP_IMAGE_FORMAT_RAW8: + bytes_per_pixel = 1; + ncpu_img_config.image_list[input_index].format |= inf_config->image_list[input_index].image_format; + break; + default: + break; + } + + if (ncpu_img_config.image_list[input_index].input_col * bytes_per_pixel % IMG_PREPROC_UNIT_BYTES != 0) + return KP_ERROR_IMAGE_INVALID_WIDTH_23; + + switch (inf_config->image_list[input_index].image_norm) + { + case KP_NORMALIZE_DISABLE: + case KP_NORMALIZE_CUSTOMIZED_DEFAULT: + break; + case KP_NORMALIZE_YOLO: + case KP_NORMALIZE_CUSTOMIZED_DIV2: + ncpu_img_config.image_list[input_index].format |= IMAGE_FORMAT_RIGHT_SHIFT_ONE_BIT; + break; + case KP_NORMALIZE_KNERON: + case KP_NORMALIZE_TENSOR_FLOW: + case KP_NORMALIZE_CUSTOMIZED_SUB128: + ncpu_img_config.image_list[input_index].format |= IMAGE_FORMAT_SUB128; + break; + case KP_NORMALIZE_CUSTOMIZED_SUB128_DIV2: + ncpu_img_config.image_list[input_index].format |= (IMAGE_FORMAT_SUB128 | IMAGE_FORMAT_RIGHT_SHIFT_ONE_BIT); + break; + } + + if (inf_config->image_list[input_index].enable_crop) + { + uint32_t crop_x1 = inf_config->image_list[input_index].crop_area.x1; + uint32_t crop_y1 = inf_config->image_list[input_index].crop_area.y1; + uint32_t crop_width = inf_config->image_list[input_index].crop_area.width; + uint32_t crop_height = inf_config->image_list[input_index].crop_area.height; + uint32_t image_width = inf_config->image_list[input_index].image_width; + uint32_t image_height = inf_config->image_list[input_index].image_height; + + if ((crop_x1 > image_width) || (crop_y1 > image_height) || + ((crop_x1 + crop_width) > image_width) || ((crop_y1 + crop_height) > image_height)) { + return KP_FW_INVALID_INPUT_CROP_PARAM_112; + } + + ncpu_img_config.image_list[input_index].params_s.crop_left = crop_x1; + ncpu_img_config.image_list[input_index].params_s.crop_top = crop_y1; + ncpu_img_config.image_list[input_index].params_s.crop_right = image_width - crop_width - crop_x1; + ncpu_img_config.image_list[input_index].params_s.crop_bottom = image_height - crop_height - crop_y1; + } else { + ncpu_img_config.image_list[input_index].params_s.crop_left = 0; + ncpu_img_config.image_list[input_index].params_s.crop_top = 0; + ncpu_img_config.image_list[input_index].params_s.crop_right = 0; + ncpu_img_config.image_list[input_index].params_s.crop_bottom = 0; + } + + if ((KP_RESIZE_DISABLE == inf_config->image_list[input_index].image_resize) && + (KP_PADDING_DISABLE == inf_config->image_list[input_index].image_padding)) { + if (inf_config->image_list[input_index].enable_crop) { + if ((inf_config->image_list[input_index].crop_area.width != model_width) || + (inf_config->image_list[input_index].crop_area.height != model_height)) { + return KP_FW_IMAGE_SIZE_NOT_MATCH_MODEL_INPUT_107; + } + } else { + if ((inf_config->image_list[input_index].image_width != model_width) || + (inf_config->image_list[input_index].image_height != model_height)) { + return KP_FW_IMAGE_SIZE_NOT_MATCH_MODEL_INPUT_107; + } + } + } else if ((KP_RESIZE_DISABLE == inf_config->image_list[input_index].image_resize) && + (KP_PADDING_DISABLE != inf_config->image_list[input_index].image_padding)) { + return KP_FW_NOT_SUPPORT_PREPROCESSING_108; + } else if ((KP_RESIZE_DISABLE != inf_config->image_list[input_index].image_resize) && + (KP_PADDING_DISABLE == inf_config->image_list[input_index].image_padding)) { + ncpu_img_config.image_list[input_index].format |= IMAGE_FORMAT_CHANGE_ASPECT_RATIO; + } else if (KP_PADDING_SYMMETRIC == inf_config->image_list[input_index].image_padding) { + ncpu_img_config.image_list[input_index].format |= IMAGE_FORMAT_SYMMETRIC_PADDING; + } + } else // no pre-processing, bypass image + { + // no color space conversion, RGBA8888 only + // no normalization + // no scaling + // no cropping + + ncpu_img_config.image_list[input_index].format |= IMAGE_FORMAT_BYPASS_PRE; + } + + dbg_msg("[%d] ncpu inf_format: 0x%X, image_format = 0x%x\n", i, ncpu_img_config.inf_format, ncpu_img_config.image_list[input_index].format); + } + + kmdw_model_config_img(&ncpu_img_config, inf_config->user_define_data); + + if (inf_config->enable_parallel) + { + kmdw_model_config_result(g_result_event, 0x1 << g_inf_index); + + g_result_ctx[g_inf_index].inf_result_buf = inf_config->inf_result_buf; + g_result_ctx[g_inf_index].inf_result_buf_size = inf_config->inf_result_buf_size; + g_result_ctx[g_inf_index].ncpu_result_buf = inf_config->ncpu_result_buf; + g_result_ctx[g_inf_index].result_callback_func = inf_config->result_callback; + + g_num_parallel_inf++; + + g_inf_index++; + if (g_inf_index >= MAX_OUTPUT_CONTEXT_NUM) + g_inf_index = 0; + } + else + kmdw_model_config_result(0, 0); + + dbg_print("ncpu_result_buf = 0x%x\n", inf_config->ncpu_result_buf); + dbg_print("model_id = %d\n", inf_config->model_id); + + int status = kmdw_model_run("", inf_config->ncpu_result_buf, inf_config->model_id, true); + + int img_idx = ncpu_img_config.image_buf_active_index; + struct kdp_img_raw_s *raw_img = kmdw_model_get_raw_img(img_idx); + + for (int i = 0; i < num_input_node; i++) { + if (NULL != inf_config->image_list[i].pad_value) { + inf_config->image_list[i].pad_value->pad_top = raw_img->image_list[i].params_s.pad_top; + inf_config->image_list[i].pad_value->pad_bottom = raw_img->image_list[i].params_s.pad_bottom; + inf_config->image_list[i].pad_value->pad_left = raw_img->image_list[i].params_s.pad_left; + inf_config->image_list[i].pad_value->pad_right = raw_img->image_list[i].params_s.pad_right; + } + + if (true == inf_config->image_list[i].enable_crop) { + inf_config->image_list[i].crop_area.x1 = raw_img->image_list[i].params_s.crop_left; + inf_config->image_list[i].crop_area.y1 = raw_img->image_list[i].params_s.crop_top; + inf_config->image_list[i].crop_area.width = inf_config->image_list[i].image_width + - raw_img->image_list[i].params_s.crop_left + - raw_img->image_list[i].params_s.crop_right; + inf_config->image_list[i].crop_area.height = inf_config->image_list[i].image_height + - raw_img->image_list[i].params_s.crop_top + - raw_img->image_list[i].params_s.crop_bottom; + } + } + + if (status == IMAGE_STATE_TIMEOUT) + return KP_FW_INFERENCE_TIMEOUT_103; + else if (status != IMAGE_STATE_DONE && status != IMAGE_STATE_NPU_BUSY) + { + if (status >= IMAGE_STATE_NCPU_INVALID_IMAGE) // defined at ipc.h + return status; + else + return KP_FW_INFERENCE_ERROR_101; + } + + else + return KP_SUCCESS; +} + +void kmdw_inference_app_send_status_code(int job_id, int error_code) +{ + // we need a result buffer + int result_buf_size; + kp_inference_header_stamp_t *result_stamp = (kp_inference_header_stamp_t *)kmdw_fifoq_manager_result_get_free_buffer(&result_buf_size); + + result_stamp->magic_type = KDP2_MAGIC_TYPE_INFERENCE; + result_stamp->total_size = sizeof(kp_inference_header_stamp_t); + result_stamp->job_id = job_id; + result_stamp->status_code = error_code; + + kmdw_fifoq_manager_result_enqueue((void *)result_stamp, result_buf_size, false); +} + +uint32_t kmdw_inference_app_get_model_raw_output_size(uint32_t model_id) +{ +#define OUT_NODE_HEAD_SIZE 24 // for 520, node's width, height, channel, radix, scale, data_layout + + /* Structure of CNN Header in setup.bin - copy from kdpio.h */ + struct cnn_header_s + { + uint32_t crc; + uint32_t version; + uint32_t key_offset; + uint32_t model_type; + uint32_t app_type; + uint32_t dram_start; + uint32_t dram_size; + uint32_t input_row; + uint32_t input_col; + uint32_t input_channel; + uint32_t cmd_start; + uint32_t cmd_size; + uint32_t weight_start; + uint32_t weight_size; + uint32_t input_start; + uint32_t input_size; + uint32_t input_radix; + uint32_t output_nums; + }; + + static uint32_t record_mid = 0; + static uint32_t record_fp_raw_output_size = 0; // fixed point data raw size including meta data, paddings.. + + if (model_id != record_mid) + { + record_mid = model_id; + record_fp_raw_output_size = 0; + + kmdw_model_fw_info_t *fw_info_p = kmdw_model_get_fw_info(true); + int num_models = (NULL == fw_info_p) ? 0 : fw_info_p->model_count; + + for (int j = 0; j < num_models; j++) + { + struct kdp_model_s *model_info = kmdw_model_get_model_info(j); + if (model_info->model_type == model_id) + { + struct cnn_header_s *cnn_header = (struct cnn_header_s *)model_info->setup_mem_addr; + record_fp_raw_output_size = + 4 /* number of output node */ + + cnn_header->output_nums * OUT_NODE_HEAD_SIZE /* per-node meta data size*/ + + model_info->output_mem_len /* one-byte fixed point data with padding */; + } + } + } + + return record_fp_raw_output_size; +} + +int kmdw_inference_get_model_input_image_size(uint32_t model_id, uint32_t input_index, uint32_t *model_input_width, uint32_t *model_input_height) +{ + uint32_t *all_model_info = kmdw_model_get_all_model_info(false); + + if (!all_model_info) { + return KP_FW_LOAD_MODEL_FAILED_104; + } + + int num_models = all_model_info[0]; + for (int j = 0; j < num_models; j++) { + struct kdp_model_s *model_info = kmdw_model_get_model_info(j); + + if (model_info->model_type == model_id) { + /* FIXME: Different between KL520 and KL70 */ + struct cnn_header_s * cnn_header = (struct cnn_header_s *)model_info->setup_mem_addr; + + *model_input_width = cnn_header->input_col; + *model_input_height = cnn_header->input_row; + + return KP_SUCCESS; + } + } + + return KP_FW_LOAD_MODEL_FAILED_104; +} + +int kmdw_inference_app_init(kmdw_inference_app_callback_t app_entry, uint32_t image_count, uint32_t result_count) +{ + kmdw_printf("\n"); + kmdw_printf("starting KDP2 middleware ...\n"); + + kmdw_fifoq_manager_init(image_count, result_count); + + _app_entry_func = app_entry; + + g_result_event = osEventFlagsNew(0); + + return 0; +} diff --git a/mdw/ipc/kmdw_ipc.c b/mdw/ipc/kmdw_ipc.c new file mode 100644 index 0000000..bc4a17e --- /dev/null +++ b/mdw/ipc/kmdw_ipc.c @@ -0,0 +1,284 @@ +/* + * Kneron NPU driver for KDP520 + * + * Copyright (C) 2022 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "io.h" +#include "kmdw_memory.h" +#include "ipc.h" +#include "kdrv_ipc.h" +#include "kmdw_ipc.h" +#include "kmdw_console.h" +#include "kmdw_model.h" +#include "base.h" +#include "kdrv_cmsis_core.h" +#include "kmdw_console.h" + +#define NCPU_IRQ 51 + +#define INPROC_ARRAY_MAX_SIZE 1000 /* 1000 uint32*/ +#define IMAGE_PREPROCESS_BUF_SIZE 0x200000 + +ipc_handler_t ipc_handler_cb; + +scpu_to_ncpu_t *out_comm_p; +ncpu_to_scpu_result_t *in_comm_p; + +#ifndef KL520 +extern osThreadId_t logger_tid; +extern logger_mgt_t logger_mgt; +#endif + +static bool bDSPBusy; + + +/** + * @brief Weak function for user to implement the specific functions\n + * Ex: Start to flash LED or start to evaluate NCPU running time + * @return IPC struct + */ +__WEAK void hook_ncpu_start(void) +{ + +} + +/** + * @brief Weak function for user to implement the specific functions\n + * Ex: Stop to flash LED or stop to evaluate NCPU running time + * @return IPC struct + */ +__WEAK void hook_ncpu_stop(void) +{ + +} + +void kmdw_ipc_trigger_int(int ipc_cmd) +{ + while(bDSPBusy == true) { + osDelay(10); + } + hook_ncpu_start(); + + if(ipc_cmd == CMD_RUN_NPU) { + ncpu_to_scpu_req_img_t *req_img_p = &in_comm_p->req_img; + + dbg_msg("DSP> %d, %d (sts %d)\n", in_comm_p->bHandledByScpu, req_img_p->bHandledByScpu, + in_comm_p->sts); + } else { + // standalone cases will not require parallel processing + ncpu_to_scpu_req_img_t *req_img_p = &in_comm_p->req_img; + req_img_p->bHandledByScpu = true; + } + + out_comm_p->cmd = ipc_cmd; + + out_comm_p->bNcpuReceived = 0; + kdrv_ipc_trigger_to_ncpu_int(); + + while(!out_comm_p->bNcpuReceived) { + // osDelay(1); //delay 1ms + } +} + +static void NCPU_IRQHandler(void) +{ + ncpu_to_scpu_req_img_t *req_img_p = &in_comm_p->req_img; + struct kdp_img_raw_s *p_raw_image; + + // kp inference debug code + if(in_comm_p->kp_dbg_status == 0xAA) // FIXME: workaround for dbg flow + { + ipc_handler_cb(p_raw_image, 0x999); + goto irq_out; + } + +#ifndef KL520 + if(in_comm_p->print_log) { + osThreadFlagsSet(logger_tid, FLAG_LOGGER_NCPU_IN); + in_comm_p->print_log = false; + goto irq_out; + } +#endif + + if (in_comm_p->sts != NCPU_STS_READY) { + dbg_msg("Note: DSP IRQ (%d, %d) %d %d %d\n", in_comm_p->bHandledByScpu, req_img_p->bHandledByScpu, + in_comm_p->sts, in_comm_p->ipc_type, in_comm_p->out_type); + bDSPBusy = true; + goto irq_out; + } + + bDSPBusy = false; + +handle_irqs: + + if (!in_comm_p->bHandledByScpu) { + + if((in_comm_p->out_type < NCPU_POSTPROC_RESULT) || (in_comm_p->out_type >= NCPU_RESULT_TYPE_MAX)){ + kmdw_printf("[DSP IRQ: wrong out_type] (%d, %d) %d %d %d\n", in_comm_p->bHandledByScpu, req_img_p->bHandledByScpu, + in_comm_p->sts, in_comm_p->ipc_type, in_comm_p->out_type); + goto irq_out; + } + + if(in_comm_p->out_type == NCPU_POSTPROC_RESULT) { + int img_idx = in_comm_p->result.postproc.img_result.seq_num; + p_raw_image = &out_comm_p->raw_images[img_idx]; + + ipc_handler_cb(p_raw_image, IMAGE_STATE_RECEIVING); + } + + if(in_comm_p->out_type == NCPU_JPEG_ENC_RESULT) { + ipc_handler_cb(p_raw_image, IMAGE_STATE_JPEG_ENC_DONE); + } + + if(in_comm_p->out_type == NCPU_JPEG_DEC_RESULT) { + ipc_handler_cb(p_raw_image, IMAGE_STATE_JPEG_DEC_DONE); + } + + if(in_comm_p->out_type == NCPU_TOF_DEC_RESULT) { + ipc_handler_cb(p_raw_image, IMAGE_STATE_TOF_DEC_DONE); + } + + in_comm_p->bHandledByScpu = true; + } + + if (!req_img_p->bHandledByScpu) { + req_img_p->bHandledByScpu = true; + ipc_handler_cb(NULL, IMAGE_STATE_ACTIVE); + } + +irq_out: + hook_ncpu_stop(); + kdrv_ipc_clear_from_ncpu_int(); + NVIC_ClearPendingIRQ((IRQn_Type)NCPU_IRQ); + + if((!in_comm_p->bHandledByScpu || !req_img_p->bHandledByScpu) && (in_comm_p->out_type == NCPU_POSTPROC_RESULT)){ + kmdw_printf("[dsp irq] (%d, %d) %d %d %d\n", in_comm_p->bHandledByScpu, req_img_p->bHandledByScpu, + in_comm_p->sts, in_comm_p->ipc_type, in_comm_p->out_type); + goto handle_irqs; + } +} + +/* ############################ + * ## Public Functions ## + * ############################ */ + +void kmdw_ipc_set_image_active(uint32_t n_index) +{ +#ifdef KL520 + out_comm_p->active_img_index = n_index; +#endif + out_comm_p->pRawimg = &out_comm_p->raw_images[n_index]; +} + +void kmdw_ipc_set_model_active(uint32_t n_index) +{ + out_comm_p->model_slot_index = n_index; +} + +void kmdw_ipc_set_model(struct kdp_model_s *model_info_addr, uint32_t info_idx, int32_t slot_idx) +{ + if (slot_idx >= MULTI_MODEL_MAX) { + dbg_msg("[ERR] too many active model is set\n"); + return; + } + + struct kdp_model_s * info = model_info_addr + info_idx; + out_comm_p->models[slot_idx] = *(info); + out_comm_p->models_type[slot_idx] = info->model_type; + + dbg_msg("[%s] idx [%u], slot [%d]\n" + "in addr [0x%x], len [%u], out addr [0x%x], len [%u]\n", + __func__, info_idx, slot_idx, + info->input_mem_addr, info->input_mem_len, info->output_mem_addr, info->output_mem_len); + + dbg_msg("buf addr [0x%x], len [%u], cmd addr [0x%x], len [%u]\n" + "weight addr [0x%x], len [%u], setup addr [0x%x], len [%u]\n", + info->buf_addr, info->buf_len, info->cmd_mem_addr, info->cmd_mem_len, + info->weight_mem_addr, info->weight_mem_len, info->setup_mem_addr, info->setup_mem_len); + + if (slot_idx + 1 > out_comm_p->num_models) { + out_comm_p->num_models = slot_idx + 1; + } +} + +void kmdw_ipc_initialize(ipc_handler_t ipc_handler) +{ +#ifndef KL520 + uint32_t nExtBufInSize, nExtBufOutSize; +#endif + + out_comm_p = (scpu_to_ncpu_t *)SCPU_IPC_MEM_ADDR; + in_comm_p = (ncpu_to_scpu_result_t *)SCPU_IPC_MEM_ADDR2; + + memset(out_comm_p, 0, sizeof(scpu_to_ncpu_t)); + memset(in_comm_p, 0, sizeof(ncpu_to_scpu_result_t)); + + out_comm_p->id = SCPU2NCPU_ID; + in_comm_p->id = NCPU2SCPU_ID; + + kmdw_console_set_log_level_scpu(LOG_ERROR); + kmdw_console_set_log_level_ncpu(LOG_ERROR); + + NVIC_SetVector((IRQn_Type)NCPU_IRQ, (uint32_t)NCPU_IRQHandler); + NVIC_EnableIRQ((IRQn_Type)NCPU_IRQ); + + uint32_t mem_len2 = IMAGE_PREPROCESS_BUF_SIZE; + uint8_t *mem_addr2 = (uint8_t*)kmdw_ddr_reserve(sizeof(uint8_t)*mem_len2); + if(mem_addr2 == 0) { + critical_msg("Error: failed to malloc IPC mem_addr2\n"); + return; + } + out_comm_p->input_mem_addr2 = (uint32_t)mem_addr2; + out_comm_p->input_mem_len2 = mem_len2; + out_comm_p->ncpu_img_req_msg_addr = (uint32_t)&in_comm_p->req_img; + out_comm_p->kp_dbg_checkpoinots = 0x0; + +#ifdef KL520 + //allocate the space for inproc array + out_comm_p->inproc_mem_addr = kmdw_ddr_reserve(sizeof(uint32_t)*INPROC_ARRAY_MAX_SIZE); +#else + /* for jpeg enc/dec or tof dec use */ + nExtBufInSize = MAX(sizeof(tof_decode_params_t), MAX(sizeof(jpeg_encode_params_t), sizeof(jpeg_decode_params_t))); + nExtBufOutSize = MAX(sizeof(tof_decode_result_t), MAX(sizeof(jpeg_encode_result_t), sizeof(jpeg_decode_result_t))); + out_comm_p->pExtInParam = (void *)kmdw_ddr_reserve(nExtBufInSize); + if(out_comm_p->pExtInParam == 0) { + critical_msg("Error: failed to malloc IPC out_comm_p->pExtInParam\n"); + return; + } + out_comm_p->pExtOutRslt = (void *)kmdw_ddr_reserve(nExtBufOutSize); + if(out_comm_p->pExtOutRslt == 0) { + critical_msg("Error: failed to malloc IPC out_comm_p->pExtOutRslt\n"); + return; + } + + in_comm_p->p_log_buf_base = (uint8_t *)&logger_mgt; +#endif + + ipc_handler_cb = ipc_handler; + bDSPBusy = false; + + kdrv_ipc_enable_to_ncpu_int(); +} + +struct scpu_to_ncpu_s* kmdw_ipc_get_output(void) +{ + return out_comm_p; +} + +ncpu_to_scpu_result_t* kmdw_ipc_get_input(void) +{ + return in_comm_p; +} + +void kdrv_ncpu_set_scpu_debug_lvl(uint32_t lvl) +{ + out_comm_p->debug_flags = (out_comm_p->debug_flags & ~0x000F0000) | (((lvl) << 16) & 0x000F0000); +} + +void kdrv_ncpu_set_ncpu_debug_lvl(uint32_t lvl) +{ + out_comm_p->debug_flags = (out_comm_p->debug_flags & ~0x0000000F) | ((lvl)&0x0000000F); +} diff --git a/mdw/kdp_usb_uvc/include/kdp_usb.h b/mdw/kdp_usb_uvc/include/kdp_usb.h new file mode 100644 index 0000000..e24b941 --- /dev/null +++ b/mdw/kdp_usb_uvc/include/kdp_usb.h @@ -0,0 +1,37 @@ +/* + * Kneron USB host API + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ +#ifndef __KDP_USB_H__ +#define __KDP_USB_H__ + +#include "kdp_usb_api.h" +#include +#include + +struct usb_device_id { + uint16_t idVendor; + uint16_t idProduct; +}; + + +#define USB_DEVICE_ID_MATCH_DEVICE \ + (USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_PRODUCT) + +/** + * USB_DEVICE - macro used to describe a specific usb device + * @vend: the 16 bit USB Vendor ID + * @prod: the 16 bit USB Product ID + * + * This macro is used to create a struct usb_device_id that matches a + * specific device. + */ +#define USB_DEVICE(vend, prod) \ + .match_flags = USB_DEVICE_ID_MATCH_DEVICE, \ + .idVendor = (vend), \ + .idProduct = (prod) + + +#endif /* __KDP_USB_H__ */ diff --git a/mdw/kdp_usb_uvc/include/kdp_usb_api.h b/mdw/kdp_usb_uvc/include/kdp_usb_api.h new file mode 100644 index 0000000..985abf3 --- /dev/null +++ b/mdw/kdp_usb_uvc/include/kdp_usb_api.h @@ -0,0 +1,80 @@ +/* + * Kneron USB host driver API + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ +#ifndef __KDP_USB_API_H__ +#define __KDP_USB_API_H__ + +#include "kdp_usb_ch9.h" + + +typedef unsigned int size_t; + +#define USB_DEVICE_ID_MATCH_VENDOR 0x0001 +#define USB_DEVICE_ID_MATCH_PRODUCT 0x0002 +#define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080 +#define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100 +#define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200 +#define USB_DEVICE_ID_MATCH_DEV_HI 0x0008 +#define USB_DEVICE_ID_MATCH_DEVICE \ + (USB_DEVICE_ID_MATCH_VENDOR | USB_DEVICE_ID_MATCH_PRODUCT) + +#define USB_DEVICE_ID_MATCH_INT_INFO \ + (USB_DEVICE_ID_MATCH_INT_CLASS | \ + USB_DEVICE_ID_MATCH_INT_SUBCLASS | \ + USB_DEVICE_ID_MATCH_INT_PROTOCOL) + + + + + +enum usb_init_type { + USB_INIT_HOST = 0, + USB_INIT_DEVICE +}; +//typedef void (*usb_complete_t)(struct urb *); + +struct usb_endpoint { + struct usb_endpoint_descriptor desc; + void *hcpriv; + unsigned char *extra; /* Extra descriptors */ + int extralen; + int enabled; + int streams; +} __attribute__ ((packed)); + +struct usb_inf_alt { + struct usb_interface_descriptor desc; + int extralen; + unsigned char *extra; + uint8_t num_ep; + struct usb_endpoint *p_ep; +} __attribute__ ((packed)); + +/* Interface */ +struct usb_interface { + struct usb_inf_alt *p_alt; + uint8_t num_alt; + uint8_t cur_num; +} __attribute__ ((packed)); + +struct usb_config { + struct usb_config_descriptor *pdesc; + uint8_t num_inf; + uint8_t cur_inf; + struct usb_interface *p_inf; +} __attribute__ ((packed)); + +struct usb_device { +// int devnum; +// int maxpacketsize; + + struct usb_device_descriptor *dev_desc; + uint8_t num_conf; + uint8_t cur_conf; + struct usb_config *pconf; /* config descriptor */ +}; + +#endif /*_USB_H_ */ diff --git a/mdw/kdp_usb_uvc/include/kdp_usb_ch9.h b/mdw/kdp_usb_uvc/include/kdp_usb_ch9.h new file mode 100644 index 0000000..ba7f036 --- /dev/null +++ b/mdw/kdp_usb_uvc/include/kdp_usb_ch9.h @@ -0,0 +1,926 @@ +/* + * This file holds USB constants and structures that are needed for + * USB device APIs. These are used by the USB device model, which is + * defined in chapter 9 of the USB 2.0 specification and in the + * Wireless USB 1.0 (spread around). + * + * USB 2.0 adds an additional "On The Go" (OTG) mode, which lets systems + * act either as a USB master/host or as a USB slave/device. That means + * the master and slave side APIs benefit from working well together. + * + * There's also "Wireless USB", using low power short range radios for + * peripheral interconnection but otherwise building on the USB framework. + * + * Note all descriptors are declared '__attribute__((packed))' so that: + * + * [a] they never get padded, either internally (USB spec writers + * probably handled that) or externally; + * + * [b] so that accessing bigger-than-a-bytes fields will never + * generate bus errors on any platform, even when the location of + * its descriptor inside a bundle isn't "naturally aligned", and + * + * [c] for consistency, removing all doubt even when it appears to + * someone that the two other points are non-issues for that + * particular descriptor type. + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + * + */ + +#ifndef __KDP_USB_CH9_H__ +#define __KDP_USB_CH9_H__ +#include +/*-------------------------------------------------------------------------*/ + +/* CONTROL REQUEST SUPPORT */ + +/* + * USB directions + * + * This bit flag is used in endpoint descriptors' bEndpointAddress field. + * It's also one of three fields in control requests bRequestType. + */ +#define USB_DIR_OUT 0x0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */ + +/* + * USB types, the second of three bRequestType fields + */ +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* + * USB recipients, the third of three bRequestType fields + */ +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 +/* From Wireless USB 1.0 */ +#define USB_RECIP_PORT 0x04 +#define USB_RECIP_RPIPE 0x05 + +/* + * Standard requests, for the bRequest field of a SETUP packet. + * + * These are qualified by the bRequestType field, so that for example + * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved + * by a GET_STATUS request. + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C +#define USB_REQ_SET_SEL 0x30 +#define USB_REQ_SET_ISOCH_DELAY 0x31 + +#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */ +#define USB_REQ_GET_ENCRYPTION 0x0E +#define USB_REQ_RPIPE_ABORT 0x0E +#define USB_REQ_SET_HANDSHAKE 0x0F +#define USB_REQ_RPIPE_RESET 0x0F +#define USB_REQ_GET_HANDSHAKE 0x10 +#define USB_REQ_SET_CONNECTION 0x11 +#define USB_REQ_SET_SECURITY_DATA 0x12 +#define USB_REQ_GET_SECURITY_DATA 0x13 +#define USB_REQ_SET_WUSB_DATA 0x14 +#define USB_REQ_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQ_LOOPBACK_DATA_READ 0x16 +#define USB_REQ_SET_INTERFACE_DS 0x17 + +/* specific requests for USB Power Delivery */ +#define USB_REQ_GET_PARTNER_PDO 20 +#define USB_REQ_GET_BATTERY_STATUS 21 +#define USB_REQ_SET_PDO 22 +#define USB_REQ_GET_VDM 23 +#define USB_REQ_SEND_VDM 24 + + +/* HID requests */ +#define USB_REQ_GET_REPORT 0x01 +#define USB_REQ_GET_IDLE 0x02 +#define USB_REQ_GET_PROTOCOL 0x03 +#define USB_REQ_SET_REPORT 0x09 +#define USB_REQ_SET_IDLE 0x0A +#define USB_REQ_SET_PROTOCOL 0x0B + +/* The Link Power Management (LPM) ECN defines USB_REQ_TEST_AND_SET command, + * used by hubs to put ports into a new L1 suspend state, except that it + * forgot to define its number ... + */ + +/* + * USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and + * are read as a bit array returned by USB_REQ_GET_STATUS. (So there + * are at most sixteen features of each type.) Hubs may also support a + * new USB_REQ_TEST_AND_SET_FEATURE to put ports into L1 suspend. + */ +#define USB_DEVICE_SELF_POWERED 0 /* (read only) */ +#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */ +#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */ +#define USB_DEVICE_BATTERY 2 /* (wireless) */ +#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */ +#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/ +#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */ +#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */ +#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */ + +/* + * Test Mode Selectors + * See USB 2.0 spec Table 9-7 + */ +#define TEST_J 1 +#define TEST_K 2 +#define TEST_SE0_NAK 3 +#define TEST_PACKET 4 +#define TEST_FORCE_EN 5 + +/* + * New Feature Selectors as added by USB 3.0 + * See USB 3.0 spec Table 9-7 + */ +#define USB_DEVICE_U1_ENABLE 48 /* dev may initiate U1 transition */ +#define USB_DEVICE_U2_ENABLE 49 /* dev may initiate U2 transition */ +#define USB_DEVICE_LTM_ENABLE 50 /* dev may send LTM */ +#define USB_INTRF_FUNC_SUSPEND 0 /* function suspend */ + +#define USB_INTR_FUNC_SUSPEND_OPT_MASK 0xFF00 +/* + * Suspend Options, Table 9-8 USB 3.0 spec + */ +#define USB_INTRF_FUNC_SUSPEND_LP (1 << (8 + 0)) +#define USB_INTRF_FUNC_SUSPEND_RW (1 << (8 + 1)) + +/* + * Interface status, Figure 9-5 USB 3.0 spec + */ +#define USB_INTRF_STAT_FUNC_RW_CAP 1 +#define USB_INTRF_STAT_FUNC_RW 2 + +#define USB_ENDPOINT_HALT 0 /* IN/OUT will STALL */ + +/* Bit array elements as returned by the USB_REQ_GET_STATUS request. */ +#define USB_DEV_STAT_U1_ENABLED 2 /* transition into U1 state */ +#define USB_DEV_STAT_U2_ENABLED 3 /* transition into U2 state */ +#define USB_DEV_STAT_LTM_ENABLED 4 /* Latency tolerance messages */ + +/* + * Feature selectors from Table 9-8 USB Power Delivery spec + */ +#define USB_DEVICE_BATTERY_WAKE_MASK 40 +#define USB_DEVICE_OS_IS_PD_AWARE 41 +#define USB_DEVICE_POLICY_MODE 42 +#define USB_PORT_PR_SWAP 43 +#define USB_PORT_GOTO_MIN 44 +#define USB_PORT_RETURN_POWER 45 +#define USB_PORT_ACCEPT_PD_REQUEST 46 +#define USB_PORT_REJECT_PD_REQUEST 47 +#define USB_PORT_PORT_PD_RESET 48 +#define USB_PORT_C_PORT_PD_CHANGE 49 +#define USB_PORT_CABLE_PD_RESET 50 +#define USB_DEVICE_CHARGING_POLICY 54 + +/** + * struct usb_ctrlrequest - SETUP data for a USB device control request + * @bRequestType: matches the USB bmRequestType field + * @bRequest: matches the USB bRequest field + * @wValue: matches the USB wValue field (le16 byte order) + * @wIndex: matches the USB wIndex field (le16 byte order) + * @wLength: matches the USB wLength field (le16 byte order) + * + * This structure is used to send control requests to a USB device. It matches + * the different fields of the USB 2.0 Spec section 9.3, table 9-2. See the + * USB spec for a fuller description of the different fields, and what they are + * used for. + * + * Note that the driver for any interface can issue control requests. + * For most devices, interfaces don't coordinate with each other, so + * such requests may be made at any time. + */ +struct usb_ctrlrequest { + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} __attribute__ ((packed)); + + + +/* + * Descriptor types ... USB 2.0 spec table 9.5 + */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 +#define USB_DT_DEVICE_QUALIFIER 0x06 +#define USB_DT_OTHER_SPEED_CONFIG 0x07 +#define USB_DT_INTERFACE_POWER 0x08 +/* these are from a minor usb 2.0 revision (ECN) */ +#define USB_DT_OTG 0x09 +#define USB_DT_DEBUG 0x0a +#define USB_DT_INTERFACE_ASSOCIATION 0x0b +/* these are from the Wireless USB spec */ +#define USB_DT_SECURITY 0x0c +#define USB_DT_KEY 0x0d +#define USB_DT_ENCRYPTION_TYPE 0x0e +#define USB_DT_BOS 0x0f +#define USB_DT_DEVICE_CAPABILITY 0x10 +#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11 +#define USB_DT_WIRE_ADAPTER 0x21 +#define USB_DT_RPIPE 0x22 +#define USB_DT_CS_RADIO_CONTROL 0x23 +/* From the T10 UAS specification */ +#define USB_DT_PIPE_USAGE 0x24 +/* From the USB 3.0 spec */ +#define USB_DT_SS_ENDPOINT_COMP 0x30 +/* From the USB 3.1 spec */ +#define USB_DT_SSP_ISOC_ENDPOINT_COMP 0x31 + +/* Conventional codes for class-specific descriptors. The convention is + * defined in the USB "Common Class" Spec (3.11). Individual class specs + * are authoritative for their usage, not the "common class" writeup. + */ +#define USB_DT_CS_DEVICE (USB_TYPE_CLASS | USB_DT_DEVICE) +#define USB_DT_CS_CONFIG (USB_TYPE_CLASS | USB_DT_CONFIG) +#define USB_DT_CS_STRING (USB_TYPE_CLASS | USB_DT_STRING) +#define USB_DT_CS_INTERFACE (USB_TYPE_CLASS | USB_DT_INTERFACE) +#define USB_DT_CS_ENDPOINT (USB_TYPE_CLASS | USB_DT_ENDPOINT) + +/* All standard descriptors have these 2 fields at the beginning */ +struct usb_descriptor_header { + uint8_t bLength; + uint8_t bDescriptorType; +} __attribute__ ((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE: Device descriptor */ +struct usb_device_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; // bcdDeviceReleaseNumber + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} __attribute__ ((packed)); + +#define USB_DT_DEVICE_SIZE 18 + +struct usb_device_qualifier_descriptor { + uint8_t bLength;// Number Size of descriptor + uint8_t bDescriptorType; // Constant Device Qualifier Type + uint16_t bcdUSB; // BCD USB specification version number (e.g., 0200H for V2.00 ) + uint8_t bDeviceClass; // Class Class Code + uint8_t bDeviceSubClass; // SubClass SubClass Code + uint8_t bDeviceProtocol; // Protocol Protocol Code + uint8_t bMaxPacketSize0; // Number Maximum packet size for other speed + uint8_t bNumConfigurations; // Number Number of Other-speed Configurations + uint8_t bReserved; // Zero Reserved for future use, must be zero +} __attribute__ ((packed)); + +struct usb_other_speed_configuration_descriptor { + uint8_t bLength; // Number Size of descriptor + uint8_t bDescriptorType; // Constant Other_speed_Configuration Type + uint16_t wTotalLength; // Number Total length of data returned + uint8_t bNumInterfaces; // Number Number of interfaces supported by this speed configuration + uint8_t bConfigurationValue; // 1 Number Value to use to select configuration + uint8_t iConfiguration; // Index Index of string descriptor + uint8_t bmAttributes; //Bitmap Same as Configuration descriptor + uint8_t bMaxPower; // mA Same as Configuration descriptor +} __attribute__ ((packed)); + +struct usb_otg_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint8_t bmAttributes; /* support for HNP, SRP, etc */ +} __attribute__ ((packed)); + +/* USB_DT_OTG (from OTG 2.0 supplement) */ +struct usb_otg20_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint8_t bmAttributes; /* support for HNP, SRP and ADP, etc */ + uint16_t bcdOTG; /* OTG and EH supplement release number + * in binary-coded decimal(i.e. 2.0 is 0200H) + */ +} __attribute__ ((packed)); +/* + * Device and/or Interface Class codes + * as found in bDeviceClass or bInterfaceClass + * and defined by www.usb.org documents + */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PHYSICAL 5 +#define USB_CLASS_STILL_IMAGE 6 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_CDC_DATA 0x0a +#define USB_CLASS_CSCID 0x0b /* chip+ smart card */ +#define USB_CLASS_CONTENT_SEC 0x0d /* content security */ +#define USB_CLASS_VIDEO 0x0e +#define USB_CLASS_WIRELESS_CONTROLLER 0xe0 +#define USB_CLASS_MISC 0xef +#define USB_CLASS_APP_SPEC 0xfe +#define USB_CLASS_VENDOR_SPEC 0xff + +#define USB_SUBCLASS_VENDOR_SPEC 0xff + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_CONFIG: Configuration descriptor information. + * + * USB_DT_OTHER_SPEED_CONFIG is the same descriptor, except that the + * descriptor type is different. Highspeed-capable devices can look + * different depending on what speed they're currently running. Only + * devices with a USB_DT_DEVICE_QUALIFIER have any OTHER_SPEED_CONFIG + * descriptors. + */ +struct usb_config_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t bMaxPower; +} __attribute__ ((packed)); + +#define USB_DT_CONFIG_SIZE 9 + +/* from config descriptor bmAttributes */ +#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */ +#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */ +#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */ +#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_STRING: String descriptor */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint16_t wData[1]; /* UTF-16LE encoded */ +} __attribute__ ((packed)); + +/* note that "string" zero is special, it holds language codes that + * the device supports, not Unicode characters. + */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_INTERFACE: Interface descriptor */ +struct usb_interface_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} __attribute__ ((packed)); + +#define USB_DT_INTERFACE_SIZE 9 + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_ENDPOINT: Endpoint descriptor */ +struct usb_endpoint_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; + + /* NOTE: these two are _only_ in audio endpoints. */ + /* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */ + uint8_t bRefresh; + uint8_t bSynchAddress; +} __attribute__ ((packed)); + +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ + +/* + * Endpoints + */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 +#define USB_ENDPOINT_MAX_ADJUSTABLE 0x80 + +/* The USB 3.0 spec redefines bits 5:4 of bmAttributes as interrupt ep type. */ +#define USB_ENDPOINT_INTRTYPE 0x30 +#define USB_ENDPOINT_INTR_PERIODIC (0 << 4) +#define USB_ENDPOINT_INTR_NOTIFICATION (1 << 4) + +//#define USB_ENDPOINT_SYNCTYPE 0x0c +//#define USB_ENDPOINT_SYNC_NONE (0 << 2) +//#define USB_ENDPOINT_SYNC_ASYNC (1 << 2) +//#define USB_ENDPOINT_SYNC_ADAPTIVE (2 << 2) +//#define USB_ENDPOINT_SYNC_SYNC (3 << 2) + +//#define USB_ENDPOINT_USAGE_MASK 0x30 +//#define USB_ENDPOINT_USAGE_DATA 0x00 +//#define USB_ENDPOINT_USAGE_FEEDBACK 0x10 +//#define USB_ENDPOINT_USAGE_IMPLICIT_FB 0x20 /* Implicit feedback Data endpoint */ + +/*-------------------------------------------------------------------------*/ + +/** + * usb_endpoint_num - get the endpoint's number + * @epd: endpoint to be checked + * + * Returns @epd's number: 0 to 15. + */ +static inline int usb_endpoint_num(const struct usb_endpoint_descriptor *epd) +{ + return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; +} + +/** + * usb_endpoint_type - get the endpoint's transfer type + * @epd: endpoint to be checked + * + * Returns one of USB_ENDPOINT_XFER_{CONTROL, ISOC, BULK, INT} according + * to @epd's transfer type. + */ +static inline int usb_endpoint_type(const struct usb_endpoint_descriptor *epd) +{ + return epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; +} + +/** + * usb_endpoint_dir_in - check if the endpoint has IN direction + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type IN, otherwise it returns false. + */ +static inline int usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN); +} + +/** + * usb_endpoint_dir_out - check if the endpoint has OUT direction + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type OUT, otherwise it returns false. + */ +static inline int usb_endpoint_dir_out( + const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT); +} + +/** + * usb_endpoint_xfer_bulk - check if the endpoint has bulk transfer type + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type bulk, otherwise it returns false. + */ +static inline int usb_endpoint_xfer_bulk( + const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_BULK); +} + +/** + * usb_endpoint_xfer_control - check if the endpoint has control transfer type + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type control, otherwise it returns false. + */ +static inline int usb_endpoint_xfer_control( + const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_CONTROL); +} + +/** + * usb_endpoint_xfer_int - check if the endpoint has interrupt transfer type + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type interrupt, otherwise it returns + * false. + */ +static inline int usb_endpoint_xfer_int( + const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_INT); +} + +/** + * usb_endpoint_xfer_isoc - check if the endpoint has isochronous transfer type + * @epd: endpoint to be checked + * + * Returns true if the endpoint is of type isochronous, otherwise it returns + * false. + */ +static inline int usb_endpoint_xfer_isoc( + const struct usb_endpoint_descriptor *epd) +{ + return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == + USB_ENDPOINT_XFER_ISOC); +} + +/** + * usb_endpoint_is_bulk_in - check if the endpoint is bulk IN + * @epd: endpoint to be checked + * + * Returns true if the endpoint has bulk transfer type and IN direction, + * otherwise it returns false. + */ +static inline int usb_endpoint_is_bulk_in( + const struct usb_endpoint_descriptor *epd) +{ + return usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_in(epd); +} + +/** + * usb_endpoint_is_bulk_out - check if the endpoint is bulk OUT + * @epd: endpoint to be checked + * + * Returns true if the endpoint has bulk transfer type and OUT direction, + * otherwise it returns false. + */ +static inline int usb_endpoint_is_bulk_out( + const struct usb_endpoint_descriptor *epd) +{ + return usb_endpoint_xfer_bulk(epd) && usb_endpoint_dir_out(epd); +} + +/** + * usb_endpoint_is_int_in - check if the endpoint is interrupt IN + * @epd: endpoint to be checked + * + * Returns true if the endpoint has interrupt transfer type and IN direction, + * otherwise it returns false. + */ +static inline int usb_endpoint_is_int_in( + const struct usb_endpoint_descriptor *epd) +{ + return usb_endpoint_xfer_int(epd) && usb_endpoint_dir_in(epd); +} + +/** + * usb_endpoint_is_int_out - check if the endpoint is interrupt OUT + * @epd: endpoint to be checked + * + * Returns true if the endpoint has interrupt transfer type and OUT direction, + * otherwise it returns false. + */ +static inline int usb_endpoint_is_int_out( + const struct usb_endpoint_descriptor *epd) +{ + return usb_endpoint_xfer_int(epd) && usb_endpoint_dir_out(epd); +} + +/** + * usb_endpoint_is_isoc_in - check if the endpoint is isochronous IN + * @epd: endpoint to be checked + * + * Returns true if the endpoint has isochronous transfer type and IN direction, + * otherwise it returns false. + */ +static inline int usb_endpoint_is_isoc_in( + const struct usb_endpoint_descriptor *epd) +{ + return usb_endpoint_xfer_isoc(epd) && usb_endpoint_dir_in(epd); +} + +/** + * usb_endpoint_is_isoc_out - check if the endpoint is isochronous OUT + * @epd: endpoint to be checked + * + * Returns true if the endpoint has isochronous transfer type and OUT direction, + * otherwise it returns false. + */ +static inline int usb_endpoint_is_isoc_out( + const struct usb_endpoint_descriptor *epd) +{ + return usb_endpoint_xfer_isoc(epd) && usb_endpoint_dir_out(epd); +} + +/** + * usb_endpoint_maxp - get endpoint's max packet size + * @epd: endpoint to be checked + * + * Returns @epd's max packet + */ +static inline int usb_endpoint_maxp(const struct usb_endpoint_descriptor *epd) +{ + return epd->wMaxPacketSize; +} + +static inline int usb_endpoint_interrupt_type( + const struct usb_endpoint_descriptor *epd) +{ + return epd->bmAttributes & USB_ENDPOINT_INTRTYPE; +} + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_SSP_ISOC_ENDPOINT_COMP: SuperSpeedPlus Isochronous Endpoint Companion + * descriptor + */ +struct usb_ssp_isoc_ep_comp_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wReseved; + uint32_t dwBytesPerInterval; +} __attribute__ ((packed)); + +#define USB_DT_SSP_ISOC_EP_COMP_SIZE 8 + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_SS_ENDPOINT_COMP: SuperSpeed Endpoint Companion descriptor */ +struct usb_ss_ep_comp_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint8_t bMaxBurst; + uint8_t bmAttributes; + uint16_t wBytesPerInterval; +} __attribute__ ((packed)); + +#define USB_DT_SS_EP_COMP_SIZE 6 + +/* Bits 4:0 of bmAttributes if this is a bulk endpoint */ +static inline int +usb_ss_max_streams(const struct usb_ss_ep_comp_descriptor *comp) +{ + int max_streams; + + if (!comp) + return 0; + + max_streams = comp->bmAttributes & 0x1f; + + if (!max_streams) + return 0; + + max_streams = 1 << max_streams; + + return max_streams; +} + +/* Bits 1:0 of bmAttributes if this is an isoc endpoint */ +#define USB_SS_MULT(p) (1 + ((p) & 0x3)) +/* Bit 7 of bmAttributes if a SSP isoc endpoint companion descriptor exists */ +#define USB_SS_SSP_ISOC_COMP(p) ((p) & (1 << 7)) + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */ +struct usb_qualifier_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint8_t bNumConfigurations; + uint8_t bRESERVED; +} __attribute__ ((packed)); + + + + +/* from usb_otg_descriptor.bmAttributes */ +#define USB_OTG_SRP (1 << 0) +#define USB_OTG_HNP (1 << 1) /* swap host/device roles */ +#define USB_OTG_ADP (1 << 2) /* support ADP */ + +#define OTG_STS_SELECTOR 0xF000 /* OTG status selector */ +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEBUG: for special highspeed devices, replacing serial console */ +struct usb_debug_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + /* bulk endpoints with 8 byte maxpacket */ + uint8_t bDebugInEndpoint; + uint8_t bDebugOutEndpoint; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_INTERFACE_ASSOCIATION: groups interfaces */ +struct usb_interface_assoc_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __attribute__ ((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_SECURITY: group of wireless security descriptors, including + * encryption types available for setting up a CC/association. + */ +struct usb_security_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint16_t wTotalLength; + uint8_t bNumEncryptionTypes; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_KEY: used with {GET,SET}_SECURITY_DATA; only public keys + * may be retrieved. + */ +struct usb_key_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint8_t tTKID[3]; + uint8_t bReserved; + uint8_t bKeyData[0]; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_ENCRYPTION_TYPE: bundled in DT_SECURITY groups */ +struct usb_encryption_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint8_t bEncryptionType; +#define USB_ENC_TYPE_UNSECURE 0 +#define USB_ENC_TYPE_WIRED 1 /* non-wireless mode */ +#define USB_ENC_TYPE_CCM_1 2 /* aes128/cbc session */ +#define USB_ENC_TYPE_RSA_1 3 /* rsa3072/sha1 auth */ + uint8_t bEncryptionValue; /* use in SET_ENCRYPTION */ + uint8_t bAuthKeyIndex; +} __attribute__((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_BOS: group of device-level capabilities */ +struct usb_bos_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} __attribute__((packed)); + +#define USB_DT_BOS_SIZE 5 + + +/*-------------------------------------------------------------------------*/ + +/* USB 2.0 defines three speeds, here's how Linux identifies them */ + +enum usb_device_speed { + USB_SPEED_UNKNOWN = 0, /* enumerating */ + USB_SPEED_LOW1, + USB_SPEED_FULL1, /* usb 1.1 */ + USB_SPEED_HIGH1, /* usb 2.0 */ + USB_SPEED_WIRELESS, /* wireless (usb 2.5) */ + USB_SPEED_SUPER, /* usb 3.0 */ + USB_SPEED_SUPER_PLUS, /* usb 3.1 */ +}; + + +enum usb_device_state { + /* NOTATTACHED isn't in the USB spec, and this state acts + * the same as ATTACHED ... but it's clearer this way. + */ + USB_STATE_NOTATTACHED = 0, + + /* chapter 9 and authentication (wireless) device states */ + USB_STATE_ATTACHED, + USB_STATE_POWERED, /* wired */ + USB_STATE_RECONNECTING, /* auth */ + USB_STATE_UNAUTHENTICATED, /* auth */ + USB_STATE_DEFAULT, /* limited function */ + USB_STATE_ADDRESS, + USB_STATE_CONFIGURED, /* most functions */ + + USB_STATE_SUSPENDED + + /* NOTE: there are actually four different SUSPENDED + * states, returning to POWERED, DEFAULT, ADDRESS, or + * CONFIGURED respectively when SOF tokens flow again. + * At this level there's no difference between L1 and L2 + * suspend states. (L2 being original USB 1.1 suspend.) + */ +}; + +enum usb3_link_state { + USB3_LPM_U0 = 0, + USB3_LPM_U1, + USB3_LPM_U2, + USB3_LPM_U3 +}; + +/* + * A U1 timeout of 0x0 means the parent hub will reject any transitions to U1. + * 0xff means the parent hub will accept transitions to U1, but will not + * initiate a transition. + * + * A U1 timeout of 0x1 to 0x7F also causes the hub to initiate a transition to + * U1 after that many microseconds. Timeouts of 0x80 to 0xFE are reserved + * values. + * + * A U2 timeout of 0x0 means the parent hub will reject any transitions to U2. + * 0xff means the parent hub will accept transitions to U2, but will not + * initiate a transition. + * + * A U2 timeout of 0x1 to 0xFE also causes the hub to initiate a transition to + * U2 after N*256 microseconds. Therefore a U2 timeout value of 0x1 means a U2 + * idle timer of 256 microseconds, 0x2 means 512 microseconds, 0xFE means + * 65.024ms. + */ +#define USB3_LPM_DISABLED 0x0 +#define USB3_LPM_U1_MAX_TIMEOUT 0x7F +#define USB3_LPM_U2_MAX_TIMEOUT 0xFE +#define USB3_LPM_DEVICE_INITIATED 0xFF + +struct usb_set_sel_req { + uint8_t u1_sel; + uint8_t u1_pel; + uint16_t u2_sel; + uint16_t u2_pel; +} __attribute__ ((packed)); + +/* + * The Set System Exit Latency control transfer provides one byte each for + * U1 SEL and U1 PEL, so the max exit latency is 0xFF. U2 SEL and U2 PEL each + * are two bytes long. + */ +#define USB3_LPM_MAX_U1_SEL_PEL 0xFF +#define USB3_LPM_MAX_U2_SEL_PEL 0xFFFF + +/*-------------------------------------------------------------------------*/ + +/* + * As per USB compliance update, a device that is actively drawing + * more than 100mA from USB must report itself as bus-powered in + * the GetStatus(DEVICE) call. + * http://compliance.usb.org/index.asp?UpdateFile=Electrical&Format=Standard#34 + */ +#define USB_SELF_POWER_VBUS_MAX_DRAW 100 + +#endif /* __KDP_USB_CH9_H__ */ diff --git a/mdw/kdp_usb_uvc/include/utils.h b/mdw/kdp_usb_uvc/include/utils.h new file mode 100644 index 0000000..2a17912 --- /dev/null +++ b/mdw/kdp_usb_uvc/include/utils.h @@ -0,0 +1,133 @@ +#ifndef _UTILS_H_ +#define _UTILS_H_ +#include +#include +#include +#include + + +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + + +#define ___PASTE(a,b) a##b + +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#define __min(t1, t2, min1, min2, x, y) ({ \ + t1 min1 = (x); \ + t2 min2 = (y); \ + (void) (&min1 == &min2); \ + min1 < min2 ? min1 : min2; }) + +#define min(x, y) \ + __min(typeof(x), typeof(y), \ + __UNIQUE_ID(min1_), __UNIQUE_ID(min2_), \ + x, y) + +#define __max(t1, t2, max1, max2, x, y) ({ \ + t1 max1 = (x); \ + t2 max2 = (y); \ + (void) (&max1 == &max2); \ + max1 > max2 ? max1 : max2; }) + +#define max(x, y) \ + __max(typeof(x), typeof(y), \ + __UNIQUE_ID(max1_), __UNIQUE_ID(max2_), \ + x, y) + +#define min3(x, y, z) min((typeof(x))min(x, y), z) +#define max3(x, y, z) max((typeof(x))max(x, y), z) + +/** + * min_not_zero - return the minimum that is _not_ zero, unless both are zero + * @x: value1 + * @y: value2 + */ +#define min_not_zero(x, y) ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); }) + +/** + * clamp - return a value clamped to a given range with strict typechecking + * @val: current value + * @lo: lowest allowable value + * @hi: highest allowable value + * + * This macro does strict typechecking of lo/hi to make sure they are of the + * same type as val. See the unnecessary pointer comparisons. + */ +#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) + +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max/clamp at all, of course. + */ +#define min_t(type, x, y) \ + __min(type, type, \ + __UNIQUE_ID(min1_), __UNIQUE_ID(min2_), \ + x, y) + +#define max_t(type, x, y) \ + __max(type, type, \ + __UNIQUE_ID(min1_), __UNIQUE_ID(min2_), \ + x, y) + +/** + * clamp_t - return a value clamped to a given range using a given type + * @type: the type of variable to use + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of type + * 'type' to make all the comparisons. + */ +#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi) + +/** + * clamp_val - return a value clamped to a given range using val's type + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of whatever + * type the input argument 'val' is. This is useful when val is an unsigned + * type and min and max are literals that will otherwise be assigned a signed + * integer type. + */ +#define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi) + + +/* + * swap - swap value of @a and @b + */ +#define swap(a, b) \ + do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +//#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE *)0)->MEMBER) + + + +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +//typedef long __kernel_long_t; +//typedef unsigned long __kernel_ulong_t; +#define BITS_PER_LONG 32 +#define UINT_MAX (~0U) + diff --git a/mdw/kdp_usb_uvc/include/uvc.h b/mdw/kdp_usb_uvc/include/uvc.h new file mode 100644 index 0000000..bb1943f --- /dev/null +++ b/mdw/kdp_usb_uvc/include/uvc.h @@ -0,0 +1,745 @@ +/* + * Universal Serial Bus Device Class Definition for Video Devices + * + * Copyright (C) 2019 Kneron + * + * This file holds USB constants and structures defined by the USB Device + * Class Definition for Video Devices. + * USB Video Class 1.5 specification + * + */ + +#ifndef __UVC_H +#define __UVC_H +#include + + +/* -------------------------------------------------------------------------- + * UVC constants + */ + +/* Appendix A. Video Device Class Codes */ +/* A.2. Video Interface Codes */ + +#define UVC_CC_VIDEO 0x0E + +/* A.2. Video Interface Subclass Codes */ +#define UVC_SC_UNDEFINED 0x00 +#define UVC_SC_VIDEOCONTROL 0x01 +#define UVC_SC_VIDEOSTREAMING 0x02 +#define UVC_SC_VIDEO_INTERFACE_COLLECTION 0x03 + +/* A.3. Video Interface Protocol Codes */ +#define UVC_PC_PROTOCOL_UNDEFINED 0x00 +#define UVC_PC_PROTOCOL_15 0x01 + +/* A.4. Video Class-Specific Descriptor Types */ + +#define CS_UNDEFINED 0x20 +#define CS_DEVICE 0x21 +#define CS_CONFIGURATION 0x22 +#define CS_STRING 0x23 +#define CS_INTERFACE 0x24 +#define CS_ENDPOINT 0x25 + +/* A.5. Video Class-Specific VC Interface Descriptor Subtypes */ +#define UVC_VC_DESCRIPTOR_UNDEFINED 0x00 +#define UVC_VC_HEADER 0x01 +#define UVC_VC_INPUT_TERMINAL 0x02 +#define UVC_VC_OUTPUT_TERMINAL 0x03 +#define UVC_VC_SELECTOR_UNIT 0x04 +#define UVC_VC_PROCESSING_UNIT 0x05 +#define UVC_VC_EXTENSION_UNIT 0x06 +#define UVC_VC_ENCODING_UNIT 0x07 + + +/* A.6. Video Class-Specific VS Interface Descriptor Subtypes */ +#define UVC_VS_UNDEFINED 0x00 +#define UVC_VS_INPUT_HEADER 0x01 +#define UVC_VS_OUTPUT_HEADER 0x02 +#define UVC_VS_STILL_IMAGE_FRAME 0x03 +#define UVC_VS_FORMAT_UNCOMPRESSED 0x04 +#define UVC_VS_FRAME_UNCOMPRESSED 0x05 +#define UVC_VS_FORMAT_MJPEG 0x06 +#define UVC_VS_FRAME_MJPEG 0x07 +#define UVC_VS_FORMAT_MPEG2TS 0x0a +#define UVC_VS_FORMAT_DV 0x0c +#define UVC_VS_COLORFORMAT 0x0d +#define UVC_VS_FORMAT_FRAME_BASED 0x10 +#define UVC_VS_FRAME_FRAME_BASED 0x11 +#define UVC_VS_FORMAT_STREAM_BASED 0x12 +#define VS_FORMAT_H264 0x13 +#define VS_FRAME_H264 0x14 +#define VS_FORMAT_H264_SIMULCAST 0x15 +#define VS_FORMAT_VP8 0x16 +#define VS_FRAME_VP8 0x17 +#define VS_FORMAT_VP8_SIMULCAST 0x18 + +/* A.7. Video Class-Specific Endpoint Descriptor Subtypes */ +#define UVC_EP_UNDEFINED 0x00 +#define UVC_EP_GENERAL 0x01 +#define UVC_EP_ENDPOINT 0x02 +#define UVC_EP_INTERRUPT 0x03 + +/* A.8. Video Class-Specific Request Codes */ +#define UVC_RC_UNDEFINED 0x00 +#define UVC_SET_CUR 0x01 +#define UVC_SET_CUR_ALL 0x11 +#define UVC_GET_CUR 0x81 +#define UVC_GET_MIN 0x82 +#define UVC_GET_MAX 0x83 +#define UVC_GET_RES 0x84 +#define UVC_GET_LEN 0x85 +#define UVC_GET_INFO 0x86 +#define UVC_GET_DEF 0x87 +#define UVC_GET_CUR_ALL 0x91 +#define UVC_GET_MIN_ALL 0x92 +#define UVC_GET_MAX_ALL 0x93 +#define UVC_GET_RES_ALL 0x94 +#define UVC_GET_DEF_ALL 0x97 + +/* A.9.1. VideoControl Interface Control Selectors */ +#define UVC_VC_CONTROL_UNDEFINED 0x00 +#define UVC_VC_VIDEO_POWER_MODE_CONTROL 0x01 +#define UVC_VC_REQUEST_ERROR_CODE_CONTROL 0x02 + +/* A.9.2. Terminal Control Selectors */ +#define UVC_TE_CONTROL_UNDEFINED 0x00 + +/* A.9.3. Selector Unit Control Selectors */ +#define UVC_SU_CONTROL_UNDEFINED 0x00 +#define UVC_SU_INPUT_SELECT_CONTROL 0x01 + +/* A.9.4. Camera Terminal Control Selectors */ +#define UVC_CT_CONTROL_UNDEFINED 0x00 +#define UVC_CT_SCANNING_MODE_CONTROL 0x01 +#define UVC_CT_AE_MODE_CONTROL 0x02 +#define UVC_CT_AE_PRIORITY_CONTROL 0x03 +#define UVC_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04 +#define UVC_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05 +#define UVC_CT_FOCUS_ABSOLUTE_CONTROL 0x06 +#define UVC_CT_FOCUS_RELATIVE_CONTROL 0x07 +#define UVC_CT_FOCUS_AUTO_CONTROL 0x08 +#define UVC_CT_IRIS_ABSOLUTE_CONTROL 0x09 +#define UVC_CT_IRIS_RELATIVE_CONTROL 0x0a +#define UVC_CT_ZOOM_ABSOLUTE_CONTROL 0x0b +#define UVC_CT_ZOOM_RELATIVE_CONTROL 0x0c +#define UVC_CT_PANTILT_ABSOLUTE_CONTROL 0x0d +#define UVC_CT_PANTILT_RELATIVE_CONTROL 0x0e +#define UVC_CT_ROLL_ABSOLUTE_CONTROL 0x0f +#define UVC_CT_ROLL_RELATIVE_CONTROL 0x10 +#define UVC_CT_PRIVACY_CONTROL 0x11 +#define UVC_CT_FOCUS_SIMPLE_CONTROL 0x12 +#define UVC_CT_WINDOW_CONTROL 0x13 +#define UVC_CT_REGION_OF_INTEREST_CONTROL 0x14 + + +/* A.9.5. Processing Unit Control Selectors */ +#define UVC_PU_CONTROL_UNDEFINED 0x00 +#define UVC_PU_BACKLIGHT_COMPENSATION_CONTROL 0x01 +#define UVC_PU_BRIGHTNESS_CONTROL 0x02 +#define UVC_PU_CONTRAST_CONTROL 0x03 +#define UVC_PU_GAIN_CONTROL 0x04 +#define UVC_PU_POWER_LINE_FREQUENCY_CONTROL 0x05 +#define UVC_PU_HUE_CONTROL 0x06 +#define UVC_PU_SATURATION_CONTROL 0x07 +#define UVC_PU_SHARPNESS_CONTROL 0x08 +#define UVC_PU_GAMMA_CONTROL 0x09 +#define UVC_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x0a +#define UVC_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0b +#define UVC_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x0c +#define UVC_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x0d +#define UVC_PU_DIGITAL_MULTIPLIER_CONTROL 0x0e +#define UVC_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x0f +#define UVC_PU_HUE_AUTO_CONTROL 0x10 +#define UVC_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x11 +#define UVC_PU_ANALOG_LOCK_STATUS_CONTROL 0x12 +#define UVC_PU_CONTRAST_AUTO_CONTROL 0x13 + +/* A.9.6. Encoding Unit Control Selectors */ + +#define UVC_EU_CONTROL_UNDEFINED 0x00 +#define UVC_EU_SELECT_LAYER_CONTROL 0x01 +#define UVC_EU_PROFILE_TOOLSET_CONTROL 0x02 +#define UVC_EU_VIDEO_RESOLUTION_CONTROL 0x03 +#define UVC_EU_MIN_FRAME_INTERVAL_CONTROL 0x04 +#define UVC_EU_SLICE_MODE_CONTROL 0x05 +#define UVC_EU_RATE_CONTROL_MODE_CONTROL 0x06 +#define UVC_EU_AVERAGE_BITRATE_CONTROL 0x07 +#define UVC_EU_CPB_SIZE_CONTROL 0x08 +#define UVC_EU_PEAK_BIT_RATE_CONTROL 0x09 +#define UVC_EU_QUANTIZATION_PARAMS_CONTROL 0x0A +#define UVC_EU_SYNC_REF_FRAME_CONTROL 0x0B +#define UVC_EU_LTR_BUFFER_CONTROL 0x0C +#define UVC_EU_LTR_PICTURE_CONTROL 0x0D +#define UVC_EU_LTR_VALIDATION_CONTROL 0x0E +#define UVC_EU_LEVEL_IDC_LIMIT_CONTROL 0x0F +#define UVC_EU_SEI_PAYLOADTYPE_CONTROL 0x10 +#define UVC_EU_QP_RANGE_CONTROL 0x11 +#define UVC_EU_PRIORITY_CONTROL 0x12 +#define UVC_EU_START_OR_STOP_LAYER_CONTROL 0x13 +#define UVC_EU_ERROR_RESILIENCY_CONTROL 0x14 + +/* A.9.7. Extension Unit Control Selectors */ + +#define UVC_XU_CONTROL_UNDEFINED 0x00 + +/* A.9.8. VideoStreaming Interface Control Selectors */ +#define UVC_VS_CONTROL_UNDEFINED 0x00 +#define UVC_VS_PROBE_CONTROL 0x01 +#define UVC_VS_COMMIT_CONTROL 0x02 +#define UVC_VS_STILL_PROBE_CONTROL 0x03 +#define UVC_VS_STILL_COMMIT_CONTROL 0x04 +#define UVC_VS_STILL_IMAGE_TRIGGER_CONTROL 0x05 +#define UVC_VS_STREAM_ERROR_CODE_CONTROL 0x06 +#define UVC_VS_GENERATE_KEY_FRAME_CONTROL 0x07 +#define UVC_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08 +#define UVC_VS_SYNC_DELAY_CONTROL 0x09 + +/* B.1. USB Terminal Types */ +#define UVC_TT_VENDOR_SPECIFIC 0x0100 +#define UVC_TT_STREAMING 0x0101 + +/* B.2. Input Terminal Types */ +#define UVC_ITT_VENDOR_SPECIFIC 0x0200 +#define UVC_ITT_CAMERA 0x0201 +#define UVC_ITT_MEDIA_TRANSPORT_INPUT 0x0202 + +/* B.3. Output Terminal Types */ +#define UVC_OTT_VENDOR_SPECIFIC 0x0300 +#define UVC_OTT_DISPLAY 0x0301 +#define UVC_OTT_MEDIA_TRANSPORT_OUTPUT 0x0302 + +/* B.4. External Terminal Types */ +#define UVC_EXTERNAL_VENDOR_SPECIFIC 0x0400 +#define UVC_COMPOSITE_CONNECTOR 0x0401 +#define UVC_SVIDEO_CONNECTOR 0x0402 +#define UVC_COMPONENT_CONNECTOR 0x0403 + +/* VIC (Video Interface Collection) described by IAD ( Interface Association Descriptor) = ONE VC + serval VS*/ + + +/* 2.4.2.2. Status Packet Type */ +#define UVC_STATUS_TYPE_CONTROL 1 +#define UVC_STATUS_TYPE_STREAMING 2 + +/* 2.4.3.3. Payload Header Information */ +#define UVC_STREAM_EOH (1 << 7) +#define UVC_STREAM_ERR (1 << 6) +#define UVC_STREAM_STI (1 << 5) +#define UVC_STREAM_RES (1 << 4) +#define UVC_STREAM_SCR (1 << 3) +#define UVC_STREAM_PTS (1 << 2) +#define UVC_STREAM_EOF (1 << 1) +#define UVC_STREAM_FID (1 << 0) + +/* 4.1.2. Control Capabilities */ +#define UVC_CONTROL_CAP_GET (1 << 0) +#define UVC_CONTROL_CAP_SET (1 << 1) +#define UVC_CONTROL_CAP_DISABLED (1 << 2) +#define UVC_CONTROL_CAP_AUTOUPDATE (1 << 3) +#define UVC_CONTROL_CAP_ASYNCHRONOUS (1 << 4) + +/* ------------------------------------------------------------------------ + * UVC structures + */ + +struct uvc_inf_assoc_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __attribute__((__packed__)); + + +/* All UVC descriptors have these 3 fields at the beginning */ +struct uvc_descriptor_header { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; +} __attribute__((__packed__)); + +/* 3.7.2. Video Control Interface Header Descriptor */ +struct uvc_vc_if_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t bcdUVC; + uint16_t wTotalLength; + uint32_t dwClockFrequency; + uint8_t bInCollection; + uint8_t baInterfaceNr[]; +} __attribute__((__packed__)); + +#define UVC_DT_HEADER_SIZE(n) (12+(n)) + +#define UVC_HEADER_DESCRIPTOR(n) \ + uvc_header_descriptor_##n + +#define DECLARE_UVC_HEADER_DESCRIPTOR(n) \ +struct UVC_HEADER_DESCRIPTOR(n) { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint16_t bcdUVC; \ + uint16_t wTotalLength; \ + uint32_t dwClockFrequency; \ + uint8_t bInCollection; \ + uint8_t baInterfaceNr[n]; \ +} __attribute__ ((packed)) + +/* 3.7.2.1. Input Terminal Descriptor */ +struct uvc_input_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t iTerminal; +} __attribute__((__packed__)); + +#define UVC_DT_INPUT_TERMINAL_SIZE 8 + +/* 3.7.2.2. Output Terminal Descriptor */ +struct uvc_output_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bSourceID; + uint8_t iTerminal; +} __attribute__((__packed__)); + +#define UVC_DT_OUTPUT_TERMINAL_SIZE 9 +#define UVC_DT_CT_CONST_LEN 15 +/* 3.7.2.3. Camera Terminal Descriptor */ +struct uvc_camera_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t iTerminal; + uint16_t wObjectiveFocalLengthMin; + uint16_t wObjectiveFocalLengthMax; + uint16_t wOcularFocalLength; + uint8_t bControlSize; + uint8_t bmControls[0]; +} __attribute__((__packed__)); + +#define UVC_DT_CAMERA_TERMINAL_SIZE(n) (15+(n)) + +/* 3.7.2.4. Selector Unit Descriptor */ +#define UVC_SU_CONST_LEN 5 +struct uvc_selector_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bUnitID; + uint8_t bNrInPins; + uint8_t baSourceID[0]; + uint8_t iSelector; +} __attribute__((__packed__)); + +#define UVC_DT_SELECTOR_UNIT_SIZE(n) (6+(n)) + +#define UVC_SELECTOR_UNIT_DESCRIPTOR(n) \ + uvc_selector_unit_descriptor_##n + +#define DECLARE_UVC_SELECTOR_UNIT_DESCRIPTOR(n) \ +struct UVC_SELECTOR_UNIT_DESCRIPTOR(n) { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bUnitID; \ + uint8_t bNrInPins; \ + uint8_t baSourceID[n]; \ + uint8_t iSelector; \ +} __attribute__ ((packed)) + +/* 3.7.2.5. Processing Unit Descriptor */ +#define UVC_PU_CONST_LEN 8 +struct uvc_processing_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bUnitID; + uint8_t bSourceID; + uint16_t wMaxMultiplier; + uint8_t bControlSize; + uint8_t bmControls[0]; + uint8_t iProcessing; + uint8_t bmVideoStandards; +} __attribute__((__packed__)); + +#define UVC_DT_PROCESSING_UNIT_SIZE(n) (9+(n)) + +/*3.7.2.6 Encoding Unit Descriptor*/ +#define UVC_EU_CONST_LEN 7 +struct uvc_encoding_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bUnitID; + uint8_t bSourceID; + uint8_t iEncoding; + uint8_t bControlSize; + uint8_t bmControls[0]; + uint8_t bmControlsRuntime[0]; +} __attribute__((__packed__)); + +/* 3.7.2.7. Extension Unit Descriptor */ +#define UVC_XU_CONST_LEN 22 +struct uvc_extension_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bUnitID; + uint8_t guidExtensionCode[16]; + uint8_t bNumControls; + uint8_t bNrInPins; + uint8_t baSourceID[0]; + uint8_t bControlSize; + uint8_t bmControls[0]; + uint8_t iExtension; +} __attribute__((__packed__)); + +#define UVC_DT_EXTENSION_UNIT_SIZE(p, n) (24+(p)+(n)) + +#define UVC_EXTENSION_UNIT_DESCRIPTOR(p, n) \ + uvc_extension_unit_descriptor_##p_##n + +#define DECLARE_UVC_EXTENSION_UNIT_DESCRIPTOR(p, n) \ +struct UVC_EXTENSION_UNIT_DESCRIPTOR(p, n) { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bUnitID; \ + uint8_t guidExtensionCode[16]; \ + uint8_t bNumControls; \ + uint8_t bNrInPins; \ + uint8_t baSourceID[p]; \ + uint8_t bControlSize; \ + uint8_t bmControls[n]; \ + uint8_t iExtension; \ +} __attribute__ ((packed)) + +/* 3.8.2.2. Class-specific VC (Video Control) Interrupt Endpoint Descriptor */ +struct uvc_control_endpoint_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t wMaxTransferSize; +} __attribute__((__packed__)); + +#define UVC_DT_CONTROL_ENDPOINT_SIZE 5 + +/* 3.9.2.1. Input Header Descriptor */ +struct uvc_input_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + uint8_t bmInfo; + uint8_t bTerminalLink; + uint8_t bStillCaptureMethod; + uint8_t bTriggerSupport; + uint8_t bTriggerUsage; + uint8_t bControlSize; + uint8_t bmaControls[]; +} __attribute__((__packed__)); + +struct uvc_ET_Head_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + +} __attribute__((__packed__)); + +#define UVC_DT_INPUT_HEADER_SIZE(n, p) (13+(n*p)) + +#define UVC_INPUT_HEADER_DESCRIPTOR(n, p) \ + uvc_input_header_descriptor_##n_##p + +#define DECLARE_UVC_INPUT_HEADER_DESCRIPTOR(n, p) \ +struct UVC_INPUT_HEADER_DESCRIPTOR(n, p) { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bNumFormats; \ + uint16_t wTotalLength; \ + uint8_t bEndpointAddress; \ + uint8_t bmInfo; \ + uint8_t bTerminalLink; \ + uint8_t bStillCaptureMethod; \ + uint8_t bTriggerSupport; \ + uint8_t bTriggerUsage; \ + uint8_t bControlSize; \ + uint8_t bmaControls[p][n]; \ +} __attribute__ ((packed)) + +/* 3.9.2.2. Output Header Descriptor */ +struct uvc_output_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + uint8_t bTerminalLink; + uint8_t bControlSize; + uint8_t bmaControls[]; +} __attribute__((__packed__)); + +#define UVC_DT_OUTPUT_HEADER_SIZE(n, p) (9+(n*p)) + +#define UVC_OUTPUT_HEADER_DESCRIPTOR(n, p) \ + uvc_output_header_descriptor_##n_##p + +#define DECLARE_UVC_OUTPUT_HEADER_DESCRIPTOR(n, p) \ +struct UVC_OUTPUT_HEADER_DESCRIPTOR(n, p) { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bNumFormats; \ + uint16_t wTotalLength; \ + uint8_t bEndpointAddress; \ + uint8_t bTerminalLink; \ + uint8_t bControlSize; \ + uint8_t bmaControls[p][n]; \ +} __attribute__ ((packed)) + + +/* 3.9.2.5 Still Image Frame Descriptor */ +struct uvc_still_image_frame_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bEndpointAddress; + uint8_t bNumImageSizePatterns; + uint16_t wWidth[0]; + uint16_t wHeight[0]; + uint8_t bNumCompressionPattern; + uint8_t bCompression[]; +} __attribute__((__packed__)); + +#define UVC_STILL_IMAGE_FRAME_DESCRIPTOR_SIZE(l, n) (6+(4*l + 2*n)) + +#define UVC_STILL_IMAGE_FRAME_DESCRIPTOR(l, n) \ + uvc_still_image_frame_descriptor_##n_##p + +#define DECLARE_UVC_STILL_IMAGE_FRAME_DESCRIPTOR(l, n) \ +struct UVC_STILL_IMAGE_FRAME_DESCRIPTOR(l, n) { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bEndpointAddress; \ + uint8_t bNumImageSizePatterns; \ + uint16_t wWidth[l]; \ + uint16_t wHeight[n]; \ + uint8_t bNumCompressionPattern; \ + uint8_t bCompression[l]; \ +} __attribute__ ((packed)) + + +/* 3.9.2.6. Color matching descriptor */ +struct uvc_color_matching_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bColorPrimaries; + uint8_t bTransferCharacteristics; + uint8_t bMatrixCoefficients; +} __attribute__((__packed__)); + +#define UVC_DT_COLOR_MATCHING_SIZE 6 + +/* 4.3.1.1. Video Probe and Commit Controls */ +struct uvc_streaming_control_data { + uint16_t wmHint; + uint8_t bFormatIndex; + uint8_t bFrameIndex; + uint32_t dwFrameInterval; + uint16_t wKeyFrameRate; + uint16_t wPFrameRate; + uint16_t wCompQuality; + uint16_t wCompWindowSize; + uint16_t wDelay; + uint32_t dwMaxVideoFrameSize; + uint32_t dwMaxPayloadTransferSize; + uint32_t dwClockFrequency; + uint8_t bmFramingInfo; + uint8_t bPreferedVersion; + uint8_t bMinVersion; + uint8_t bMaxVersion; + uint8_t bUsage; + uint8_t bBitDrpthLuma; + uint8_t bmSetting; + uint8_t bMaxNumberOfRefFeamesPlus1; + uint16_t wRateControlModes; + uint8_t bmLayoutPerStream[8]; +} __attribute__((__packed__)); + +struct uvc_vs_still_control_data { + uint8_t bFormatIndex; + uint8_t bFrameIndex; + uint8_t bCompressionIndex; + uint32_t dwMaxVideoFrameSize; + uint32_t dwMaxPayloadTransferSize; +} __attribute__((__packed__)); + +struct uvc_format_desc_head { + uint8_t bLength; + uint8_t bDescriptorType;// Constant CS_INTERFACE Descriptor type. + uint8_t bDescriptorSubtype; // Constant VS_FORMAT_MJPEG Descriptor subtype 3 + uint8_t bFormatIndex; +} __attribute__((__packed__)); + +struct uvc_frame_desc_head { + uint8_t bLength; + uint8_t bDescriptorType;// Constant CS_INTERFACE Descriptor type. + uint8_t bDescriptorSubtype; // Constant VS_FORMAT_MJPEG Descriptor subtype 3 + uint8_t bFrameIndex; +} __attribute__((__packed__)); + +/* Uncompressed Payload - 3.1.1. Uncompressed Video Format Descriptor */ +struct uvc_format_uncompressed { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bNumFrameDescriptors; + uint8_t guidFormat[16]; + uint8_t bBitsPerPixel; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterfaceFlags; + uint8_t bCopyProtect; +} __attribute__((__packed__)); + +#define UVC_DT_FORMAT_UNCOMPRESSED_SIZE 27 + +/* Uncompressed Payload - 3.1.2. Uncompressed Video Frame Descriptor */ +struct uvc_frame_uncompressed { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFrameIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwMaxVideoFrameBufferSize; + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t dwFrameInterval[]; +} __attribute__((__packed__)); + +#define UVC_DT_FRAME_UNCOMPRESSED_SIZE(n) (26+4*(n)) + +#define UVC_FRAME_UNCOMPRESSED(n) \ + uvc_frame_uncompressed_##n + +#define DECLARE_UVC_FRAME_UNCOMPRESSED(n) \ +struct UVC_FRAME_UNCOMPRESSED(n) { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bFrameIndex; \ + uint8_t bmCapabilities; \ + uint16_t wWidth; \ + uint16_t wHeight; \ + uint32_t dwMinBitRate; \ + uint32_t dwMaxBitRate; \ + uint32_t dwMaxVideoFrameBufferSize; \ + uint32_t dwDefaultFrameInterval; \ + uint8_t bFrameIntervalType; \ + uint32_t dwFrameInterval[n]; \ +} __attribute__ ((__packed__)) + +/* MJPEG Payload - 3.1.1. MJPEG Video Format Descriptor */ +struct uvc_format_mjpeg { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bNumFrameDescriptors; + uint8_t bmFlags; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterfaceFlags; + uint8_t bCopyProtect; +} __attribute__((__packed__)); + +#define UVC_DT_FORMAT_MJPEG_SIZE 11 + +/* MJPEG Payload - 3.1.2. MJPEG Video Frame Descriptor */ +struct uvc_frame_mjpeg { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFrameIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwMaxVideoFrameBufferSize; + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t dwFrameInterval[]; +} __attribute__((__packed__)); + +#define UVC_DT_FRAME_MJPEG_SIZE(n) (26+4*(n)) + +#define UVC_FRAME_MJPEG(n) \ + uvc_frame_mjpeg_##n + +#define DECLARE_UVC_FRAME_MJPEG(n) \ +struct UVC_FRAME_MJPEG(n) { \ + uint8_t bLength; \ + uint8_t bDescriptorType; \ + uint8_t bDescriptorSubType; \ + uint8_t bFrameIndex; \ + uint8_t bmCapabilities; \ + uint16_t wWidth; \ + uint16_t wHeight; \ + uint32_t dwMinBitRate; \ + uint32_t dwMaxBitRate; \ + uint32_t dwMaxVideoFrameBufferSize; \ + uint32_t dwDefaultFrameInterval; \ + uint8_t bFrameIntervalType; \ + uint32_t dwFrameInterval[n]; \ +} __attribute__ ((packed)) + +struct uvc_format_frame_based { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFrameIndex; + uint8_t bNumFrameDescriptors; + uint8_t guidFormat[16]; + uint8_t bBitsPerPixel; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterfaceFlags; + uint8_t bCopyProtect; + uint8_t bVariableSize; +} __attribute__((__packed__)); + +#endif /* __UVC_H */ + diff --git a/mdw/kdp_usb_uvc/include/uvc_camera.h b/mdw/kdp_usb_uvc/include/uvc_camera.h new file mode 100644 index 0000000..b054cc4 --- /dev/null +++ b/mdw/kdp_usb_uvc/include/uvc_camera.h @@ -0,0 +1,691 @@ +/******************************************************************** +* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. +* +* The information contained herein is property of Kneron, Inc. +* Terms and conditions of usage are described in detail in Kneron +* STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. +* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed +* from the file. +********************************************************************/ +#ifndef __UVC_CAMERA_H__ +#define __UVC_CAMERA_H__ +#include +#include +#include "kmdw_status.h" + +#define SCANNING_MODE 0x1 +#define AUTO_EXPOSURE_MODE 0x2 +#define AUTO_EXPOSURE_PRIORITY 0x4 +#define EXPOSURE_TIME_ABSOLUTE 0x8 +#define EXPOSURE_TIME_RELATIVE 0x10 +#define FOCUS_ABSOLUTE 0x20 +#define FOCUS_RELATIVE 0x40 +#define IRIS_ABSOLUTE 0x80 +#define IRIS_RELATIVE 0x100 +#define ZOOM_ABSOLUTE 0x200 +#define ZOOM_RELATIVE 0x400 +#define PANTILT_ABSOLUTE 0x800 +#define PANTILT_RELATIVE 0x1000 +#define ROLL_ABSOLUTE 0x2000 +#define ROLL_RELATIVE 0x4000 +#define FOCUS_AUTO 0x20000 +#define PRIVACY 0x40000 +#define FOCUS_SIMPLE 0x80000 +#define WINDOW 0x100000 +#define REGION_OF_INTEREST 0x200000 + +#define BRIGHTNESS 0x1 +#define CONTRAST 0x2 +#define HUE 0x4 +#define SATURATION 0x8 +#define SHARPNESS 0x10 +#define GAMMA 0x20 +#define WHITE_BALANCE_TEMPERATURE 0x40 +#define WHITE_BALANCE_COMPONENT 0x80 +#define BACKLIGHT_COMPENSATION 0x100 +#define GAIN 0x200 +#define POWER_LINE_FREQUENCY 0x400 +#define HUE_AUTO 0x800 +#define WHITE_BALANCE_TEMPERATURE_AUTO 0x1000 +#define WHITE_BALANCE_COMPONENT_AUTO 0x2000 +#define DIGITAL_MULTIPLIER 0x4000 +#define DIGITAL_MULTIPLIER_LIMIT 0x8000 +#define ANALOG_VIDEO_STANDARD 0x10000 +#define ANALOG_VIDEO_LOCK_STATUS 0x20000 +#define CONTRAST_AUTO 0x40000 + +#define UVC_SET_CUR 0x01 +#define UVC_GET_CUR 0x81 +#define UVC_GET_MIN 0x82 +#define UVC_GET_MAX 0x83 +#define UVC_GET_RES 0x84 +#define UVC_GET_LEN 0x85 +#define UVC_GET_INFO 0x86 +#define UVC_GET_DEF 0x87 + +#define SCANNING_MODE_CTL_INTERLACED 0x0 +#define SCANNING_MODE_CTL_PROGRESSIVE 0x1 +enum scm_req { + SCM_SET_CUR = 0x01, + SCM_GET_CUR = 0x81, + SCM_GET_CAP = 0x86 +}; + +struct ct_scm { + enum scm_req req; + uint8_t caps; + bool bScanningMode; +}; + +#define EXPOSURE_MANUAL_MODE 0x1 +#define EXPOSURE_AUTO_MODE 0x2 +#define EXPOSURE_SHUTTER_PRIORITY_MODE 0x4 +#define EXPOSURE_APERTURE_PRIORITY_MODE 0x8 +enum aem_req { + AEM_SET_CUR = 0x01, + AEM_GET_CUR = 0x81, + AEM_GET_RES = 0x84, + AEM_GET_CAP = 0x86, + AEM_GET_DEF = 0x87 +}; + +struct ct_aem { + enum aem_req req; + uint8_t caps; + uint8_t bAutoExposureMode; +}; + +#define EXPOSURE_FRAME_RATE_CONSTANT 0x0 +#define EXPOSURE_FRAME_RATE_VARIED 0x1 +enum aep_req { + AEP_SET_CUR = 0x01, + AEP_GET_CUR = 0x81, + AEP_GET_CAP = 0x86 +}; + +struct ct_aep { + enum aep_req req; + uint8_t caps; + uint8_t bAutoExposurePriority; +}; + +enum eta_req { + ETA_SET_CUR = 0x01, + ETA_GET_CUR = 0x81, + ETA_GET_MIN = 0x82, + ETA_GET_MAX = 0x83, + ETA_GET_RES = 0x84, + ETA_GET_CAP = 0x86, + ETA_GET_DEF = 0x87, +}; + +struct ct_eta { + enum eta_req req; + uint8_t caps; + uint32_t bExposureTimeAbsolute; +}; + +enum etr_req { + ETR_SET_CUR = 0x01, + ETR_GET_CUR = 0x81, + ETR_GET_CAP = 0x86 +}; + +struct ct_etr { + enum etr_req req; + uint8_t caps; + int8_t bExposureTimeRelative; +}; + +enum focus_a_req { + FA_SET_CUR = 0x01, + FA_GET_CUR = 0x81, + FA_GET_MIN = 0x82, + FA_GET_MAX = 0x83, + FA_GET_RES = 0x84, + FA_GET_CAP = 0x86, + FA_GET_DEF = 0x87, +}; + +struct ct_focus_a { + enum focus_a_req req; + uint8_t caps; + uint16_t wFocusAbsolute; +}; + +enum fr_req { + FR_SET_CUR = 0x01, + FR_GET_CUR = 0x81, + FR_GET_MIN = 0x82, + FR_GET_MAX = 0x83, + FR_GET_RES = 0x84, + FR_GET_CAP = 0x86, + FR_GET_DEF = 0x87 +}; + +struct ct_focus_r_data { + int8_t bFocusRelative; + uint8_t bSpeed; +}; + +struct ct_focus_r{ + enum fr_req req; + uint8_t caps; + struct ct_focus_r_data data; +}; + +#define FSR_FULL_RANGE 0x1 +#define FSR_MACRO 0x2 +#define FSR_PEOPLE 0x3 +#define FSR_SCENE 0x4 +enum fsr_req { + FSR_SET_CUR = 0x01, + FSR_GET_CUR = 0x81, + FSR_GET_CAP = 0x86, + FSR_GET_DEF = 0x87 +}; + +struct ct_focus_sr{ + enum fsr_req req; + uint8_t caps; + uint8_t bFocus; +}; + +enum fauto_req { + FAUTO_SET_CUR = 0x01, + FAUTO_GET_CUR = 0x81, + FAUTO_GET_CAP = 0x86, + FAUTO_GET_DEF = 0x87 +}; + +struct ct_fauto{ + enum fauto_req req; + uint8_t caps; + uint8_t bFocusAuto; +}; + +enum irisa_req { + IRISA_SET_CUR = 0x01, + IRISA_GET_CUR = 0x81, + IRISA_GET_MIN = 0x82, + IRISA_GET_MAX = 0x83, + IRISA_GET_RES = 0x84, + IRISA_GET_CAP = 0x86, + IRISA_GET_DEF = 0x87 +}; + +struct ct_iris_a { + enum irisa_req req; + uint8_t caps; + uint16_t wIrisAbsolute; +}; + +enum irisr_req { + IRISR_SET_CUR = 0x01, + IRISR_GET_CUR = 0x81, + IRISR_GET_CAP = 0x86 +}; + +struct ct_iris_r{ + enum irisr_req req; + uint8_t caps; + uint8_t bIrisRelative; +}; + +enum zooma_req { + ZOOMA_SET_CUR = 0x01, + ZOOMA_GET_CUR = 0x81, + ZOOMA_GET_MIN = 0x82, + ZOOMA_GET_MAX = 0x83, + ZOOMA_GET_RES = 0x84, + ZOOMA_GET_CAP = 0x86, + ZOOMA_GET_DEF = 0x87 +}; + +struct ct_zoom_a{ + enum zooma_req req; + uint8_t caps; + uint16_t wObjectiveFocalLength; +}; + +enum zoomr_req { + ZOOMR_SET_CUR = 0x01, + ZOOMR_GET_CUR = 0x81, + ZOOMR_GET_MIN = 0x82, + ZOOMR_GET_MAX = 0x83, + ZOOMR_GET_RES = 0x84, + ZOOMR_GET_CAP = 0x86, + ZOOMR_GET_DEF = 0x87 +}; + +#define ZOOM_STOP 0x0 +#define ZOOM_TELE_DIR 0x1 +#define ZOOM_WIDE_AGLE_DIR 0xFF +#define DIGITAL_ZOOM_OFF 0x0 +#define DIGITAL_ZOOM_ON 0x1 +struct ct_zoomr_data{ + int8_t bZoom; + bool bDigitalZoom; + uint16_t bSpeed; +}; + +struct ct_zoom_r{ + enum zoomr_req req; + uint8_t caps; + struct ct_zoomr_data data; +}; + +enum pantilta_req { + TILTA_SET_CUR = 0x01, + TILTA_GET_CUR = 0x81, + TILTA_GET_MIN = 0x82, + TILTA_GET_MAX = 0x83, + TILTA_GET_RES = 0x84, + TILTA_GET_CAP = 0x86, + TILTA_GET_DEF = 0x87, +}; + +struct ct_pan_tilta_data { + int32_t dwPanAbsolute; + int32_t dwTiltAbsolute; +}; + +struct ct_pan_tilt_a{ + enum pantilta_req req; + uint8_t caps; + struct ct_pan_tilta_data data; +}; + +enum pantiltr_req { + TILTR_SET_CUR = 0x01, + TILTR_GET_CUR = 0x81, + TILTR_GET_MIN = 0x82, + TILTR_GET_MAX = 0x83, + TILTR_GET_RES = 0x84, + TILTR_GET_CAP = 0x86, + TILTR_GET_DEF = 0x87, +}; + +#define PAN_STOP 0x0 +#define PAN_CLOSEWISE_DIR 0x1 +#define PAN_COUNTER_CLOSEWISE_DIR 0xFF +#define TILT_STOP 0x0 +#define TILT_POINT_IMG_UP 0x1 +#define TILT_POINT_IMG_DOWN 0xFF +struct ct_pan_tiltr_data { + int8_t bPanRelative; + uint8_t bPanSpeed; + int8_t bTiltRelative; + uint8_t bTiltSpeed; +}; + +struct ct_pan_tilt_r { + enum pantiltr_req req; + uint8_t caps; + struct ct_pan_tiltr_data data; +}; + +enum rolla_req { + ROLLA_SET_CUR = 0x01, + ROLLA_GET_CUR = 0x81, + ROLLA_GET_MIN = 0x82, + ROLLA_GET_MAX = 0x83, + ROLLA_GET_RES = 0x84, + ROLLA_GET_CAP = 0x86, + ROLLA_GET_DEF = 0x87, +}; + +struct ct_roll_a { + enum rolla_req req; + uint8_t caps; + int16_t wAbsolute; +}; + +enum rollr_req { + ROLLR_SET_CUR = 0x01, + ROLLR_GET_CUR = 0x81, + ROLLR_GET_MIN = 0x82, + ROLLR_GET_MAX = 0x83, + ROLLR_GET_RES = 0x84, + ROLLR_GET_CAP = 0x86, + ROLLR_GET_DEF = 0x87, +}; + +struct ct_rollr_data { + int8_t bRollRelative; + uint8_t bSpeed; +}; + +struct ct_roll_r { + enum rollr_req req; + uint8_t caps; + struct ct_rollr_data data; +}; + +enum ps_req { + PS_SET_CUR = 0x01, + PS_GET_CUR = 0x81, + PS_GET_CAP = 0x86, +}; + +#define SHUTTER_OPEN 0x0 +#define SHUTTER_CLOSE 0x1 +struct ct_privacy_shutter { + enum ps_req req; + uint8_t caps; + bool bPrivacy; +}; + +enum dwindow_req { + DWINDOW_SET_CUR = 0x01, + DWINDOW_GET_CUR = 0x81, + DWINDOW_GET_MIN = 0x82, + DWINDOW_GET_MAX = 0x83, + DWINDOW_GET_DEF = 0x87, +}; + +struct ct_dwindow_data { + uint16_t wWindow_Top; + uint16_t wWindow_Left; + uint16_t wWindow_Bottom; + uint16_t wWindow_Right; + uint16_t wNumSteps; + uint16_t bmNumStepsUnits; +}; + +struct ct_dwindow{ + enum dwindow_req req; + struct ct_dwindow_data data; +}; + +enum roi_req { + ROI_SET_CUR = 0x01, + ROI_GET_CUR = 0x81, + ROI_GET_MIN = 0x82, + ROI_GET_MAX = 0x83, + ROI_GET_DEF = 0x87, +}; + +struct ct_roi_data { + uint16_t wROI_Top; + uint16_t wROI_Left; + uint16_t wROI_Bottom; + uint16_t wROI_Right; + uint16_t bmAutoControls; +}; + +struct ct_roi{ + enum roi_req req; + struct ct_roi_data data; +}; + +enum backlight_req { + BKC_SET_CUR = 0x01, + BKC_GET_CUR = 0x81, + BKC_GET_MIN = 0x82, + BKC_GET_MAX = 0x83, + BKC_GET_RES = 0x84, + BKC_GET_CAP = 0x86, + BKC_GET_DEF = 0x87 +}; + +struct pu_backlight { + enum backlight_req req; + uint8_t caps; + uint16_t wBacklightCompensation; +}; + +enum brightness_req { + BRIGHTNESS_SET_CUR = 0x01, + BRIGHTNESS_GET_CUR = 0x81, + BRIGHTNESS_GET_MIN = 0x82, + BRIGHTNESS_GET_MAX = 0x83, + BRIGHTNESS_GET_RES = 0x84, + BRIGHTNESS_GET_CAP = 0x86, + BRIGHTNESS_GET_DEF = 0x87, +}; + +struct pu_brightness { + enum brightness_req req; + uint8_t caps; + int16_t wBrightness; +}; + +enum contrast_req { + CONTRAST_SET_CUR = 0x01, + CONTRAST_GET_CUR = 0x81, + CONTRAST_GET_MIN = 0x82, + CONTRAST_GET_MAX = 0x83, + CONTRAST_GET_RES = 0x84, + CONTRAST_GET_CAP = 0x86, + CONTRAST_GET_DEF = 0x87, +}; + +struct pu_contrast { + enum contrast_req req; + uint8_t caps; + uint16_t wContrast; +}; + +enum contrast_auto_req { + CONTRASTA_SET_CUR = 0x01, + CONTRASTA_GET_CUR = 0x81, + CONTRASTA_GET_CAP = 0x86, + CONTRASTA_GET_DEF = 0x87, +}; + +struct pu_contrast_auto { + enum contrast_auto_req req; + uint8_t caps; + uint8_t bContrastAuto; +}; + +enum gain_req { + GAIN_SET_CUR = 0x01, + GAIN_GET_CUR = 0x81, + GAIN_GET_MIN = 0x82, + GAIN_GET_MAX = 0x83, + GAIN_GET_RES = 0x84, + GAIN_GET_CAP = 0x86, + GAIN_GET_DEF = 0x87, +}; + +struct pu_gain { + enum gain_req req; + uint8_t caps; + uint16_t wGain; +}; + +enum power_line_freq_req { + POWER_LINE_FREQUENCY_SET_CUR = 0x01, + POWER_LINE_FREQUENCY_GET_CUR = 0x81, + POWER_LINE_FREQUENCY_GET_CAP = 0x86, + POWER_LINE_FREQUENCY_GET_DEF = 0x87, +}; + +#define PLF_DSIABLE 0x0 +#define PLF_50HZ 0x1 +#define PLF_60HZ 0x2 +#define PLF_AUTO 0x3 +struct pu_power_line_frequency { + enum power_line_freq_req req; + uint8_t caps; + uint8_t bPowerLineFrequency; +}; + +enum hue_req { + HUE_SET_CUR = 0x01, + HUE_GET_CUR = 0x81, + HUE_GET_MIN = 0x82, + HUE_GET_MAX = 0x83, + HUE_GET_RES = 0x84, + HUE_GET_CAP = 0x86, + HUE_GET_DEF = 0x87, +}; + +struct pu_hue { + enum hue_req req; + uint8_t caps; + uint16_t wHue; +}; + +enum hue_auto_req { + HUEA_SET_CUR = 0x01, + HUEA_GET_CUR = 0x81, + HUEA_GET_CAP = 0x86, + HUEA_GET_DEF = 0x87, +}; + +struct pu_hue_auto { + enum hue_auto_req req; + uint8_t caps; + uint8_t bHueAuto; +}; + +enum saturation_req { + SATURATION_SET_CUR = 0x01, + SATURATION_GET_CUR = 0x81, + SATURATION_GET_MIN = 0x82, + SATURATION_GET_MAX = 0x83, + SATURATION_GET_RES = 0x84, + SATURATION_GET_CAP = 0x86, + SATURATION_GET_DEF = 0x87, +}; + +struct pu_saturation { + enum saturation_req req; + uint8_t caps; + uint16_t wSaturation; +}; + +enum sharpness_req { + SHARPNESS_SET_CUR = 0x01, + SHARPNESS_GET_CUR = 0x81, + SHARPNESS_GET_MIN = 0x82, + SHARPNESS_GET_MAX = 0x83, + SHARPNESS_GET_RES = 0x84, + SHARPNESS_GET_CAP = 0x86, + SHARPNESS_GET_DEF = 0x87, +}; + +struct pu_sharpness { + enum sharpness_req req; + uint8_t caps; + uint16_t wSharpness; +}; + +enum gamma_req { + GAMMA_SET_CUR = 0x01, + GAMMA_GET_CUR = 0x81, + GAMMA_GET_MIN = 0x82, + GAMMA_GET_MAX = 0x83, + GAMMA_GET_RES = 0x84, + GAMMA_GET_CAP = 0x86, + GAMMA_GET_DEF = 0x87, +}; + +struct pu_gamma { + enum gamma_req req; + uint8_t caps; + uint16_t wGamma; +}; + +enum wbt_req { + WBT_SET_CUR = 0x01, + WBT_GET_CUR = 0x81, + WBT_GET_MIN = 0x82, + WBT_GET_MAX = 0x83, + WBT_GET_RES = 0x84, + WBT_GET_CAP = 0x86, + WBT_GET_DEF = 0x87, +}; + +struct pu_white_balance_temp { + enum wbt_req req; + uint8_t caps; + uint16_t wWhiteBalanceTemperature; +}; + +enum wbt_auto_req { + WBTA_SET_CUR = 0x01, + WBTA_GET_CUR = 0x81, + WBTA_GET_CAP = 0x86, + WBTA_GET_DEF = 0x87, +}; + +struct pu_white_balance_temp_auto { + enum wbt_auto_req req; + uint8_t caps; + uint8_t bWhiteBalanceTemperatureAuto; +}; + +enum whitebalance_comp_req { + WBC_SET_CUR = 0x01, + WBC_GET_CUR = 0x81, + WBC_GET_MIN = 0x82, + WBC_GET_MAX = 0x83, + WBC_GET_RES = 0x84, + WBC_GET_CAP = 0x86, + WBC_GET_DEF = 0x87, +}; + +struct pu_whitebalance_comp_data { + int16_t wWhiteBalanceBlue; + int16_t wWhiteBalanceRed; +}; + +struct pu_whitebalance_comp { + enum whitebalance_comp_req req; + uint8_t caps; + struct pu_whitebalance_comp_data data; +}; + +enum wbc_auto_req { + WBCA_SET_CUR = 0x01, + WBCA_GET_CUR = 0x81, + WBCA_GET_CAP = 0x86, + WBCA_GET_DEF = 0x87, +}; + +struct pu_wbc_auto { + enum wbc_auto_req req; + uint8_t caps; + uint8_t bWhiteBalanceComponentAuto; +}; + +enum dmpl_req { + MPL_SET_CUR = 0x01, + MPL_GET_CUR = 0x81, + MPL_GET_MIN = 0x82, + MPL_GET_MAX = 0x83, + MPL_GET_RES = 0x84, + MPL_GET_CAP = 0x86, + MPL_GET_DEF = 0x87, +}; + +struct pu_dmultiplier { + enum dmpl_req req; + uint8_t caps; + uint16_t wMultiplierStep; +}; + +enum dmpl_limit_req { + DMPL_SET_CUR = 0x01, + DMPL_GET_CUR = 0x81, + DMPL_GET_MIN = 0x82, + DMPL_GET_MAX = 0x83, + DMPL_GET_RES = 0x84, + DMPL_GET_CAP = 0x86, + DMPL_GET_DEF = 0x87, +}; + +struct pu_dmultiplierlimit { + enum dmpl_limit_req req; + uint8_t caps; + uint16_t wMultiplierLimit; +}; + +#endif // __UVC_CAMERA_H__ + diff --git a/mdw/kdp_usb_uvc/include/uvc_ctrl.h b/mdw/kdp_usb_uvc/include/uvc_ctrl.h new file mode 100644 index 0000000..ad98d12 --- /dev/null +++ b/mdw/kdp_usb_uvc/include/uvc_ctrl.h @@ -0,0 +1,232 @@ +#ifndef UVC_CTRL_H +#define UVC_CTRL_H +#include "uvc_dev.h" + +/* Control flags */ +#define UVC_CTRL_FLAG_SET_CUR (1 << 0) +#define UVC_CTRL_FLAG_GET_CUR (1 << 1) +#define UVC_CTRL_FLAG_GET_MIN (1 << 2) +#define UVC_CTRL_FLAG_GET_MAX (1 << 3) +#define UVC_CTRL_FLAG_GET_RES (1 << 4) +#define UVC_CTRL_FLAG_GET_INFO (1 << 5) +#define UVC_CTRL_FLAG_GET_DEF (1 << 6) +#define UVC_CTRL_FLAG_GET_LEN (1 << 7) +/* Control should be saved at suspend and restored at resume. */ +#define UVC_CTRL_FLAG_RESTORE (1 << 9) +/* Control can be updated by the camera. */ +#define UVC_CTRL_FLAG_AUTO_UPDATE (1 << 10) + +#define UVC_CTRL_FLAG_GET_RANGE \ + (UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MIN | \ + UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_RES | \ + UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO) +#define VC_CTRL_NUM 2 +#define DEVICE_POWER_MODE_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO +#define REQUEST_ERROR_CODE_FLAG UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO + + +#define CT_CTRL_NUM 22 +#define SCANNING_MODE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO +#define AUTO_EXPOSURE_MODE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_RES | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_DEF +#define AUTO_EXPOSURE_PRIORITY_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO +#define EXPOSURE_TIME_ABSOLUTE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define EXPOSURE_TIME_RELATIVE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO +#define FOCUS_ABSOLUTE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define FOCUS_RELATIVE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define IRIS_ABSOLUTE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define IRIS_RELATIVE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO +#define ZOOM_ABSOLUTE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define ZOOM_RELATIVE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define PANTILT_ABSOLUTE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define PANTILT_RELATIVE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define ROLL_ABSOLUTE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define ROLL_RELATIVE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define FOCUS_AUTO_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_DEF +#define PRIVACY_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO +#define FOCUS_SIMPLE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_DEF +#define WINDOW_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_DEF +#define REGION_OF_INTEREST_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_DEF + +#define PU_CTRL_NUM 19 +#define BRIGHTNESS_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define CONTRAST_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define HUE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define SATURATION_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define SHARPNESS_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define GAMMA_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define WHITE_BALANCE_TEMPERATURE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define WHITE_BALANCE_COMPONENT_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define BACKLIGHT_COMPENSATION_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define GAIN_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define POWER_LINE_FREQUENCY_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_DEF +#define HUE_AUTO_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_DEF +#define WHITE_BALANCE_TEMPERATURE_AUTO_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_DEF +#define WHITE_BALANCE_COMPONENT_AUTO_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_DEF +#define DIGITAL_MULTIPLIER_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define DIGITAL_MULTIPLIER_LIMIT_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_RANGE +#define ANALOG_VIDEO_STANDARD_CTL_FLAG UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO +#define ANALOG_VIDEO_LOCK_STATUS_CTL_FLAG UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO +#define CONTRAST_AUTO_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_DEF + +#define EU_CTRL_NUM 20 + +#define SELECT_LAYER_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define PROFILE_AND_TOOLSET_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define VIDEO_RESOLUTION_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define MINIMUM_FRAME_INTERVAL_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define SLICE_MODE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define RATE_CONTROL_MODE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define AVERAGE_BIT_RATE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define CPB_SIZE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define PEAK_BIT_RATE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define QUANTIZATION_PARAMETER_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN | UVC_CTRL_FLAG_GET_RES +#define SYNCHRONIZATION_AND_LONGTERM_REFERENCE_FRAME_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define LONG_TERM_BUFFER_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define PICTURE_LONG_TERM_REFERENCE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define LTR_VALIDATION_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define LEVEL_IDC_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF +#define SEI_MESSAGE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_INFO +#define QP_RANGE_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN | UVC_CTRL_FLAG_GET_RES +#define PRIORITY_ID_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define START_OR_STOP_LAYER_VIEW_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_INFO | UVC_CTRL_FLAG_GET_LEN +#define ERROR_RESILIENCY_CTL_FLAG UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_RES + +struct uvc_xu_control_query { + uint8_t unit; + uint8_t selector; + uint8_t query; /* Video Class-Specific Request Code, */ + /* defined in linux/usb/video.h A.8. */ + uint16_t size; + + uint8_t *data; +}; + +int uvc_ctrl_init_device(struct uvc_device *dev); + +#define HOST_SET_CLASS_INTF 0x21 +#define HOST_GET_CLASS_INTF 0xA1 + + +struct uvc_usb_ctrlreq { + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint8_t *data; +} __attribute__ ((packed)); + + + +// uvc_eu_ctrlreq_data +struct eu_select_layer { + uint16_t wLayerOrViewID; +}; +struct eu_profile { + uint16_t wProfile; + uint16_t wConstrainedToolset; + uint8_t bmSettings; +}; + +struct eu_videoresolution { + uint16_t wWidth; + uint16_t wHeight; +}; +struct eu_min_frame_interval { + uint32_t dwFrameInterval; +}; +struct eu_slicemode { + uint16_t wSliceMode; + uint16_t wSliceConfigSetting; +}; +struct eu_ratecontrolmode { + uint8_t bRateControlMode; + uint32_t dwAverageBitRate; + uint32_t dwCPBsize; + uint32_t dwPeakBitRate; +}; +struct eu_qpprime { + uint16_t wQpPrime_I; + uint16_t wQpPrime_P; + uint16_t wQpPrime_B; +}; + +struct eu_syncframe { + uint8_t bSyncFrameType; + uint16_t wSyncFrameInterval; + uint8_t bGradualDecoderRefresh; +}; + +struct eu_ltrbuffers { + uint8_t bNumHostControlLTRBuffers; + uint8_t bTrustMode; +}; + +struct eu_ltrpicture { + uint8_t bPutAtPositionInLTRBuffer; + uint8_t bLTRMode; +}; + +struct eu_ltrvalidation { + uint16_t bmValidLTRs; +}; + +struct eu_levelidc { + uint8_t bLevelIDC; +}; + +struct eu_seimessages { + uint8_t bmSEIMessages[8]; +}; + +struct eu_range { + uint8_t bMinQp; + uint8_t bMaxQp; +}; + +struct eu_priority { + uint8_t bPriority; +}; + +struct start_stop_layer { + uint8_t bUpdate; +}; + +struct ErrorResiliencyFeatures { + uint16_t bmErrorResiliencyFeatures; +}; + + +struct vs_synch_delay { + uint16_t wDelay; +}; + +struct vs_streamerrorcode { + uint8_t bStreamErrorCode; +}; + +struct vs_generatekeyframe { + uint8_t bGenerateKeyFrame; +}; + +struct vs_updateframe { + uint8_t bStartFrameSegment; + uint8_t bEndFrameSegment; +}; + +struct vs_still_image_trigger { + uint8_t bTrigger; +}; + +int uvc_init_stream_ctl(struct uvc_device *udev, struct uvc_streaming *stream); +int uvc_vs_probe(struct uvc_streaming *stream, struct uvc_streaming_control_data *probe); +//int uvc_find_control(struct uvc_device *udev, uint32_t cid); + +int uvc_ctrl_get(struct ctrl_info *ctrl, struct uvc_device *dev, uint8_t req_num); +int uvc_ctrl_set(struct uvc_device *udev, struct ctrl_info *info); +//void set_ct_ctrl_flag(struct ctrl_info *info); +//void set_pu_ctrl_flag(struct ctrl_info *info); + +int uvc_send_ctl(struct uvc_device *udev, uint32_t cid, uint16_t req, uint8_t *para, uint8_t len); +int uvc_init_device_ctrl(struct uvc_device *udev); +#endif // UVC_CTRL_H diff --git a/mdw/kdp_usb_uvc/include/uvc_dev.h b/mdw/kdp_usb_uvc/include/uvc_dev.h new file mode 100644 index 0000000..14c2b8b --- /dev/null +++ b/mdw/kdp_usb_uvc/include/uvc_dev.h @@ -0,0 +1,339 @@ +/* + * Kneron UVC driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ +#ifndef _UVC_DEV_H_ +#define _UVC_DEV_H_ + +#include +#include + +#define FLAGS_UVC_CAMERA_INIT_DONE_EVT BIT24 +#define FLAGS_UVC_CAMERA_INIT_FAILED_EVT BIT25 +#define UVC_TERM_INPUT 0x0000 +#define UVC_TERM_OUTPUT 0x8000 +#define UVC_TERM_DIRECTION(term) ((term)->type & 0x8000) + +#define UVC_ENTITY_TYPE(entity) ((entity)->type & 0x7fff) +#define UVC_ENTITY_IS_UNIT(entity) (((entity)->type & 0xff00) == 0) +#define UVC_ENTITY_IS_TERM(entity) (((entity)->type & 0xff00) != 0) +#define UVC_ENTITY_IS_ITERM(entity) \ + (UVC_ENTITY_IS_TERM(entity) && \ + ((entity)->type & 0x8000) == UVC_TERM_INPUT) +#define UVC_ENTITY_IS_OTERM(entity) \ + (UVC_ENTITY_IS_TERM(entity) && \ + ((entity)->type & 0x8000) == UVC_TERM_OUTPUT) + +#define UVC_ET_IT UVC_TERM_INPUT +#define UVC_ET_OT UVC_TERM_OUTPUT + +#define UVC_ET_CT 0x1 +#define UVC_ET_PU 0x2 +#define UVC_ET_SU 0x3 +#define UVC_ET_EU 0x4 +#define UVC_ET_XU 0x5 +#define UVC_DEV_INF 0x6 +#define UVC_DEF 0 +#define UVC_CUR 1 +#define UVC_MIN 2 +#define UVC_MAX 3 +#define UVC_RES 4 + + +#define DRIVER_VERSION "1.0.1" +#define UVC_CTRL_CONTROL_TIMEOUT 30 +#define UVC_CTRL_STREAMING_TIMEOUT 5000 + +#define UVC_FMT_FLAG_COMPRESSED 0x00000001 +#define UVC_FMT_FLAG_STREAM 0x00000002 + + +struct uvc_format_desc { + char *name; + uint32_t fcc; +}; + +struct kdp_uvc_id { + + uint16_t idVendor; + uint16_t idProduct; + +}; + +#define CAP_SUPPORT_GET 0x0 +#define CAP_SUPPORT_SET 0x1 +#define STATE_DISABLED_AUTO_MODE_STATE 0x2 +#define CAP_SUPPORT_AUTOUPDATE_CTRL 0x4 +#define CAP_SUPPORT_ASYNC_CTRL 0x8 +#define STATE_DISABLED_INCOMP_COMMIT_STATE 0x10 + +#define UVC_ENTITY_FLAG_DEFAULT (1 << 0) +#define PARAM_ARRAY_SIZE 5 +struct ctrl_info { + uint32_t cid; + uint8_t eid; + uint8_t cs; + bool supported; + bool cached; + uint8_t para_size; + uint8_t *para; + uint8_t caps; + uint8_t len; + uint8_t ctl_flag; +}__attribute__((packed,aligned(4))); + +struct uvc_ct { + uint16_t wObjectiveFocalLengthMin; + uint16_t wObjectiveFocalLengthMax; + uint16_t wOcularFocalLength; + uint32_t bmControls; + struct ctrl_info *data; +}__attribute__((packed,aligned(4))); + +struct uvc_it { + uint8_t id; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + struct uvc_ct *ct; +}__attribute__((packed,aligned(4))); + +struct uvc_ot { + uint8_t id; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t baSourceID; +}__attribute__((packed,aligned(4))); + +struct uvc_su { + uint8_t id; + uint8_t bNrInPins; + uint8_t *baSourceID; + +}__attribute__((packed,aligned(4))); + +struct uvc_pu { + uint8_t id; + uint8_t baSourceID; + uint16_t wMaxMultiplier; + uint32_t bmControls; + uint8_t bmVideoStandards; + struct ctrl_info *data; +}__attribute__((packed,aligned(4))); + +struct uvc_xu { + uint8_t id; + uint8_t bNrInPins; + uint8_t *baSourceID; + uint8_t bNumControls; + uint32_t bmControls; + struct ctrl_info *data; +}__attribute__((packed,aligned(4))); + +struct uvc_eu { + uint8_t id; + uint8_t s_id; + uint8_t bSourceID; + uint8_t bNumControls; + uint32_t bmControls; + uint32_t bmControlsRuntime; + struct ctrl_info *data; +}__attribute__((packed,aligned(4))); + +struct uvc_control { + uint8_t entity_id; + uint8_t index; /* Bit index in bmControls */ + uint8_t size; + uint8_t flags; +}__attribute__((packed,aligned(4))); + +struct uvc_streaming_header { + uint8_t bNumFormats; + uint8_t bEndpointAddress; + uint8_t bTerminalLink; + uint8_t bControlSize; + uint8_t *bmaControls; + uint8_t bmInfo; + uint8_t bStillCaptureMethod; + uint8_t bTriggerSupport; + uint8_t bTriggerUsage; +}__attribute__((packed,aligned(4))); + +struct uvc_decode_op { + struct uvc_buffer *buf; + void *dst; + const uint8_t *src; + int len; +}__attribute__((packed,aligned(4))); + +struct uvc_color_mat_desc { + uint8_t bColorPrimaries; + uint8_t bTransferCharacteristics; + uint8_t bMatrixCoefficients; +} __attribute__((packed,aligned(4))); + +struct uvc_vs_format { + uint8_t len; + union { + struct uvc_format_uncompressed *p_uncomp; + struct uvc_format_mjpeg *p_mjpg; + } format; + uint8_t num_frame; + uint8_t curr_framenum; + uint8_t frame_len; + union { + struct uvc_frame_uncompressed *p_uncomp; + struct uvc_frame_mjpeg *p_mjpg; + } frame; +}__attribute__((packed,aligned(4))); + +struct cont_frame_intervals { + uint32_t dwMinFrameInterval; // Number Shortest frame interval supported (at highest frame rate), in 100ns units. 30 + uint32_t dwMaxFrameInterval; // Number Longest frame interval supported (at lowest frame rate), in 100ns units. 34 + uint32_t dwFrameIntervalStep; // +}__attribute__((packed,aligned(4))); + +struct uvc_frame { + uint8_t bDescriptorType; + uint8_t bFrameIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwMaxVideoFrameBufferSize; + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t *dwFrameInterval; +}__attribute__((packed,aligned(4))); + +struct uvc_format { + uint8_t type; + uint8_t index; + uint8_t bpp; + uint8_t colorspace; + uint32_t fcc; + char name[32]; + unsigned int nframes; + uint8_t cur_frame_num; + struct uvc_frame *frame; + struct uvc_frame *cur_frame; +}__attribute__((packed,aligned(4))); + +struct uvc_vs_alt_intf { + uint8_t ep_type; + uint16_t addr; + uint16_t maxpacketsize; + uint8_t interval; + uint8_t alt_num; +}__attribute__((packed,aligned(4))); + +struct uvc_vs_ctl_data { + uint16_t wmHint; + uint8_t bFormatIndex; + uint8_t bFrameIndex; + uint32_t dwFrameInterval; + + uint16_t wDelay; + uint32_t dwMaxVideoFrameSize; + uint32_t dwMaxPayloadTransferSize; + uint32_t dwClockFrequency; + + uint8_t bPreferedVersion; + uint8_t bMinVersion; + uint8_t bMaxVersion; +}__attribute__((packed,aligned(4))); + +struct ctrl_vs_info { + bool cached; + struct uvc_streaming_control_data *def; + struct uvc_streaming_control_data *curr; + struct uvc_streaming_control_data *minimum; + struct uvc_streaming_control_data *maximum; + struct uvc_streaming_control_data *res; + uint8_t caps; + uint16_t len; +}__attribute__((packed,aligned(4))); + +struct uvc_streaming { + // struct uvc_device *uvc_dev; + int ifnum; + uint8_t num_alt; + uint8_t curr_altnum; + struct uvc_vs_alt_intf *if_alt; + uint8_t num_ep; + uint16_t ep_addr; +// struct uvc_streaming_header header; + + uint8_t ep_type; + uint8_t TerminalId; + uint8_t ControlSize; + unsigned int nformats; + struct uvc_format *format; + int8_t cur_format_num; + struct uvc_format *cur_format; + + struct ctrl_vs_info *vs_ctrl_info; + struct uvc_color_mat_desc *color_match; + + USBH_PIPE_HANDLE isoch_pipe; + + uint32_t imagesize; + uint32_t frame_buf; + int write_idx; + bool running; +}__attribute__((packed,aligned(4))); + +struct uvc_vc_int_ep { + uint16_t addr; + uint16_t maxpacketsize; + uint16_t wMaxTransferSize; + uint8_t interval; + // struct urb *int_urb; +}__attribute__((packed,aligned(4))); + +struct uvc_device { + char name[32]; + uint32_t device_caps; + struct kdp_uvc_id *id; + + uint8_t num_inf; + uint8_t vc_inf; + struct ctrl_info *inf_ctl; + + uint16_t uvc_version; + uint32_t clock_frequency; + + uint8_t nITs; + struct uvc_it *IT; + uint8_t nOTs; + struct uvc_ot *OT; + uint8_t nSUs; + struct uvc_su *SU; + uint8_t nPUs; + struct uvc_pu *PU; +// uint8_t nEUs; +// struct uvc_eu *EU; + uint8_t nXUs; + struct uvc_xu *XU; + + /* Video Streaming */ + uint8_t num_vs_inf; + + struct uvc_streaming *curr_stream; + struct uvc_streaming *stream; + /* Status Interrupt Endpoint */ + struct uvc_vc_int_ep *int_ep; + + uint8_t *status; + bool inited; + bool opened; + +}__attribute__((packed,aligned(4))); + +struct uvc_entity *uvc_entity_by_id(struct uvc_device *dev, int id); +struct uvc_device *video_dev(const char *pname); +//int usb_uvc_id_lookup(uint16_t idVendor, uint16_t idProduct); +void kmdw_cam_uvc_init(void); +#endif //_UVC_DEV_H_ diff --git a/mdw/kdp_usb_uvc/include/uvc_internal_api.h b/mdw/kdp_usb_uvc/include/uvc_internal_api.h new file mode 100644 index 0000000..9189aa8 --- /dev/null +++ b/mdw/kdp_usb_uvc/include/uvc_internal_api.h @@ -0,0 +1,400 @@ +/* + * Kneron UVC driver + * + * Copyright (C) 2020 Kneron, Inc. All rights reserved. + * + */ +#ifndef __UVC_API_INTERNAL_H__ +#define __UVC_API_INTERNAL_H__ + +#define VIDEO_MAX_FRAME 32 + +#define ET_POS 28 +#define UVC_CID_DEV_INF_CLASS_BASE (UVC_DEV_INF << ET_POS) +#define DEVICE_POWER_MODE_LEN 0x1 +#define DEVICE_POWER_MODE_LEN 0x1 +#define UVC_CID_DEVICE_POWER_MODE UVC_CID_DEV_INF_CLASS_BASE | UVC_VC_VIDEO_POWER_MODE_CONTROL + +#define POWER_MODECTL_FULL_POWER 0000b +#define POWER_MODECTL_DEVICE_DEP_POWER 0001b +#define POWER_MODECTL_DEVICE_DEP_POWER_SUPPORTED 0x10 +#define POWER_MODECTL_POWER_BY_USB 0x20 +#define POWER_MODECTL_POWER_BY_BATTERY 0x40 +#define POWER_MODECTL_POWER_BY_BY_AC 0x80 + +//#define SCANNING_MODE_CTL_PROGRESSIVE 0x1 + +#define DEVICE_REQUEST_ERROR_CODE_LEN 0x1 +#define UVC_CID_REQUEST_ERROR_CODE UVC_CID_DEV_INF_CLASS_BASE | UVC_VC_REQUEST_ERROR_CODE_CONTROL << 24 +#define REQUEST_ERROR_CTL + +/* CT control IDs */ +#define UVC_CID_CAMERA_CLASS_BASE (UVC_ET_CT << ET_POS) +#define SCANNING_MODE 0x1 +#define AUTO_EXPOSURE_MODE 0x2 +#define AUTO_EXPOSURE_PRIORITY 0x4 +#define EXPOSURE_TIME_ABSOLUTE 0x8 +#define EXPOSURE_TIME_RELATIVE 0x10 +#define FOCUS_ABSOLUTE 0x20 +#define FOCUS_RELATIVE 0x40 +#define IRIS_ABSOLUTE 0x80 +#define IRIS_RELATIVE 0x100 +#define ZOOM_ABSOLUTE 0x200 +#define ZOOM_RELATIVE 0x400 +#define PANTILT_ABSOLUTE 0x800 +#define PANTILT_RELATIVE 0x1000 +#define ROLL_ABSOLUTE 0x2000 +#define ROLL_RELATIVE 0x4000 +#define FOCUS_AUTO 0x20000 +#define PRIVACY 0x40000 +#define FOCUS_SIMPLE 0x80000 +#define WINDOW 0x100000 +#define REGION_OF_INTEREST 0x200000 + + +#define SCANNING_MODE_LEN 0x1 +#define AUTO_EXPOSURE_MODE_LEN 0x1 +#define AUTO_EXPOSURE_PRIORITY_LEN 0x1 +#define EXPOSURE_TIME_ABSOLUTE_LEN 0x4 +#define EXPOSURE_TIME_RELATIVE_LEN 0x1 +#define FOCUS_ABSOLUTE_LEN 0x2 +#define FOCUS_RELATIVE_LEN 0x2 +#define IRIS_ABSOLUTE_LEN 0x2 +#define IRIS_RELATIVE_LEN 0x2 +#define ZOOM_ABSOLUTE_LEN 0x2 +#define ZOOM_RELATIVE_LEN 0x3 +#define PANTILT_ABSOLUTE_LEN 0x8 +#define PANTILT_RELATIVE_LEN 0x4 +#define ROLL_ABSOLUTE_LEN 0x2 +#define ROLL_RELATIVE_LEN 0x2 +#define FOCUS_AUTO_LEN 0x1 +#define PRIVACY_LEN 0x1 +#define FOCUS_SIMPLE_LEN 0x1 +#define WINDOW_LEN 0xc +#define REGION_OF_INTEREST_LEN 0xa + + +#define UVC_CID_SCANNING_MODE UVC_CID_CAMERA_CLASS_BASE | SCANNING_MODE +#define UVC_CID_AUTO_EXPOSURE_MODE UVC_CID_CAMERA_CLASS_BASE | AUTO_EXPOSURE_MODE +#define UVC_CID_AUTO_EXPOSURE_PRIORITY UVC_CID_CAMERA_CLASS_BASE | AUTO_EXPOSURE_PRIORITY +#define UVC_CID_EXPOSURE_TIME_ABSOLUTE UVC_CID_CAMERA_CLASS_BASE | EXPOSURE_TIME_ABSOLUTE +#define UVC_CID_EXPOSURE_TIME_RELATIVE UVC_CID_CAMERA_CLASS_BASE | EXPOSURE_TIME_RELATIVE +#define UVC_CID_FOCUS_ABSOLUTE UVC_CID_CAMERA_CLASS_BASE | FOCUS_ABSOLUTE +#define UVC_CID_FOCUS_RELATIVE UVC_CID_CAMERA_CLASS_BASE | FOCUS_RELATIVE +#define UVC_CID_IRIS_ABSOLUTE UVC_CID_CAMERA_CLASS_BASE | IRIS_ABSOLUTE +#define UVC_CID_IRIS_RELATIVE UVC_CID_CAMERA_CLASS_BASE | IRIS_RELATIVE +#define UVC_CID_ZOOM_ABSOLUTE UVC_CID_CAMERA_CLASS_BASE | ZOOM_ABSOLUTE +#define UVC_CID_ZOOM_RELATIVE UVC_CID_CAMERA_CLASS_BASE | ZOOM_RELATIVE +#define UVC_CID_PANTILT_ABSOLUTE UVC_CID_CAMERA_CLASS_BASE | PANTILT_ABSOLUTE +#define UVC_CID_PANTILT_RELATIVE UVC_CID_CAMERA_CLASS_BASE | PANTILT_RELATIVE +#define UVC_CID_ROLL_ABSOLUTE UVC_CID_CAMERA_CLASS_BASE | ROLL_ABSOLUTE +#define UVC_CID_ROLL_RELATIVE UVC_CID_CAMERA_CLASS_BASE | ROLL_RELATIVE +#define UVC_CID_FOCUS_AUTO UVC_CID_CAMERA_CLASS_BASE | FOCUS_AUTO +#define UVC_CID_PRIVACY UVC_CID_CAMERA_CLASS_BASE | PRIVACY +#define UVC_CID_FOCUS_SIMPLE UVC_CID_CAMERA_CLASS_BASE | FOCUS_SIMPLE +#define UVC_CID_WINDOW UVC_CID_CAMERA_CLASS_BASE | WINDOW +#define UVC_CID_REGION_OF_INTEREST UVC_CID_CAMERA_CLASS_BASE | REGION_OF_INTEREST + + +#define SCANNING_MODE_CTL_INTERLACED 0x0 +#define SCANNING_MODE_CTL_PROGRESSIVE 0x1 + +#define AUTO_EXPOSURE_MODE_CTL_MODE_MANUAL 0x1 +#define AUTO_EXPOSURE_MODE_CTL_MODE_AUTO 0x2 +#define AUTO_EXPOSURE_MODE_CTL_MODE_SHUTTER_PRIO 0x4 +#define AUTO_EXPOSURE_MODE_CTL_MODE_APERTURE_PRIO 0x8 + +#define AUTO_EXPOSURE_PRI_CTL_FRAMERAT_CONST 0x0 +#define AUTO_EXPOSURE_PRI_CTL_FRAMERAT_VARIED 0x1 + +#define EXPOSURE_TIME_REL_CTL_DEF 0x0 +#define EXPOSURE_TIME_REL_CTL_INC_BY_1STEP 0x1 +#define EXPOSURE_TIME_REL_CTL_DEC_BY_1_STEP 0xFF + +#define FOCUS_REL_CTL_REL_STOP 0x0 +#define FOCUS_REL_CTL_REL_NEAR_DIR 0x1 +#define FOCUS_REL_CTL_REL_INFINITE_DIR 0xFF + +#define FOCUS_SIMPLE_CTL_FULL_RANGE 0x00 +#define FOCUS_SIMPLE_CTL_MACRO_LESS_THAN_0_3M 0x01 +#define FOCUS_SIMPLE_CTL_PEOPLE_0_3M_TO_3M 0x02 +#define FOCUS_SIMPLE_CTL_SCENE_3M_TO_INFINITY 0x03 + +#define IRIS_REL_CTL_REL_DEF 0x0 +#define IRIS_REL_CTL_REL_OPEN_BY_1STEP 0x1 +#define IRIS_REL_CTL_REL_CLOSE_BY_1STEP 0xFF + +#define ZOOM_REL_CTL_ZOOM_STOP 0x0 +#define ZOOM_REL_CTL_ZOOM_TO_TELEPHOTO_DIR 0x1 +#define ZOOM_REL_CTL_ZOOM_TO_WIDEANGLE_DIR 0xFF +#define ZOOM_REL_CTL_DIGITALZOOM_OFF 0x0 +#define ZOOM_REL_CTL_DIGITALZOOM_ON 0x1 + +#define PANTILT_REL_CTL_STOP 0x0 +#define PANTILT_REL_CTL_PLANE_UP 0x1 +#define PANTILT_REL_CTL_PLANE_DOWN 0xFF + +#define ROLL_RELATIVE_CTL_STOP 0x0 +#define ROLL_RELATIVE_CTL_CLOCKWISE_ROTATION 0x1 +#define ROLL_RELATIVE_CTL_COUNTER_CLOCKWISE_ROTATION 0xFF + +#define PRIVACY_CTL_OPEN 0x0 +#define PRIVACY_CTL_CLOSE 0x1 + +#define WINDOWS_CTL_STEPUNIT_VIDEOFRAME 0x1 +#define WINDOWS_CTL_STEPUNIT_MILLISECONDS 0x2 + +#define ROI_CTL_AUTOCTL_EXPOSURE 0x1 +#define ROI_CTL_AUTOCTL_IRIS 0x2 +#define ROI_CTL_AUTOCTL_WHITE_BALANCE 0x4 +#define ROI_CTL_AUTOCTL_FOCUS 0x8 +#define ROI_CTL_AUTOCTL_FACE_DETECT 0x10 +#define ROI_CTL_AUTOCTL_AUTO_DETECT_TRACK 0x20 +#define ROI_CTL_AUTOCTL_IMAGE_STABILIZATION 0x40 +#define ROI_CTL_AUTOCTL_HIGHER_QUALITY 0x80 + +/*PU ctl */ + +#define BRIGHTNESS 0x1 +#define CONTRAST 0x2 +#define HUE 0x4 +#define SATURATION 0x8 +#define SHARPNESS 0x10 +#define GAMMA 0x20 +#define WHITE_BALANCE_TEMPERATURE 0x40 +#define WHITE_BALANCE_COMPONENT 0x80 +#define BACKLIGHT_COMPENSATION 0x100 +#define GAIN 0x200 +#define POWER_LINE_FREQUENCY 0x400 +#define HUE_AUTO 0x800 +#define WHITE_BALANCE_TEMPERATURE_AUTO 0x1000 +#define WHITE_BALANCE_COMPONENT_AUTO 0x2000 +#define DIGITAL_MULTIPLIER 0x4000 +#define DIGITAL_MULTIPLIER_LIMIT 0x8000 +#define ANALOG_VIDEO_STANDARD 0x10000 +#define ANALOG_VIDEO_LOCK_STATUS 0x20000 +#define CONTRAST_AUTO 0x40000 + +#define BRIGHTNESS_LEN 0x2 +#define CONTRAST_LEN 0x2 +#define HUE_LEN 0x2 +#define SATURATION_LEN 0x2 +#define SHARPNESS_LEN 0x2 +#define GAMMA_LEN 0x2 +#define WHITE_BALANCE_TEMPERATURE_LEN 0x2 +#define WHITE_BALANCE_COMPONENT_LEN 0x2 +#define BACKLIGHT_COMPENSATION_LEN 0x2 +#define GAIN_LEN 0x2 +#define POWER_LINE_FREQUENCY_LEN 0x1 +#define HUE_AUTO_LEN 0x1 +#define WHITE_BALANCE_TEMPERATURE_AUTO_LEN 0x1 +#define WHITE_BALANCE_COMPONENT_AUTO_LEN 0x1 +#define DIGITAL_MULTIPLIER_LEN 0x2 +#define DIGITAL_MULTIPLIER_LIMIT_LEN 0x2 +#define ANALOG_VIDEO_STANDARD_LEN 0x1 +#define ANALOG_VIDEO_LOCK_STATUS_LEN 0x1 +#define CONTRAST_AUTO_LEN 0x1 + +#define UVC_CID_PU_CLASS_BASE (UVC_ET_PU << ET_POS) +#define UVC_CID_BRIGHTNESS UVC_CID_PU_CLASS_BASE | BRIGHTNESS +#define UVC_CID_CONTRAST UVC_CID_PU_CLASS_BASE | CONTRAST +#define UVC_CID_HUE UVC_CID_PU_CLASS_BASE | HUE +#define UVC_CID_SATURATION UVC_CID_PU_CLASS_BASE | SATURATION +#define UVC_CID_SHARPNESS UVC_CID_PU_CLASS_BASE | SHARPNESS +#define UVC_CID_GAMMA UVC_CID_PU_CLASS_BASE | GAMMA +#define UVC_CID_WHITE_BALANCE_TEMPERATURE UVC_CID_PU_CLASS_BASE | WHITE_BALANCE_TEMPERATURE +#define UVC_CID_WHITE_BALANCE_COMPONENT UVC_CID_PU_CLASS_BASE | WHITE_BALANCE_COMPONENT +#define UVC_CID_BACKLIGHT_COMPENSATION UVC_CID_PU_CLASS_BASE | BACKLIGHT_COMPENSATION +#define UVC_CID_GAIN UVC_CID_PU_CLASS_BASE | GAIN +#define UVC_CID_POWER_LINE_FREQUENCY UVC_CID_PU_CLASS_BASE | POWER_LINE_FREQUENCY +#define UVC_CID_HUE_AUTO UVC_CID_PU_CLASS_BASE | HUE_AUTO +#define UVC_CID_WHITE_BALANCE_TEMPERATURE_AUTO UVC_CID_PU_CLASS_BASE | WHITE_BALANCE_TEMPERATURE_AUTO +#define UVC_CID_WHITE_BALANCE_COMPONENT_AUTO UVC_CID_PU_CLASS_BASE | WHITE_BALANCE_COMPONENT_AUTO +#define UVC_CID_DIGITAL_MULTIPLIER UVC_CID_PU_CLASS_BASE | DIGITAL_MULTIPLIER +#define UVC_CID_DIGITAL_MULTIPLIER_LIMIT UVC_CID_PU_CLASS_BASE | DIGITAL_MULTIPLIER_LIMIT +#define UVC_CID_ANALOG_VIDEO_STANDARD UVC_CID_PU_CLASS_BASE | ANALOG_VIDEO_STANDARD +#define UVC_CID_ANALOG_VIDEO_LOCK_STATUS UVC_CID_PU_CLASS_BASE | ANALOG_VIDEO_LOCK_STATUS +#define UVC_CID_CONTRAST_AUTO UVC_CID_PU_CLASS_BASE | CONTRAST_AUTO + +#define BACKLIGHT_COMPENSATION_CTL_DISABLED 0x0 + +#define CONTRAST_AUTO_CTL_AUTO_ADJUSTMENT_ENABLED 0x1 + + +#define POWER_LINE_FREQUENCY_CTL_DISABLED 0 +#define POWER_LINE_FREQUENCY_CTL_50HZ 1 +#define POWER_LINE_FREQUENCY_CTL_60HZ 2 + +#define HUE_AUTO_CTL_AUTO_ADJUSTMENT_ENABLED 0x1 + +#define SATURATION_CTL_GRAYSCALE 0x0 + +#define GAMMA_CTL_GAMMA_MIN 1 +#define GAMMA_CTL_GAMMA_MAX 500 + +#define WHITE_BALANCE_TEMPERATURE_AUTO_CTL_AUTO_ADJUSTMENT_ENABLED 0x1 +#define WHITE_BALANCE_COMPONENT_AUTO_CTL_AUTO_ADJUSTMENT_ENABLED 0x1 + +#define UVC_CID_EU_CLASS_BASE (UVC_ET_EU << ET_POS) +#define SELECT_LAYER 0x1 +#define PROFILE_AND_TOOLSET 0x2 +#define VIDEO_RESOLUTION 0x4 +#define MINIMUM_FRAME_INTERVAL 0x8 +#define SLICE_MODE 0x10 +#define RATE_CONTROL_MODE 0x20 +#define AVERAGE_BIT_RATE 0x40 +#define CPB_SIZE 0x80 +#define PEAK_BIT_RATE 0x100 +#define QUANTIZATION_PARAMETER 0x200 +#define SYNCHRONIZATION_AND_LONGTERM_REFERENCE_FRAME 0x400 +#define LONG_TERM_BUFFER 0x800 +#define PICTURE_LONG_TERM_REFERENCE 0x1000 +#define LTR_VALIDATION 0x2000 +#define LEVEL_IDC 0x4000 +#define SEI_MESSAGE 0x8000 +#define QP_RANGE 0x10000 +#define PRIORITY_ID 0x20000 +#define START_OR_STOP_LAYER_VIEW 0x40000 +#define ERROR_RESILIENCY 0x80000 + +#define SELECT_LAYERL_LEN 0x2 +#define PROFILE_AND_TOOLSET_LEN 0x5 +#define VIDEO_RESOLUTION_LEN 0x4 +#define MINIMUM_FRAME_INTERVAL_LEN 0x4 +#define SLICE_MODE_LEN 0x4 +#define RATE_CONTROL_MODE_LEN 0x1 +#define AVERAGE_BIT_RATE_LEN 0x4 +#define CPB_SIZE_LEN 0x4 +#define PEAK_BIT_RATE_LEN 0x4 +#define QUANTIZATION_PARAMETER_LEN 0x6 +#define SYNCHRONIZATION_AND_LONGTERM_REFERENCE_FRAME_LEN 0x4 +#define LONG_TERM_BUFFER_LEN 0x2 +#define PICTURE_LONG_TERM_REFERENCE_LEN 0x2 +#define LTR_VALIDATION_LEN 0x2 +#define LEVEL_IDC_LEN 0x1 +#define SEI_MESSAGE_LEN 0x8 +#define QP_RANGE_LEN 0x2 +#define PRIORITY_ID_LEN 0x1 +#define START_OR_STOP_LAYER_VIEW_LEN 0x1 +#define ERROR_RESILIENCY_LEN 0x2 + +#define UVC_CID_SELECT_LAYER UVC_CID_EU_CLASS_BASE | SELECT_LAYER +#define UVC_CID_PROFILE_AND_TOOLSET UVC_CID_EU_CLASS_BASE | PROFILE_AND_TOOLSET +#define UVC_CID_VIDEO_RESOLUTION UVC_CID_EU_CLASS_BASE | VIDEO_RESOLUTION +#define UVC_CID_MINIMUM_FRAME_INTERVAL UVC_CID_EU_CLASS_BASE | MINIMUM_FRAME_INTERVAL +#define UVC_CID_SLICE_MODE UVC_CID_EU_CLASS_BASE | SLICE_MODE +#define UVC_CID_RATE_CONTROL_MODE UVC_CID_EU_CLASS_BASE | RATE_CONTROL_MODE +#define UVC_CID_AVERAGE_BIT_RATE UVC_CID_EU_CLASS_BASE | AVERAGE_BIT_RATE +#define UVC_CID_CPB_SIZE UVC_CID_EU_CLASS_BASE | CPB_SIZE +#define UVC_CID_PEAK_BIT_RATE UVC_CID_EU_CLASS_BASE | PEAK_BIT_RATE +#define UVC_CID_QUANTIZATION_PARAMETER UVC_CID_EU_CLASS_BASE | QUANTIZATION_PARAMETER +#define UVC_CID_SYNCHRONIZATION_AND_LONGTERM_REFERENCE_FRAME UVC_CID_EU_CLASS_BASE | SYNCHRONIZATION_AND_LONGTERM_REFERENCE_FRAME +#define UVC_CID_LONG_TERM_BUFFER UVC_CID_EU_CLASS_BASE | LONG_TERM_BUFFER +#define UVC_CID_PICTURE_LONG_TERM_REFERENCE UVC_CID_EU_CLASS_BASE | PICTURE_LONG_TERM_REFERENCE +#define UVC_CID_LTR_VALIDATION UVC_CID_EU_CLASS_BASE | LTR_VALIDATION +#define UVC_CID_LEVEL_IDC UVC_CID_EU_CLASS_BASE | LEVEL_IDC +#define UVC_CID_SEI_MESSAGE UVC_CID_EU_CLASS_BASE | SEI_MESSAGE +#define UVC_CID_QP_RANGE UVC_CID_EU_CLASS_BASE | QP_RANGE +#define UVC_CID_PRIORITY_ID UVC_CID_EU_CLASS_BASE | PRIORITY_ID +#define UVC_CID_START_OR_STOP_LAYER_VIEW UVC_CID_EU_CLASS_BASE | START_OR_STOP_LAYER_VIEW +#define UVC_CID_ERROR_RESILIENCY UVC_CID_EU_CLASS_BASE | ERROR_RESILIENCY + +#define RATE_CONTROL_MODE_CTL_MODE_VBR 0x1 +#define RATE_CONTROL_MODE_CTL_MODE_CBR 0x2 +#define RATE_CONTROL_MODE_CTL_MODE_Constant_QP 0x3 +#define RATE_CONTROL_MODE_CTL_MODE_GVBR 0x4 +#define RATE_CONTROL_MODE_CTL_MODE_VBRN 0x5 +#define RATE_CONTROL_MODE_CTL_MODE_GVBRN 0x6 + +#define PROFILE_AND_TOOLSET_CTL_CONSTRAINED_BASELINE_PROFILE 0x4240 +#define PROFILE_AND_TOOLSET_CTL_BASELINE_PROFILE 0x4200 +#define PROFILE_AND_TOOLSET_CTL_MAIN_PROFILE 0x4D00 +#define PROFILE_AND_TOOLSET_CTL_CONSTRAINED_HIGH_PROFILE 0x640C +#define PROFILE_AND_TOOLSET_CTL_HIGH_PROFILE 0x6400 +#define PROFILE_AND_TOOLSET_CTL_SCALABLE_CONSTRAINED_BASELINE_PROFILE 0x5304 +#define PROFILE_AND_TOOLSET_CTL_SCALABLE_BASELINE_PROFILE 0x5300 +#define PROFILE_AND_TOOLSET_CTL_SCALABLE_CONSTRAINED_HIGH_PROFILE 0x5604 +#define PROFILE_AND_TOOLSET_CTL_SCALABLE_HIGH_PROFILE 0x5600 +#define PROFILE_AND_TOOLSET_CTL_MULTIVIEW_HIGH_PROFILE 0x7600 +#define PROFILE_AND_TOOLSET_CTL_STEREO_HIGH_PROFILE 0x8000 + +#define SLICE_MODE_CTL_MODE_MAX_MBS_PER_SLICE 0x0 +#define SLICE_MODE_CTL_MODE_TARGET_COMPRESSED_SIZE_PER_SLICE 0x1 +#define SLICE_MODE_CTL_MODE_NUMBER_OF_SLICES_PER_FRAME 0x2 +#define SLICE_MODE_CTL_MODE_NUMBER_OF_MACROBLOCK_ROWS_PER_SLICE 0x3 + +#define SYNC_AND_LTR_FRAME_CTL_RESET 0x0 +#define SYNC_AND_LTR_FRAME_CTL_IDR 0x1 +#define SYNC_AND_LTR_FRAME_CTL_LONG_TERM_REF_IDR 0x2 +#define SYNC_AND_LTR_FRAME_CTL_NON_IDR_RAND_I_FRAME 0x3 +#define SYNC_AND_LTR_FRAME_CTL_LTR_NON_IDR_RAND_I_FRAME 0x4 +#define SYNC_AND_LTR_FRAME_CTL_LTR_P_FRAME 0x5 + +#define LONG_TERM_BUFFER_CTL_TRUSTMODE_NOT_TRUST 0x0 +#define LONG_TERM_BUFFER_CTL_TRUSTMODE_TRUST 0x1 + +#define SEI_MESSAGE_CTL_BUFFERING_PERIOD 0x1 +#define SEI_MESSAGE_CTL_PIC_TIMING 0x2 +#define SEI_MESSAGE_CTL_PAN_SCAN_RECT 0x4 +#define SEI_MESSAGE_CTL_FILLER_PAYLOAD 0x8 +#define SEI_MESSAGE_CTL_USER_DATA_REGISTERED_ITU_T_T35 0x10 +#define SEI_MESSAGE_CTL_USER_DATA_UNREGISTERED 0x20 +#define SEI_MESSAGE_CTL_RECOVERY_POINT 0x40 +#define SEI_MESSAGE_CTL_DEC_REF_PIC_MARKING_REPETITION 0x80 +#define SEI_MESSAGE_CTL_SPARE_PIC 0x100 +#define SEI_MESSAGE_CTL_SCENE_INFO 0x200 +#define SEI_MESSAGE_CTL_SUB_SEQ_INFO 0x400 +#define SEI_MESSAGE_CTL_SUB_SEQ_LAYER_CHARACTERISTICS 0x800 +#define SEI_MESSAGE_CTL_SUB_SEQ_CHARACTERISTICS 0x1000 +#define SEI_MESSAGE_CTL_FULL_FRAME_FREEZE 0x2000 +#define SEI_MESSAGE_CTL_FULL_FRAME_FREEZE_RELEASE 0x4000 +#define SEI_MESSAGE_CTL_FULL_FRAME_SNAPSHOT 0x8000 +#define SEI_MESSAGE_CTL_PROGRESSIVE_REFINEMENT_SEGMENT_START 0x10000 +#define SEI_MESSAGE_CTL_PROGRESSIVE_REFINEMENT_SEGMENT_END 0x20000 +#define SEI_MESSAGE_CTL_MOTION_CONSTRAINED_SLICE_GROUP_SET 0x40000 +#define SEI_MESSAGE_CTL_FILM_GRAIN_CHARACTERISTICS 0x80000 +#define SEI_MESSAGE_CTL_DEBLOCKING_FILTER_DISPLAY_PREFERENCE 0x100000 +#define SEI_MESSAGE_CTL_STEREO_VIDEO_INFO 0x200000 +#define SEI_MESSAGE_CTL_POST_FILTER_HINT 0x400000 +#define SEI_MESSAGE_CTL_TONE_MAPPING_INFO 0x800000 +#define SEI_MESSAGE_CTL_SCALABILITY_INFO 0x1000000 +#define SEI_MESSAGE_CTL_SUB_PIC_SCALABLE_LAYER 0x2000000 +#define SEI_MESSAGE_CTL_NON_REQUIRED_LAYER_REP 0x4000000 +#define SEI_MESSAGE_CTL_PRIORITY_LAYER_INFO 0x8000000 +#define SEI_MESSAGE_CTL_LAYERS_NOT_PRESENT 0x10000000 +#define SEI_MESSAGE_CTL_LAYER_DEPENDENCY_CHANGE 0x20000000 +#define SEI_MESSAGE_CTL_SCALABLE_NESTING 0x40000000 +#define SEI_MESSAGE_CTL_BASE_LAYER_TEMPORAL_HRD 0x80000000 +#define SEI_MESSAGE_CTL_QUALITY_LAYER_INTEGRITY_CHECK 0x100000000 +#define SEI_MESSAGE_CTL_REDUNDANT_PIC_PROPERTY 0x200000000 +#define SEI_MESSAGE_CTL_TL0_DEP_REP_INDEX 0x400000000 +#define SEI_MESSAGE_CTL_TL_SWITCHING_POINT 0x800000000 +#define SEI_MESSAGE_CTL_PARALLEL_DECODING_INFO 0x1000000000 +#define SEI_MESSAGE_CTL_MVC_SCALABLE_NESTING 0x2000000000 +#define SEI_MESSAGE_CTL_VIEW_SCALABILITY_INFO 0x4000000000 +#define SEI_MESSAGE_CTL_MULTIVIEW_SCENE_INFO 0x8000000000 +#define SEI_MESSAGE_CTL_MULTIVIEW_ACQUISITION_INFO 0x10000000000 +#define SEI_MESSAGE_CTL_NON_REQUIRED_VIEW_COMPONENT 0x20000000000 +#define SEI_MESSAGE_CTL_VIEW_DEPENDENCY_CHANGE 0x40000000000 +#define SEI_MESSAGE_CTL_OPERATION_POINTS_NOT_PRESENT 0x80000000000 +#define SEI_MESSAGE_CTL_BASE_VIEW_TEMPORAL_HRD 0x100000000000 +#define SEI_MESSAGE_CTL_FRAME_PACKING_ARRANGEMENT 0x200000000000 + +#define UVC_CID_XU_CLASS_BASE (UVC_ET_XU << ET_POS) + +#define UVC_VSCID_PROBE_CONTROL UVC_VS_PROBE_CONTROL +#define UVC_VSCID_COMMIT_CONTROL UVC_VS_COMMIT_CONTROL +#define UVC_VSCID_STILL_PROBE UVC_VS_STILL_PROBE_CONTROL +#define UVC_VSCID_STILL_COMMIT UVC_VS_STILL_COMMIT_CONTROL +#define UVC_VSCID_STILL_IMAGE_TRIGGER UVC_VS_STILL_IMAGE_TRIGGER_CONTROL +#define UVC_VSCID_STREAM_ERROR_CODE UVC_VS_STREAM_ERROR_CODE_CONTROL +#define UVC_VSCID_GENERATE_KEY_FRAME UVC_VS_GENERATE_KEY_FRAME_CONTROL +#define UVC_VSCID_UPDATE_FRAME_SEGMENT UVC_VS_UPDATE_FRAME_SEGMENT_CONTROL +#define UVC_VSCID_SYNC_DELAY UVC_VS_SYNC_DELAY_CONTROL + +#define PROBE_LEN 48 +#define PROFILE_AND_TOOLSET_LEN 0x5 +#define UVC_VSCID_PROBE UVC_VS_PROBE_CONTROL << 8 +#define UVC_VSCID_COMMIT UVC_VS_COMMIT_CONTROL << 8 + +#endif // __UVC_API_INTERNAL_H__ diff --git a/mdw/kdp_usb_uvc/include/uvc_utils.h b/mdw/kdp_usb_uvc/include/uvc_utils.h new file mode 100644 index 0000000..b9d33aa --- /dev/null +++ b/mdw/kdp_usb_uvc/include/uvc_utils.h @@ -0,0 +1,131 @@ +#ifndef _UTILS_H +#define _UTILS_H +#include +#include +#include +#include + + +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1 << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +//#define NULL (void *) 0 +#define ___PASTE(a,b) a##b +//#define __PASTE(a,b) ___PASTE(a,b) +#define __UNIQUE_ID(prefix) __PASTE(__PASTE(__UNIQUE_ID_, prefix), __COUNTER__) + +#define __min(t1, t2, min1, min2, x, y) ({ \ + t1 min1 = (x); \ + t2 min2 = (y); \ + (void) (&min1 == &min2); \ + min1 < min2 ? min1 : min2; }) + +#define min(x, y) \ + __min(typeof(x), typeof(y), \ + __UNIQUE_ID(min1_), __UNIQUE_ID(min2_), \ + x, y) + +#define __max(t1, t2, max1, max2, x, y) ({ \ + t1 max1 = (x); \ + t2 max2 = (y); \ + (void) (&max1 == &max2); \ + max1 > max2 ? max1 : max2; }) + +#define max(x, y) \ + __max(typeof(x), typeof(y), \ + __UNIQUE_ID(max1_), __UNIQUE_ID(max2_), \ + x, y) + +#define min3(x, y, z) min((typeof(x))min(x, y), z) +#define max3(x, y, z) max((typeof(x))max(x, y), z) + +/** + * min_not_zero - return the minimum that is _not_ zero, unless both are zero + * @x: value1 + * @y: value2 + */ +#define min_not_zero(x, y) ({ \ + typeof(x) __x = (x); \ + typeof(y) __y = (y); \ + __x == 0 ? __y : ((__y == 0) ? __x : min(__x, __y)); }) + +/** + * clamp - return a value clamped to a given range with strict typechecking + * @val: current value + * @lo: lowest allowable value + * @hi: highest allowable value + * + * This macro does strict typechecking of lo/hi to make sure they are of the + * same type as val. See the unnecessary pointer comparisons. + */ +#define clamp(val, lo, hi) min((typeof(val))max(val, lo), hi) + +/* + * ..and if you can't take the strict + * types, you can specify one yourself. + * + * Or not use min/max/clamp at all, of course. + */ +#define min_t(type, x, y) \ + __min(type, type, \ + __UNIQUE_ID(min1_), __UNIQUE_ID(min2_), \ + x, y) + +#define max_t(type, x, y) \ + __max(type, type, \ + __UNIQUE_ID(min1_), __UNIQUE_ID(min2_), \ + x, y) + +/** + * clamp_t - return a value clamped to a given range using a given type + * @type: the type of variable to use + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of type + * 'type' to make all the comparisons. + */ +#define clamp_t(type, val, lo, hi) min_t(type, max_t(type, val, lo), hi) + +/** + * clamp_val - return a value clamped to a given range using val's type + * @val: current value + * @lo: minimum allowable value + * @hi: maximum allowable value + * + * This macro does no typechecking and uses temporary variables of whatever + * type the input argument 'val' is. This is useful when val is an unsigned + * type and min and max are literals that will otherwise be assigned a signed + * integer type. + */ +#define clamp_val(val, lo, hi) clamp_t(typeof(val), val, lo, hi) + + +/* + * swap - swap value of @a and @b + */ +#define swap(a, b) \ + do { typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0) + +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +//#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE *)0)->MEMBER) + + + +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + +#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) + +#endif + + diff --git a/mdw/kdp_usb_uvc/include/uvc_video.h b/mdw/kdp_usb_uvc/include/uvc_video.h new file mode 100644 index 0000000..ca5f542 --- /dev/null +++ b/mdw/kdp_usb_uvc/include/uvc_video.h @@ -0,0 +1,15 @@ +#ifndef UVC_VIDEO_H +#define UVC_VIDEO_H + +#include + + +int uvc_video_init(struct uvc_device *dev); + +int uvc_video_enable(struct uvc_streaming *stream); + +int uvc_video_disable(struct uvc_streaming *stream); + + +#endif // UVC_VIDEO_H + diff --git a/mdw/kdp_usb_uvc/src/kdp_uvc.c b/mdw/kdp_usb_uvc/src/kdp_uvc.c new file mode 100644 index 0000000..a92dee8 --- /dev/null +++ b/mdw/kdp_usb_uvc/src/kdp_uvc.c @@ -0,0 +1,1819 @@ +/* + * KDP UVC driver + * + * Copyright (C) 2019 - 2020 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include +#include "kneron_mozart.h" +#include "kdp_usb.h" +#include "uvc.h" +#include +#include +#include "kmdw_memory.h" +#include "uvc_internal_api.h" +#include "kmdw_camera.h" +#include "kmdw_display.h" +#include "delay.h" +#include "uvc_camera.h" +#include "kmdw_usbh.h" +#include "kmdw_uvc.h" +#include "kmdw_console.h" +#define FLAGS_YOLO_STOP_EVT BIT1 + +#define KDP_UVC_DRIVER_DESC "KDP UVC driver" +#define KDP_UVC_DRIVER 1 +#define MIN(a,b) (((a)<(b))?(a):(b)) +#define MAX(a,b) (((a)>(b))?(a):(b)) +#define ROUND_UP(x, y) ((((x) + (y - 1)) / y) * y) + +static struct uvc_device uvc_video_s; +static struct uvc_device *uvc_video_device = &uvc_video_s; +static USBH_PIPE_HANDLE isoch_pipe = 0; +osThreadId_t tid_to_notify; + +#define NUM_FRAME 7 +#define FRMAE_SIZE (640 * 480 * 2) // VGA YUV420 + +// FIXME: temp solution (ping pong buffer) to remove kdrv_fb_mgr, need to test if 520 uvc device is ready +uint32_t ping_pong_buf_addr[2] = {0}; + +void USBH_UVC_Get_Frame(uint32_t *frame_ptr, uint32_t *frame_size, int *index) +{ + struct uvc_device *udev = uvc_video_device; + struct uvc_streaming *stream = udev->curr_stream; +#ifdef UVC_USER_ERR + if (frame_size != FRMAE_SIZE) + kmdw_printf("uvc_example: frame_ptr 0x%p frame_size %u is wrong\n", frame_ptr, frame_size); +#endif + *frame_ptr = stream->frame_buf; + *frame_size = udev->curr_stream->cur_format->bpp * udev->curr_stream->cur_format->cur_frame->wWidth * udev->curr_stream->cur_format->cur_frame->wHeight; + *index = stream->write_idx; +} + + +struct uvc_device *video_dev(const char *pname) +{ + if (!memcmp(uvc_video_device->name, pname, sizeof (*pname))) { + return uvc_video_device; + } + + return NULL; +} + +static int kdp_uvc_get_ctl_list(uint32_t *ctl_list) +{ + struct uvc_device *udev = uvc_video_device; + ctl_list[0] = udev->IT[0].ct->bmControls; + ctl_list[1] = udev->PU[0].bmControls; + + return 0; +} + +static int uvc_list_ctl(uint32_t *data) +{ + return kdp_uvc_get_ctl_list(data); +} + +static int uvc_scanning_mode_ctl(struct uvc_device *udev, struct ct_scm *ctl) +{ + if (ctl->req == SCM_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_SCANNING_MODE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_SCANNING_MODE, ctl->req, (uint8_t *)&ctl->bScanningMode, SCANNING_MODE_LEN); +} + +static int uvc_exposure_mode_ctl(struct uvc_device *udev, struct ct_aem *ctl) +{ + if (ctl->req == AEM_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_AUTO_EXPOSURE_MODE, ctl->req, &ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_AUTO_EXPOSURE_MODE, ctl->req, &ctl->bAutoExposureMode, AUTO_EXPOSURE_MODE_LEN); +} + +static int uvc_exposure_priority_ctl(struct uvc_device *udev, struct ct_aep *ctl) +{ + if (ctl->req == AEP_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_AUTO_EXPOSURE_PRIORITY, ctl->req, &ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_AUTO_EXPOSURE_PRIORITY, ctl->req, &ctl->bAutoExposurePriority, AUTO_EXPOSURE_PRIORITY_LEN); +} + +static int uvc_exposure_time_abs_ctl(struct uvc_device *udev, struct ct_eta *ctl) +{ + if (ctl->req == ETA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_EXPOSURE_TIME_ABSOLUTE, ctl->req, &ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_EXPOSURE_TIME_ABSOLUTE, ctl->req, (uint8_t *)&ctl->bExposureTimeAbsolute, EXPOSURE_TIME_ABSOLUTE_LEN); +} + +static int uvc_shutter_speed_ctl(struct uvc_device *udev, struct ct_etr *ctl) +{ + if (ctl->req == ETA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_EXPOSURE_TIME_RELATIVE, ctl->req, &ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_EXPOSURE_TIME_RELATIVE, ctl->req, (uint8_t *)&ctl->bExposureTimeRelative, EXPOSURE_TIME_RELATIVE_LEN); +} + +static int uvc_focus_auto_ctl(struct uvc_device *udev, struct ct_fauto *ctl) +{ + if (ctl->req == FAUTO_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_FOCUS_AUTO, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_FOCUS_AUTO, ctl->req, (uint8_t *)&ctl->bFocusAuto, FOCUS_AUTO_LEN); +} + +static int uvc_focus_abs_ctl(struct uvc_device *udev, struct ct_focus_a *ctl) +{ + if (ctl->req == FA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_FOCUS_ABSOLUTE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_FOCUS_ABSOLUTE, ctl->req, (uint8_t *)&ctl->wFocusAbsolute, FOCUS_ABSOLUTE_LEN); +} + +static int uvc_focus_rel_ctl(struct uvc_device *udev, struct ct_focus_r *ctl) +{ + if (ctl->req == FR_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_FOCUS_RELATIVE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_FOCUS_RELATIVE, ctl->req, (uint8_t *)&ctl->data, FOCUS_RELATIVE_LEN); +} + +static int uvc_focus_simple_range_ctl(struct uvc_device *udev, struct ct_focus_sr *ctl) +{ + if (ctl->req == FSR_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_FOCUS_SIMPLE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_FOCUS_SIMPLE, ctl->req, (uint8_t *)&ctl->bFocus, FOCUS_SIMPLE_LEN); +} + +static int uvc_iris_abs_ctl(struct uvc_device *udev, struct ct_iris_a *ctl) +{ + if (ctl->req == IRISA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_IRIS_ABSOLUTE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_IRIS_ABSOLUTE, ctl->req, (uint8_t *)&ctl->wIrisAbsolute, IRIS_ABSOLUTE_LEN); +} + +static int uvc_iris_rel_ctl(struct uvc_device *udev, struct ct_iris_r *ctl) +{ + if (ctl->req == IRISR_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_IRIS_RELATIVE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_IRIS_RELATIVE, ctl->req, (uint8_t *)&ctl->bIrisRelative, IRIS_ABSOLUTE_LEN); +} + +static int uvc_zoom_abs_ctl(struct uvc_device *udev, struct ct_zoom_a *ctl) +{ + if (ctl->req == ZOOMA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_ZOOM_ABSOLUTE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_ZOOM_ABSOLUTE, ctl->req, (uint8_t *)&ctl->wObjectiveFocalLength, FOCUS_ABSOLUTE_LEN); +} + +static int uvc_zoom_rel_ctl(struct uvc_device *udev, struct ct_zoom_r *ctl) +{ + if (ctl->req == ZOOMR_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_ZOOM_RELATIVE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_ZOOM_RELATIVE, ctl->req, (uint8_t *)&ctl->data, FOCUS_RELATIVE_LEN); +} + +static int uvc_hue_ctl(struct uvc_device *udev, struct pu_hue *ctl) +{ + if (ctl->req == HUE_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_HUE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_HUE, ctl->req, (uint8_t *)&ctl->wHue, HUE_LEN); +} + +static int uvc_hue_auto_ctl(struct uvc_device *udev, struct pu_hue_auto * ctl) +{ + if (ctl->req == HUEA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_HUE_AUTO, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_HUE_AUTO, ctl->req, (uint8_t *)&ctl->bHueAuto, HUE_AUTO_LEN); +} + +static int uvc_pan_tilt_abs_ctl(struct uvc_device *udev, struct ct_pan_tilt_a *ctl) +{ + if (ctl->req == TILTA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_PANTILT_ABSOLUTE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_PANTILT_ABSOLUTE, ctl->req, (uint8_t *)&ctl->data, PANTILT_ABSOLUTE_LEN); +} + +static int uvc_pan_tilt_rel_ctl(struct uvc_device *udev, struct ct_pan_tilt_r *ctl) +{ + if (ctl->req == TILTR_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_PANTILT_RELATIVE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_PANTILT_RELATIVE, ctl->req, (uint8_t *)&ctl->data, PANTILT_RELATIVE_LEN); +} + +static int uvc_roll_abs_ctl(struct uvc_device *udev, struct ct_roll_a *ctl) +{ + if (ctl->req == ROLLA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_ROLL_ABSOLUTE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_ROLL_ABSOLUTE, ctl->req, (uint8_t *)&ctl->wAbsolute, PANTILT_ABSOLUTE_LEN); +} + +static int uvc_roll_rel_ctl(struct uvc_device *udev, struct ct_roll_r *ctl) +{ + if (ctl->req == ROLLR_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_ROLL_RELATIVE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_ROLL_RELATIVE, ctl->req, (uint8_t *)&ctl->data, ROLL_RELATIVE_LEN); +} + +static int uvc_digital_windows_ctl(struct uvc_device *udev, struct ct_dwindow *ctl) +{ + return uvc_send_ctl(udev, UVC_CID_WINDOW, ctl->req, (uint8_t *)&ctl->data, WINDOW_LEN); +} + +static int uvc_roi_ctl(struct uvc_device *udev, struct ct_roi *ctl) +{ + return uvc_send_ctl(udev, UVC_CID_REGION_OF_INTEREST, ctl->req, (uint8_t *)&ctl->data, REGION_OF_INTEREST_LEN); +} + +static int uvc_privacy_shutter_ctl(struct uvc_device *udev, struct ct_privacy_shutter *ctl) +{ + if (ctl->req == PS_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_PRIVACY, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_PRIVACY, ctl->req, (uint8_t *)&ctl->bPrivacy, PRIVACY_LEN); +} + +static int uvc_backlight_compensation_ctl(struct uvc_device *udev, struct pu_backlight *ctl) +{ + if (ctl->req == BKC_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_BACKLIGHT_COMPENSATION, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_BACKLIGHT_COMPENSATION, ctl->req, (uint8_t *)&ctl->wBacklightCompensation, BACKLIGHT_COMPENSATION_LEN); +} + +static int uvc_brightness_ctl(struct uvc_device *udev, struct pu_brightness *ctl) +{ + if (ctl->req == BKC_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_BRIGHTNESS, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_BRIGHTNESS, ctl->req, (uint8_t *)&ctl->wBrightness, BRIGHTNESS_LEN); +} + +static int uvc_contrast_ctl(struct uvc_device *udev, struct pu_contrast *ctl) +{ + if (ctl->req == BKC_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_CONTRAST, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_CONTRAST, ctl->req, (uint8_t *)&ctl->wContrast, CONTRAST_LEN); +} + +static int uvc_contrast_auto_ctl(struct uvc_device *udev, struct pu_contrast_auto *ctl) +{ + if (ctl->req == CONTRASTA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_CONTRAST_AUTO, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_CONTRAST_AUTO, ctl->req, (uint8_t *)&ctl->bContrastAuto, CONTRAST_AUTO_LEN); +} + +static int uvc_gain_ctl(struct uvc_device *udev, struct pu_gain *ctl) +{ + if (ctl->req == GAIN_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_GAIN, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_GAIN, ctl->req, (uint8_t *)&ctl->wGain, GAIN_LEN); +} + +static int uvc_power_line_frequency_ctl(struct uvc_device *udev, struct pu_power_line_frequency *ctl) +{ + if (ctl->req == GAIN_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_POWER_LINE_FREQUENCY, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_POWER_LINE_FREQUENCY, ctl->req, (uint8_t *)&ctl->bPowerLineFrequency, POWER_LINE_FREQUENCY_LEN); +} + +static int uvc_saturation_ctl(struct uvc_device *udev, struct pu_saturation *ctl) +{ + if (ctl->req == SATURATION_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_SATURATION, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_SATURATION, ctl->req, (uint8_t *)&ctl->wSaturation, SATURATION_LEN); +} + +static int uvc_sharpness_ctl(struct uvc_device *udev, struct pu_sharpness *ctl) +{ + if (ctl->req == SHARPNESS_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_SHARPNESS, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_SHARPNESS, ctl->req, (uint8_t *)&ctl->wSharpness, SHARPNESS_LEN); +} + +static int uvc_gamma_ctl(struct uvc_device *udev, struct pu_gamma *ctl) +{ + if (ctl->req == GAMMA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_GAMMA, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_GAMMA, ctl->req, (uint8_t *)&ctl->wGamma, GAMMA_LEN); +} + +static int uvc_white_balance_temperature_ctl(struct uvc_device *udev, struct pu_white_balance_temp *ctl) +{ + if (ctl->req == WBT_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_WHITE_BALANCE_TEMPERATURE, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_WHITE_BALANCE_TEMPERATURE, ctl->req, (uint8_t *)&ctl->wWhiteBalanceTemperature, WHITE_BALANCE_TEMPERATURE_LEN); +} + +static int uvc_white_balance_temperature_auto_ctl(struct uvc_device *udev, struct pu_wbc_auto *ctl) +{ + if (ctl->req == WBTA_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_WHITE_BALANCE_TEMPERATURE_AUTO, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_WHITE_BALANCE_TEMPERATURE_AUTO, ctl->req, (uint8_t *)&ctl->bWhiteBalanceComponentAuto, WHITE_BALANCE_TEMPERATURE_AUTO_LEN); +} + +static int uvc_white_balance_compont_ctl(struct uvc_device *udev, struct pu_whitebalance_comp *ctl) +{ + if (ctl->req == WBC_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_WHITE_BALANCE_COMPONENT, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_WHITE_BALANCE_COMPONENT, ctl->req, (uint8_t *)&ctl->data, WHITE_BALANCE_COMPONENT_LEN); +} + +static int uvc_white_balance_compont_auto_ctl(struct uvc_device *udev, struct pu_wbc_auto *ctl) +{ + if (ctl->req == WBC_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_WHITE_BALANCE_COMPONENT_AUTO, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_WHITE_BALANCE_COMPONENT_AUTO, ctl->req, (uint8_t *)&ctl->bWhiteBalanceComponentAuto, WHITE_BALANCE_COMPONENT_AUTO_LEN); +} + +static int uvc_digital_multiplier_ctl(struct uvc_device *udev, struct pu_dmultiplier *ctl) +{ + if (ctl->req == MPL_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_DIGITAL_MULTIPLIER, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_DIGITAL_MULTIPLIER, ctl->req, (uint8_t *)&ctl->wMultiplierStep, DIGITAL_MULTIPLIER_LEN); +} + +static int uvc_digital_multiplier_limit_ctl(struct uvc_device *udev, struct pu_dmultiplierlimit *ctl) +{ + if (ctl->req == DMPL_GET_CAP) + return uvc_send_ctl(udev, UVC_CID_DIGITAL_MULTIPLIER_LIMIT, ctl->req, (uint8_t *)&ctl->caps, 1); + else + return uvc_send_ctl(udev, UVC_CID_DIGITAL_MULTIPLIER_LIMIT, ctl->req, (uint8_t *)&ctl->wMultiplierLimit, DIGITAL_MULTIPLIER_LIMIT_LEN); +} + +static kmdw_status_t kdp_uvc_ioctl(uint32_t cam_idx, uint32_t cid, void *data, uint16_t len) +{ + struct uvc_device *udev = uvc_video_device; + int ret; + + if ((true != udev->opened) || (NULL == udev)) { + return KMDW_STATUS_ERROR; + } + + switch (cid) + { + + case CID_SCANNING_MODE: + if (len >= sizeof (struct ct_scm)) + ret = uvc_scanning_mode_ctl(udev, (struct ct_scm *) data); + else + ret = -1; + break; + + case CID_AUTO_EXPOSURE_MODE: + if (len >= sizeof (struct ct_aem)) + ret = uvc_exposure_mode_ctl(udev, (struct ct_aem *) data); + else + ret = -1; + break; + + case CID_AUTO_EXPOSURE_PRIORITY: + if (len >= sizeof (struct ct_aep)) + ret = uvc_exposure_priority_ctl(udev, (struct ct_aep *)data); + else + ret = -1; + break; + + case CID_EXPOSURE_TIME_ABSOLUTE: + if (len >= sizeof (struct ct_eta)) + ret = uvc_exposure_time_abs_ctl(udev, (struct ct_eta *)data); + else + ret = -1; + break; + + case CID_EXPOSURE_TIME_RELATIVE: + if (len >= sizeof (struct ct_etr)) + ret = uvc_shutter_speed_ctl(udev, (struct ct_etr *) data); + else + ret = -1; + break; + + case CID_FOCUS_AUTO: + if (len >= sizeof (struct ct_fauto)) + ret = uvc_focus_auto_ctl(udev, (struct ct_fauto *) data); + else + ret = -1; + break; + + case CID_FOCUS_ABSOLUTE: + if (len >= sizeof (struct ct_focus_a)) + ret = uvc_focus_abs_ctl(udev, (struct ct_focus_a *) data); + else + ret = -1; + break; + + case CID_FOCUS_RELATIVE: + if (len >= sizeof (struct ct_focus_r)) + ret = uvc_focus_rel_ctl(udev, (struct ct_focus_r *) data); + else + ret = -1; + break; + + case CID_IRIS_ABSOLUTE: + if (len >= sizeof (struct ct_iris_a)) + ret = uvc_iris_abs_ctl(udev, (struct ct_iris_a *) data); + else + ret = -1; + break; + + case CID_IRIS_RELATIVE: + if (len >= sizeof (struct ct_iris_r)) + ret = uvc_iris_rel_ctl(udev, (struct ct_iris_r *) data); + else + ret = -1; + break; + + case CID_ZOOM_ABSOLUTE: + if (len >= sizeof (struct ct_zoom_a)) + ret = uvc_zoom_abs_ctl(udev, (struct ct_zoom_a *) data); + else + ret = -1; + break; + + case CID_ZOOM_RELATIVE: + if (len >= sizeof (struct ct_zoom_r)) + ret = uvc_zoom_rel_ctl(udev, (struct ct_zoom_r *) data); + else + ret = -1; + break; + + case CID_PANTILT_ABSOLUTE: + if (len >= sizeof (struct ct_pan_tilt_a)) + ret = uvc_pan_tilt_abs_ctl(udev, (struct ct_pan_tilt_a *) data); + else + ret = -1; + break; + + case CID_PANTILT_RELATIVE: + if (len >= sizeof (struct ct_pan_tilt_r)) + ret = uvc_pan_tilt_rel_ctl(udev, (struct ct_pan_tilt_r *) data); + else + ret = -1; + break; + + case CID_ROLL_ABSOLUTE: + if (len >= sizeof (struct ct_roll_a)) + ret = uvc_roll_abs_ctl(udev, (struct ct_roll_a *) data); + else + ret = -1; + break; + + case CID_ROLL_RELATIVE: + if (len >= sizeof (struct ct_roll_r)) + ret = uvc_roll_rel_ctl(udev, (struct ct_roll_r *) data); + else + ret = -1; + break; + + case CID_PRIVACY: + if (len >= sizeof (struct ct_privacy_shutter)) + ret = uvc_privacy_shutter_ctl(udev, (struct ct_privacy_shutter *) data); + else + ret = -1; + break; + + case CID_FOCUS_SIMPLE: + if (len >= sizeof (struct ct_focus_sr)) + ret = uvc_focus_simple_range_ctl(udev, (struct ct_focus_sr *) data); + else + ret = -1; + break; + + case CID_DIGITAL_WINDOW: + if (len >= sizeof (struct ct_dwindow)) + ret = uvc_digital_windows_ctl(udev, (struct ct_dwindow *) data); + else + ret = -1; + break; + + case CID_REGION_OF_INTEREST: + if (len >= sizeof (struct ct_roi)) + ret = uvc_roi_ctl(udev, (struct ct_roi *) data); + else + ret = -1; + break; + + case CID_BRIGHTNESS: + if (len >= sizeof (struct pu_brightness)) + ret = uvc_brightness_ctl(udev, (struct pu_brightness *) data); + else + ret = -1; + break; + + case CID_CONTRAST: + if (len >= sizeof (struct pu_contrast)) + ret = uvc_contrast_ctl(udev, (struct pu_contrast *) data); + else + ret = -1; + break; + + case CID_HUE: + if (len >= sizeof (struct pu_hue)) + ret = uvc_hue_ctl(udev, (struct pu_hue *) data); + else + ret = -1; + break; + + case CID_SATURATION: + if (len >= sizeof (struct pu_saturation)) + ret = uvc_saturation_ctl(udev, (struct pu_saturation *) data); + else + ret = -1; + break; + + case CID_SHARPNESS: + if (len >= sizeof (struct pu_sharpness)) + ret = uvc_sharpness_ctl(udev, (struct pu_sharpness *) data); + else + ret = -1; + break; + + case CID_GAMMA: + if (len >= sizeof (struct pu_gamma)) + ret = uvc_gamma_ctl(udev, (struct pu_gamma *) data); + else + ret = -1; + break; + + case CID_WHITE_BALANCE_TEMPERATURE: + if (len >= sizeof (struct pu_white_balance_temp)) + ret = uvc_white_balance_temperature_ctl(udev, (struct pu_white_balance_temp *) data); + else + ret = -1; + break; + + case CID_WHITE_BALANCE_COMPONENT: + if (len >= sizeof (struct pu_whitebalance_comp)) + ret = uvc_white_balance_compont_ctl(udev, (struct pu_whitebalance_comp *) data); + else + ret = -1; + break; + + case CID_BACKLIGHT_COMPENSATION: + if (len >= sizeof (struct pu_backlight)) + ret = uvc_backlight_compensation_ctl(udev, (struct pu_backlight *) data); + else + ret = -1; + break; + + case CID_GAIN: + if (len >= sizeof (struct pu_gain)) + ret = uvc_gain_ctl(udev, (struct pu_gain *) data); + else + ret = -1; + break; + + case CID_POWER_LINE_FREQUENCY: + if (len >= sizeof (struct pu_power_line_frequency)) + ret = uvc_power_line_frequency_ctl(udev, (struct pu_power_line_frequency *) data); + else + ret = -1; + break; + + case CID_HUE_AUTO: + if (len >= sizeof (struct pu_hue_auto)) + ret = uvc_hue_auto_ctl(udev, (struct pu_hue_auto *) data); + else + ret = -1; + break; + + case CID_WHITE_BALANCE_TEMPERATURE_AUTO: + if (len >= sizeof (struct pu_wbc_auto)) + ret = uvc_white_balance_temperature_auto_ctl(udev, (struct pu_wbc_auto *) data); + else + ret = -1; + break; + + case CID_WHITE_BALANCE_COMPONENT_AUTO: + if (len >= sizeof (struct pu_wbc_auto)) + ret = uvc_white_balance_compont_auto_ctl(udev, (struct pu_wbc_auto *) data); + else + ret = -1; + break; + + case CID_DIGITAL_MULTIPLIER: + if (len >= sizeof (struct pu_dmultiplier)) + ret = uvc_digital_multiplier_ctl(udev, (struct pu_dmultiplier *) data); + else + ret = -1; + break; + + case CID_DIGITAL_MULTIPLIER_LIMIT: + if (len >= sizeof (struct pu_dmultiplierlimit)) + ret = uvc_digital_multiplier_limit_ctl(udev, (struct pu_dmultiplierlimit *) data); + else + ret = -1; + break; + + case CID_CONTRAST_AUTO: + if (len >= sizeof (struct pu_contrast_auto)) + ret = uvc_contrast_auto_ctl(udev, (struct pu_contrast_auto *) data); + else + ret = -1; + break; + + case CID_LIST_ALL: + if (len >= 2 * sizeof (uint32_t)) + ret = uvc_list_ctl((uint32_t *) data); + else + ret = -1; + break; + + default: + ret = -1; + break; + } + if (ret < 0) + return KMDW_STATUS_ERROR; + return KMDW_STATUS_OK; + +} + +static uint32_t uvc_k_get_bytesperline(const struct uvc_format *format, + const struct uvc_frame *frame) +{ + return format->bpp * frame->wWidth; +} + +static uint32_t uvc_try_frame_interval(struct uvc_frame *frame, uint32_t interval) +{ + uint32_t new_interval; + int i; + if (frame->bFrameIntervalType != 0) { + uint32_t best = 0xFFFFFFFF, dist; + for (i = 0; i < frame->bFrameIntervalType; ++i) { + dist = interval > frame->dwFrameInterval[i] + ? interval - frame->dwFrameInterval[i] + : frame->dwFrameInterval[i] - interval; + if (dist > best) + break; + best = dist; + } + new_interval = frame->dwFrameInterval[i-1]; + } else { + const uint32_t min = frame->dwFrameInterval[0]; + const uint32_t max = frame->dwFrameInterval[1]; + const uint32_t step = frame->dwFrameInterval[2]; + + new_interval = min + (new_interval - min + step/2) / step * step; + if (interval > max) + interval = max; + } + return new_interval; +} + +static kmdw_status_t kdp_uvc_stream_off(uint32_t cam_idx) +{ + struct uvc_device *udev = uvc_video_device; + struct uvc_streaming *stream = udev->curr_stream; + + if (0 > uvc_video_disable(stream)) + return KMDW_STATUS_ERROR; + return KMDW_STATUS_OK; +} + +static kmdw_status_t kdp_uvc_stream_on(uint32_t cam_idx) +{ + struct uvc_device *udev = uvc_video_device; + struct uvc_streaming *stream = udev->curr_stream; + + if (0 > uvc_video_enable(stream)) + return KMDW_STATUS_ERROR; + return KMDW_STATUS_OK; + +} + +static kmdw_status_t kdp_uvc_start_capture(uint32_t cam_idx, kmdw_camera_callback_t img_cb) +{ + struct uvc_device *udev = uvc_video_device; + struct uvc_streaming *stream = udev->curr_stream; + + if (udev->opened != true) + return KMDW_STATUS_ERROR; + if ((NULL == udev) || (stream == NULL)) + return KMDW_STATUS_ERROR; + if (0 > uvc_video_enable(stream)) + return KMDW_STATUS_ERROR; + return KMDW_STATUS_OK; +} + +static kmdw_status_t kdp_uvc_stop_capture(uint32_t cam_idx) +{ + struct uvc_device *udev = uvc_video_device; + struct uvc_streaming *stream = udev->curr_stream; + + if (udev->opened != true) + return KMDW_STATUS_ERROR; + if ((NULL == udev) || (stream == NULL)) + return KMDW_STATUS_ERROR; + if (0 > uvc_video_disable(stream)) + return KMDW_STATUS_ERROR; + return KMDW_STATUS_OK; + +} + +#define TILE_BLOCK_MAX_W 10 +#define TILE_BLOCK_MAX_H 6 +#define TILE_BLOCKS_MAX (TILE_BLOCK_MAX_W * TILE_BLOCK_MAX_H) // + + +static kmdw_status_t kdp_uvc_buffer_init(uint32_t cam_idx, uint32_t buf_addr_0, uint32_t buf_addr_1) +{ + struct uvc_device *udev = uvc_video_device; + uint32_t sizeImage = udev->curr_stream->cur_format->bpp * udev->curr_stream->cur_format->cur_frame->wWidth * udev->curr_stream->cur_format->cur_frame->wHeight; + + if (0 != udev->curr_stream->frame_buf) + return KMDW_STATUS_OK; + if (0 == isoch_pipe) + isoch_pipe = USBH_UVC_PipeCreate_Isoch(0, udev->curr_stream->if_alt[udev->curr_stream->curr_altnum-1].addr, + udev->curr_stream->if_alt[udev->curr_stream->curr_altnum-1].maxpacketsize, + udev->curr_stream->if_alt[udev->curr_stream->curr_altnum-1].interval); + + udev->curr_stream->isoch_pipe = isoch_pipe; + + if (0 == udev->curr_stream->isoch_pipe) + return KMDW_STATUS_ERROR; + + udev->curr_stream->frame_buf = buf_addr_0; + + ping_pong_buf_addr[0] = buf_addr_0; + ping_pong_buf_addr[1] = buf_addr_1; + + return KMDW_STATUS_OK; +} + +static kmdw_status_t kdp_uvc_get_format(uint32_t cam_idx, struct cam_format *p) +{ + struct uvc_device *udev = uvc_video_device; + struct uvc_frame *frame; + struct uvc_format *format; + + format = udev->curr_stream->cur_format; + frame = udev->curr_stream->cur_format->cur_frame; + + if (format == NULL || frame == NULL) { + return KMDW_STATUS_ERROR; + } + + p->pixelformat = format->fcc; + p->width = frame->wWidth; + p->height = frame->wHeight; + p->bytesperline = uvc_k_get_bytesperline(format, frame); + p->sizeimage = udev->stream->vs_ctrl_info->curr->dwMaxVideoFrameSize; + p->colorspace = format->colorspace; + return KMDW_STATUS_OK; +} + +static int uvc_try_format(struct uvc_streaming *stream, + struct cam_format *cam_fmt, struct uvc_format **uvc_format, + struct uvc_frame **uvc_frame) +{ + struct uvc_format *format = NULL; + struct uvc_frame *frame = NULL; + uint16_t rw, rh; + unsigned int d, maxd; + unsigned int i; + uint32_t interval; + int ret = 0; + + for (i = 0; i < stream->nformats; ++i) { + format = &stream->format[i]; + if (format->fcc == cam_fmt->pixelformat) + break; + } + if (i == stream->nformats) { + format = stream->cur_format; + cam_fmt->pixelformat = format->fcc; + } + + rw = cam_fmt->width; + rh = cam_fmt->height; + maxd = (unsigned int)-1; + + for (i = 0; i < format->nframes; ++i) { + uint16_t w = format->frame[i].wWidth; + uint16_t h = format->frame[i].wHeight; + + d = MIN(w, rw) * MIN(h, rh); + d = w*h + rw*rh - 2*d; + if (d < maxd) { + maxd = d; + frame = &format->frame[i]; + } + if (maxd == 0) + break; + } + if (NULL == frame) { + return -1; + } + + interval = frame->dwDefaultFrameInterval; + stream->vs_ctrl_info->curr->wmHint = 1; /* dwFrameInterval */ + stream->vs_ctrl_info->curr->bFormatIndex = format->index; + stream->vs_ctrl_info->curr->bFrameIndex = frame->bFrameIndex; + stream->vs_ctrl_info->curr->dwFrameInterval = uvc_try_frame_interval(frame, interval); + cam_fmt->width = frame->wWidth; + cam_fmt->height = frame->wHeight; + cam_fmt->bytesperline = uvc_k_get_bytesperline(format, frame); + cam_fmt->sizeimage = format->bpp * frame->wWidth * frame->wHeight; + cam_fmt->colorspace = format->colorspace; + stream->imagesize = format->bpp * frame->wWidth * frame->wHeight; + if (uvc_format != NULL) + *uvc_format = format; + if (uvc_frame != NULL) + *uvc_frame = frame; + + return ret; +} + +static kmdw_status_t kdp_uvc_set_format(uint32_t cam_idx, struct cam_format *p) +{ + struct uvc_device *udev = uvc_video_device; + + struct uvc_format *format; + struct uvc_frame *frame; + + if (0 > uvc_try_format(udev->curr_stream, p, &format, &frame)) + return KMDW_STATUS_ERROR; + + udev->curr_stream->cur_format = format; + udev->curr_stream->cur_format->cur_frame = frame; + + return KMDW_STATUS_OK; +} + +static kmdw_status_t kdp_uvc_query_capability(uint32_t cam_idx, struct cam_capability *cap) +{ + strncpy((char *)cap->driver, "KDP UVC", sizeof(cap->driver)); + + strncpy(cap->desc, KDP_UVC_DRIVER_DESC, sizeof(cap->desc)); + cap->version = KDP_UVC_DRIVER; + cap->capabilities = V2K_CAP_VIDEO_CAPTURE | V2K_CAP_STREAMING | V2K_CAP_DEVICE_CAPS; + + return KMDW_STATUS_OK; +} + + +static kmdw_status_t kdp_uvc_close(uint32_t cam_idx) +{ + struct uvc_device *udev; + if (NULL == (udev = video_dev("video0"))) + return KMDW_STATUS_ERROR; + kdp_uvc_stream_off(cam_idx); + udev->opened = false; + return KMDW_STATUS_OK; +} + +static kmdw_status_t kdp_uvc_open (uint32_t cam_idx) +{ + struct uvc_device *udev; + if (NULL == (udev = video_dev("video0"))) + return KMDW_STATUS_ERROR; + if (udev->inited == false) { + if (KMDW_STATUS_ERROR == kdp_uvc_buffer_init(cam_idx, NULL, NULL)) + return KMDW_STATUS_ERROR; + } + udev->opened = true; + return KMDW_STATUS_OK; +} + +static struct cam_ops kdp_uvc_ops = { + .open = kdp_uvc_open, + .close = kdp_uvc_close, + .query_capability = kdp_uvc_query_capability, + .set_format = kdp_uvc_set_format, + .get_format = kdp_uvc_get_format, + .buffer_init = kdp_uvc_buffer_init, + .start_capture = kdp_uvc_start_capture, + .stop_capture = kdp_uvc_stop_capture, + .stream_on = kdp_uvc_stream_on, + .stream_off = kdp_uvc_stream_off, + .ioctl = kdp_uvc_ioctl, + +}; + + +int uvc_parse_vs_data_ep(struct uvc_streaming *stream, uint8_t *p_data) +{ + + struct usb_interface_descriptor *vs_inf; + struct usb_endpoint_descriptor *ep; + uint16_t off = 0; + int i = 0; + vs_inf = (struct usb_interface_descriptor *)(p_data + off); + stream->ifnum = vs_inf->bInterfaceNumber; + stream->num_ep = vs_inf->bNumEndpoints; + stream->num_alt = 0; + + while (vs_inf->bInterfaceNumber == stream->ifnum) { + if (vs_inf->bDescriptorType != USB_DT_INTERFACE) + return -1; + if (vs_inf->bInterfaceClass != UVC_CC_VIDEO) + return -1; + if (vs_inf->bInterfaceSubClass != UVC_SC_VIDEOSTREAMING) + return -1; + stream->num_alt++; + off += vs_inf->bLength; + ep = (struct usb_endpoint_descriptor*) (p_data + off); + off += ep->bLength; + vs_inf = (struct usb_interface_descriptor *)(p_data + off); + } + stream->if_alt = (struct uvc_vs_alt_intf*)malloc(stream->num_alt * sizeof (struct uvc_vs_alt_intf)); + if (NULL == stream->if_alt) + return -1; +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ stream->if_alt %p\n", stream->if_alt); +#endif + memset(stream->if_alt, 0, stream->num_alt * sizeof (struct uvc_vs_alt_intf)); + off = 0; + vs_inf = (struct usb_interface_descriptor *)(p_data + off); + while (vs_inf->bInterfaceNumber == stream->ifnum) { + off += vs_inf->bLength; + ep = (struct usb_endpoint_descriptor*) (p_data + off); + off += ep->bLength; + + stream->if_alt[i].addr = ep->bEndpointAddress; + stream->if_alt[i].ep_type = ep->bmAttributes; + stream->if_alt[i].maxpacketsize = ep->wMaxPacketSize; + stream->if_alt[i].alt_num = vs_inf->bAlternateSetting; + stream->if_alt[i++].interval = ep->bInterval; + vs_inf = (struct usb_interface_descriptor *)(p_data + off); + } + stream->curr_altnum = 1; + return off; +} +static int uvc_parse_still_image(struct uvc_streaming *stream, uint8_t *p_data) +{ + struct uvc_still_image_frame_descriptor *still_image_frame = (struct uvc_still_image_frame_descriptor *)p_data; + if (still_image_frame->bDescriptorType != CS_INTERFACE) + return -1; + if (still_image_frame->bDescriptorSubType != UVC_VS_STILL_IMAGE_FRAME) + return 0; + + return still_image_frame->bLength; +} +static int uvc_parse_color_match(struct uvc_streaming *stream, uint8_t *p_data) +{ + + struct uvc_color_matching_descriptor *color_match = (struct uvc_color_matching_descriptor *)p_data; + + if (color_match->bDescriptorType != CS_INTERFACE) + return -1; + if (color_match->bDescriptorSubType != UVC_VS_COLORFORMAT) + return 0; + return color_match->bLength; +} + + +static int uvc_parse_vs_frame(struct uvc_frame *frame, uint8_t *p_data, uint8_t type) +{ + struct uvc_frame_uncompressed *frame_uncomp; + + if (type == UVC_VS_FORMAT_UNCOMPRESSED ) { + frame_uncomp = (struct uvc_frame_uncompressed *)p_data; + frame->bDescriptorType = frame_uncomp->bDescriptorSubType; + frame->bFrameIndex = frame_uncomp->bFrameIndex; + frame->bmCapabilities = frame_uncomp->bmCapabilities; + frame->wWidth = frame_uncomp->wWidth; + frame->wHeight = frame_uncomp->wHeight; + frame->dwMinBitRate = frame_uncomp->dwMinBitRate; + frame->dwMaxBitRate = frame_uncomp->dwMaxBitRate; + frame->dwMaxVideoFrameBufferSize = frame_uncomp->dwMaxVideoFrameBufferSize; + frame->dwDefaultFrameInterval = frame_uncomp->dwDefaultFrameInterval; + frame->bFrameIntervalType = frame_uncomp->bFrameIntervalType; + if (frame->bFrameIntervalType == 0) { + frame->dwFrameInterval = (uint32_t*)malloc(sizeof (struct cont_frame_intervals)); + memset(frame->dwFrameInterval, 0, sizeof (struct cont_frame_intervals)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ frame->dwFrameInterval %p\n", frame->dwFrameInterval); +#endif + ((struct cont_frame_intervals*)frame->dwFrameInterval)->dwMinFrameInterval = frame_uncomp->dwFrameInterval[0]; + ((struct cont_frame_intervals*)frame->dwFrameInterval)->dwMaxFrameInterval = frame_uncomp->dwFrameInterval[1]; + ((struct cont_frame_intervals*)frame->dwFrameInterval)->dwFrameIntervalStep = frame_uncomp->dwFrameInterval[2]; + } else { + frame->dwFrameInterval = (uint32_t *)malloc(frame->bFrameIntervalType * sizeof (uint32_t)); + if (NULL == frame->dwFrameInterval) + return -1; +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ frame->dwFrameInterval %p\n", frame->dwFrameInterval); +#endif + memset(frame->dwFrameInterval, 0, frame->bFrameIntervalType * sizeof (uint32_t)); + uint32_t *p = (uint32_t*) frame->dwFrameInterval; + for ( int j = 0; j < frame->bFrameIntervalType; j++) { + p[j] = frame_uncomp->dwFrameInterval[j]; + } + } + } + return 0; +} + +static int32_t uvc_parse_vs_format(struct uvc_format *format, uint8_t *p_data) +{ + struct uvc_format_desc_head *format_h = (struct uvc_format_desc_head *) p_data; + uint16_t off = 0; + struct uvc_frame_desc_head *frame_h; + + if (format_h->bDescriptorType != CS_INTERFACE) + return -1; + + if (format_h->bDescriptorSubtype == UVC_VS_FORMAT_MJPEG) { + struct uvc_format_mjpeg *f_mjpeg = (struct uvc_format_mjpeg *)p_data; + + off += f_mjpeg->bLength; + format->nframes = f_mjpeg->bNumFrameDescriptors; + format->type = UVC_VS_FORMAT_MJPEG; + } else if (format_h->bDescriptorSubtype == UVC_VS_FORMAT_UNCOMPRESSED) { + struct uvc_format_uncompressed *f_uncomp = (struct uvc_format_uncompressed *)p_data; + off += f_uncomp->bLength; + format->nframes = f_uncomp->bNumFrameDescriptors; + format->type = UVC_VS_FORMAT_UNCOMPRESSED; + format->fcc = V2K_PIX_FMT_YCBCR; + format->bpp = f_uncomp->bBitsPerPixel >>3; + format->index = f_uncomp->bFormatIndex; + + } else if (format_h->bDescriptorSubtype == UVC_VS_FORMAT_FRAME_BASED) { + struct uvc_format_frame_based *f_frame_based = (struct uvc_format_frame_based *)p_data; + off += f_frame_based->bLength; + format->nframes = f_frame_based->bNumFrameDescriptors; + format->type = UVC_VS_FORMAT_FRAME_BASED; + } + format->frame = (struct uvc_frame *) malloc(format->nframes * sizeof( struct uvc_frame)); + if (NULL == format->frame) + return -1; + memset(format->frame, 0, format->nframes * sizeof( struct uvc_frame)); + +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ format->frame %p\n", format->frame); +#endif + for (int i = 0; i < format->nframes; i++) { + frame_h = (struct uvc_frame_desc_head*) (p_data + off); + uvc_parse_vs_frame(&format->frame[i], p_data + off, format->type); + if (format->frame[i].bDescriptorType == UVC_VS_FRAME_UNCOMPRESSED) + format->cur_frame_num = 0; + off += frame_h->bLength; + } + format->cur_frame = &format->frame[format->cur_frame_num]; + return off; +} + + +int uvc_parse_vs_inf(struct uvc_streaming *stream, const uint8_t *buffer) +{ + int ret; + uint32_t off = 0; + struct usb_interface_descriptor *p_inf = (struct usb_interface_descriptor * )buffer; + struct uvc_input_header_descriptor *in_head; + off += p_inf->bLength; + + if (p_inf->bDescriptorType != USB_DT_INTERFACE) + return -1; + if (p_inf->bInterfaceClass != UVC_CC_VIDEO) + return -1; + if (p_inf->bInterfaceSubClass != UVC_SC_VIDEOSTREAMING) + return -1; + + stream->ifnum = p_inf->bInterfaceNumber; + + in_head = (struct uvc_input_header_descriptor *) &buffer[off]; + + if (in_head->bDescriptorType != CS_INTERFACE) + return -1; + if (in_head->bDescriptorSubType != UVC_VS_INPUT_HEADER) + return -1; + stream->nformats = in_head->bNumFormats; + stream->ep_addr = in_head->bEndpointAddress; + stream->TerminalId = in_head->bTerminalLink; + stream->ControlSize = in_head->bControlSize; + stream->cur_format_num = -1; + off += in_head->bLength; + + stream->format = ( struct uvc_format *)malloc( in_head->bNumFormats * sizeof( struct uvc_format )); + if (NULL == stream->format) + return -1; + memset(stream->format, 0, in_head->bNumFormats * sizeof( struct uvc_format )); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ stream->nformats %x\n", stream->nformats); + kmdw_printf("@@ stream->format %p\n", stream->format); +#endif + for (int i = 0; i < in_head->bNumFormats; i++) { + + off += uvc_parse_vs_format(&(stream->format[i]), (uint8_t *)&buffer[off]); + if (stream->format[i].type == UVC_VS_FORMAT_UNCOMPRESSED) { + if (0 > stream->cur_format_num) + stream->cur_format_num = i; + } + else + stream->cur_format_num = 0; + if (0 > (ret = uvc_parse_still_image(stream, (uint8_t *)&buffer[off]))) + return ret; + off += ret; + if (0 > (ret = uvc_parse_color_match(stream, (uint8_t *)&buffer[off]))) + return ret; + off += ret; + } + + stream->cur_format =(struct uvc_format *) &(stream->format[stream->cur_format_num]); + + return off; +} + +static int uvc_parse_vc_int_ep(struct uvc_device *dev, + const uint8_t *buffer) +{ + uint32_t off = 0; + struct usb_endpoint_descriptor *ep = (struct usb_endpoint_descriptor *) buffer; + struct uvc_control_endpoint_descriptor *vc_int_ep; + + if (ep->bDescriptorType != USB_DT_ENDPOINT) + return -1; + if (ep->bmAttributes != USB_ENDPOINT_XFER_INT) + return -1; + dev->int_ep = (struct uvc_vc_int_ep *)malloc(sizeof( struct uvc_vc_int_ep)); + if (NULL == dev->int_ep ) + return -1; + memset(dev->int_ep, 0, sizeof( struct uvc_vc_int_ep)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->int_ep %p\n", dev->int_ep); +#endif + dev->int_ep->addr= ep->bEndpointAddress; + dev->int_ep->interval = ep->bInterval; + dev->int_ep->maxpacketsize = ep->wMaxPacketSize; + off += ep->bLength; + vc_int_ep = (struct uvc_control_endpoint_descriptor *)(buffer + off); + if (vc_int_ep->bDescriptorType != CS_ENDPOINT) + return -1; + if (vc_int_ep->bDescriptorSubType != USB_ENDPOINT_XFER_INT) + return -1; + dev->int_ep->wMaxTransferSize = vc_int_ep->wMaxTransferSize; + off += vc_int_ep->bLength; + + return off; +} + +static int uvc_parse_ET(struct uvc_device *dev, + const uint8_t *buffer, int buflen) +{ + + struct uvc_ET_Head_descriptor *et_head = (struct uvc_ET_Head_descriptor *)buffer; + + uint32_t off = 0; + uint16_t buf_len_t = buflen; + uint8_t* buf_t = (uint8_t * )buffer; + + while (buf_len_t) { + if (et_head->bDescriptorSubType == UVC_VC_INPUT_TERMINAL) { + + struct uvc_input_terminal_descriptor *IT = (struct uvc_input_terminal_descriptor *)(buf_t + off); + buf_len_t -= IT->bLength; + off += IT->bLength; + dev->nITs++; + } + if (et_head->bDescriptorSubType == UVC_VC_OUTPUT_TERMINAL) { + + struct uvc_output_terminal_descriptor *OT = (struct uvc_output_terminal_descriptor *) (buf_t + off); + buf_len_t -= OT->bLength; + off += OT->bLength; + dev->nOTs++; + } + if (et_head->bDescriptorSubType == UVC_VC_SELECTOR_UNIT) { + + struct uvc_selector_unit_descriptor *SU = (struct uvc_selector_unit_descriptor *) (buf_t + off); + buf_len_t -= SU->bLength; + off += SU->bLength; + dev->nSUs++; + } + if (et_head->bDescriptorSubType == UVC_VC_PROCESSING_UNIT) { + + struct uvc_processing_unit_descriptor *PU = (struct uvc_processing_unit_descriptor *) (buf_t + off); + buf_len_t -= PU->bLength; + off += PU->bLength; + dev->nPUs++; + } + + if (et_head->bDescriptorSubType == UVC_VC_EXTENSION_UNIT) { + + struct uvc_extension_unit_descriptor *XU = (struct uvc_extension_unit_descriptor *) (buf_t + off); + + buf_len_t -= XU->bLength; + off += XU->bLength; + dev->nXUs++; + } + + et_head = (struct uvc_ET_Head_descriptor *)((uint8_t*) buf_t + off); + + } + + if (dev->nITs != 0) { + dev->IT = (struct uvc_it *) malloc(dev->nITs * sizeof(struct uvc_it)); + if (NULL == dev->IT ) + return -ENOMEM; + memset(dev->IT, 0, dev->nITs * sizeof (struct uvc_it)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->IT %p\n", dev->IT); + kmdw_printf("@@ dev->IT size %x\n", dev->nITs * sizeof(struct uvc_it)); +#endif + } + if (dev->nOTs != 0) { + dev->OT = (struct uvc_ot *) malloc(dev->nOTs * sizeof(struct uvc_ot)); + if (NULL == dev->OT) + return -ENOMEM; + memset(dev->OT, 0, dev->nOTs * sizeof (struct uvc_ot)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->OT %p\n", dev->OT); + kmdw_printf("@@ dev->OT size %x\n", dev->nOTs * sizeof(struct uvc_ot)); +#endif + } + if (dev->nSUs != 0) { + dev->SU = (struct uvc_su *) malloc(dev->nSUs * sizeof(struct uvc_su)); + if (NULL == dev->SU) + return -ENOMEM; + memset(dev->SU, 0, dev->nSUs * sizeof (struct uvc_su)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->SU %p\n", dev->SU); + kmdw_printf("@@ dev->SU size %x\n", dev->nSUs * sizeof(struct uvc_ot)); +#endif + } + if (dev->nPUs != 0) { + dev->PU = (struct uvc_pu *) malloc(dev->nPUs * sizeof(struct uvc_pu)); + if (NULL == dev->PU) + return -ENOMEM; + memset(dev->PU, 0, dev->nPUs * sizeof (struct uvc_pu)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->PU %p\n", dev->PU); + kmdw_printf("@@ dev->PU size %x\n", dev->nPUs * sizeof(struct uvc_pu)); +#endif + } + + if (dev->nXUs != 0) { + dev->XU = (struct uvc_xu *) malloc(dev->nXUs * sizeof(struct uvc_xu)); + if (NULL == dev->XU) + return -ENOMEM; + memset(dev->XU, 0, dev->nXUs * sizeof (struct uvc_xu)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->XU %p\n", dev->XU); + kmdw_printf("@@ dev->XU size %x\n", dev->nXUs * sizeof(struct uvc_xu)); +#endif + } + + buf_len_t = buflen; + buf_t = (uint8_t * )buffer; + et_head = (struct uvc_ET_Head_descriptor *) buffer; + off = 0; + uint8_t c = 0, o = 0, s = 0, p = 0, x = 0; + + while (buf_len_t) { + if (et_head->bDescriptorSubType == UVC_VC_INPUT_TERMINAL) { + + struct uvc_input_terminal_descriptor *IT = (struct uvc_input_terminal_descriptor *)(buf_t + off); + buf_len_t -= IT->bLength; + off += IT->bLength; + dev->IT[c].id = IT->bTerminalID; + dev->IT[c].wTerminalType = IT->wTerminalType; + if (IT->wTerminalType == UVC_ITT_CAMERA) { + + struct uvc_camera_terminal_descriptor* CT = (struct uvc_camera_terminal_descriptor *) IT; + dev->IT[c].ct = (struct uvc_ct*)malloc(sizeof (struct uvc_ct)); + if (NULL == dev->IT[c].ct) + return -ENOMEM; + memset(dev->IT[c].ct, 0, sizeof (struct uvc_ct)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->IT[c].ct %p\n", dev->IT[c].ct); +#endif + dev->IT[c].ct->wObjectiveFocalLengthMax = CT->wObjectiveFocalLengthMax; + dev->IT[c].ct->wObjectiveFocalLengthMin = CT->wObjectiveFocalLengthMin; + dev->IT[c].ct->wOcularFocalLength = CT->wOcularFocalLength; + for (int j = 0; j < CT->bControlSize; j++) + dev->IT[c].ct->bmControls |= (uint8_t )((uint8_t *)CT+ UVC_DT_CT_CONST_LEN)[j] << j*8 ; + + } + c++; + } + if (et_head->bDescriptorSubType == UVC_VC_OUTPUT_TERMINAL) { + + struct uvc_output_terminal_descriptor * OT = (struct uvc_output_terminal_descriptor *) (buf_t + off); + buf_len_t -= OT->bLength; + off += OT->bLength; + + dev->OT[o].id = OT->bTerminalID; + dev->OT[o].bAssocTerminal= OT->bAssocTerminal; + dev->OT[o].wTerminalType = OT->wTerminalType; + dev->OT[o++].baSourceID = OT->bSourceID; + } + + if (et_head->bDescriptorSubType == UVC_VC_SELECTOR_UNIT) { + + struct uvc_selector_unit_descriptor *SU = (struct uvc_selector_unit_descriptor *) (buf_t + off); + buf_len_t -= SU->bLength; + off += SU->bLength; + dev->SU[s].id = SU->bUnitID; + dev->SU[s].bNrInPins = SU->bNrInPins; + dev->SU[s].baSourceID = (uint8_t *)malloc(dev->SU[s].bNrInPins); + if (NULL == dev->SU[s].baSourceID) + return -ENOMEM; + memset(dev->SU[s].baSourceID, 0, dev->SU[s].bNrInPins); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->SU[s].baSourceID %p\n", dev->SU[s].baSourceID); +#endif + for (int j =0 ; j < dev->SU[s].bNrInPins; j++) + dev->SU[s].baSourceID[j] = (uint8_t )((uint8_t *)SU + UVC_SU_CONST_LEN)[j]; + s++; + } + if (et_head->bDescriptorSubType == UVC_VC_PROCESSING_UNIT) { + + struct uvc_processing_unit_descriptor *PU = (struct uvc_processing_unit_descriptor *) (buf_t + off); + int j; + buf_len_t -= PU->bLength; + off += PU->bLength; + dev->PU[p].id = PU->bUnitID; + dev->PU[p].baSourceID = PU->bSourceID; + for (j = 0 ; j < PU->bControlSize; j++) + dev->PU[p].bmControls |= (uint8_t )((uint8_t *)PU + UVC_PU_CONST_LEN)[j] << j*8; + + dev->PU[p++].bmVideoStandards = (uint8_t )((uint8_t *)PU + UVC_PU_CONST_LEN)[++j]; + + } + + if (et_head->bDescriptorSubType == UVC_VC_EXTENSION_UNIT) { + + struct uvc_extension_unit_descriptor *XU = (struct uvc_extension_unit_descriptor *) (buf_t + off); + uint8_t controlsize = 0; + int j = 0; + buf_len_t -= XU->bLength; + off += XU->bLength; + dev->XU[x].id = XU->bUnitID; + dev->XU[x].bNumControls = XU->bNumControls; + dev->XU[x].bNrInPins = XU->bNrInPins; + dev->XU[x].baSourceID = (uint8_t *)malloc(dev->XU[x].bNrInPins); + if (NULL == dev->XU[x].baSourceID) + return -ENOMEM; + memset(dev->XU[x].baSourceID, 0, dev->XU[x].bNrInPins); + +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->XU[x].baSourceID %p\n", dev->XU[x].baSourceID); +#endif + for (j = 0 ; j < dev->XU[x].bNrInPins; j++) + dev->XU[x].baSourceID[j] = (uint8_t )((uint8_t *)XU + UVC_XU_CONST_LEN)[j]; + controlsize = (uint8_t )((uint8_t *)XU + UVC_XU_CONST_LEN)[j++]; + + for (j = 0 ; j < controlsize; j++) + dev->XU[x].bmControls |= (uint8_t )((uint8_t *)XU + UVC_XU_CONST_LEN + dev->XU[x].bNrInPins + 1)[j] << j*8; + + x++; + } + + et_head = (struct uvc_ET_Head_descriptor *)((uint8_t*) buf_t + off); + // c = 0; o = 0; s = 0; p = 0; x = 0; + } + + return 0; +} + +static int uvc_parse_vs(struct uvc_device *dev, uint8_t *buffer) +{ + int ret; + uint32_t off = 0; + + dev->stream = (struct uvc_streaming *) malloc(dev->num_vs_inf * sizeof (struct uvc_streaming)); + + if (NULL == dev->stream) + return -1; +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->stream %p\n", dev->stream); +#endif + memset(dev->stream, 0, dev->num_vs_inf * sizeof (struct uvc_streaming)); + for (int i = 0; i < dev->num_vs_inf; i++) { + + dev->stream[i].frame_buf = 0; + dev->stream[i].running = false; + if (0 > (ret = uvc_parse_vs_inf(&dev->stream[i], &buffer[off]))) + return ret; + off += ret; + + off += uvc_parse_vs_data_ep(&dev->stream[i], &buffer[off]); + dev->stream[i].vs_ctrl_info = (struct ctrl_vs_info *)malloc(sizeof (struct ctrl_vs_info)); + if (NULL == dev->stream[i].vs_ctrl_info) + return -ENOMEM; + memset(dev->stream[i].vs_ctrl_info, 0, sizeof (struct ctrl_vs_info)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->stream[i].vs_ctrl_info %p\n", dev->stream[i].vs_ctrl_info); +#endif + dev->stream[i].vs_ctrl_info->def = (struct uvc_streaming_control_data*) malloc(sizeof (struct uvc_streaming_control_data)); + if (NULL == dev->stream[i].vs_ctrl_info->def) + return -ENOMEM; + memset(dev->stream[i].vs_ctrl_info->def, 0, sizeof (struct uvc_streaming_control_data)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->stream[i].vs_ctrl_info->def %p\n", dev->stream[i].vs_ctrl_info->def); +#endif + dev->stream[i].vs_ctrl_info->curr = (struct uvc_streaming_control_data*) malloc(sizeof (struct uvc_streaming_control_data)); + if (NULL == dev->stream[i].vs_ctrl_info->curr) + return -ENOMEM; + memset(dev->stream[i].vs_ctrl_info->curr, 0, sizeof (struct uvc_streaming_control_data)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->stream[i].vs_ctrl_info->curr %p\n", dev->stream[i].vs_ctrl_info->curr); +#endif + dev->stream[i].vs_ctrl_info->minimum = (struct uvc_streaming_control_data*) malloc(sizeof (struct uvc_streaming_control_data)); + if (NULL == dev->stream[i].vs_ctrl_info->minimum) + return -ENOMEM; + memset(dev->stream[i].vs_ctrl_info->minimum, 0, sizeof (struct uvc_streaming_control_data)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->stream[i].vs_ctrl_info->minimum %p\n", dev->stream[i].vs_ctrl_info->minimum); +#endif + dev->stream[i].vs_ctrl_info->maximum = (struct uvc_streaming_control_data*) malloc(sizeof (struct uvc_streaming_control_data)); + if (NULL == dev->stream[i].vs_ctrl_info->maximum) + return -ENOMEM; + memset(dev->stream[i].vs_ctrl_info->maximum, 0, sizeof (struct uvc_streaming_control_data)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->stream[i].vs_ctrl_info->maximum %p\n", dev->stream[i].vs_ctrl_info->maximum); +#endif + dev->stream[i].vs_ctrl_info->res = (struct uvc_streaming_control_data*) malloc(sizeof (struct uvc_streaming_control_data)); + if (NULL == dev->stream[i].vs_ctrl_info->res) + return -ENOMEM; + memset(dev->stream[i].vs_ctrl_info->res, 0, sizeof (struct uvc_streaming_control_data)); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ dev->stream[i].vs_ctrl_info->res %p\n", dev->stream[i].vs_ctrl_info->res); +#endif + } + + dev->curr_stream = &dev->stream[0]; + + return ret; +} + +static int uvc_parse_vc(struct uvc_device *dev, uint8_t *buffer) +{ + struct usb_interface_descriptor *p_inf = (struct usb_interface_descriptor * )buffer; + struct uvc_vc_if_header_descriptor *c_inf; + uint32_t len_ET; + uint32_t off = 0; + int ret; + + if (p_inf->bInterfaceClass != UVC_CC_VIDEO) + return -1; + if (p_inf->bInterfaceSubClass != UVC_SC_VIDEOCONTROL) + return -1; + off += p_inf->bLength; + + dev->vc_inf = p_inf->bInterfaceNumber; + c_inf = (struct uvc_vc_if_header_descriptor *)&buffer[off]; + len_ET = c_inf->wTotalLength - c_inf->bLength; + dev->num_vs_inf = c_inf->bInCollection; + dev->uvc_version = c_inf->bcdUVC; + dev->clock_frequency = c_inf->dwClockFrequency; + off += c_inf->bLength; + + if (0 > (ret = uvc_parse_ET(dev, &buffer[off], len_ET))) + return ret; + off += len_ET; + if (0 > (ret = uvc_parse_vc_int_ep(dev, &buffer[off]))) + return ret; + off += ret; + + return off; +} + +static int kdp_uvc_parse_config(uint8_t *buf) +{ + struct usb_config_descriptor *conf = (struct usb_config_descriptor *)buf; + struct uvc_device *uvc_dev = uvc_video_device; + int32_t off = 0; + uint8_t num_inf; + int ret; + struct uvc_inf_assoc_descriptor *iad; + + off += conf->bLength; +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ buf = %p\n", buf); +#endif + iad = (struct uvc_inf_assoc_descriptor *)&buf[off]; + if (iad->bDescriptorType != 0xb) + return -1; + if (iad->bFunctionClass != UVC_CC_VIDEO) + return -1; + if (iad->bFunctionSubClass != UVC_SC_VIDEO_INTERFACE_COLLECTION) + return -1; + off += iad->bLength; +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ iad = %p\n", iad); +#endif + num_inf = iad->bInterfaceCount; + + // memset((void *) uvc_dev, 0, sizeof (struct uvc_device)); + uvc_dev->num_inf = num_inf; + + strncpy(uvc_dev->name, "video0", sizeof uvc_dev->name); + + if (0 > (ret = uvc_parse_vc(uvc_dev, &buf[off]))) { + + return -1; + } + off +=ret; + if (0 > (ret = uvc_parse_vs(uvc_dev, &buf[off]))) { + uvc_dev->inited = false; + return -1; + } + uvc_dev->inited = true; + return 0; +} + +static struct kdp_uvc_id uvc_ids[] = { + { + .idVendor = 0xc45, + .idProduct = 0x6366 + }, + { + .idVendor = 0x46d, + .idProduct = 0x85c + }, + { + .idVendor = 0x41e, + .idProduct = 0x4095 + }, + { + .idVendor = 0x45e, + .idProduct = 0x772 + }, + { + .idVendor = 0x58f, + .idProduct = 0x806 + }, + {} +}; + +struct kdp_uvc_id *usb_uvc_id_lookup(uint16_t idVendor, uint16_t idProduct) +{ + for (int i = 0; i < sizeof uvc_ids / sizeof (struct kdp_uvc_id); i++) + if ((uvc_ids[i].idVendor == idVendor) && (uvc_ids[i].idProduct == idProduct)) + return &uvc_ids[i]; +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ camera idVendor = 0x%x, idProduct = 0x%x is not in supported list\n", idVendor, idProduct); +#endif + return NULL; +} + +usbStatus USBH_UVC_Disconnected(void) +{ + struct uvc_device *uvc_dev = uvc_video_device; + + if (true == uvc_dev->curr_stream->running) { + USBH_UVC_PipeStop_Isoch(uvc_dev->curr_stream->isoch_pipe); + uvc_dev->curr_stream->running = false; + } + + isoch_pipe = 0; + if (NULL == uvc_dev) + return usbOK; + if (true == uvc_dev->opened) + kdp_uvc_close(0); + if (false == uvc_dev->inited) + return usbOK; + if (NULL != uvc_dev->IT) { + for (int i = 0 ; i < uvc_dev->nITs; i++) { + if (NULL != uvc_dev->IT[i].ct) { + for (int j = 0; j < CT_CTRL_NUM; j++) { + if (NULL != uvc_dev->IT[i].ct->data) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->IT[i].ct->data %p\n", uvc_dev->IT[i].ct->data); +#endif + if (uvc_dev->IT[i].ct->data[j].para != NULL) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ j = 0x%x\n", j); + kmdw_printf("@@ uvc_dev->IT[i].ct->data[j].para %p\n", uvc_dev->IT[i].ct->data[j].para); +#endif + free(uvc_dev->IT[i].ct->data[j].para); + } + free(uvc_dev->IT[i].ct->data); + } + } + +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->IT[i].ct %p\n", uvc_dev->IT[i].ct); +#endif + free(uvc_dev->IT[i].ct); + } + } +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->IT5 %p\n", uvc_dev->IT); +#endif + free(uvc_dev->IT); + } + if (NULL != uvc_dev->OT) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->OT %p\n", uvc_dev->OT); +#endif + free(uvc_dev->OT); + } + if (NULL != uvc_dev->PU) { + for (int i = 0 ; i < uvc_dev->nPUs; i++) { + if (NULL != uvc_dev->PU[i].data) { + for (int j = 0; j < PU_CTRL_NUM; j++) { + + if (uvc_dev->PU[i].data[j].para != NULL) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->PU[i].data[j].para %p\n", uvc_dev->PU[i].data[j].para); +#endif + free(uvc_dev->PU[i].data[j].para); + } + } +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->PU[i].data %p\n", uvc_dev->PU[i].data); +#endif + free(uvc_dev->PU[i].data); + } + + } +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->PU %p\n", uvc_dev->PU); +#endif + free(uvc_dev->PU); + } + if (NULL != uvc_dev->XU) { + for (int i = 0 ; i < uvc_dev->nXUs; i++) { + if (uvc_dev->XU[i].baSourceID != NULL) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->XU[i].baSourceID %p\n", uvc_dev->XU[i].baSourceID); +#endif + free(uvc_dev->XU[i].baSourceID); + } + } +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->XU %p\n", uvc_dev->XU); +#endif + free(uvc_dev->XU); + } + if (NULL != uvc_dev->SU) { + for (int i = 0; i < uvc_dev->nSUs; i++) + if (uvc_dev->SU[i].baSourceID != 0) + free(uvc_dev->SU[i].baSourceID); + free(uvc_dev->SU); + } + for (int i = 0; i < uvc_dev->num_vs_inf; i++) { + if (NULL != uvc_dev->stream[i].vs_ctrl_info->curr) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].vs_ctrl_info->curr %p\n", uvc_dev->stream[i].vs_ctrl_info->curr); +#endif + free(uvc_dev->stream[i].vs_ctrl_info->curr); + } + if (NULL != uvc_dev->stream[i].vs_ctrl_info->def) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].vs_ctrl_info->def %p\n", uvc_dev->stream[i].vs_ctrl_info->def); +#endif + free(uvc_dev->stream[i].vs_ctrl_info->def); + } + if (NULL != uvc_dev->stream[i].vs_ctrl_info->minimum) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].vs_ctrl_info->minimum %p\n", uvc_dev->stream[i].vs_ctrl_info->minimum); +#endif + free(uvc_dev->stream[i].vs_ctrl_info->minimum); + } + if (NULL != uvc_dev->stream[i].vs_ctrl_info->maximum) + { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].vs_ctrl_info->maximum %p\n", uvc_dev->stream[i].vs_ctrl_info->maximum); +#endif + free(uvc_dev->stream[i].vs_ctrl_info->maximum); + } + if (NULL != uvc_dev->stream[i].vs_ctrl_info->res) + { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].vs_ctrl_info->res %p\n", uvc_dev->stream[i].vs_ctrl_info->res); +#endif + free(uvc_dev->stream[i].vs_ctrl_info->res); + } + if (NULL != uvc_dev->stream[i].vs_ctrl_info) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].vs_ctrl_info %p\n", uvc_dev->stream[i].vs_ctrl_info); +#endif + free(uvc_dev->stream[i].vs_ctrl_info); + } + if (NULL != uvc_dev->stream[i].if_alt) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].if_alt %p\n", uvc_dev->stream[i].if_alt); +#endif + free(uvc_dev->stream[i].if_alt); + } + for (int j = 0; j < uvc_dev->stream[i].nformats; j++) { + for (int k = 0; k < uvc_dev->stream[i].format[j].nframes; k++) { + if (NULL != uvc_dev->stream[i].format[j].frame[k].dwFrameInterval) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].format[j].frame[k].dwFrameInterval %p\n", uvc_dev->stream[i].format[j].frame[k].dwFrameInterval); +#endif + free(uvc_dev->stream[i].format[j].frame[k].dwFrameInterval); + } + } + if (NULL != uvc_dev->stream[i].format[j].frame) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].format[j].frame %p\n", uvc_dev->stream[i].format[j].frame); +#endif + free(uvc_dev->stream[i].format[j].frame); + } + } + if (NULL != uvc_dev->stream[i].format) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream[i].format %p\n", uvc_dev->stream[i].format); +#endif + free(uvc_dev->stream[i].format); + } + } + if (NULL != uvc_dev->stream) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->stream %p\n", uvc_dev->stream); +#endif + free(uvc_dev->stream); + } + if (NULL != uvc_dev->int_ep) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ free uvc_dev->int_ep %p\n", uvc_dev->int_ep); +#endif + free(uvc_dev->int_ep); + } + memset(uvc_dev, 0, sizeof (struct uvc_device)); + + // osThreadFlagsSet(tid_to_notify, FLAGS_YOLO_STOP_EVT); + osThreadFlagsSet(tid_to_notify, FLAGS_UVC_CAMERA_INIT_FAILED_EVT); +#ifdef KDP_UVC_DEBUG + kmdw_printf("%s: USBH_UVC_Disconnected() OK\n", __func__); +#endif + return usbOK; +} + +static int kdp_uvc_init(void) +{ + if (false == uvc_video_device->inited) + return -1; + if (0 > uvc_init_device_ctrl(uvc_video_device)) + return -1; + if (0 > uvc_video_init(uvc_video_device)) + return -1; + if (KMDW_STATUS_ERROR == kdp_uvc_buffer_init(KDP_CAM_0, NULL, NULL)) + return -1; + uvc_video_device->inited = true; + return 0; +} + +uint8_t USBH_UVC_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc) +{ + struct uvc_device *uvc_dev = uvc_video_device; + struct kdp_uvc_id *id = usb_uvc_id_lookup(ptr_dev_desc->idVendor, ptr_dev_desc->idProduct); + memset((void *) uvc_dev, 0, sizeof (struct uvc_device)); + uvc_dev->id = id; + kmdw_printf("vendor id is 0x%x, product ID is 0x%x\n", uvc_dev->id->idVendor, uvc_dev->id->idProduct); + return kdp_uvc_parse_config((uint8_t *)ptr_cfg_desc); +} + +usbStatus USBH_UVC_Initialize(uint8_t instance) +{ + + if (0 > kdp_uvc_init()) { + osThreadFlagsSet(tid_to_notify, FLAGS_UVC_CAMERA_INIT_FAILED_EVT); + while (1) {}; + } + + osThreadFlagsSet(tid_to_notify, FLAGS_UVC_CAMERA_INIT_DONE_EVT); + + return usbOK; +} + +void kmdw_cam_uvc_init(void) +{ + usbStatus usb_status; + + tid_to_notify = osThreadGetId(); + + kmdw_camera_controller_register(KDP_CAM_0, &kdp_uvc_ops); + + // init USB host through MDK middleware + usb_status = USBH_Initialize(0U); + + if (usb_status != usbOK) + kmdw_printf("%s: USBH_Initialize() failed %d\n", __func__, usb_status); + else + kmdw_printf("%s: USBH_Initialize() OK\n", __func__); +} diff --git a/mdw/kdp_usb_uvc/src/uvc_ctrl.c b/mdw/kdp_usb_uvc/src/uvc_ctrl.c new file mode 100644 index 0000000..47946b9 --- /dev/null +++ b/mdw/kdp_usb_uvc/src/uvc_ctrl.c @@ -0,0 +1,1020 @@ +/* + * uvc_ctrl.c + * + * Copyright (C) 2019 - 2020 Kneron, Inc. All rights reserved. + * + */ + +#include "errno.h" +#include "uvc_ctrl.h" +#include "uvc_video.h" +#include "uvc_utils.h" +#include "uvc_internal_api.h" +#include "kmdw_memory.h" +#include "kmdw_uvc.h" +#include "kmdw_console.h" +#include "uvc_camera.h" + +#ifdef KDP_UVC +#ifdef KDP_UVC_DEBUG +#define uvc_msg(fmt, ...) MSG(LOG_ERROR, "[%s] " fmt, __func__, ##__VA_ARGS__) +#else +#define uvc_msg(fmt, ...) +#endif + +struct uvc_req { + USB_SETUP_PACKET req; + uint8_t *data; +} vc_req = {0}; + +static int uvc_create_ctl_req(struct ctrl_info *ctrl, uint8_t inf_ep, uint8_t req_num) +{ + memset(&vc_req, 0, sizeof (struct uvc_req)); + if ((((ctrl->cid >> ET_POS) & 0xF) != UVC_DEV_INF) && + (((ctrl->cid >> ET_POS) & 0xF) != UVC_ET_PU) && + (((ctrl->cid >> ET_POS) & 0xF) != UVC_ET_EU) && + (((ctrl->cid >> ET_POS) & 0xF) != UVC_ET_XU) && + (((ctrl->cid >> ET_POS) & 0xF) != UVC_ET_CT)) + return -1; + if ((req_num == UVC_SET_CUR)||(req_num == UVC_SET_CUR_ALL)) { + vc_req.req.bmRequestType.Recipient = USB_REQUEST_TO_INTERFACE; + vc_req.req.bmRequestType.Dir = USB_REQUEST_HOST_TO_DEVICE; + vc_req.req.bmRequestType.Type = USB_REQUEST_CLASS; + } else if ((req_num == UVC_GET_CUR)||(req_num == UVC_GET_MIN) || + (req_num == UVC_GET_MAX)|| (req_num == UVC_GET_RES)|| + (req_num == UVC_GET_INFO)||(req_num == UVC_GET_DEF)|| + (req_num == UVC_GET_CUR_ALL)||(req_num == UVC_GET_MIN_ALL) || + (req_num == UVC_GET_MAX_ALL)||(req_num == UVC_GET_RES_ALL) || + (req_num == UVC_GET_DEF_ALL)) { + vc_req.req.bmRequestType.Recipient = USB_REQUEST_TO_INTERFACE; + vc_req.req.bmRequestType.Dir = USB_REQUEST_DEVICE_TO_HOST; + vc_req.req.bmRequestType.Type = USB_REQUEST_CLASS; + } else + return -1; + + if ((req_num == UVC_SET_CUR_ALL) || (req_num == UVC_GET_CUR_ALL) || + (req_num == UVC_GET_MAX_ALL) || (req_num == UVC_GET_DEF_ALL) || + (req_num == UVC_GET_RES_ALL)) { + vc_req.req.wIndex = ctrl->eid << 8; + vc_req.req.wValue = 0; + } else { + vc_req.req.wIndex = inf_ep | (ctrl->eid << 8); + vc_req.req.wValue = ctrl->cs << 8; + vc_req.req.wLength = ctrl->para_size; + if ((req_num == UVC_SET_CUR ) || (req_num == UVC_GET_CUR) || + (req_num == UVC_GET_MIN ) || (req_num == UVC_GET_MAX) || + (req_num == UVC_GET_RES )) + vc_req.data = &ctrl->para[(0xF & req_num)* ctrl->para_size]; + else if (req_num == UVC_GET_DEF) { + // kmdw_printf("@@ ctrl->para[0] %p\n", &ctrl->para[0]); + vc_req.data = &ctrl->para[0];} + else if (req_num == UVC_GET_LEN) { + vc_req.data = &ctrl->len; + vc_req.req.wLength = 1; + } else if (req_num == UVC_GET_INFO) { + vc_req.data = &ctrl->caps; + vc_req.req.wLength = 1; + } + } + vc_req.req.bRequest= req_num; + + return 0; +} + +static int uvc_query_ctrl(struct uvc_device *dev, int timeout) +{ + if (0 != USBH_ControlTransfer(0,&vc_req.req, (uint8_t *) vc_req.data, vc_req.req.wLength)) { + return -1; + } + return 0; +} + + +static struct ctrl_info *uvc_find_control(struct uvc_device *udev, uint32_t cid) +{ + if ((UVC_CID_DEVICE_POWER_MODE) == cid) { + + return udev->inf_ctl; + } + else if ((UVC_CID_CAMERA_CLASS_BASE) == (cid & 0xF0000000)) { + for (int i = 0; i < udev->nITs; i++){ + + if (((cid & 0xFFFFFFF) & udev->IT->ct->bmControls) != 0) { + int j; + for (j = 0; j < ET_POS; j++) { + if ((cid & 1) == 0x1) + break; + cid >>= 1; + } + return &udev->IT->ct->data[j]; + } + } + } else if (UVC_CID_PU_CLASS_BASE == (cid & 0xF0000000)) { + for (int i = 0; i < udev->nPUs; i++) + + if (((cid & 0xFFFFFFF) & udev->PU->bmControls) != 0) { + int j; + for (j = 0; j < ET_POS; j++) { + if ((cid & 1) == 0x1) + break; + cid >>= 1; + } + return &udev->PU->data[j]; + } + + } else if (UVC_CID_XU_CLASS_BASE == (cid >> ET_POS)) { + for ( int i = 0; i < udev->nXUs; i++) + + if (((cid & 0xFFF) & udev->XU->bmControls) != 0) { + int j; + for (j = 0; j < ET_POS; j++) { + if ((cid & 1) == 0x1) + break; + cid >>= 1; + } + return &udev->XU->data[j]; + } + } +// kmdw_printf("no control found \n" ); + return NULL; +} + + +int uvc_send_ctrl_req(struct uvc_device *dev, struct ctrl_info *ctrl, uint8_t req) +{ + int ret; + uint8_t flag_t; + + if (req == UVC_SET_CUR) + flag_t = UVC_CTRL_FLAG_SET_CUR; + else if (req == UVC_GET_CUR ) + flag_t = UVC_CTRL_FLAG_GET_CUR; + else if (req == UVC_GET_MIN) + flag_t = UVC_CTRL_FLAG_GET_MIN; + else if (req == UVC_GET_MAX) + flag_t = UVC_CTRL_FLAG_GET_MAX; + else if (req == UVC_GET_RES) + flag_t = UVC_CTRL_FLAG_GET_RES; + else if (req == UVC_GET_LEN) + flag_t = UVC_CTRL_FLAG_GET_LEN; + else if (req == UVC_GET_INFO) + flag_t = UVC_CTRL_FLAG_GET_INFO; + else if (req == UVC_GET_DEF) + flag_t = UVC_CTRL_FLAG_GET_DEF; + + if (ctrl->ctl_flag & flag_t) { + if (0 > (ret = uvc_create_ctl_req(ctrl, dev->vc_inf, req))) + return ret; + return uvc_query_ctrl(dev, UVC_CTRL_CONTROL_TIMEOUT); + } + return -1; +} + + +static int uvc_ctrl_cache(struct ctrl_info *ctrl_data, struct uvc_device *udev) +{ + int ret; + + if (true == ctrl_data->supported) { + if ((udev->id->idVendor == 0x058F) && (udev->id->idProduct == 0x0806)) { + + } + else { + if (ctrl_data->ctl_flag & UVC_CTRL_FLAG_GET_DEF) { + uvc_create_ctl_req(ctrl_data, udev->vc_inf, UVC_GET_DEF); + if (0 > (ret = uvc_query_ctrl(udev, UVC_CTRL_CONTROL_TIMEOUT))) + return ret; + } + } + if (ctrl_data->ctl_flag & UVC_CTRL_FLAG_GET_MIN) { + uvc_create_ctl_req(ctrl_data, udev->vc_inf, UVC_GET_MIN); + if (0 > (ret = uvc_query_ctrl(udev, UVC_CTRL_CONTROL_TIMEOUT))) + return ret; + } + if (ctrl_data->ctl_flag & UVC_CTRL_FLAG_GET_MAX) { + uvc_create_ctl_req(ctrl_data, udev->vc_inf, UVC_GET_MAX); + if (0 > (ret = uvc_query_ctrl(udev, UVC_CTRL_CONTROL_TIMEOUT))) + return ret; + } + if (ctrl_data->ctl_flag & UVC_CTRL_FLAG_GET_RES) { + uvc_create_ctl_req(ctrl_data, udev->vc_inf, UVC_GET_RES); + if (0 > (ret = uvc_query_ctrl(udev, UVC_CTRL_CONTROL_TIMEOUT))) + return ret; + } + if (ctrl_data->ctl_flag & UVC_CTRL_FLAG_GET_INFO) { + uvc_create_ctl_req(ctrl_data, udev->vc_inf, UVC_GET_INFO); + if (0 > (ret = uvc_query_ctrl(udev, UVC_CTRL_CONTROL_TIMEOUT))) + return ret; + } + if (ctrl_data->ctl_flag & UVC_CTRL_FLAG_GET_LEN) { + uvc_create_ctl_req(ctrl_data, udev->vc_inf, UVC_GET_LEN); + if (0 > (ret = uvc_query_ctrl(udev, UVC_CTRL_CONTROL_TIMEOUT))) + return ret; + } + if (ctrl_data->ctl_flag & UVC_CTRL_FLAG_GET_CUR) { + uvc_create_ctl_req(ctrl_data, udev->vc_inf, UVC_GET_CUR); + if (0 > (ret = uvc_query_ctrl(udev, UVC_CTRL_CONTROL_TIMEOUT))) + return ret; + } + ctrl_data->cached = true; + } + return 0; +} + +static int set_pu_ctrl_flag(struct ctrl_info *info) +{ + + if (info->cid & BRIGHTNESS) { + info->ctl_flag = BRIGHTNESS_CTL_FLAG; + info->cs = UVC_PU_BRIGHTNESS_CONTROL; + info->para_size = BRIGHTNESS_LEN; + info->para = (uint8_t *) malloc(BRIGHTNESS_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, BRIGHTNESS_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & CONTRAST) { + info->cs = UVC_PU_CONTRAST_CONTROL; + info->ctl_flag = CONTRAST_CTL_FLAG; + info->para_size = CONTRAST_LEN; + info->para = (uint8_t *) malloc(CONTRAST_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, CONTRAST_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & HUE) { + info->cs = UVC_PU_HUE_CONTROL; + info->ctl_flag = HUE_CTL_FLAG; + info->para_size = HUE_LEN; + info->para = (uint8_t *) malloc(HUE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, HUE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & SATURATION) { + info->cs = UVC_PU_SATURATION_CONTROL; + info->ctl_flag = SATURATION_CTL_FLAG; + info->para_size = SATURATION_LEN; + info->para = (uint8_t *) malloc(SATURATION_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, SATURATION_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & SHARPNESS) { + info->cs = UVC_PU_SHARPNESS_CONTROL; + info->ctl_flag = SHARPNESS_CTL_FLAG; + info->para_size = SHARPNESS_LEN; + info->para = (uint8_t *) malloc(SHARPNESS_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, SHARPNESS_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & GAMMA) { + info->cs = UVC_PU_GAMMA_CONTROL; + info->ctl_flag = GAMMA_CTL_FLAG; + info->para_size = GAMMA_LEN; + info->para = (uint8_t *) malloc(GAMMA_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, GAMMA_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & WHITE_BALANCE_TEMPERATURE) { + info->cs = UVC_PU_WHITE_BALANCE_TEMPERATURE_CONTROL; + info->ctl_flag = WHITE_BALANCE_TEMPERATURE_CTL_FLAG; + info->para_size = WHITE_BALANCE_TEMPERATURE_LEN; + info->para = (uint8_t *) malloc(WHITE_BALANCE_TEMPERATURE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, WHITE_BALANCE_TEMPERATURE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & WHITE_BALANCE_COMPONENT) { + info->cs = UVC_PU_WHITE_BALANCE_COMPONENT_CONTROL; + info->ctl_flag = WHITE_BALANCE_COMPONENT_CTL_FLAG; + info->para_size = WHITE_BALANCE_COMPONENT_LEN; + info->para = (uint8_t *) malloc(WHITE_BALANCE_COMPONENT_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, WHITE_BALANCE_COMPONENT_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & BACKLIGHT_COMPENSATION) { + info->cs = UVC_PU_BACKLIGHT_COMPENSATION_CONTROL; + info->ctl_flag = BACKLIGHT_COMPENSATION_CTL_FLAG; + info->para_size = BACKLIGHT_COMPENSATION_LEN; + info->para = (uint8_t *) malloc(BACKLIGHT_COMPENSATION_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, BACKLIGHT_COMPENSATION_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & GAIN) { + info->cs = UVC_PU_GAIN_CONTROL; + info->ctl_flag = GAIN_CTL_FLAG; + info->para_size = GAIN_LEN; + info->para = (uint8_t *) malloc(GAIN_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, GAIN_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & POWER_LINE_FREQUENCY) { + info->cs = UVC_PU_POWER_LINE_FREQUENCY_CONTROL; + info->ctl_flag = POWER_LINE_FREQUENCY_CTL_FLAG; + info->para_size = POWER_LINE_FREQUENCY_LEN; + info->para = (uint8_t *) malloc(POWER_LINE_FREQUENCY_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, POWER_LINE_FREQUENCY_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & HUE_AUTO) { + info->cs = UVC_PU_HUE_AUTO_CONTROL; + info->ctl_flag = HUE_AUTO_CTL_FLAG; + info->para_size = HUE_AUTO_LEN; + info->para = (uint8_t *) malloc(HUE_AUTO_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, HUE_AUTO_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & WHITE_BALANCE_TEMPERATURE_AUTO) { + info->cs = UVC_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL; + info->ctl_flag = WHITE_BALANCE_TEMPERATURE_AUTO_CTL_FLAG; + info->para_size = WHITE_BALANCE_TEMPERATURE_AUTO_LEN; + info->para = (uint8_t *) malloc(WHITE_BALANCE_TEMPERATURE_AUTO_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, WHITE_BALANCE_TEMPERATURE_AUTO_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & WHITE_BALANCE_COMPONENT_AUTO) { + info->cs = UVC_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL; + info->ctl_flag = WHITE_BALANCE_COMPONENT_AUTO_CTL_FLAG; + info->para_size = WHITE_BALANCE_COMPONENT_AUTO_LEN; + info->para = (uint8_t *) malloc(WHITE_BALANCE_COMPONENT_AUTO_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, WHITE_BALANCE_COMPONENT_AUTO_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & DIGITAL_MULTIPLIER) { + info->cs = UVC_PU_DIGITAL_MULTIPLIER_CONTROL; + info->ctl_flag = DIGITAL_MULTIPLIER_CTL_FLAG; + info->para_size = DIGITAL_MULTIPLIER_LEN; + info->para = (uint8_t *) malloc(DIGITAL_MULTIPLIER_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, DIGITAL_MULTIPLIER_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & DIGITAL_MULTIPLIER_LIMIT) { + info->cs =UVC_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL; + info->ctl_flag = DIGITAL_MULTIPLIER_LIMIT_CTL_FLAG; + info->para_size = DIGITAL_MULTIPLIER_LIMIT_LEN; + info->para = (uint8_t *) malloc(DIGITAL_MULTIPLIER_LIMIT_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, DIGITAL_MULTIPLIER_LIMIT_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & ANALOG_VIDEO_STANDARD) { + info->cs = UVC_PU_ANALOG_VIDEO_STANDARD_CONTROL; + info->ctl_flag = ANALOG_VIDEO_STANDARD_CTL_FLAG; + info->para_size = ANALOG_VIDEO_STANDARD_LEN; + info->para = (uint8_t *) malloc(ANALOG_VIDEO_STANDARD_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, ANALOG_VIDEO_STANDARD_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & ANALOG_VIDEO_LOCK_STATUS) { + info->cs = UVC_PU_ANALOG_LOCK_STATUS_CONTROL; + info->ctl_flag = ANALOG_VIDEO_LOCK_STATUS_CTL_FLAG; + info->para_size = ANALOG_VIDEO_LOCK_STATUS_LEN; + info->para = (uint8_t *) malloc(ANALOG_VIDEO_LOCK_STATUS_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, ANALOG_VIDEO_LOCK_STATUS_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & CONTRAST_AUTO) { + info->cs = UVC_PU_CONTRAST_AUTO_CONTROL; + info->ctl_flag = CONTRAST_AUTO_CTL_FLAG; + info->para_size = CONTRAST_AUTO_LEN; + info->para = (uint8_t *) malloc(CONTRAST_AUTO_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, CONTRAST_AUTO_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } + return 0; +} + +static int set_ct_ctrl_flag(struct ctrl_info *info) +{ + if (info->cid & SCANNING_MODE) { + info->ctl_flag = SCANNING_MODE_CTL_FLAG; + info->cs = UVC_CT_SCANNING_MODE_CONTROL; + info->para_size = SCANNING_MODE_LEN; + info->para = (uint8_t *) malloc(SCANNING_MODE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, SCANNING_MODE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & AUTO_EXPOSURE_MODE) { + info->ctl_flag = AUTO_EXPOSURE_MODE_CTL_FLAG; + info->cs = UVC_CT_AE_MODE_CONTROL; + info->para_size = AUTO_EXPOSURE_MODE_LEN; + info->para = (uint8_t *) malloc(AUTO_EXPOSURE_MODE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, AUTO_EXPOSURE_MODE_LEN * PARAM_ARRAY_SIZE); + } else if (info->cid & AUTO_EXPOSURE_PRIORITY) { + info->ctl_flag = AUTO_EXPOSURE_PRIORITY_CTL_FLAG; + info->cs = UVC_CT_AE_PRIORITY_CONTROL; + info->para_size = AUTO_EXPOSURE_PRIORITY_LEN; + info->para = (uint8_t *) malloc(AUTO_EXPOSURE_PRIORITY_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, AUTO_EXPOSURE_PRIORITY_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & EXPOSURE_TIME_ABSOLUTE) { + info->ctl_flag = EXPOSURE_TIME_ABSOLUTE_CTL_FLAG; + info->cs = UVC_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL; + info->para_size = EXPOSURE_TIME_ABSOLUTE_LEN; + info->para = (uint8_t *) malloc(EXPOSURE_TIME_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, EXPOSURE_TIME_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & EXPOSURE_TIME_RELATIVE) { + info->ctl_flag = EXPOSURE_TIME_RELATIVE_CTL_FLAG; + info->cs = UVC_CT_EXPOSURE_TIME_RELATIVE_CONTROL; + info->para_size = EXPOSURE_TIME_RELATIVE_LEN; + info->para = (uint8_t *) malloc(EXPOSURE_TIME_RELATIVE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, EXPOSURE_TIME_RELATIVE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & FOCUS_ABSOLUTE) { + info->ctl_flag = FOCUS_ABSOLUTE_CTL_FLAG; + info->cs = UVC_CT_FOCUS_ABSOLUTE_CONTROL; + info->para_size = FOCUS_ABSOLUTE_LEN; + info->para = (uint8_t *) malloc(FOCUS_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, FOCUS_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & FOCUS_RELATIVE) { + info->ctl_flag = FOCUS_RELATIVE_CTL_FLAG; + info->cs = UVC_CT_FOCUS_RELATIVE_CONTROL; + info->para_size = FOCUS_RELATIVE_LEN; + info->para = (uint8_t *) malloc(FOCUS_RELATIVE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, FOCUS_RELATIVE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & IRIS_ABSOLUTE) { + info->ctl_flag = IRIS_ABSOLUTE_CTL_FLAG; + info->cs = UVC_CT_IRIS_ABSOLUTE_CONTROL; + info->para_size = IRIS_ABSOLUTE_LEN; + info->para = (uint8_t *) malloc(IRIS_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, IRIS_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & IRIS_RELATIVE) { + info->ctl_flag = IRIS_RELATIVE_CTL_FLAG; + info->cs =UVC_CT_IRIS_RELATIVE_CONTROL; + info->para_size = IRIS_RELATIVE_LEN; + info->para = (uint8_t *) malloc(IRIS_RELATIVE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, IRIS_RELATIVE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & ZOOM_ABSOLUTE) { + info->ctl_flag = ZOOM_ABSOLUTE_CTL_FLAG; + info->cs = UVC_CT_ZOOM_ABSOLUTE_CONTROL; + info->para_size = ZOOM_ABSOLUTE_LEN; + info->para = (uint8_t *) malloc(ZOOM_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, ZOOM_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & ZOOM_RELATIVE) { + info->ctl_flag = ZOOM_RELATIVE_CTL_FLAG; + info->cs = UVC_CT_ZOOM_RELATIVE_CONTROL; + info->para_size = ZOOM_RELATIVE_LEN; + info->para = (uint8_t *) malloc(ZOOM_RELATIVE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, ZOOM_RELATIVE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & PANTILT_ABSOLUTE) { + info->ctl_flag = PANTILT_ABSOLUTE_CTL_FLAG; + info->cs = UVC_CT_PANTILT_ABSOLUTE_CONTROL; + info->para_size = PANTILT_ABSOLUTE_LEN; + info->para = (uint8_t *) malloc(PANTILT_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, PANTILT_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & PANTILT_RELATIVE) { + info->ctl_flag = PANTILT_RELATIVE_CTL_FLAG; + info->cs = UVC_CT_PANTILT_RELATIVE_CONTROL; + info->para_size = PANTILT_RELATIVE_LEN; + info->para = (uint8_t *) malloc(PANTILT_RELATIVE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, PANTILT_RELATIVE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & ROLL_ABSOLUTE) { + info->ctl_flag = ROLL_ABSOLUTE_CTL_FLAG; + info->cs = UVC_CT_ROLL_ABSOLUTE_CONTROL; + info->para_size = ROLL_ABSOLUTE_LEN; + info->para = (uint8_t *) malloc(ROLL_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, ROLL_ABSOLUTE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & ROLL_RELATIVE) { + info->ctl_flag = ROLL_RELATIVE_CTL_FLAG; + info->cs = UVC_CT_ROLL_RELATIVE_CONTROL; + info->para_size = ROLL_RELATIVE_LEN; + info->para = (uint8_t *) malloc(ROLL_RELATIVE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, ROLL_RELATIVE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & FOCUS_AUTO) { + info->ctl_flag = FOCUS_AUTO_CTL_FLAG; + info->cs = UVC_CT_FOCUS_AUTO_CONTROL; + info->para_size = FOCUS_AUTO_LEN; + info->para = (uint8_t *) malloc(FOCUS_AUTO_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, FOCUS_AUTO_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & PRIVACY) { + info->ctl_flag = PRIVACY_CTL_FLAG; + info->cs = UVC_CT_PRIVACY_CONTROL; + info->para_size = PRIVACY_LEN; + info->para = (uint8_t *) malloc(PRIVACY_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, PRIVACY_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & FOCUS_SIMPLE) { + info->ctl_flag = FOCUS_SIMPLE_CTL_FLAG; + info->cs = UVC_CT_FOCUS_SIMPLE_CONTROL; + info->para_size = FOCUS_SIMPLE_LEN; + info->para = (uint8_t *) malloc(FOCUS_SIMPLE_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, FOCUS_SIMPLE_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & WINDOW) { + info->ctl_flag = WINDOW_CTL_FLAG; + info->cs = UVC_CT_WINDOW_CONTROL; + info->para_size = WINDOW_LEN; + info->para = (uint8_t *) malloc(WINDOW_LEN * PARAM_ARRAY_SIZE); +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + if (0 != info->para) + memset(info->para, 0, WINDOW_LEN * PARAM_ARRAY_SIZE); + else + return -1; + } else if (info->cid & REGION_OF_INTEREST) { + info->ctl_flag = REGION_OF_INTEREST_CTL_FLAG; + info->cs = UVC_CT_REGION_OF_INTEREST_CONTROL; + info->para_size = REGION_OF_INTEREST_LEN; + info->para = (uint8_t *) malloc(REGION_OF_INTEREST_LEN * PARAM_ARRAY_SIZE); + if (0 != info->para) + memset(info->para, 0, REGION_OF_INTEREST_LEN * PARAM_ARRAY_SIZE); + else + return -1; +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ info->para %p\n", info->para); +#endif + } + return 0; +} + +static void uvc_memory_copy(uint8_t *dst, uint8_t *src, uint8_t len) +{ + for (int i = 0; i < len; i++) + dst[i] = src[i]; + return; +} + +int uvc_send_ctl(struct uvc_device *udev, uint32_t cid, uint16_t req, uint8_t *para, uint8_t len) +{ + struct ctrl_info *ctrl; + + if (NULL == (ctrl = uvc_find_control(udev, cid))) + return -EINVAL; + + if (req & 0x80) { + if (0 > uvc_send_ctrl_req(udev, ctrl, req)) + return -1; + if (req == UVC_GET_CUR) { + uvc_memory_copy(para, &ctrl->para[UVC_CUR * len], len); + return 0; + } else if (req == UVC_GET_MIN) { + uvc_memory_copy(para, &ctrl->para[UVC_MIN * len], len); + return 0; + } else if (req == UVC_GET_MAX) { + uvc_memory_copy(para, &ctrl->para[UVC_MAX * len], len); + return 0; + } else if (req == UVC_GET_RES) { + uvc_memory_copy(para, &ctrl->para[UVC_RES * len], len); + return 0; + } else if (req == UVC_GET_LEN) { + *para = ctrl->len; + return 0; + } else if (req == UVC_GET_INFO) { + *para = ctrl->caps; + return 0; + } else if (req == UVC_GET_DEF) { + uvc_memory_copy(para, &ctrl->para[UVC_DEF * len], len); + return 0; + } else + return -1; + } else { + if (req == UVC_SET_CUR) { + if (!(ctrl->ctl_flag & UVC_CTRL_FLAG_GET_RES)) + { + if ((ctrl->cid == (UVC_CID_FOCUS_AUTO)) || + (ctrl->cid == (UVC_CID_PRIVACY)) || + (ctrl->cid == (UVC_CID_SCANNING_MODE))) { + ctrl->para[UVC_CUR] = (*para == 0) ? 0 : 1; + } else if ((ctrl->cid == (UVC_CID_EXPOSURE_TIME_RELATIVE)) + || (ctrl->cid == (UVC_CID_IRIS_RELATIVE))) { + ctrl->para[UVC_CUR] = (*para == 0) ? 0: ((*para != 0xFF) ? 1: *para); + } else if ((ctrl->cid == (UVC_CID_CONTRAST_AUTO)) + || (ctrl->cid == (UVC_CID_HUE_AUTO)) + || (ctrl->cid == (UVC_CID_WHITE_BALANCE_TEMPERATURE_AUTO)) + || (ctrl->cid == (UVC_CID_WHITE_BALANCE_COMPONENT_AUTO))){ + ctrl->para[UVC_CUR] = *para; + } else if (ctrl->cid == (UVC_CID_AUTO_EXPOSURE_PRIORITY)) { + struct ctrl_info *ctr_t; + if (NULL == (ctr_t = uvc_find_control(udev, UVC_CID_AUTO_EXPOSURE_MODE))) + return -EINVAL; + if (ctr_t->para[UVC_CUR] & 0x6) { + ctrl->para[UVC_CUR] = (*para == 0) ? 0 : 1; + } + else + return -EINVAL; + } else if (ctrl->cid == (UVC_CID_FOCUS_SIMPLE)) { + if (*para >= 4) + *para = 0; + ctrl->para[UVC_CUR] = *para; + } else if ((ctrl->cid == (UVC_CID_WINDOW)) || (ctrl->cid == (UVC_CID_REGION_OF_INTEREST))) { + for (int i = 0; i < len; i++) + uvc_memory_copy(&ctrl->para[UVC_CUR * len], para, len); + } else if (ctrl->cid == (UVC_CID_POWER_LINE_FREQUENCY)) { + if (*para >= 3) + *para = 3; + ctrl->para[UVC_CUR] = *para; + } + } + else { + if (ctrl->cid == (UVC_CID_ZOOM_RELATIVE)) { + struct ct_zoomr_data *min = (struct ct_zoomr_data *)&ctrl->para[UVC_MIN *len]; + struct ct_zoomr_data *max = (struct ct_zoomr_data *)&ctrl->para[UVC_MAX *len]; + struct ct_zoomr_data *step = (struct ct_zoomr_data *)&ctrl->para[UVC_RES *len]; + struct ct_zoomr_data *cur = (struct ct_zoomr_data *)&ctrl->para[UVC_CUR *len]; + struct ct_zoomr_data *zr_para = (struct ct_zoomr_data *) para; + uint8_t zr_step; + + if (step->bSpeed == 0) + zr_step = 1; + + cur->bDigitalZoom = (zr_para->bDigitalZoom == 0) ? 0: 1; + cur->bZoom = (zr_para->bZoom == 0) ? 0: ((zr_para->bZoom != 0xFF) ? 1: zr_para->bZoom); + cur->bSpeed = cur->bSpeed + ((uint32_t)(zr_para->bSpeed - min->bSpeed) + (zr_step >> 0x1)) / zr_step * zr_step; + cur->bSpeed = clamp(cur->bSpeed, min->bSpeed, max->bSpeed); + + } else if (ctrl->cid == (UVC_CID_AUTO_EXPOSURE_MODE)) { + if ((*para == 0) || ((*para & (*para - 1)) != 0) || (*para > 8) + || (!((*para == 0) & ctrl->para[UVC_RES]))) + { + *para = 0x1; + } + ctrl->para[UVC_CUR]= *para; + } else if (ctrl->cid == (UVC_CID_EXPOSURE_TIME_ABSOLUTE)) { + struct ctrl_info *ctr_t; + if (NULL == (ctr_t = uvc_find_control(udev, UVC_CID_AUTO_EXPOSURE_MODE))) + return -EINVAL; + if (ctr_t->para[UVC_CUR] & 0x6) { + uint32_t *min = (uint32_t *)&ctrl->para[UVC_MIN *len]; + uint32_t *max = (uint32_t *)&ctrl->para[UVC_MAX *len]; + uint32_t *step = (uint32_t *)&ctrl->para[UVC_RES *len]; + uint32_t *cur = (uint32_t *)&ctrl->para[UVC_CUR *len]; + uint32_t *zr_para = (uint32_t *) para; + uint8_t zr_step; + //kmdw_printf("min is 0x%x, max is 0x%x, step is 0x%x, cur is 0x%x, param is 0x%x \n",*min, *max, *step, *cur, *zr_para); + if (*step == 0) + zr_step = 1; + *cur = *zr_para; + *cur = *min + ((uint32_t)(*zr_para - *min) + (zr_step >> 0x1)) / zr_step * zr_step; + *cur = clamp(*cur, *min, *max); + } + else + return -EINVAL; + } else if (ctrl->cid == (UVC_CID_FOCUS_ABSOLUTE)) { + struct ctrl_info *ctr_t; + if (NULL == (ctr_t = uvc_find_control(udev, UVC_CID_FOCUS_AUTO))) + return -EINVAL; + if (ctr_t->para[UVC_CUR] & 0x1) + return -EINVAL; + uint16_t *min = (uint16_t *)&ctrl->para[UVC_MIN *len]; + uint16_t *max = (uint16_t *)&ctrl->para[UVC_MAX *len]; + uint16_t *step = (uint16_t *)&ctrl->para[UVC_RES *len]; + uint16_t *cur = (uint16_t *)&ctrl->para[UVC_CUR *len]; + uint16_t *zr_para = (uint16_t *) para; + uint16_t fa_step = *step; + if (fa_step == 0) + fa_step = 1; + *cur = *min + ((uint16_t)(*zr_para - *min) + (fa_step >> 0x1)) / fa_step * fa_step; + *cur = clamp(*cur, *min, *max); + } else if (ctrl->cid == (UVC_CID_FOCUS_RELATIVE)) { + struct ct_focus_r_data *min = (struct ct_focus_r_data *)&ctrl->para[UVC_MIN *len]; + struct ct_focus_r_data *max = (struct ct_focus_r_data *)&ctrl->para[UVC_MAX *len]; + struct ct_focus_r_data *step = (struct ct_focus_r_data *)&ctrl->para[UVC_RES *len]; + struct ct_focus_r_data *cur = (struct ct_focus_r_data *)&ctrl->para[UVC_CUR *len]; + struct ct_focus_r_data *zr_para = (struct ct_focus_r_data *) para; + uint8_t zr_step; + if (step->bSpeed == 0) + zr_step = 1; + cur->bFocusRelative = (zr_para->bFocusRelative == 0) ? 0: + ((zr_para->bFocusRelative != (int8_t) 0xFF) ? 1: zr_para->bFocusRelative); + cur->bSpeed = min->bSpeed + ((uint32_t)(zr_para->bSpeed - min->bSpeed) + (zr_step >> 0x1)) / zr_step * zr_step; + cur->bSpeed = clamp(cur->bSpeed, min->bSpeed, max->bSpeed); + } else if (ctrl->cid == (UVC_CID_PANTILT_ABSOLUTE)) { + struct ct_pan_tilta_data *min = (struct ct_pan_tilta_data *)&ctrl->para[UVC_MIN *len]; + struct ct_pan_tilta_data *max = (struct ct_pan_tilta_data *)&ctrl->para[UVC_MAX *len]; + struct ct_pan_tilta_data *step = (struct ct_pan_tilta_data *)&ctrl->para[UVC_RES *len]; + struct ct_pan_tilta_data *cur = (struct ct_pan_tilta_data *)&ctrl->para[UVC_CUR *len]; + struct ct_pan_tilta_data *zr_para = (struct ct_pan_tilta_data *) para; + int32_t zr_step; + if (step->dwPanAbsolute == 0) + zr_step = 1; + + cur->dwPanAbsolute = min->dwPanAbsolute + ((uint32_t)(zr_para->dwPanAbsolute - min->dwPanAbsolute) + + (zr_step >> 0x1)) / zr_step * zr_step; + cur->dwPanAbsolute = clamp(cur->dwPanAbsolute, min->dwPanAbsolute, max->dwPanAbsolute); + if (step->dwTiltAbsolute == 0) + zr_step = 1; + cur->dwTiltAbsolute = min->dwTiltAbsolute + ((uint32_t)(zr_para->dwTiltAbsolute - min->dwTiltAbsolute) + + (zr_step >> 0x1)) / zr_step * zr_step; + cur->dwTiltAbsolute = clamp(cur->dwTiltAbsolute, min->dwTiltAbsolute, max->dwTiltAbsolute); + } else if (ctrl->cid == (UVC_CID_PANTILT_RELATIVE)) { + struct ct_pan_tiltr_data *min = (struct ct_pan_tiltr_data *)&ctrl->para[UVC_MIN *len]; + struct ct_pan_tiltr_data *max = (struct ct_pan_tiltr_data *)&ctrl->para[UVC_MAX *len]; + struct ct_pan_tiltr_data *step = (struct ct_pan_tiltr_data *)&ctrl->para[UVC_RES *len]; + struct ct_pan_tiltr_data *cur = (struct ct_pan_tiltr_data *)&ctrl->para[UVC_CUR *len]; + struct ct_pan_tiltr_data *zr_para = (struct ct_pan_tiltr_data *) para; + int32_t zr_step; + + cur->bPanRelative = (zr_para->bPanRelative == 0) ? 0 : + ((zr_para->bPanRelative != (int8_t) 0xFF) ? 1 : zr_para->bPanRelative); + cur->bTiltRelative = (zr_para->bTiltRelative == 0) ? 0: + ((zr_para->bTiltRelative != (int8_t) 0xFF) ? 1: zr_para->bTiltRelative); + if (step->bPanSpeed == 0) + zr_step = 1; + cur->bPanSpeed = min->bPanSpeed + + ((uint32_t)(zr_para->bPanSpeed - min->bPanSpeed) + (zr_step >> 0x1)) / zr_step * zr_step; + cur->bPanSpeed = clamp(cur->bPanSpeed, min->bPanSpeed, max->bPanSpeed); + if (step->bTiltSpeed == 0) + zr_step = 1; + cur->bTiltSpeed = min->bTiltSpeed + + ((uint32_t)(zr_para->bTiltSpeed - min->bTiltSpeed) + (zr_step >> 0x1)) / zr_step * zr_step; + cur->bTiltSpeed = clamp(cur->bTiltSpeed, min->bTiltSpeed, max->bTiltSpeed); + } else if (ctrl->cid == (UVC_CID_WHITE_BALANCE_COMPONENT)) { + struct pu_whitebalance_comp_data *min = (struct pu_whitebalance_comp_data *)&ctrl->para[UVC_MIN *len]; + struct pu_whitebalance_comp_data *max = (struct pu_whitebalance_comp_data *)&ctrl->para[UVC_MAX *len]; + struct pu_whitebalance_comp_data *step = (struct pu_whitebalance_comp_data *)&ctrl->para[UVC_RES *len]; + struct pu_whitebalance_comp_data *cur = (struct pu_whitebalance_comp_data *)&ctrl->para[UVC_CUR *len]; + struct pu_whitebalance_comp_data *zr_para = (struct pu_whitebalance_comp_data *) para; + int32_t zr_step; + + if (step->wWhiteBalanceBlue == 0) + zr_step = 1; + cur->wWhiteBalanceBlue = min->wWhiteBalanceBlue + + ((uint32_t)(zr_para->wWhiteBalanceBlue - min->wWhiteBalanceBlue) + + (zr_step >> 0x1)) / zr_step * zr_step; + cur->wWhiteBalanceBlue = clamp(cur->wWhiteBalanceBlue, min->wWhiteBalanceBlue, max->wWhiteBalanceBlue); + if (step->wWhiteBalanceRed == 0) + zr_step = 1; + cur->wWhiteBalanceRed = min->wWhiteBalanceRed + + ((uint32_t)(zr_para->wWhiteBalanceRed - min->wWhiteBalanceRed) + + (zr_step >> 0x1)) / zr_step * zr_step; + cur->wWhiteBalanceRed = clamp(cur->wWhiteBalanceRed, min->wWhiteBalanceRed, max->wWhiteBalanceRed); + } else { + if (ctrl->cid == (UVC_CID_IRIS_ABSOLUTE)) { + struct ctrl_info *ctr_t; + if (NULL == (ctr_t = uvc_find_control(udev, UVC_CID_AUTO_EXPOSURE_MODE))) + return -EINVAL; + if (ctr_t->para[UVC_CUR] & 0x6) { + return -EINVAL; + } + } + if (ctrl->cid == (UVC_CID_WHITE_BALANCE_TEMPERATURE)) { + struct ctrl_info *ctr_t; + if (NULL == (ctr_t = uvc_find_control(udev, UVC_CID_WHITE_BALANCE_TEMPERATURE_AUTO))) + return -EINVAL; + if (ctr_t->para[UVC_CUR] & 0x1) { + return -EINVAL; + } + } + if (ctrl->cid == (UVC_CID_WHITE_BALANCE_COMPONENT)) { + struct ctrl_info *ctr_t; + if (NULL == (ctr_t = uvc_find_control(udev, UVC_CID_WHITE_BALANCE_COMPONENT_AUTO))) + return -EINVAL; + if (ctr_t->para[UVC_CUR] & 0x1) { + return -EINVAL; + } + } + uint16_t *min = (uint16_t *)&ctrl->para[UVC_MIN *2]; + uint16_t *max = (uint16_t *)&ctrl->para[UVC_MAX *2]; + uint16_t *step = (uint16_t *)&ctrl->para[UVC_RES *2]; + uint16_t *cur = (uint16_t *)&ctrl->para[UVC_CUR *2]; + uint16_t *zr_para = (uint16_t *) para; + uint16_t fa_step = *step; + if (fa_step == 0) + fa_step = 1; +// kmdw_printf("min is 0x%x, max is 0x%x, step is 0x%x, cur is 0x%x, param is 0x%x \n",*min, *max, *step, *cur, *zr_para); + *cur = *min + ((uint16_t)(*zr_para - *min) + (fa_step >> 0x1)) / fa_step * fa_step; + *cur = clamp(*cur, *min, *max); + } + } + return uvc_send_ctrl_req(udev, ctrl, req); + } else + return -1; + } +} + +static uint32_t pow(int n) +{ + long long power = 1; + + for(int i=1; i<=n; i++) { + power = power * 2; + } + return power; +} + +int uvc_init_device_ctrl(struct uvc_device *udev) +{ + for (int i = 0; i < udev->nITs; i++) { + if (0 == udev->IT[i].ct->bmControls) + break; + if (NULL == (udev->IT[i].ct->data = (struct ctrl_info *)malloc(CT_CTRL_NUM *sizeof(struct ctrl_info)))) + return -ENOMEM; + memset(udev->IT[i].ct->data, 0, CT_CTRL_NUM *sizeof(struct ctrl_info)); + + for (int j = 0; j < CT_CTRL_NUM; j++) { + udev->IT[i].ct->data[j].cid = pow(j); + if (udev->IT[i].ct->bmControls & udev->IT[i].ct->data[j].cid) { +#ifdef KDP_UVC_DEBUG + kmdw_printf("@@ udev->IT[i].ct->data[j].cid 0x%x\n", udev->IT[i].ct->data[j].cid); +#endif + udev->IT[i].ct->data[j].supported = true; + if (0 > set_ct_ctrl_flag(&udev->IT[i].ct->data[j])) + return -1; + udev->IT[i].ct->data[j].cid |= UVC_CID_CAMERA_CLASS_BASE; + udev->IT[i].ct->data[j].eid = udev->IT[i].id; + uvc_ctrl_cache(&udev->IT[i].ct->data[j], udev); + } else { + // udev->IT[i].ct->data[j] = false; + } + } + } + for (int i = 0; i < udev->nPUs; i++) { + + if (NULL == (udev->PU[i].data = (struct ctrl_info *)malloc(PU_CTRL_NUM *sizeof(struct ctrl_info)))) + return -ENOMEM; + memset(udev->PU[i].data, 0, PU_CTRL_NUM *sizeof(struct ctrl_info)); + for (int j = 0; j < PU_CTRL_NUM; j++) { + + udev->PU[i].data[j].cid = pow(j); + if (udev->PU[i].bmControls & udev->PU[i].data[j].cid) { + if (0 > set_pu_ctrl_flag(&udev->PU[i].data[j])) + return -1; + udev->PU[i].data[j].supported = true; + udev->PU[i].data[j].cid |= UVC_CID_PU_CLASS_BASE; + udev->PU[i].data[j].eid = udev->PU[i].id; + uvc_ctrl_cache(&udev->PU[i].data[j], udev); + } else { + udev->PU[i].data[j].supported = false; + } + + } + } + + return 0; + +} +#endif + diff --git a/mdw/kdp_usb_uvc/src/uvc_example.c b/mdw/kdp_usb_uvc/src/uvc_example.c new file mode 100644 index 0000000..8f50860 --- /dev/null +++ b/mdw/kdp_usb_uvc/src/uvc_example.c @@ -0,0 +1,2784 @@ +/* + * KDP UVC test and example + * + * Copyright (C) 2019 - 2020 Kneron, Inc. All rights reserved. + * + */ + +#include "kmdw_camera.h" +#include "kmdw_console.h" +#include "uvc_camera.h" +#include "kmdw_status.h" +#ifdef KDP_UVC_DEBUG +int uvc_camera_cotrol_list(uint32_t cam_idx) +{ + uint32_t ctl_list[2] = {0,0}; + + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_LIST_ALL, ctl_list, sizeof (ctl_list))) + { + info_msg("*** UVC list error\n"); + return -1; + } + info_msg("*** UVC control list \n"); + if (ctl_list[0] & SCANNING_MODE) { + info_msg("Scanning Mode \n"); + } + if (ctl_list[0] & AUTO_EXPOSURE_MODE) { + info_msg("Auto-Exposure Mode \n"); + } + if (ctl_list[0] & AUTO_EXPOSURE_PRIORITY) { + info_msg("Auto-Exposure Priority \n"); + } + if (ctl_list[0] & EXPOSURE_TIME_ABSOLUTE) { + info_msg("Exposure Time (Absolute) \n"); + } + if (ctl_list[0] & EXPOSURE_TIME_RELATIVE) { + info_msg("Exposure Time (Relative) \n"); + } + if (ctl_list[0] & FOCUS_ABSOLUTE) { + info_msg("Focus (Absolute) \n"); + } + if (ctl_list[0] & FOCUS_RELATIVE) { + info_msg("Focus (Relative) \n"); + } + if (ctl_list[0] & IRIS_ABSOLUTE) { + info_msg("Iris (Absolute) \n"); + } + if (ctl_list[0] & IRIS_RELATIVE) { + info_msg("Iris (Relative) \n"); + } + if (ctl_list[0] & ZOOM_ABSOLUTE) { + info_msg("Zoom (Absolute)\n"); + } + if (ctl_list[0] & ZOOM_RELATIVE) { + info_msg("Zoom (Relative) \n"); + } + if (ctl_list[0] & PANTILT_ABSOLUTE) { + info_msg("Pan (Absolute) \n"); + } + if (ctl_list[0] & PANTILT_RELATIVE) { + info_msg("Pan (Relative) \n"); + } + if (ctl_list[0] & ROLL_ABSOLUTE) { + info_msg("Roll (Absolute) \n"); + } + if (ctl_list[0] & ROLL_RELATIVE) { + info_msg("Roll (Relative) \n"); + } + if (ctl_list[0] & FOCUS_AUTO) { + info_msg("focus, auto\n"); + } + if (ctl_list[0] & PRIVACY) { + info_msg("privacy \n"); + } + if (ctl_list[0] & FOCUS_SIMPLE) { + info_msg("focus,simple \n"); + } + if (ctl_list[0] & WINDOW) { + info_msg("window \n"); + } + if (ctl_list[0] & REGION_OF_INTEREST) { + info_msg("region_of_interest \n"); + } + + if (ctl_list[1] & BRIGHTNESS) { + info_msg("Brightness \n"); + } + if (ctl_list[1] & CONTRAST) { + info_msg("Contrast \n"); + } + if (ctl_list[1] & HUE) { + info_msg("Hue \n"); + } + if (ctl_list[1] & SATURATION) { + info_msg("Saturation \n"); + } + if (ctl_list[1] & SHARPNESS) { + info_msg("Sharpness \n"); + } + if (ctl_list[1] & GAMMA) { + info_msg("Gamma \n"); + } + if (ctl_list[1] & WHITE_BALANCE_TEMPERATURE) { + info_msg("White Balance Temperature \n"); + } + if (ctl_list[1] & WHITE_BALANCE_COMPONENT) { + info_msg("White Balance Component \n"); + } + if (ctl_list[1] & BACKLIGHT_COMPENSATION) { + info_msg("Backlight Compensation \n"); + } + if (ctl_list[1] & GAIN) { + info_msg("Gain \n"); + } + if (ctl_list[1] & POWER_LINE_FREQUENCY) { + info_msg("Power Line Frequency \n"); + } + if (ctl_list[1] & HUE_AUTO) { + info_msg("Hue, Auto \n"); + } + if (ctl_list[1] & WHITE_BALANCE_TEMPERATURE_AUTO) { + info_msg("White Balance Temperature, Auto \n"); + } + if (ctl_list[1] & WHITE_BALANCE_COMPONENT_AUTO) { + info_msg("White Balance Component, Auto \n"); + } + if (ctl_list[1] & DIGITAL_MULTIPLIER) { + info_msg("Digital Multiplier \n"); + } + if (ctl_list[1] & DIGITAL_MULTIPLIER_LIMIT) { + info_msg("Digital Multiplier Limit \n"); + } + if (ctl_list[1] & ANALOG_VIDEO_STANDARD) { + info_msg("analog_video_standard \n"); + } + if (ctl_list[1] & ANALOG_VIDEO_LOCK_STATUS) { + info_msg("analog_video_lock_status \n"); + } + if (ctl_list[1] & CONTRAST_AUTO) { + info_msg("auto-contrast mode \n"); + } + + info_msg("----------------------------------- \n"); + return 0; +} + + +static void uvc_scanning_mode_test(int cam_idx) +{ + struct ct_scm scm; + info_msg("*** UVC test scanning mode \n"); + + scm.req = SCM_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SCANNING_MODE, &scm, sizeof (struct ct_scm))) + { + info_msg("*** UVC scanning mode is not supported \n"); + return; + } + info_msg("*** UVC scanning mode cap is 0x%x\n", scm.caps); + scm.bScanningMode = 0; + scm.req = SCM_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SCANNING_MODE, &scm, sizeof (struct ct_scm))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + + if (scm.bScanningMode == SCANNING_MODE_CTL_INTERLACED ) + info_msg("*** UVC scanning mode is interlaced \n"); + + if (scm.bScanningMode == SCANNING_MODE_CTL_PROGRESSIVE ) + info_msg("*** UVC scanning mode is progressive \n"); + + scm.bScanningMode = SCANNING_MODE_CTL_PROGRESSIVE; + scm.req = SCM_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SCANNING_MODE, &scm, sizeof (struct ct_scm))) + { + info_msg("*** UVC SET current scanning mode is error \n"); + return; + } + + info_msg("*** UVC test verfication \n"); + scm.bScanningMode = 0; + scm.req = SCM_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SCANNING_MODE, &scm, sizeof (struct ct_scm))) + { + info_msg("*** UVC SET current scanning mode is error \n"); + return; + } + + info_msg("*** UVC current scanning mode is 0x%x \n", scm.bScanningMode); + info_msg("*** UVC test pass \n"); +} + +static void uvc_exposure_mode_test(int cam_idx) +{ + struct ct_aem aem; + + info_msg("*** UVC test exposure mode \n"); + aem.req = AEM_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_MODE, &aem, sizeof (struct ct_aem))) + { + info_msg("*** UVC CID_AUTO_EXPOSURE_MODE is not supported \n"); + return; + } + info_msg("*** UVC exposure mode cap is 0x%x\n", aem.caps); + aem.bAutoExposureMode = 0; + aem.req = AEM_GET_DEF; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_MODE, &aem, sizeof (struct ct_aem))) + { + info_msg("*** UVC exposure mode is not supported \n"); + return; + } + + if (aem.bAutoExposureMode & EXPOSURE_MANUAL_MODE) + info_msg("*** default is exposure manual mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_AUTO_MODE) + info_msg("*** default is exposure auto mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_SHUTTER_PRIORITY_MODE) + info_msg("*** default is exposure shutter priority mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_APERTURE_PRIORITY_MODE) + info_msg("*** default is exposure aperture priority mode \n"); + + aem.bAutoExposureMode = 0; + aem.req = AEM_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_MODE, &aem, sizeof (struct ct_aem))) + { + info_msg("*** UVC resolution is not supported \n"); + return; + } + if (aem.bAutoExposureMode & EXPOSURE_MANUAL_MODE) + info_msg("*** manual mode is supported \n"); + if (aem.bAutoExposureMode & EXPOSURE_AUTO_MODE) + info_msg("*** exposure auto mode is supported \n"); + if (aem.bAutoExposureMode & EXPOSURE_SHUTTER_PRIORITY_MODE) + info_msg("*** exposure shutter priority mode is supported\n"); + if (aem.bAutoExposureMode & EXPOSURE_APERTURE_PRIORITY_MODE) + info_msg("*** exposure aperture priority mode is supported\n"); + + aem.bAutoExposureMode = 0; + aem.req = AEM_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_MODE, &aem, sizeof (struct ct_aem))) + { + info_msg("*** UVC exposure mode is not supported \n"); + return; + } + + if (aem.bAutoExposureMode & EXPOSURE_MANUAL_MODE) + info_msg("*** current is exposure manual mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_AUTO_MODE) + info_msg("*** current is exposure auto mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_SHUTTER_PRIORITY_MODE) + info_msg("*** current is exposure shutter priority mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_APERTURE_PRIORITY_MODE) + info_msg("*** current is exposure aperture priority mode \n"); + + aem.bAutoExposureMode = EXPOSURE_MANUAL_MODE; + aem.req = AEM_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_MODE, &aem, sizeof (struct ct_aem))) + { + info_msg("*** UVC exposure mode is not supported \n"); + return; + } + aem.bAutoExposureMode = 0; + aem.req = AEM_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_MODE, &aem, sizeof (struct ct_aem))) + { + info_msg("*** UVC GET exposure mode is error \n"); + return; + } + if (aem.bAutoExposureMode & EXPOSURE_MANUAL_MODE) + info_msg("*** current exposure manual mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_AUTO_MODE) + info_msg("*** current exposure auto mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_SHUTTER_PRIORITY_MODE) + info_msg("*** current exposure shutter priority mode \n"); + if (aem.bAutoExposureMode & EXPOSURE_APERTURE_PRIORITY_MODE) + info_msg("*** current exposure aperture priority mode \n"); + + info_msg("*** UVC test pass \n"); +} + +static void uvc_exposure_priority_test(int cam_idx) +{ + struct ct_aep aep; + info_msg("*** UVC test exposure priority mode \n"); + aep.req = AEP_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_PRIORITY, &aep, sizeof (struct ct_aep))) + { + info_msg("*** UVC exposure priority is not supported \n"); + return; + } + info_msg("*** UVC exposure priority cap is 0x%x\n", aep.caps); + aep.bAutoExposurePriority = 0; + aep.req = AEP_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_PRIORITY, &aep, sizeof (struct ct_aep))) + { + info_msg("*** UVC GET exposure priority mode is error \n"); + return; + } + info_msg("*** UVC current exposure priority is 0x%x \n", aep.bAutoExposurePriority); + + aep.bAutoExposurePriority = EXPOSURE_FRAME_RATE_CONSTANT; + aep.req = AEP_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_PRIORITY, &aep, sizeof (struct ct_aep))) + { + info_msg("*** UVC SET exposure priority is error, camera is not in Auto Mode or Shuttter Priority Mode \n"); + return; + } + + info_msg("*** UVC test verfication \n"); + aep.bAutoExposurePriority = 0; + aep.req = AEP_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_PRIORITY, &aep, sizeof (struct ct_aep))) + { + info_msg("*** UVC GET exposure priority is error \n"); + return; + } + + info_msg("*** UVC current exposure priority is 0x%x \n", aep.bAutoExposurePriority); + info_msg("*** UVC test pass \n"); +} + +static void uvc_exposure_time_test(uint32_t cam_idx) +{ + struct ct_eta eta; + + info_msg("*** UVC test exposure time \n"); + eta.caps = 0; + eta.req = ETA_GET_CAP; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_ABSOLUTE, &eta, sizeof (struct ct_eta))) + { + info_msg("*** UVC exposure time is not supported \n"); + return; + } + info_msg("*** UVC exposure priority time caps is 0x%x\n", eta.caps); + + eta.bExposureTimeAbsolute = 0; + eta.req = ETA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_ABSOLUTE, &eta, sizeof (struct ct_eta))) + { + info_msg("*** UVC exposure time is not supported \n"); + return; + } + info_msg("*** UVC default exposure priority time is 0x%x\n", eta.bExposureTimeAbsolute); + + eta.bExposureTimeAbsolute = 0; + eta.req = ETA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_ABSOLUTE, &eta, sizeof (struct ct_eta))) + { + info_msg("*** UVC exposure time is not supported \n"); + return; + } + info_msg("*** UVC current exposure priority time is 0x%x\n", eta.bExposureTimeAbsolute); + + eta.bExposureTimeAbsolute = 0; + eta.req = ETA_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_ABSOLUTE, &eta, sizeof (struct ct_eta))) + { + info_msg("*** UVC exposure time is not supported \n"); + return; + } + info_msg("*** UVC min exposure priority time is 0x%x\n", eta.bExposureTimeAbsolute); + + eta.bExposureTimeAbsolute = 0; + eta.req = ETA_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_ABSOLUTE, &eta, sizeof (struct ct_eta))) + { + info_msg("*** UVC exposure time is not supported \n"); + return; + } + info_msg("*** UVC max exposure priority time is 0x%x\n", eta.bExposureTimeAbsolute); + + eta.bExposureTimeAbsolute = 0; + eta.req = ETA_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_ABSOLUTE, &eta, sizeof (struct ct_eta))) + { + info_msg("*** UVC resolution is not supported \n"); + return; + } + info_msg("*** UVC exposure priority resolution is 0x%x\n", eta.bExposureTimeAbsolute); + + + eta.bExposureTimeAbsolute = 4; + if (!(eta.caps & 0x2)) + { + info_msg("*** UVC set exposure time not support \n"); + return; + } + eta.bExposureTimeAbsolute = 4; + eta.req = ETA_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_ABSOLUTE, &eta, sizeof (struct ct_eta))) + { + info_msg("*** UVC set exposure time error , camera is not in Auto Mode or Shuttter Priority Mode\n"); + return; + } + + eta.bExposureTimeAbsolute = 0; + eta.req = ETA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_AUTO_EXPOSURE_MODE, &eta, sizeof (struct ct_eta))) + { + info_msg("*** UVC get exposure time error \n"); + return; + } + info_msg("*** UVC exposure time is 0x%x \n", eta.bExposureTimeAbsolute); + info_msg("*** UVC test pass \n"); +} + +static void uvc_shutter_speed_test(int cam_idx) +{ + struct ct_etr etr; + + info_msg("*** UVC test shutter speed \n"); + etr.caps = 0; + etr.req = ETR_GET_CAP; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_RELATIVE, &etr, sizeof (struct ct_etr))) + { + info_msg("*** UVC shutter speed is not supported \n"); + return; + } + info_msg("*** UVC shutter speed caps is 0x%x\n", etr.caps); + + etr.bExposureTimeRelative = 0; + etr.req = ETR_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_RELATIVE, &etr, sizeof (struct ct_etr))) + { + info_msg("*** UVC shutter speed is not supported \n"); + return; + } + info_msg("*** UVC shutter speed is 0x%x\n", etr.bExposureTimeRelative); + + etr.bExposureTimeRelative = 0xFF; + etr.req = ETR_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_RELATIVE, &etr, sizeof (struct ct_etr))) + { + info_msg("*** UVC shutter speed is not supported \n"); + return; + } + etr.bExposureTimeRelative = 0; + etr.req = ETR_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_EXPOSURE_TIME_RELATIVE, &etr, sizeof (struct ct_etr))) + { + info_msg("*** UVC shutter speed is not supported \n"); + return; + } + info_msg("*** UVC shutter speed is 0x%x\n", etr.bExposureTimeRelative); + info_msg("*** UVC test pass \n"); +} + + +static void uvc_focus_absolute_test(uint32_t cam_idx) +{ + struct ct_focus_a focus; + info_msg("*** UVC test focues absolute focus \n"); + + focus.caps = 0; + focus.req = FA_GET_CAP; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_ABSOLUTE, &focus, sizeof (struct ct_focus_a))) + { + info_msg("*** UVC focus absolute is not supported \n"); + return; + } + info_msg("*** UVC focus absolute caps is 0x%x\n", focus.caps); + + focus.wFocusAbsolute = 0; + focus.req = FA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_ABSOLUTE, &focus, sizeof (struct ct_focus_a))) + { + info_msg("*** UVC focus absolute is not supported \n"); + return; + } + info_msg("*** UVC default focus absolute is 0x%x\n", focus.wFocusAbsolute); + + focus.wFocusAbsolute = 0; + focus.req = FA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_ABSOLUTE, &focus, sizeof (struct ct_focus_a))) + { + info_msg("*** UVC focus absolute is not supported \n"); + return; + } + info_msg("*** UVC current focus absolute is 0x%x\n", focus.wFocusAbsolute); + + focus.wFocusAbsolute = 0; + focus.req = FA_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_ABSOLUTE, &focus, sizeof (struct ct_focus_a))) + { + info_msg("*** UVC focus absolute is not supported \n"); + return; + } + info_msg("*** UVC min focus absolute is 0x%x\n", focus.wFocusAbsolute); + + focus.wFocusAbsolute = 0; + focus.req = FA_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_ABSOLUTE, &focus, sizeof (struct ct_focus_a))) + { + info_msg("*** UVC focus absolute is not supported \n"); + return; + } + info_msg("*** UVC maximum focus absolute is 0x%x\n", focus.wFocusAbsolute); + + focus.wFocusAbsolute = 0; + focus.req = FA_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_ABSOLUTE, &focus, sizeof (struct ct_focus_a))) + { + info_msg("*** UVC focus resolution is not supported \n"); + return; + } + info_msg("*** UVC focus absolute resolution is 0x%x\n", focus.wFocusAbsolute); + if (!(focus.caps & 0x2)) + { + info_msg("*** UVC set exposure time not support \n"); + return; + } + focus.wFocusAbsolute = 2; + focus.req = FA_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_ABSOLUTE, &focus, sizeof (struct ct_focus_a))) + { + info_msg("*** UVC camera is auto-focus mode \n"); + return; + } + focus.wFocusAbsolute = 0; + focus.req = FA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_ABSOLUTE, &focus, sizeof (struct ct_focus_a))) + { + info_msg("*** UVC GET focus absolute \n"); + return; + } + info_msg("*** UVC current focus absolute is 0x%x \n", focus.wFocusAbsolute); + info_msg("*** UVC test pass \n"); +} + +static void uvc_focus_relative_test(int cam_idx) +{ + struct ct_focus_r focus_r; + + info_msg("*** UVC test focus relative length \n"); + + focus_r.req = FR_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_RELATIVE, &focus_r, sizeof (struct ct_focus_r))) + { + info_msg("*** UVC focus relative is not supported \n"); + return; + } + info_msg("*** UVC focus relative cap is 0x%x\n", focus_r.caps); + + focus_r.data.bFocusRelative = 0; + focus_r.data.bSpeed = 0; + focus_r.req = FR_GET_DEF; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_RELATIVE, &focus_r, sizeof (struct ct_focus_r))) + { + info_msg("*** UVC GET current focus relative is error \n"); + return; + } + info_msg("*** UVC default focus relative is 0x%x\n", focus_r.data.bFocusRelative); + info_msg("*** UVC default Speed is 0x%x\n", focus_r.data.bSpeed); + + + focus_r.data.bFocusRelative = 0; + focus_r.data.bSpeed = 0; + focus_r.req = FR_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_RELATIVE, &focus_r, sizeof (struct ct_focus_r))) + { + info_msg("*** UVC GET current focus relative is error \n"); + return; + } + info_msg("*** UVC current focus relative is 0x%x\n", focus_r.data.bFocusRelative); + info_msg("*** UVC current Speed is 0x%x\n", focus_r.data.bSpeed); + + focus_r.data.bFocusRelative = 0; + focus_r.data.bSpeed = 0; + focus_r.req = FR_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_RELATIVE, &focus_r, sizeof (struct ct_focus_r))) + { + info_msg("*** UVC GET current focus relative is error \n"); + return; + } + info_msg("*** UVC Mim focus relative is 0x%x\n", focus_r.data.bFocusRelative); + info_msg("*** UVC Mim Speed is 0x%x\n", focus_r.data.bSpeed); + + focus_r.data.bFocusRelative = 0; + focus_r.data.bSpeed = 0; + focus_r.req = FR_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_RELATIVE, &focus_r, sizeof (struct ct_focus_r))) + { + info_msg("*** UVC GET current focus relative is error \n"); + return; + } + info_msg("*** UVC Max focus relative is 0x%x\n", focus_r.data.bFocusRelative); + info_msg("*** UVC Max Speed is 0x%x\n", focus_r.data.bSpeed); + + focus_r.data.bFocusRelative = 0; + focus_r.data.bSpeed = 0; + focus_r.req = FR_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_RELATIVE, &focus_r, sizeof (struct ct_focus_r))) + { + info_msg("*** UVC GET current focus resolution is error \n"); + return; + } + info_msg("*** UVC focus relative resolution is 0x%x\n", focus_r.data.bFocusRelative); + info_msg("*** UVC Speed resolution is 0x%x\n", focus_r.data.bSpeed); + + focus_r.data.bFocusRelative = 0xFF; + focus_r.data.bSpeed = 1; + focus_r.req = FR_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_RELATIVE, &focus_r, sizeof (struct ct_focus_r))) + { + info_msg("*** UVC SET focus relative is error \n"); + return; + } + + info_msg("*** UVC test verfication \n"); + focus_r.data.bFocusRelative = 0xFF; + focus_r.data.bSpeed = 1; + focus_r.req = FR_GET_CUR; + + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_RELATIVE, &focus_r, sizeof (struct ct_focus_r))) + { + info_msg("*** UVC GET focus relative is error \n"); + return; + } + + info_msg("*** UVC current focus relative is 0x%x \n", focus_r.data.bFocusRelative); + info_msg("*** UVC current speed is 0x%x \n", focus_r.data.bSpeed); + info_msg("*** UVC test pass \n"); + +} + +static void uvc_focus_len_range_test(int cam_idx) +{ + struct ct_focus_sr focus_sr; + info_msg("*** UVC test focus len range \n"); + + focus_sr.req = FSR_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_SIMPLE, &focus_sr, sizeof (struct ct_focus_sr))) + { + info_msg("*** UVC focus len range is not supported \n"); + return; + } + info_msg("*** UVC focus len range cap is 0x%x\n", focus_sr.caps); + focus_sr.bFocus = 0; + focus_sr.req = FSR_GET_DEF; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_SIMPLE, &focus_sr, sizeof (struct ct_focus_sr))) + { + info_msg("*** UVC GET current focus len range is error \n"); + return; + } + info_msg("*** UVC focus len range is 0x%x\n", focus_sr.bFocus); + + focus_sr.bFocus = 0; + focus_sr.req = FSR_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_SIMPLE, &focus_sr, sizeof (struct ct_focus_sr))) + { + info_msg("*** UVC GET current focus len range is error \n"); + return; + } + info_msg("*** UVC focus len range is 0x%x\n", focus_sr.bFocus); + + focus_sr.bFocus = FSR_FULL_RANGE; + focus_sr.req = FSR_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_SIMPLE, &focus_sr, sizeof (struct ct_focus_sr))) + { + info_msg("*** UVC SET current focus len range is error \n"); + return; + } + + info_msg("*** UVC test verfication \n"); + focus_sr.bFocus = 0; + focus_sr.req = FSR_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_SIMPLE, &focus_sr, sizeof (struct ct_focus_sr))) + { + info_msg("*** UVC SET current focus len range is error \n"); + return; + } + + info_msg("*** UVC current focus len range is 0x%x \n", focus_sr.bFocus); + info_msg("*** UVC test pass \n"); +} + +static void uvc_focus_auto_test(int cam_idx) +{ + struct ct_fauto fauto; + info_msg("*** UVC test focus auto \n"); + + fauto.req = FAUTO_GET_CAP; + fauto.caps = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_AUTO, &fauto, sizeof (struct ct_fauto))) + { + info_msg("*** UVC focus auto is not supported \n"); + return; + } + info_msg("*** UVC focus auto cap is 0x%x\n", fauto.caps); + + fauto.bFocusAuto = 0; + fauto.req = FAUTO_GET_DEF; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_AUTO, &fauto, sizeof (struct ct_fauto))) + { + info_msg("*** UVC GET default focus is error \n"); + return; + } + info_msg("*** UVC default focus auto is 0x%x\n", fauto.bFocusAuto); + fauto.bFocusAuto = 0; + fauto.req = FAUTO_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_AUTO, &fauto, sizeof (struct ct_fauto))) + { + info_msg("*** UVC GET current focus len range is error \n"); + return; + } + info_msg("*** UVC current focus auto is 0x%x\n", fauto.bFocusAuto); + fauto.bFocusAuto = 1; + fauto.req = FAUTO_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_AUTO, &fauto, sizeof (struct ct_fauto))) + { + info_msg("*** UVC SET current focus is error \n"); + return; + } + + info_msg("*** UVC test verfication \n"); + fauto.bFocusAuto = 0; + fauto.req = FAUTO_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_FOCUS_AUTO, &fauto, sizeof (struct ct_fauto))) + { + info_msg("*** UVC GET current focus is error \n"); + return; + } + info_msg("*** UVC current focus auto is 0x%x\n", fauto.bFocusAuto); + info_msg("*** UVC test pass \n"); +} + + +static void uvc_iris_absolute_test(int cam_idx) +{ + struct ct_iris_a iris; + info_msg("*** UVC test aperture setting\n"); + + iris.req = IRISA_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_ABSOLUTE, &iris, sizeof (struct ct_iris_a))) + { + info_msg("*** UVC iris absolute is not supported \n"); + return; + } + info_msg("*** UVC iris absolute cap is 0x%x\n", iris.caps); + iris.wIrisAbsolute = 0; + iris.req = IRISA_GET_RES; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_ABSOLUTE, &iris, sizeof (struct ct_iris_a))) + { + info_msg("*** UVC GET iris resolution is error \n"); + return; + } + info_msg("*** UVC iris absolute resolution is 0x%x\n", iris.wIrisAbsolute); + + iris.wIrisAbsolute = 0; + iris.req = IRISA_GET_DEF; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_ABSOLUTE, &iris, sizeof (struct ct_iris_a))) + { + info_msg("*** UVC GET default iris is error \n"); + return; + } + info_msg("*** UVC default iris absolute is 0x%x\n", iris.wIrisAbsolute); + + iris.wIrisAbsolute = 0; + iris.req = IRISA_GET_MIN; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_ABSOLUTE, &iris, sizeof (struct ct_iris_a))) + { + info_msg("*** UVC GET iris min is error \n"); + return; + } + info_msg("*** UVC min iris absolute is 0x%x\n", iris.wIrisAbsolute); + + iris.wIrisAbsolute = 0; + iris.req = IRISA_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_ABSOLUTE, &iris, sizeof (struct ct_iris_a))) + { + info_msg("*** UVC GET iris max is error \n"); + return; + } + info_msg("*** UVC max iris absolute is 0x%x\n", iris.wIrisAbsolute); + + iris.wIrisAbsolute = 0; + iris.req = IRISA_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_ABSOLUTE, &iris, sizeof (struct ct_iris_a))) + { + info_msg("*** UVC GET current iris is error \n"); + return; + } + info_msg("*** UVC current iris absolute is 0x%x\n", iris.wIrisAbsolute); + if (!(iris.caps & 0x2)) + { + info_msg("*** UVC set iris absolute is not supported \n"); + return; + } + iris.wIrisAbsolute = 0; + iris.req = IRISA_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_ABSOLUTE, &iris, sizeof (struct ct_iris_a))) + { + info_msg("*** UVC GET current iris is error \n"); + return; + } + + info_msg("*** UVC test verfication \n"); + iris.wIrisAbsolute = 0; + iris.req = IRISA_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_ABSOLUTE, &iris, sizeof (struct ct_iris_a))) + { + info_msg("*** UVC GET current iris is error \n"); + return; + } + info_msg("*** UVC current iris is 0x%x \n", iris.wIrisAbsolute); + + info_msg("*** UVC test pass \n"); +} + +static void uvc_iris_relative_test(int cam_idx) +{ + struct ct_iris_r iris; + info_msg("*** UVC test iris relative\n"); + + iris.req = IRISR_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_RELATIVE, &iris, sizeof (struct ct_iris_r))) + { + info_msg("*** UVC iris relative is not supported \n"); + return; + } + info_msg("*** UVC iris relative caps is 0x%x\n", iris.caps); + iris.bIrisRelative = 0; + iris.req = IRISR_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_RELATIVE, &iris, sizeof (struct ct_iris_r))) + { + info_msg("*** UVC GET iris relative is error \n"); + return; + } + info_msg("*** UVC current iris is 0x%x \n", iris.bIrisRelative); + iris.bIrisRelative = 0xFF; + iris.req = IRISR_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_RELATIVE, &iris, sizeof (struct ct_iris_r))) + { + info_msg("*** UVC SET iris relative is error \n"); + return; + } + + info_msg("*** UVC test verfication \n"); + iris.bIrisRelative = 0x0; + iris.req = IRISR_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_IRIS_RELATIVE, &iris, sizeof (struct ct_iris_r))) + { + info_msg("*** UVC GET iris relative is error \n"); + return; + } + + info_msg("*** UVC iris relative is 0x%x \n", iris.bIrisRelative); + info_msg("*** UVC test pass \n"); +} + +static void uvc_zoom_absolute_test(int cam_idx) +{ + struct ct_zoom_a zoom; + info_msg("*** UVC test zoom absolute \n"); + + zoom.caps = 0; + zoom.req = ZOOMA_GET_CAP; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_ABSOLUTE, &zoom, sizeof (struct ct_zoom_a))) + { + info_msg("*** UVC zoom absolute is not supported \n"); + return; + } + info_msg("*** UVC zoom absolute cap is 0x%x\n", zoom.caps); + + zoom.wObjectiveFocalLength = 0; + zoom.req = ZOOMA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_ABSOLUTE, &zoom, sizeof (struct ct_zoom_a))) + { + info_msg("*** UVC GET default zoom absolute is error \n"); + return; + } + info_msg("*** UVC GET default zoom is 0x%x\n", zoom.wObjectiveFocalLength); + + zoom.wObjectiveFocalLength = 0; + zoom.req = ZOOMA_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_ABSOLUTE, &zoom, sizeof (struct ct_zoom_a))) + { + info_msg("*** UVC GET min zoom absolute is error \n"); + return; + } + info_msg("*** UVC GET min zoom absolute is 0x%x\n", zoom.wObjectiveFocalLength); + + zoom.wObjectiveFocalLength = 0; + zoom.req = ZOOMA_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_ABSOLUTE, &zoom, sizeof (struct ct_zoom_a))) + { + info_msg("*** UVC max zoom absolute is error \n"); + return; + } + info_msg("*** UVC GET max zoom absolute is 0x%x\n", zoom.wObjectiveFocalLength); + zoom.wObjectiveFocalLength = 0; + zoom.req = ZOOMA_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_ABSOLUTE, &zoom, sizeof (struct ct_zoom_a))) + { + info_msg("*** UVC resolution zoom absolute is error \n"); + return; + } + info_msg("*** UVC zoom absolute resolution is 0x%x \n", zoom.wObjectiveFocalLength); + + if (!(zoom.caps & 0x2)) + { + info_msg("*** UVC set exposure time not support \n"); + return; + } + zoom.wObjectiveFocalLength = 0; + zoom.req = ZOOMA_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_ABSOLUTE, &zoom, sizeof (struct ct_zoom_a))) + { + info_msg("*** UVC SET zoom absolute is error \n"); + return; + } + info_msg("*** UVC current zoom absolute is 0x%x \n", zoom.wObjectiveFocalLength); + zoom.wObjectiveFocalLength = 2; + zoom.req = ZOOMA_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_ABSOLUTE, &zoom, sizeof (struct ct_zoom_a))) + { + info_msg("*** UVC SET zoom absolute is error \n"); + return; + } + + info_msg("*** UVC test verfication \n"); + zoom.wObjectiveFocalLength = 0; + zoom.req = ZOOMA_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_ABSOLUTE, &zoom, sizeof (struct ct_zoom_a))) + { + info_msg("*** UVC SET zoom absolute is error \n"); + return; + } + info_msg("*** UVC current zoom absolute is 0x%x \n", zoom.wObjectiveFocalLength); + + info_msg("*** UVC test pass \n"); +} + +static void uvc_zoom_relative_test(int cam_idx) +{ + struct ct_zoom_r zoom; + + info_msg("*** UVC test zoom relative \n"); + + zoom.req = ZOOMR_GET_CAP; + zoom.caps = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_RELATIVE, &zoom, sizeof (struct ct_zoom_r))) + { + info_msg("*** UVC zoom relative is not supported \n"); + return; + } + info_msg("*** UVC zoom relative cap is 0x%x\n", zoom.caps); + + zoom.req = ZOOMR_GET_DEF; + zoom.data.bDigitalZoom = 0; + zoom.data.bSpeed = 0; + zoom.data.bZoom = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_RELATIVE, &zoom, sizeof (struct ct_zoom_r))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + info_msg("*** UVC default bDigitalZoom is 0x%x\n", zoom.data.bDigitalZoom); + info_msg("*** UVC default bSpeed is 0x%x\n", zoom.data.bSpeed); + info_msg("*** UVC default bZoom is 0x%x\n", zoom.data.bZoom); + + zoom.req = ZOOMR_GET_MIN; + zoom.data.bDigitalZoom = 0; + zoom.data.bSpeed = 0; + zoom.data.bZoom = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_RELATIVE, &zoom, sizeof (struct ct_zoom_r))) + { + info_msg("*** UVC GET min zoom relative is error \n"); + return; + } + info_msg("*** UVC min bDigitalZoom is 0x%x\n", zoom.data.bDigitalZoom); + info_msg("*** UVC min bSpeed is 0x%x\n", zoom.data.bSpeed); + info_msg("*** UVC min bZoom is 0x%x\n", zoom.data.bZoom); + + zoom.req = ZOOMR_GET_MAX; + zoom.data.bDigitalZoom = 0; + zoom.data.bSpeed = 0; + zoom.data.bZoom = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_RELATIVE, &zoom, sizeof (struct ct_zoom_r))) + { + info_msg("*** UVC GET max zoom relative is error \n"); + return; + } + info_msg("*** UVC max bDigitalZoom is 0x%x\n", zoom.data.bDigitalZoom); + info_msg("*** UVC max bSpeed is 0x%x\n", zoom.data.bSpeed); + info_msg("*** UVC max bZoom is 0x%x\n", zoom.data.bZoom); + + zoom.req = ZOOMR_GET_RES; + zoom.data.bDigitalZoom = 0; + zoom.data.bSpeed = 0; + zoom.data.bZoom = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_RELATIVE, &zoom, sizeof (struct ct_zoom_r))) + { + info_msg("*** UVC GET max zoom resolution is error \n"); + return; + } + info_msg("*** UVC bDigitalZoom resolution is 0x%x\n", zoom.data.bDigitalZoom); + info_msg("*** UVC bSpeed resolution is 0x%x\n", zoom.data.bSpeed); + info_msg("*** UVC bZoom resolution is 0x%x\n", zoom.data.bZoom); + + zoom.req = ZOOMR_SET_CUR; + zoom.data.bDigitalZoom = 1; + zoom.data.bSpeed = 1; + zoom.data.bZoom = 1; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_RELATIVE, &zoom, sizeof (struct ct_zoom_r))) + { + info_msg("*** UVC GET max zoom relative is error \n"); + return; + } + info_msg("*** UVC test verfication \n"); + zoom.req = ZOOMR_GET_CUR; + zoom.data.bDigitalZoom = 0; + zoom.data.bSpeed = 0; + zoom.data.bZoom = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ZOOM_RELATIVE, &zoom, sizeof (struct ct_zoom_r))) + { + info_msg("*** UVC SET current scanning mode is error \n"); + return; + } + info_msg("*** UVC bDigitalZoom resolution is 0x%x\n", zoom.data.bDigitalZoom); + info_msg("*** UVC bSpeed resolution is 0x%x\n", zoom.data.bSpeed); + info_msg("*** UVC bZoom resolution is 0x%x\n", zoom.data.bZoom); + info_msg("*** UVC test pass \n"); +} + +static void uvc_pan_tilt_absolute_test(int cam_idx) +{ + struct ct_pan_tilt_a pan_tilt; + info_msg("*** UVC test pan tilt absolute \n"); + + pan_tilt.req = TILTA_GET_CAP; + pan_tilt.caps = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_ABSOLUTE, &pan_tilt, sizeof (struct ct_pan_tilt_a))) + { + info_msg("*** UVC pan tilt is not supported \n"); + return; + } + info_msg("*** UVC pan tilt cap is 0x%x\n", pan_tilt.caps); + + pan_tilt.data.dwPanAbsolute = 0; + pan_tilt.data.dwTiltAbsolute = 0; + pan_tilt.req = TILTA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_ABSOLUTE, &pan_tilt, sizeof (struct ct_pan_tilt_a))) + { + info_msg("*** UVC GET default pan tilt test is error \n"); + return; + } + info_msg("*** UVC default pan tilt dwPanAbsolute is 0x%x\n", pan_tilt.data.dwPanAbsolute); + info_msg("*** UVC default pan tilt dwTiltAbsolute is 0x%x\n", pan_tilt.data.dwTiltAbsolute); + pan_tilt.data.dwPanAbsolute = 0; + pan_tilt.data.dwTiltAbsolute = 0; + pan_tilt.req = TILTA_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_ABSOLUTE, &pan_tilt, sizeof (struct ct_pan_tilt_a))) + { + info_msg("*** UVC GET min pan tilt test is error \n"); + return; + } + info_msg("*** UVC min pan tilt dwPanAbsolute is 0x%x\n", pan_tilt.data.dwPanAbsolute); + info_msg("*** UVC min pan tilt dwTiltAbsolute is 0x%x\n", pan_tilt.data.dwTiltAbsolute); + pan_tilt.data.dwPanAbsolute = 0; + pan_tilt.data.dwTiltAbsolute = 0; + pan_tilt.req = TILTA_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_ABSOLUTE, &pan_tilt, sizeof (struct ct_pan_tilt_a))) + { + info_msg("*** UVC GET max pan tilt test error \n"); + return; + } + info_msg("*** UVC max pan tilt dwPanAbsolute is 0x%x\n", pan_tilt.data.dwPanAbsolute); + info_msg("*** UVC max pan tilt dwTiltAbsolute is 0x%x\n", pan_tilt.data.dwTiltAbsolute); + pan_tilt.data.dwPanAbsolute = 0; + pan_tilt.data.dwTiltAbsolute = 0; + pan_tilt.req = TILTA_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_ABSOLUTE, &pan_tilt, sizeof (struct ct_pan_tilt_a))) + { + info_msg("*** UVC GET pan tilt resolution is error \n"); + return; + } + info_msg("*** UVC resulotion pan tilt dwPanAbsolute is 0x%x\n", pan_tilt.data.dwPanAbsolute); + info_msg("*** UVC resulotion pan tilt dwTiltAbsolute is 0x%x\n", pan_tilt.data.dwTiltAbsolute); + pan_tilt.data.dwPanAbsolute = 0; + pan_tilt.data.dwTiltAbsolute = 0; + pan_tilt.req = TILTA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_ABSOLUTE, &pan_tilt, sizeof (struct ct_pan_tilt_a))) + { + info_msg("*** UVC GET current pan tilt is error \n"); + return; + } + info_msg("*** UVC current pan tilt dwPanAbsolute is 0x%x\n", pan_tilt.data.dwPanAbsolute); + info_msg("*** UVC current pan tilt dwTiltAbsolute is 0x%x\n", pan_tilt.data.dwTiltAbsolute); + + info_msg("*** UVC test verfication \n"); + if (!(pan_tilt.caps & 0x2)) + { + info_msg("*** UVC set exposure time not support \n"); + return; + } + pan_tilt.data.dwPanAbsolute = 1; + pan_tilt.data.dwTiltAbsolute = 1; + pan_tilt.req = TILTA_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_ABSOLUTE, &pan_tilt, sizeof (struct ct_pan_tilt_a))) + { + info_msg("*** UVC SET pan tilt is error \n"); + return; + } + + + pan_tilt.data.dwPanAbsolute = 0; + pan_tilt.data.dwTiltAbsolute = 0; + + pan_tilt.req = TILTA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_ABSOLUTE, &pan_tilt, sizeof (struct ct_pan_tilt_a))) + { + info_msg("*** UVC SET current scanning mode is error \n"); + return; + } + info_msg("*** UVC current pan tilt dwPanAbsolute is 0x%x\n", pan_tilt.data.dwPanAbsolute); + info_msg("*** UVC current pan tilt dwTiltAbsolute is 0x%x\n", pan_tilt.data.dwTiltAbsolute); + info_msg("*** UVC test pass \n"); +} + +static void uvc_pan_tilt_direction_test(int cam_idx) +{ + struct ct_pan_tilt_r pan_tilt; + + info_msg("*** UVC test set pan_tilt direction \n"); + + pan_tilt.caps = 0; + pan_tilt.req = TILTR_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_RELATIVE, &pan_tilt, sizeof (struct ct_pan_tilt_r))) + { + info_msg("*** UVC pan tilt is not supported \n"); + return; + } + info_msg("*** UVC pan tilt cap is 0x%x\n", pan_tilt.caps); + + pan_tilt.data.bPanRelative = 0; + pan_tilt.data.bPanSpeed = 0; + pan_tilt.data.bTiltRelative = 0; + pan_tilt.data.bTiltSpeed = 0; + pan_tilt.req = TILTR_GET_DEF; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_RELATIVE, &pan_tilt, sizeof (struct ct_pan_tilt_r))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + + pan_tilt.data.bPanRelative = 0; + pan_tilt.data.bPanSpeed = 0; + pan_tilt.data.bTiltRelative = 0; + pan_tilt.data.bTiltSpeed = 0; + pan_tilt.req = TILTR_GET_MIN; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_RELATIVE, &pan_tilt, sizeof (struct ct_pan_tilt_r))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + + pan_tilt.data.bPanRelative = 0; + pan_tilt.data.bPanSpeed = 0; + pan_tilt.data.bTiltRelative = 0; + pan_tilt.data.bTiltSpeed = 0; + pan_tilt.req = TILTR_GET_MAX; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_RELATIVE, &pan_tilt, sizeof (struct ct_pan_tilt_r))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + + pan_tilt.data.bPanRelative = 0; + pan_tilt.data.bPanSpeed = 0; + pan_tilt.data.bTiltRelative = 0; + pan_tilt.data.bTiltSpeed = 0; + pan_tilt.req = TILTR_GET_RES; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_RELATIVE, &pan_tilt, sizeof (struct ct_pan_tilt_r))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + + pan_tilt.data.bPanRelative = 0; + pan_tilt.data.bPanSpeed = 0; + pan_tilt.data.bTiltRelative = 0; + pan_tilt.data.bTiltSpeed = 0; + pan_tilt.req = TILTR_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_RELATIVE, &pan_tilt, sizeof (struct ct_pan_tilt_r))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + + pan_tilt.data.bPanRelative = 1; + pan_tilt.data.bPanSpeed = 2; + pan_tilt.data.bTiltRelative = 3; + pan_tilt.data.bTiltSpeed = 4; + pan_tilt.req = TILTR_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_RELATIVE, &pan_tilt, sizeof (struct ct_pan_tilt_r))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + info_msg("*** UVC test verfication \n"); + pan_tilt.data.bPanRelative = 0; + pan_tilt.data.bPanSpeed = 0; + pan_tilt.data.bTiltRelative = 0; + pan_tilt.data.bTiltSpeed = 0; + pan_tilt.req = TILTR_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_PANTILT_RELATIVE, &pan_tilt, sizeof (struct ct_pan_tilt_r))) + { + info_msg("*** UVC GET current scanning mode is error \n"); + return; + } + info_msg("*** UVC test pass \n"); +} + +static void uvc_roll_test(int cam_idx) +{ + struct ct_roll_a roll; + + info_msg("*** UVC test roll \n"); + + roll.req = ROLLA_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_ABSOLUTE, &roll, sizeof (struct ct_roll_a))) + { + info_msg("*** UVC roll is not supported \n"); + return; + } + info_msg("*** UVC roll cap is 0x%x\n", roll.caps); + + roll.wAbsolute = 0; + roll.req = ROLLA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_ABSOLUTE, &roll, sizeof (struct ct_roll_a))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC default roll is 0x%x\n", roll.wAbsolute); + roll.wAbsolute = 0; + roll.req = ROLLA_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_ABSOLUTE, &roll, sizeof (struct ct_roll_a))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC min roll is 0x%x\n", roll.wAbsolute); + roll.wAbsolute = 0; + roll.req = ROLLA_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_ABSOLUTE, &roll, sizeof (struct ct_roll_a))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC max roll is 0x%x\n", roll.wAbsolute); + roll.wAbsolute = 0; + roll.req = ROLLA_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_ABSOLUTE, &roll, sizeof (struct ct_roll_a))) + { + info_msg("*** UVC GET resolution roll is error \n"); + return; + } + info_msg("*** UVC resolution roll is 0x%x\n", roll.wAbsolute); + roll.wAbsolute = 0; + roll.req = ROLLA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_ABSOLUTE, &roll, sizeof (struct ct_roll_a))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC current roll is 0x%x\n", roll.wAbsolute); + if (!(roll.caps & 0x2)) + { + info_msg("*** UVC set roll supported \n"); + return; + } + roll.wAbsolute = 1; + roll.req = ROLLA_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_ABSOLUTE, &roll, sizeof (struct ct_roll_a))) + { + info_msg("*** UVC SET set curret is error \n"); + return; + } + + roll.wAbsolute = 0; + roll.req = ROLLA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_ABSOLUTE, &roll, sizeof (struct ct_roll_a))) + { + info_msg("*** UVC GET current roll is error \n"); + return; + } + info_msg("*** UVC current roll is 0x%x\n", roll.wAbsolute); + info_msg("*** UVC test pass \n"); +} + +static void uvc_roll_direction_test(int cam_idx) +{ + struct ct_roll_r roll; + roll.req = ROLLR_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC roll relative is not supported \n"); + return; + } + info_msg("*** UVC roll cap is 0x%x\n", roll.caps); + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll relative is error \n"); + return; + } + info_msg("*** UVC default roll bRollRelative is 0x%x\n", roll.data.bRollRelative); + info_msg("*** UVC default roll bSpeed is 0x%x\n", roll.data.bSpeed); + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET min roll is error \n"); + return; + } + info_msg("*** UVC min roll bRollRelative is 0x%x\n", roll.data.bRollRelative); + info_msg("*** UVC min roll bSpeed is 0x%x\n", roll.data.bSpeed); + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET max roll is error \n"); + return; + } + info_msg("*** UVC max roll bRollRelative is 0x%x\n", roll.data.bRollRelative); + info_msg("*** UVC max roll bSpeed is 0x%x\n", roll.data.bSpeed); + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET resolution roll is error \n"); + return; + } + info_msg("*** UVC default resolution bRollRelative is 0x%x\n", roll.data.bRollRelative); + info_msg("*** UVC default resolution bSpeed is 0x%x\n", roll.data.bSpeed); + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET currnt roll is error \n"); + return; + } + info_msg("*** UVC current bRollRelative is 0x%x\n", roll.data.bRollRelative); + info_msg("*** UVC current bSpeed is 0x%x\n", roll.data.bSpeed); + roll.data.bRollRelative = 1; + roll.data.bSpeed = 1; + roll.req = ROLLR_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC current bRollRelative is 0x%x\n", roll.data.bRollRelative); + info_msg("*** UVC current bSpeed is 0x%x\n", roll.data.bSpeed); + info_msg("*** UVC test pass \n"); +} + +static void uvc_shutter_test(int cam_idx) +{ + struct ct_roll_r roll; + roll.req = ROLLR_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC roll is not supported \n"); + return; + } + info_msg("*** UVC roll cap is 0x%x\n", roll.caps); + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET resolution roll is error \n"); + return; + } + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + roll.data.bRollRelative = 1; + roll.data.bSpeed = 1; + roll.req = ROLLR_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + roll.data.bRollRelative = 0; + roll.data.bSpeed = 0; + roll.req = ROLLR_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_ROLL_RELATIVE, &roll, sizeof (struct ct_roll_r))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC test pass \n"); +} + + +static void uvc_digital_windows_test(int cam_idx) +{ + struct ct_dwindow dwindow; + + dwindow.data.wWindow_Top = 0; + dwindow.data.wWindow_Left = 0; + dwindow.data.wWindow_Bottom = 0; + dwindow.data.wWindow_Right = 0; + dwindow.data.wNumSteps = 0; + dwindow.data.bmNumStepsUnits = 0; + dwindow.req = DWINDOW_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_WINDOW, &dwindow, sizeof (struct ct_dwindow))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC default wWindow_Top is 0x%x\n", dwindow.data.wWindow_Top); + info_msg("*** UVC default wWindow_Left is 0x%x\n", dwindow.data.wWindow_Left); + info_msg("*** UVC default wWindow_Bottom is 0x%x\n", dwindow.data.wWindow_Bottom); + info_msg("*** UVC default wWindow_Right is 0x%x\n", dwindow.data.wWindow_Right); + info_msg("*** UVC default wNumSteps is 0x%x\n", dwindow.data.wNumSteps); + info_msg("*** UVC default bmNumStepsUnits is 0x%x\n", dwindow.data.bmNumStepsUnits); + dwindow.data.wWindow_Top = 0; + dwindow.data.wWindow_Left = 0; + dwindow.data.wWindow_Bottom = 0; + dwindow.data.wWindow_Right = 0; + dwindow.data.wNumSteps = 0; + dwindow.data.bmNumStepsUnits = 0; + dwindow.req = DWINDOW_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_WINDOW, &dwindow, sizeof (struct ct_dwindow))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + info_msg("*** UVC min wWindow_Top is 0x%x\n", dwindow.data.wWindow_Top); + info_msg("*** UVC min wWindow_Left is 0x%x\n", dwindow.data.wWindow_Left); + info_msg("*** UVC min wWindow_Bottom is 0x%x\n", dwindow.data.wWindow_Bottom); + info_msg("*** UVC min wWindow_Right is 0x%x\n", dwindow.data.wWindow_Right); + info_msg("*** UVC min wNumSteps is 0x%x\n", dwindow.data.wNumSteps); + info_msg("*** UVC min bmNumStepsUnits is 0x%x\n", dwindow.data.bmNumStepsUnits); + dwindow.req = DWINDOW_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_WINDOW, &dwindow, sizeof (struct ct_dwindow))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + info_msg("*** UVC max wWindow_Top is 0x%x\n", dwindow.data.wWindow_Top); + info_msg("*** UVC max wWindow_Left is 0x%x\n", dwindow.data.wWindow_Left); + info_msg("*** UVC max wWindow_Bottom is 0x%x\n", dwindow.data.wWindow_Bottom); + info_msg("*** UVC max wWindow_Right is 0x%x\n", dwindow.data.wWindow_Right); + info_msg("*** UVC max wNumSteps is 0x%x\n", dwindow.data.wNumSteps); + info_msg("*** UVC max bmNumStepsUnits is 0x%x\n", dwindow.data.bmNumStepsUnits); + dwindow.req = DWINDOW_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_WINDOW, &dwindow, sizeof (struct ct_dwindow))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC current wWindow_Top is 0x%x\n", dwindow.data.wWindow_Top); + info_msg("*** UVC current wWindow_Left is 0x%x\n", dwindow.data.wWindow_Left); + info_msg("*** UVC current wWindow_Bottom is 0x%x\n", dwindow.data.wWindow_Bottom); + info_msg("*** UVC current wWindow_Right is 0x%x\n", dwindow.data.wWindow_Right); + info_msg("*** UVC current wNumSteps is 0x%x\n", dwindow.data.wNumSteps); + info_msg("*** UVC current bmNumStepsUnits is 0x%x\n", dwindow.data.bmNumStepsUnits); + dwindow.data.wWindow_Top = 1; + dwindow.data.wWindow_Left = 2; + dwindow.data.wWindow_Bottom = 3; + dwindow.data.wWindow_Right = 3; + dwindow.data.wNumSteps = 1; + dwindow.data.bmNumStepsUnits = 1; + dwindow.req = DWINDOW_SET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_WINDOW, &dwindow, sizeof (struct ct_dwindow))) + { + info_msg("*** UVC SET default windows is error \n"); + return; + } + dwindow.data.wWindow_Top = 0; + dwindow.data.wWindow_Left = 0; + dwindow.data.wWindow_Bottom = 0; + dwindow.data.wWindow_Right = 0; + dwindow.data.wNumSteps = 0; + dwindow.data.bmNumStepsUnits = 0; + dwindow.req = DWINDOW_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_WINDOW, &dwindow, sizeof (struct ct_dwindow))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC current wWindow_Top is 0x%x\n", dwindow.data.wWindow_Top); + info_msg("*** UVC current wWindow_Left is 0x%x\n", dwindow.data.wWindow_Left); + info_msg("*** UVC current wWindow_Bottom is 0x%x\n", dwindow.data.wWindow_Bottom); + info_msg("*** UVC current wWindow_Right is 0x%x\n", dwindow.data.wWindow_Right); + info_msg("*** UVC current wNumSteps is 0x%x\n", dwindow.data.wNumSteps); + info_msg("*** UVC current bmNumStepsUnits is 0x%x\n", dwindow.data.bmNumStepsUnits); + info_msg("*** UVC test pass \n"); +} + +static void uvc_digital_roi_test(int cam_idx) +{ + struct ct_roi roi; + + roi.req = ROI_GET_DEF; + roi.data.wROI_Top = 0; + roi.data.wROI_Left = 0; + roi.data.wROI_Bottom = 0; + roi.data.wROI_Right = 0; + roi.data.bmAutoControls = 0; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_REGION_OF_INTEREST, &roi, sizeof (struct ct_roi))) + { + info_msg("*** UVC roll is not supported \n"); + return; + } + info_msg("*** UVC default wROI_Top is 0x%x\n", roi.data.wROI_Top); + info_msg("*** UVC default wROI_Left is 0x%x\n", roi.data.wROI_Left); + info_msg("*** UVC default wROI_Bottom is 0x%x\n", roi.data.wROI_Bottom); + info_msg("*** UVC default wROI_Right is 0x%x\n", roi.data.wROI_Right); + info_msg("*** UVC default bmAutoControls is 0x%x\n", roi.data.bmAutoControls); + + roi.req = ROI_GET_MIN; + roi.data.wROI_Top = 0; + roi.data.wROI_Left = 0; + roi.data.wROI_Bottom = 0; + roi.data.wROI_Right = 0; + roi.data.bmAutoControls = 0; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_REGION_OF_INTEREST, &roi, sizeof (struct ct_roi))) + { + info_msg("*** UVC roll is not supported \n"); + return; + } + info_msg("*** UVC min wROI_Top is 0x%x\n", roi.data.wROI_Top); + info_msg("*** UVC min wROI_Left is 0x%x\n", roi.data.wROI_Left); + info_msg("*** UVC min wROI_Bottom is 0x%x\n", roi.data.wROI_Bottom); + info_msg("*** UVC min wROI_Right is 0x%x\n", roi.data.wROI_Right); + info_msg("*** UVC min bmAutoControls is 0x%x\n", roi.data.bmAutoControls); + + roi.req = ROI_GET_MAX; + roi.data.wROI_Top = 0; + roi.data.wROI_Left = 0; + roi.data.wROI_Bottom = 0; + roi.data.wROI_Right = 0; + roi.data.bmAutoControls = 0; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_REGION_OF_INTEREST, &roi, sizeof (struct ct_roi))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC max wROI_Top is 0x%x\n", roi.data.wROI_Top); + info_msg("*** UVC max wROI_Left is 0x%x\n", roi.data.wROI_Left); + info_msg("*** UVC max wROI_Bottom is 0x%x\n", roi.data.wROI_Bottom); + info_msg("*** UVC max wROI_Right is 0x%x\n", roi.data.wROI_Right); + info_msg("*** UVC max bmAutoControls is 0x%x\n", roi.data.bmAutoControls); + + roi.req = ROI_GET_CUR; + roi.data.wROI_Top = 0; + roi.data.wROI_Left = 0; + roi.data.wROI_Bottom = 0; + roi.data.wROI_Right = 0; + roi.data.bmAutoControls = 0; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_REGION_OF_INTEREST, &roi, sizeof (struct ct_roi))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC current wROI_Top is 0x%x\n", roi.data.wROI_Top); + info_msg("*** UVC current wROI_Left is 0x%x\n", roi.data.wROI_Left); + info_msg("*** UVC current wROI_Bottom is 0x%x\n", roi.data.wROI_Bottom); + info_msg("*** UVC current wROI_Right is 0x%x\n", roi.data.wROI_Right); + info_msg("*** UVC current bmAutoControls is 0x%x\n", roi.data.bmAutoControls); + roi.req = ROI_SET_CUR; + roi.data.wROI_Top = 2; + roi.data.wROI_Left = 2; + roi.data.wROI_Bottom = 2; + roi.data.wROI_Right = 2; + roi.data.bmAutoControls = 4; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_REGION_OF_INTEREST, &roi, sizeof (struct ct_roi))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + + roi.req = ROI_GET_CUR; + roi.data.wROI_Top = 0; + roi.data.wROI_Left = 0; + roi.data.wROI_Bottom = 0; + roi.data.wROI_Right = 0; + roi.data.bmAutoControls = 0; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_REGION_OF_INTEREST, &roi, sizeof (struct ct_roi))) + { + info_msg("*** UVC GET default roll is error \n"); + return; + } + info_msg("*** UVC current wROI_Top is 0x%x\n", roi.data.wROI_Top); + info_msg("*** UVC current wROI_Left is 0x%x\n", roi.data.wROI_Left); + info_msg("*** UVC current wROI_Bottom is 0x%x\n", roi.data.wROI_Bottom); + info_msg("*** UVC current wROI_Right is 0x%x\n", roi.data.wROI_Right); + info_msg("*** UVC current bmAutoControls is 0x%x\n", roi.data.bmAutoControls); + info_msg("*** UVC test pass \n"); +} + + +static void uvc_backlight_compensation_test(int cam_idx) +{ + struct pu_backlight backlight; + backlight.req = BKC_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BACKLIGHT_COMPENSATION, &backlight, sizeof (struct pu_backlight))) + { + info_msg("*** UVC backlight is not supported \n"); + return; + } + info_msg("*** UVC backlight cap is 0x%x\n", backlight.caps); + + backlight.wBacklightCompensation = 0; + backlight.req = BKC_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BACKLIGHT_COMPENSATION, &backlight, sizeof (struct pu_backlight))) + { + info_msg("*** UVC GET default wBacklightCompensation is error \n"); + return; + } + info_msg("*** UVC default wBacklightCompensation is 0x%x\n", backlight.wBacklightCompensation); + backlight.wBacklightCompensation = 0; + backlight.req = BKC_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BACKLIGHT_COMPENSATION, &backlight, sizeof (struct pu_backlight))) + { + info_msg("*** UVC GET min wBacklightCompensation is error \n"); + return; + } + info_msg("*** UVC min wBacklightCompensation is 0x%x\n", backlight.wBacklightCompensation); + backlight.wBacklightCompensation = 0; + backlight.req = BKC_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BACKLIGHT_COMPENSATION, &backlight, sizeof (struct pu_backlight))) + { + info_msg("*** UVC GET max wBacklightCompensation is error \n"); + return; + } + info_msg("*** UVC max wBacklightCompensation is 0x%x\n", backlight.wBacklightCompensation); + backlight.wBacklightCompensation = 0; + backlight.req = BKC_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BACKLIGHT_COMPENSATION, &backlight, sizeof (struct pu_backlight))) + { + info_msg("*** UVC GET resolution wBacklightCompensation is error \n"); + return; + } + info_msg("*** UVC resulation is 0x%x\n", backlight.wBacklightCompensation); + backlight.wBacklightCompensation = 0; + backlight.req = BKC_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BACKLIGHT_COMPENSATION, &backlight, sizeof (struct pu_backlight))) + { + info_msg("*** UVC GET current wBacklightCompensation is error \n"); + return; + } + info_msg("*** UVC current wBacklightCompensation is 0x%x\n", backlight.wBacklightCompensation); + backlight.wBacklightCompensation = 1; + backlight.req = BKC_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BACKLIGHT_COMPENSATION, &backlight, sizeof (struct pu_backlight))) + { + info_msg("*** UVC SET wBacklightCompensation is error \n"); + return; + } + + backlight.wBacklightCompensation = 0; + backlight.req = BKC_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BACKLIGHT_COMPENSATION, &backlight, sizeof (struct pu_backlight))) + { + info_msg("*** UVC GET current wBacklightCompensation is error \n"); + return; + } + info_msg("*** UVC current wBacklightCompensation is 0x%x\n", backlight.wBacklightCompensation); + info_msg("*** UVC test pass \n"); +} + +static void uvc_brightness_test(int cam_idx) +{ + struct pu_brightness brightness; + brightness.req = BRIGHTNESS_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BRIGHTNESS, &brightness, sizeof (struct pu_brightness))) + { + info_msg("*** UVC brightness is not supported \n"); + return; + } + info_msg("*** UVC brightness cap is 0x%x\n", brightness.caps); + + brightness.wBrightness = 0; + brightness.req = BRIGHTNESS_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BRIGHTNESS, &brightness, sizeof (struct pu_brightness))) + { + info_msg("*** UVC GET default brightness is error \n"); + return; + } + info_msg("*** UVC default brightness is 0x%x\n", brightness.wBrightness); + brightness.wBrightness = 0; + brightness.req = BRIGHTNESS_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BRIGHTNESS, &brightness, sizeof (struct pu_brightness))) + { + info_msg("*** UVC GET min brightness is error \n"); + return; + } + info_msg("*** UVC min brightness is 0x%x\n", brightness.wBrightness); + brightness.wBrightness = 0; + brightness.req = BRIGHTNESS_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BRIGHTNESS, &brightness, sizeof (struct pu_brightness))) + { + info_msg("*** UVC GET max brightness is error \n"); + return; + } + info_msg("*** UVC max brightness is 0x%x\n", brightness.wBrightness); + brightness.wBrightness = 0; + brightness.req = BRIGHTNESS_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BRIGHTNESS, &brightness, sizeof (struct pu_brightness))) + { + info_msg("*** UVC GET resolution brightness is error \n"); + return; + } + info_msg("*** UVC resolution brightness is 0x%x\n", brightness.wBrightness); + brightness.wBrightness = 0; + brightness.req = BRIGHTNESS_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BRIGHTNESS, &brightness, sizeof (struct pu_brightness))) + { + info_msg("*** UVC GET current brightness is error \n"); + return; + } + info_msg("*** UVC current brightness is 0x%x\n", brightness.wBrightness); + brightness.wBrightness = 1; + brightness.req = BRIGHTNESS_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BRIGHTNESS, &brightness, sizeof (struct pu_brightness))) + { + info_msg("*** UVC SET current brightness is error \n"); + return; + } + + brightness.wBrightness = 0; + brightness.req = BRIGHTNESS_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_BRIGHTNESS, &brightness, sizeof (struct pu_brightness))) + { + info_msg("*** UVC GET current brightness is error \n"); + return; + } + info_msg("*** UVC current brightness is 0x%x\n", brightness.wBrightness); + info_msg("*** UVC test pass \n"); +} + + +static void uvc_contrast_test(int cam_idx) +{ + struct pu_contrast contrast; + contrast.req = CONTRAST_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST, &contrast, sizeof (struct pu_contrast))) + { + info_msg("*** UVC contrast is not supported \n"); + return; + } + info_msg("*** UVC contrast cap is 0x%x\n", contrast.caps); + + contrast.wContrast = 0; + contrast.req = CONTRAST_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST, &contrast, sizeof (struct pu_contrast))) + { + info_msg("*** UVC GET default contrast is error \n"); + return; + } + info_msg("*** UVC default contrast is 0x%x\n", contrast.wContrast); + contrast.wContrast = 0; + contrast.req = CONTRAST_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST, &contrast, sizeof (struct pu_contrast))) + { + info_msg("*** UVC min contrast roll is error \n"); + return; + } + info_msg("*** UVC min contrast is 0x%x\n", contrast.wContrast); + contrast.wContrast = 0; + contrast.req = CONTRAST_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST, &contrast, sizeof (struct pu_contrast))) + { + info_msg("*** UVC GET max contrast is error \n"); + return; + } + info_msg("*** UVC max contrast is 0x%x\n", contrast.wContrast); + contrast.wContrast = 0; + contrast.req = CONTRAST_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST, &contrast, sizeof (struct pu_contrast))) + { + info_msg("*** UVC GET resolution is error \n"); + return; + } + info_msg("*** UVC resolution contrast is 0x%x\n", contrast.wContrast); + contrast.wContrast = 0; + contrast.req = CONTRAST_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST, &contrast, sizeof (struct pu_contrast))) + { + info_msg("*** UVC GET current contrast error \n"); + return; + } + + contrast.wContrast = 1; + contrast.req = CONTRAST_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST, &contrast, sizeof (struct pu_contrast))) + { + info_msg("*** UVC SET default contrast. is error \n"); + return; + } + + contrast.wContrast = 0; + contrast.req = CONTRAST_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST, &contrast, sizeof (struct pu_contrast))) + { + info_msg("*** UVC GET default contrast. is error \n"); + return; + } + info_msg("*** UVC current contrast is 0x%x\n", contrast.wContrast); + info_msg("*** UVC test pass \n"); + +} + +static void uvc_auto_contrast_test(int cam_idx) +{ + struct pu_contrast_auto contrast; + contrast.req = CONTRASTA_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST_AUTO, &contrast, sizeof (struct pu_contrast_auto))) + { + info_msg("*** UVC auto contrast is not supported \n"); + return; + } + info_msg("*** UVC auto contrast cap is 0x%x\n", contrast.caps); + + contrast.bContrastAuto = 0; + contrast.req = CONTRASTA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST_AUTO, &contrast, sizeof (struct pu_contrast_auto))) + { + info_msg("*** UVC GET default auto contrast is error \n"); + return; + } + info_msg("*** UVC default auto contrast is 0x%x\n", contrast.bContrastAuto); + contrast.bContrastAuto = 0; + contrast.req = CONTRASTA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST_AUTO, &contrast, sizeof (struct pu_contrast_auto))) + { + info_msg("*** UVC GET default auto contrast is error \n"); + return; + } + info_msg("*** UVC current auto contrast is 0x%x\n", contrast.bContrastAuto); + contrast.bContrastAuto = 1; + contrast.req = CONTRASTA_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST_AUTO, &contrast, sizeof (struct pu_contrast_auto))) + { + info_msg("*** UVC GET default auto contrast is error \n"); + return; + } + + contrast.bContrastAuto = 0; + contrast.req = CONTRASTA_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_CONTRAST_AUTO, &contrast, sizeof (struct pu_contrast_auto))) + { + info_msg("*** UVC GET default auto contrast is error \n"); + return; + } + info_msg("*** UVC current auto contrast is 0x%x\n", contrast.bContrastAuto); + info_msg("*** UVC test pass \n"); + +} + +static void uvc_gain_test(int cam_idx) +{ + struct pu_gain gain; + gain.req = GAIN_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAIN, &gain, sizeof (struct pu_gain))) + { + info_msg("*** UVC gain is not supported \n"); + return; + } + info_msg("*** UVC gain cap is 0x%x\n", gain.caps); + + gain.wGain = 0; + gain.req = GAIN_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAIN, &gain, sizeof (struct pu_gain))) + { + info_msg("*** UVC GET default gain is error \n"); + return; + } + info_msg("*** UVC default gain is 0x%x\n", gain.wGain); + gain.wGain = 0; + gain.req = GAIN_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAIN, &gain, sizeof (struct pu_gain))) + { + info_msg("*** UVC GET min gain is error \n"); + return; + } + info_msg("*** UVC min gain is 0x%x\n", gain.wGain); + gain.wGain = 0; + gain.req = GAIN_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAIN, &gain, sizeof (struct pu_gain))) + { + info_msg("*** UVC GET max gain is error \n"); + return; + } + info_msg("*** UVC max gain is 0x%x\n", gain.wGain); + gain.wGain = 0; + gain.req = GAIN_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAIN, &gain, sizeof (struct pu_gain))) + { + info_msg("*** UVC GET resolution gain is error \n"); + return; + } + info_msg("*** UVC resolution gain is 0x%x\n", gain.wGain); + gain.wGain = 0; + gain.req = GAIN_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAIN, &gain, sizeof (struct pu_gain))) + { + info_msg("*** UVC GET current gain is error \n"); + return; + } + info_msg("*** UVC GET current gain is 0x%x\n", gain.wGain); + gain.wGain = 1; + gain.req = GAIN_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAIN, &gain, sizeof (struct pu_gain))) + { + info_msg("*** UVC SET current gain is error \n"); + return; + } + + gain.wGain = 0; + gain.req = GAIN_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAIN, &gain, sizeof (struct pu_gain))) + { + info_msg("*** UVC GET current gain is error \n"); + return; + } + info_msg("*** UVC GET current gain is 0x%x\n", gain.wGain); + info_msg("*** UVC test pass \n"); +} + +static void uvc_power_line_frequency_test(int cam_idx) +{ + struct pu_power_line_frequency frequency; + frequency.req = POWER_LINE_FREQUENCY_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_POWER_LINE_FREQUENCY, &frequency, sizeof (struct pu_power_line_frequency))) + { + info_msg("*** UVC power line frequency is not supported \n"); + return; + } + info_msg("*** UVC power line frequency cap is 0x%x\n", frequency.caps); + + frequency.bPowerLineFrequency = 0; + frequency.req = POWER_LINE_FREQUENCY_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_POWER_LINE_FREQUENCY, &frequency, sizeof (struct pu_power_line_frequency))) + { + info_msg("*** UVC GET default power line frequency is error \n"); + return; + } + info_msg("*** UVC default power line frequency is 0x%x\n", frequency.bPowerLineFrequency); + frequency.bPowerLineFrequency = 0; + frequency.req = POWER_LINE_FREQUENCY_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_POWER_LINE_FREQUENCY, &frequency, sizeof (struct pu_power_line_frequency))) + { + info_msg("*** UVC GET current power line frequency is error \n"); + return; + } + info_msg("*** UVC current power line frequency is 0x%x\n", frequency.bPowerLineFrequency); + frequency.bPowerLineFrequency = PLF_AUTO; + frequency.req = POWER_LINE_FREQUENCY_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_POWER_LINE_FREQUENCY, &frequency, sizeof (struct pu_power_line_frequency))) + { + info_msg("*** UVC SET default power line frequency is error \n"); + return; + } + + frequency.bPowerLineFrequency = 0; + frequency.req = POWER_LINE_FREQUENCY_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_POWER_LINE_FREQUENCY, &frequency, sizeof (struct pu_power_line_frequency))) + { + info_msg("*** UVC GET current power line frequency is error \n"); + return; + } + info_msg("*** UVC current power line frequency is 0x%x\n", frequency.bPowerLineFrequency); + info_msg("*** UVC test pass \n"); +} + + +static void uvc_saturation_test(int cam_idx) +{ + struct pu_saturation saturation; + saturation.req = SATURATION_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SATURATION, &saturation, sizeof (struct pu_saturation))) + { + info_msg("*** UVC saturation is not supported \n"); + return; + } + info_msg("*** UVC saturation cap is 0x%x\n", saturation.caps); + + saturation.wSaturation = 0; + saturation.req = SATURATION_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SATURATION, &saturation, sizeof (struct pu_saturation))) + { + info_msg("*** UVC GET default saturation is error \n"); + return; + } + info_msg("*** UVC GET current saturation is 0x%x\n", saturation.wSaturation); + saturation.wSaturation = 0; + saturation.req = SATURATION_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SATURATION, &saturation, sizeof (struct pu_saturation))) + { + info_msg("*** UVC GET min saturation is error \n"); + return; + } + info_msg("*** UVC GET current saturation is 0x%x\n", saturation.wSaturation); + saturation.wSaturation = 0; + saturation.req = SATURATION_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SATURATION, &saturation, sizeof (struct pu_saturation))) + { + info_msg("*** UVC GET max saturation is error \n"); + return; + } + info_msg("*** UVC GET current saturation is 0x%x\n", saturation.wSaturation); + saturation.wSaturation = 0; + saturation.req = SATURATION_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SATURATION, &saturation, sizeof (struct pu_saturation))) + { + info_msg("*** UVC GET resolution saturation is error \n"); + return; + } + info_msg("*** UVC GET resolution saturation is 0x%x\n", saturation.wSaturation); + saturation.wSaturation = 0; + saturation.req = SATURATION_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SATURATION, &saturation, sizeof (struct pu_saturation))) + { + info_msg("*** UVC GET current saturation is error \n"); + return; + } + info_msg("*** UVC GET current saturation is 0x%x\n", saturation.wSaturation); + saturation.wSaturation = 1; + saturation.req = SATURATION_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SATURATION, &saturation, sizeof (struct pu_saturation))) + { + info_msg("*** UVC SET current saturation is error \n"); + return; + } + + saturation.wSaturation = 0; + saturation.req = SATURATION_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SATURATION, &saturation, sizeof (struct pu_saturation))) + { + info_msg("*** UVC GET current saturation is error \n"); + return; + } + info_msg("*** UVC GET current saturation is 0x%x\n", saturation.wSaturation); + info_msg("*** UVC test pass \n"); + +} + +static void uvc_sharpness_test(int cam_idx) +{ + struct pu_sharpness sharpness; + sharpness.req = SHARPNESS_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SHARPNESS, &sharpness, sizeof (struct pu_sharpness))) + { + info_msg("*** UVC sharpness is not supported \n"); + return; + } + info_msg("*** UVC sharpness cap is 0x%x\n", sharpness.caps); + + sharpness.wSharpness = 0; + sharpness.req = SHARPNESS_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SHARPNESS, &sharpness, sizeof (struct pu_sharpness))) + { + info_msg("*** UVC GET default sharpness is error \n"); + return; + } + info_msg("*** UVC GET default sharpness is 0x%x\n", sharpness.wSharpness); + sharpness.wSharpness = 0; + sharpness.req = SHARPNESS_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SHARPNESS, &sharpness, sizeof (struct pu_sharpness))) + { + info_msg("*** UVC GET min sharpness is error \n"); + return; + } + info_msg("*** UVC GET min sharpness is 0x%x\n", sharpness.wSharpness); + sharpness.wSharpness = 0; + sharpness.req = SHARPNESS_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SHARPNESS, &sharpness, sizeof (struct pu_sharpness))) + { + info_msg("*** UVC GET max sharpness is error \n"); + return; + } + info_msg("*** UVC GET max sharpness is 0x%x\n", sharpness.wSharpness); + sharpness.wSharpness = 0; + sharpness.req = SHARPNESS_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SHARPNESS, &sharpness, sizeof (struct pu_sharpness))) + { + info_msg("*** UVC GET resolution sharpness is error \n"); + return; + } + info_msg("*** UVC resolution is 0x%x\n", sharpness.wSharpness); + sharpness.wSharpness = 0; + sharpness.req = SHARPNESS_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SHARPNESS, &sharpness, sizeof (struct pu_sharpness))) + { + info_msg("*** UVC GET current sharpness is error \n"); + return; + } + info_msg("*** UVC GET current sharpness is 0x%x\n", sharpness.wSharpness); + sharpness.wSharpness = 1; + sharpness.req = SHARPNESS_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SHARPNESS, &sharpness, sizeof (struct pu_sharpness))) + { + info_msg("*** UVC GET current sharpness is error \n"); + return; + } + + sharpness.wSharpness = 0; + sharpness.req = SHARPNESS_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_SHARPNESS, &sharpness, sizeof (struct pu_sharpness))) + { + info_msg("*** UVC GET current sharpness is error \n"); + return; + } + info_msg("*** UVC GET current sharpness is 0x%x\n", sharpness.wSharpness); + info_msg("*** UVC test pass \n"); +} + +static void uvc_gamma_test(int cam_idx) +{ + struct pu_gamma gamma; + gamma.req = GAMMA_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAMMA, &gamma, sizeof (struct pu_gamma))) + { + info_msg("*** UVC gamma is not supported \n"); + return; + } + info_msg("*** UVC gamma cap is 0x%x\n", gamma.caps); + + gamma.wGamma = 0; + gamma.req = GAMMA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAMMA, &gamma, sizeof (struct pu_gamma))) + { + info_msg("*** UVC GET default gamma is error \n"); + return; + } + info_msg("*** UVC default gamma is 0x%x\n", gamma.wGamma); + gamma.wGamma = 0; + gamma.req = GAMMA_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAMMA, &gamma, sizeof (struct pu_gamma))) + { + info_msg("*** UVC GET default gamma is error \n"); + return; + } + info_msg("*** UVC min gamma is 0x%x\n", gamma.wGamma); + gamma.wGamma = 0; + gamma.req = GAMMA_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAMMA, &gamma, sizeof (struct pu_gamma))) + { + info_msg("*** UVC GET default gamma is error \n"); + return; + } + info_msg("*** UVC max gamma is 0x%x\n", gamma.wGamma); + gamma.wGamma = 0; + gamma.req = GAMMA_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAMMA, &gamma, sizeof (struct pu_gamma))) + { + info_msg("*** UVC resolution is error \n"); + return; + } + info_msg("*** UVC resolution is 0x%x\n", gamma.wGamma); + gamma.wGamma = 0; + gamma.req = GAMMA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAMMA, &gamma, sizeof (struct pu_gamma))) + { + info_msg("*** UVC GET current gamma is error \n"); + return; + } + info_msg("*** UVC current gamma is 0x%x\n", gamma.wGamma); + gamma.wGamma = 1; + gamma.req = GAMMA_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAMMA, &gamma, sizeof (struct pu_gamma))) + { + info_msg("*** UVC SET current gamma is error \n"); + return; + } + + gamma.wGamma = 0; + gamma.req = GAMMA_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_GAMMA, &gamma, sizeof (struct pu_gamma))) + { + info_msg("*** UVC GET current gamma is error \n"); + return; + } + info_msg("*** UVC current gamma is 0x%x\n", gamma.wGamma); + info_msg("*** UVC test pass \n"); +} + + +static void uvc_white_balance_temperature_test(int cam_idx) +{ + struct pu_white_balance_temp wbt; + wbt.req = WBT_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE, &wbt, sizeof (struct pu_white_balance_temp))) + { + info_msg("*** UVC white balance temperature is not supported \n"); + return; + } + info_msg("*** UVC white balance temperature cap is 0x%x\n", wbt.caps); + + wbt.wWhiteBalanceTemperature = 0; + wbt.req = WBT_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE, &wbt, sizeof (struct pu_white_balance_temp))) + { + info_msg("*** UVC GET default white balance temperature is error \n"); + return; + } + info_msg("*** UVC default white balance temperature is 0x%x\n", wbt.wWhiteBalanceTemperature); + wbt.wWhiteBalanceTemperature = 0; + wbt.req = WBT_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE, &wbt, sizeof (struct pu_white_balance_temp))) + { + info_msg("*** UVC GET min white balance temperature is error \n"); + return; + } + info_msg("*** UVC min white balance temperature is 0x%x\n", wbt.wWhiteBalanceTemperature); + wbt.wWhiteBalanceTemperature = 0; + wbt.req = WBT_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE, &wbt, sizeof (struct pu_white_balance_temp))) + { + info_msg("*** UVC GET max white balance temperature is error \n"); + return; + } + info_msg("*** UVC max white balance temperature is 0x%x\n", wbt.wWhiteBalanceTemperature); + wbt.wWhiteBalanceTemperature = 0; + wbt.req = WBT_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE, &wbt, sizeof (struct pu_white_balance_temp))) + { + info_msg("*** UVC GET resolution white balance temperature is error \n"); + return; + } + info_msg("*** UVC resolution is 0x%x\n", wbt.wWhiteBalanceTemperature); + wbt.wWhiteBalanceTemperature = 0; + wbt.req = WBT_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE, &wbt, sizeof (struct pu_white_balance_temp))) + { + info_msg("*** UVC GET current white_balance_temperature is error \n"); + return; + } + info_msg("*** UVC current white balance temperature is 0x%x\n", wbt.wWhiteBalanceTemperature); + wbt.wWhiteBalanceTemperature = 0x7d0; + wbt.req = WBT_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE, &wbt, sizeof (struct pu_white_balance_temp))) + { + info_msg("*** UVC SET current white_balance_temperature is error \n"); + return; + } + + wbt.wWhiteBalanceTemperature = 0; + wbt.req = WBT_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE, &wbt, sizeof (struct pu_white_balance_temp))) + { + info_msg("*** UVC GET current white balance temperature is error \n"); + return; + } + info_msg("*** UVC current white balance temperature is 0x%x\n", wbt.wWhiteBalanceTemperature); + info_msg("*** UVC test pass \n"); +} + +static void uvc_white_balance_compont_test(int cam_idx) +{ + struct pu_whitebalance_comp wbc; + wbc.req = WBC_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT, &wbc, sizeof (struct pu_whitebalance_comp))) + { + info_msg("*** UVC white balance compont is not supported \n"); + return; + } + info_msg("*** UVC white balance compont cap is 0x%x\n", wbc.caps); + + wbc.data.wWhiteBalanceBlue = 0; + wbc.data.wWhiteBalanceRed = 0; + wbc.req = WBC_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT, &wbc, sizeof (struct pu_whitebalance_comp))) + { + info_msg("*** UVC GET default white balance compont is error \n"); + return; + } + info_msg("*** UVC default white balance compont blue is 0x%x\n", wbc.data.wWhiteBalanceBlue); + info_msg("*** UVC default white balance compont red is 0x%x\n", wbc.data.wWhiteBalanceRed); + wbc.data.wWhiteBalanceBlue = 0; + wbc.data.wWhiteBalanceRed = 0; + wbc.req = WBC_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT, &wbc, sizeof (struct pu_whitebalance_comp))) + { + info_msg("*** UVC GET min white balance compont is error \n"); + return; + } + info_msg("*** UVC min white balance compont blue is 0x%x\n", wbc.data.wWhiteBalanceBlue); + info_msg("*** UVC min white balance compont red is 0x%x\n", wbc.data.wWhiteBalanceRed); + wbc.data.wWhiteBalanceBlue = 0; + wbc.data.wWhiteBalanceRed = 0; + wbc.req = WBC_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT, &wbc, sizeof (struct pu_whitebalance_comp))) + { + info_msg("*** UVC GET max white balance compont is error \n"); + return; + } + info_msg("*** UVC max white balance compont blue is 0x%x\n", wbc.data.wWhiteBalanceBlue); + info_msg("*** UVC max white balance compont red is 0x%x\n", wbc.data.wWhiteBalanceRed); + wbc.data.wWhiteBalanceBlue = 0; + wbc.data.wWhiteBalanceRed = 0; + wbc.req = WBC_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT, &wbc, sizeof (struct pu_whitebalance_comp))) + { + info_msg("*** UVC GET resolution is error \n"); + return; + } + + wbc.data.wWhiteBalanceBlue = 0; + wbc.data.wWhiteBalanceRed = 0; + wbc.req = WBC_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT, &wbc, sizeof (struct pu_whitebalance_comp))) + { + info_msg("*** UVC GET current white balance compont is error \n"); + return; + } + info_msg("*** UVC current white balance compont blue is 0x%x\n", wbc.data.wWhiteBalanceBlue); + info_msg("*** UVC current white balance compont red is 0x%x\n", wbc.data.wWhiteBalanceRed); + wbc.data.wWhiteBalanceBlue = 1; + wbc.data.wWhiteBalanceRed = 1; + wbc.req = WBC_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT, &wbc, sizeof (struct pu_whitebalance_comp))) + { + info_msg("*** UVC SET current white balance compont is error \n"); + return; + } + + wbc.data.wWhiteBalanceBlue = 0; + wbc.data.wWhiteBalanceRed = 0; + wbc.req = WBC_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT, &wbc, sizeof (struct pu_whitebalance_comp))) + { + info_msg("*** UVC GET current white balance compont is error \n"); + return; + } + info_msg("*** UVC current white balance compont blue is 0x%x\n", wbc.data.wWhiteBalanceBlue); + info_msg("*** UVC current white balance compont red is 0x%x\n", wbc.data.wWhiteBalanceRed); + info_msg("*** UVC test pass \n"); +} + +static void uvc_auto_white_balance_temperature_test(int cam_idx) +{ + struct pu_white_balance_temp_auto wbt_auto; + wbt_auto.req = WBTA_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE_AUTO, &wbt_auto, sizeof (struct pu_white_balance_temp_auto))) + { + info_msg("*** UVC auto white balance temperature is not supported \n"); + return; + } + info_msg("*** UVC auto white balance temperature cap is 0x%x\n", wbt_auto.caps); + + wbt_auto.bWhiteBalanceTemperatureAuto = 0; + wbt_auto.req = WBTA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE_AUTO, &wbt_auto, sizeof (struct pu_white_balance_temp_auto))) + { + info_msg("*** UVC GET default auto white balance temperature is error \n"); + return; + } + info_msg("*** UVC default auto white balance temperature cap is 0x%x\n", wbt_auto.bWhiteBalanceTemperatureAuto); + wbt_auto.bWhiteBalanceTemperatureAuto = 0; + wbt_auto.req = WBTA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE_AUTO, &wbt_auto, sizeof (struct pu_white_balance_temp_auto))) + { + info_msg("*** UVC GET current auto white balance temperature is error \n"); + return; + } + info_msg("*** UVC current auto white balance temperature cap is 0x%x\n", wbt_auto.bWhiteBalanceTemperatureAuto); + wbt_auto.bWhiteBalanceTemperatureAuto = 0; + wbt_auto.req = WBTA_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE_AUTO, &wbt_auto, sizeof (struct pu_white_balance_temp_auto))) + { + info_msg("*** UVC SET current auto white balance temperature error \n"); + return; + } + + wbt_auto.bWhiteBalanceTemperatureAuto = 0; + wbt_auto.req = WBTA_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_TEMPERATURE_AUTO, &wbt_auto, sizeof (struct pu_white_balance_temp_auto))) + { + info_msg("*** UVC GET current auto white balance temperature is error \n"); + return; + } + info_msg("*** UVC current auto white balance temperature is 0x%x\n", wbt_auto.bWhiteBalanceTemperatureAuto); + info_msg("*** UVC test pass \n"); + +} + +static void uvc_auto_white_balance_compont_test(int cam_idx) +{ + struct pu_wbc_auto wbc; + wbc.req = WBCA_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT_AUTO, &wbc, sizeof (struct pu_wbc_auto))) + { + info_msg("*** UVC auto white balance compont is not supported \n"); + return; + } + info_msg("*** UVC auto white balance_compont cap is 0x%x\n", wbc.caps); + + wbc.bWhiteBalanceComponentAuto = 0; + wbc.req = WBCA_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT_AUTO, &wbc, sizeof (struct pu_wbc_auto))) + { + info_msg("*** UVC GET default auto white balance compont is error \n"); + return; + } + info_msg("*** UVC default auto white balance_compont is 0x%x\n", wbc.bWhiteBalanceComponentAuto); + wbc.bWhiteBalanceComponentAuto = 0; + wbc.req = WBCA_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT_AUTO, &wbc, sizeof (struct pu_wbc_auto))) + { + info_msg("*** UVC GET default current white balance compont is error \n"); + return; + } + info_msg("*** UVC current auto white balance_compont is 0x%x\n", wbc.bWhiteBalanceComponentAuto); + wbc.bWhiteBalanceComponentAuto = 1; + wbc.req = WBCA_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT_AUTO, &wbc, sizeof (struct pu_wbc_auto))) + { + info_msg("*** UVC SET default auto white balance compont is error \n"); + return; + } + + wbc.bWhiteBalanceComponentAuto = 0; + wbc.req = WBCA_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_WHITE_BALANCE_COMPONENT_AUTO, &wbc, sizeof (struct pu_wbc_auto))) + { + info_msg("*** UVC GET current auto white balance compont is error \n"); + return; + } + info_msg("*** UVC current auto white balance_compont is 0x%x\n", wbc.bWhiteBalanceComponentAuto); + info_msg("*** UVC test pass \n"); + +} + +static void uvc_set_digital_multiplier(int cam_idx) +{ + struct pu_dmultiplier dmlpr; + dmlpr.req = MPL_GET_CAP; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER, &dmlpr, sizeof (struct pu_dmultiplier))) + { + info_msg("*** UVC digital multiplier is not supported \n"); + return; + } + info_msg("*** UVC digital multiplier cap is 0x%x\n", dmlpr.caps); + + dmlpr.wMultiplierStep = 0; + dmlpr.req = MPL_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER, &dmlpr, sizeof (struct pu_dmultiplier))) + { + info_msg("*** UVC GET default digital multiplier is error \n"); + return; + } + info_msg("*** UVC default digital multiplier is 0x%x\n", dmlpr.wMultiplierStep); + dmlpr.wMultiplierStep = 0; + dmlpr.req = MPL_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER, &dmlpr, sizeof (struct pu_dmultiplier))) + { + info_msg("*** UVC GET min digital multiplier is error \n"); + return; + } + info_msg("*** UVC min digital multiplier is 0x%x\n", dmlpr.wMultiplierStep); + dmlpr.wMultiplierStep = 0; + dmlpr.req = MPL_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER, &dmlpr, sizeof (struct pu_dmultiplier))) + { + info_msg("*** UVC GET max digital multiplier is error \n"); + return; + } + info_msg("*** UVC max digital multiplier is 0x%x\n", dmlpr.wMultiplierStep); + dmlpr.wMultiplierStep = 0; + dmlpr.req = MPL_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER, &dmlpr, sizeof (struct pu_dmultiplier))) + { + info_msg("*** UVC GET resolution is error \n"); + return; + } + info_msg("*** UVC resolution is 0x%x\n", dmlpr.wMultiplierStep); + dmlpr.wMultiplierStep = 0; + dmlpr.req = MPL_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER, &dmlpr, sizeof (struct pu_dmultiplier))) + { + info_msg("*** UVC GET current digital multiplier is error \n"); + return; + } + info_msg("*** UVC current digital multiplier is 0x%x\n", dmlpr.wMultiplierStep); + dmlpr.wMultiplierStep = 0; + dmlpr.req = MPL_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER, &dmlpr, sizeof (struct pu_dmultiplier))) + { + info_msg("*** UVC SET current digital multiplier is error \n"); + return; + } + + dmlpr.wMultiplierStep = 0; + dmlpr.req = MPL_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER, &dmlpr, sizeof (struct pu_dmultiplier))) + { + info_msg("*** UVC GET current digital multiplier is error \n"); + return; + } + info_msg("*** UVC current digital multiplier is 0x%x\n", dmlpr.wMultiplierStep); + info_msg("*** UVC test pass \n"); +} + +static void uvc_digital_multiplier_limit_test(int cam_idx) +{ + struct pu_dmultiplierlimit dmlpl; + dmlpl.req = DMPL_GET_CAP; + dmlpl.caps = 0; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER_LIMIT, &dmlpl, sizeof (struct pu_dmultiplierlimit))) + { + info_msg("*** UVC digital multiplier limit is not supported \n"); + return; + } + info_msg("*** UVC digital multiplier limit cap is 0x%x\n", dmlpl.caps); + + dmlpl.wMultiplierLimit = 0; + dmlpl.req = DMPL_GET_DEF; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER_LIMIT, &dmlpl, sizeof (struct pu_dmultiplierlimit))) + { + info_msg("*** UVC GET default digital multiplier limit is error \n"); + return; + } + info_msg("*** UVC default digital multiplier limit cap is 0x%x\n", dmlpl.wMultiplierLimit); + dmlpl.wMultiplierLimit = 0; + dmlpl.req = DMPL_GET_MIN; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER_LIMIT, &dmlpl, sizeof (struct pu_dmultiplierlimit))) + { + info_msg("*** UVC GET min digital multiplier limit is error \n"); + return; + } + info_msg("*** UVC min digital multiplier limit cap is 0x%x\n", dmlpl.wMultiplierLimit); + dmlpl.wMultiplierLimit = 0; + dmlpl.req = DMPL_GET_MAX; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER_LIMIT, &dmlpl, sizeof (struct pu_dmultiplierlimit))) + { + info_msg("*** UVC GET max digital multiplier limit is error \n"); + return; + } + info_msg("*** UVC max digital multiplier limit cap is 0x%x\n", dmlpl.wMultiplierLimit); + dmlpl.wMultiplierLimit = 0; + dmlpl.req = DMPL_GET_RES; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER_LIMIT, &dmlpl, sizeof (struct pu_dmultiplierlimit))) + { + info_msg("*** UVC GET resolution is error \n"); + return; + } + info_msg("*** UVC resolution is 0x%x\n", dmlpl.wMultiplierLimit); + dmlpl.wMultiplierLimit = 0; + dmlpl.req = DMPL_GET_CUR; + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER_LIMIT, &dmlpl, sizeof (struct pu_dmultiplierlimit))) + { + info_msg("*** UVC GET current digital multiplier limit is error \n"); + return; + } + info_msg("*** UVC current digital multiplier limit cap is 0x%x\n", dmlpl.wMultiplierLimit); + dmlpl.wMultiplierLimit = 0; + dmlpl.req = DMPL_SET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER_LIMIT, &dmlpl, sizeof (struct pu_dmultiplierlimit))) + { + info_msg("*** UVC SET current digital multiplier limit is error \n"); + return; + } + + dmlpl.wMultiplierLimit = 0; + dmlpl.req = DMPL_GET_CUR; + + if (KMDW_STATUS_ERROR == kmdw_camera_ioctl(cam_idx, CID_DIGITAL_MULTIPLIER_LIMIT, &dmlpl, sizeof (struct pu_dmultiplierlimit))) + { + info_msg("*** UVC GET current digital multiplier limit is error \n"); + return; + } + info_msg("*** UVC current digital multiplier limit cap is 0x%x\n", dmlpl.wMultiplierLimit); + info_msg("*** UVC test pass \n"); +} + +int sample_uvc_ctl_test(void) +{ + int ret, cam_idx = 0; + + if (0 != (ret = kmdw_camera_open(cam_idx))) + return ret; + ret = uvc_camera_cotrol_list(cam_idx); + uvc_scanning_mode_test(cam_idx); + + uvc_exposure_mode_test(cam_idx); + uvc_exposure_priority_test(cam_idx); + uvc_exposure_time_test(cam_idx); + + uvc_shutter_speed_test(cam_idx); + + uvc_focus_auto_test(cam_idx); + uvc_focus_absolute_test(cam_idx); + uvc_focus_relative_test(cam_idx); + uvc_focus_len_range_test(cam_idx); + + + uvc_iris_absolute_test(cam_idx); + uvc_iris_relative_test(cam_idx); + + uvc_zoom_absolute_test(cam_idx); + uvc_zoom_relative_test(cam_idx); + + uvc_pan_tilt_absolute_test(cam_idx); + uvc_pan_tilt_direction_test(cam_idx); + + uvc_roll_test(cam_idx); + uvc_roll_direction_test(cam_idx); + uvc_shutter_test(cam_idx); + uvc_digital_windows_test(cam_idx); + uvc_digital_roi_test(cam_idx); + + uvc_backlight_compensation_test(cam_idx); + uvc_brightness_test(cam_idx); + uvc_contrast_test(cam_idx); + uvc_auto_contrast_test(cam_idx); + uvc_gain_test(cam_idx); + uvc_power_line_frequency_test(cam_idx); + uvc_saturation_test(cam_idx); + uvc_sharpness_test(cam_idx); + uvc_gamma_test(cam_idx); + uvc_white_balance_temperature_test(cam_idx); + uvc_white_balance_compont_test(cam_idx); + uvc_auto_white_balance_temperature_test(cam_idx); + uvc_auto_white_balance_compont_test(cam_idx); + uvc_set_digital_multiplier(cam_idx); + uvc_digital_multiplier_limit_test(cam_idx); + + return ret; +} +#endif + diff --git a/mdw/kdp_usb_uvc/src/uvc_video.c b/mdw/kdp_usb_uvc/src/uvc_video.c new file mode 100644 index 0000000..16fd754 --- /dev/null +++ b/mdw/kdp_usb_uvc/src/uvc_video.c @@ -0,0 +1,178 @@ +/* + * uvc_video.c + * + * Copyright (C) 2019 - 2020 Kneron, Inc. All rights reserved. + * + */ +#include "uvc_utils.h" +#include +#include +#include +#include +#include "kmdw_console.h" +#include "kmdw_usbh.h" +#include "kmdw_uvc.h" +#include "kmdw_camera.h" +#include "media/kdp_inference.h" + +#define NSEC_PER_SEC 1000000000L +#ifdef KDP_UVC +#ifdef KDP_UVC_DEBUG +#define uvc_msg(fmt, ...) MSG(LOG_ERROR, "[%s] " fmt, __func__, ##__VA_ARGS__) +#else +#define uvc_msg(fmt, ...) +#endif + +#define UINT_MAX (~0U) +#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) + +extern struct kapp_camera_settings { + uint32_t width; /**< Camera image width*/ + uint32_t height; /**< Camera image hieght*/ + uint32_t pixelformat; /**< Camera image pixel format*/ +} cam_settings[IMGSRC_NUM]; + +static int uvc_find_frame_index(struct uvc_format *format, uint16_t wWidth, uint16_t wHeight) +{ + int i; + + for ( i = 0; i < format->nframes; i++) { + struct uvc_frame *frame = &format->frame[i]; + if ((frame->wWidth == wWidth) && (frame->wHeight == wHeight)) + break; + } + if (i == format->nframes) + return -1; + format->cur_frame = &format->frame[i]; + format->cur_frame_num = i + 1; + return 0; +} + +static int uvc_find_best_alt(struct uvc_streaming *stream) +{ + struct uvc_vs_alt_intf *intf = stream->if_alt; + int i; + + unsigned int bandwidth; + + uint16_t psize; + unsigned int best_psize = UINT_MAX; + + uint8_t altsetting = 0; + + uint32_t interval = stream->cur_format->cur_frame->dwFrameInterval[0]; + + bandwidth = stream->cur_format->cur_frame->wWidth + * stream->cur_format->cur_frame->wHeight + * stream->cur_format->bpp; + + bandwidth *= 10000000 / interval + 1; + bandwidth /= 1000; // one usb + bandwidth /= 8; + bandwidth += 12; + bandwidth = bandwidth > 1024? bandwidth : 1024; + + if (bandwidth == 0) { + bandwidth = 1; + } + + for (i = 0; i < stream->num_alt; i++) { + psize = intf[i].maxpacketsize; + psize = (psize & 0x07ff) * (1 + ((psize >> 11) & 3)); + + if (psize >= bandwidth && psize <= best_psize) { + altsetting = intf[i].alt_num; + best_psize = psize; + break; + } + } + if (0 == altsetting) + return -1; + + stream->vs_ctrl_info->curr->wmHint = 1; + stream->vs_ctrl_info->curr->dwFrameInterval = interval; + stream->vs_ctrl_info->curr->bFormatIndex = stream->cur_format->index; + stream->vs_ctrl_info->curr->bFrameIndex = stream->cur_format->cur_frame->bFrameIndex; + stream->curr_altnum = altsetting; +#ifdef KDP_UVC_DEBUG +// kmdw_printf("@@ stream->vs_ctrl_info->curr->wmHint %x\n", stream->vs_ctrl_info->curr->wmHint); +// kmdw_printf("@@ stream->vs_ctrl_info->curr->dwFrameInterval %x\n", stream->vs_ctrl_info->curr->dwFrameInterval); +// kmdw_printf("@@ stream->vs_ctrl_info->curr->bFormatIndex %x\n", stream->vs_ctrl_info->curr->bFormatIndex); +// kmdw_printf("@@ stream->vs_ctrl_info->curr->bFrameIndex %x\n", stream->vs_ctrl_info->curr->bFrameIndex); + // kmdw_printf("@@ stream->curr_altnum %x\n", stream->curr_altnum); + // kmdw_printf("@@ intf[i].maxpacketsize 0x%x\n", intf[i].maxpacketsize); +#endif + + return 0; +} + +static int stream_negotiation(struct uvc_streaming *stream) +{ + + if (0 != USBH_UVC_VS_Control(0, SET_CUR, VS_PROBE_CONTROL, (UVC_PROBE_COMMIT_CONTROL *) stream->vs_ctrl_info->curr)) + return -1; + if (0 != USBH_UVC_VS_Control(0, GET_MIN, VS_PROBE_CONTROL, (UVC_PROBE_COMMIT_CONTROL *) stream->vs_ctrl_info->minimum)) + return -1; + if (0 != USBH_UVC_VS_Control(0, GET_MAX, VS_PROBE_CONTROL, (UVC_PROBE_COMMIT_CONTROL *) stream->vs_ctrl_info->maximum)) + return -1; + if (0 != USBH_UVC_VS_Control(0, SET_CUR, VS_PROBE_CONTROL, (UVC_PROBE_COMMIT_CONTROL *) stream->vs_ctrl_info->curr)) + return -1; + if (0 != USBH_UVC_VS_Control(0, GET_CUR, VS_PROBE_CONTROL, (UVC_PROBE_COMMIT_CONTROL *) stream->vs_ctrl_info->curr)) + return -1; + if (0 != USBH_UVC_VS_Control(0, SET_CUR, VS_COMMIT_CONTROL, (UVC_PROBE_COMMIT_CONTROL *) stream->vs_ctrl_info->curr)) + return -1; + + return 0; +} + +int uvc_video_disable(struct uvc_streaming *stream) +{ + if (stream->running == true) { + + USBH_Pipe_ISOCH_Stop(stream->isoch_pipe); + stream->running = false; + } + return 0; +} + +int uvc_video_enable(struct uvc_streaming *stream) +{ + int ret = 0; + + if (stream->running == false) { + stream_negotiation(stream); + USBH_DeviceRequest_SetInterface(0, stream->ifnum, stream->curr_altnum); + USBH_UVC_PipeStart_Isoch(stream->isoch_pipe); + stream->running = true; + } + return ret; +} + +int uvc_video_init(struct uvc_device *udev) +{ + int i, j; + struct uvc_format *format = (struct uvc_format *) NULL; + + for (i = 0; i < udev->num_vs_inf; i++) { + for (j = 0; j < udev->stream[i].nformats; j++) { + format = &udev->stream[i].format[j]; + if (format->type == UVC_VS_FORMAT_UNCOMPRESSED) + break; + } + if (j < udev->stream[i].nformats) + break; + } + + if ((j == udev->stream[i].nformats) || (i == udev->num_vs_inf)) + return -1; + + udev->curr_stream->cur_format = format; + udev->curr_stream = &udev->stream[i]; + if (0 > uvc_find_frame_index(udev->curr_stream->cur_format, cam_settings[KDP_CAM_0].width, cam_settings[KDP_CAM_0].height)) + return -1; + if (0 > uvc_find_best_alt(udev->curr_stream)) + return -1; + + return 0; +} +#endif diff --git a/mdw/memory/kmdw_memory.c b/mdw/memory/kmdw_memory.c new file mode 100644 index 0000000..a435c98 --- /dev/null +++ b/mdw/memory/kmdw_memory.c @@ -0,0 +1,76 @@ +#include +#include "kmdw_memory.h" +#include "kmdw_console.h" + +/* ddr malloc direction : from tail(bigger address) to head (smaller) */ + +static uint32_t s_ddr_addr_tail = 0; +static uint32_t s_ddr_addr_boundary = 0; + +static uint32_t s_ddr_system_reserve_addr = 0; +static uint32_t s_ddr_system_reserve_size = 0; + +void kmdw_ddr_init(uint32_t start_addr, uint32_t end_addr) +{ + s_ddr_addr_boundary = start_addr; //(lower addr) ex. 0x11100000 + s_ddr_addr_tail = end_addr; //(higher addr) ex. 0x1111FFFF +} + +int kmdw_ddr_set_ddr_boundary(uint32_t boundary) +{ + if (boundary >= s_ddr_addr_tail) + return -1; + else { + s_ddr_addr_boundary = boundary; + return 0; + } +} + + +uint32_t kmdw_ddr_reserve(uint32_t numbyte) +{ + uint32_t aligned_numbyte; + uint32_t tail_tmp; + + if(numbyte == 0) + return 0; + + if(s_ddr_addr_boundary == 0) + return 0; //not initialized yet + + aligned_numbyte = ALIGN16(numbyte); + tail_tmp = s_ddr_addr_tail; + tail_tmp = ALIGN16_FLOOR(tail_tmp - aligned_numbyte); + + if(tail_tmp <= s_ddr_addr_boundary) + { + err_msg("Failed DDR allocation: %8d(before aligned) bytes [ 0x%x(<=0x%x) : 0x%x]\n", + numbyte, tail_tmp, s_ddr_addr_boundary, s_ddr_addr_tail); + return 0; + } + else + { + dbg_msg("[DBG] DDR allocated: %8d [ *0x%x : 0x%x]\n", + numbyte, tail_tmp, s_ddr_addr_tail); + + s_ddr_addr_tail = tail_tmp - 1; + return tail_tmp; // aligned address + } +} + +uint32_t kmdw_ddr_get_heap_tail() +{ + return s_ddr_addr_tail; +} + +void kmdw_ddr_store_system_reserve(uint32_t start_addr, uint32_t end_addr) +{ + s_ddr_system_reserve_addr = start_addr; + s_ddr_system_reserve_size = (end_addr - start_addr + 1); +} + +void kmdw_ddr_get_system_reserve(uint32_t *start_addr, uint32_t *ddr_size) +{ + *start_addr = s_ddr_system_reserve_addr; + *ddr_size = s_ddr_system_reserve_size; +} diff --git a/mdw/model/kmdw_model.c b/mdw/model/kmdw_model.c new file mode 100644 index 0000000..68fc88d --- /dev/null +++ b/mdw/model/kmdw_model.c @@ -0,0 +1,1417 @@ +/* + * Kneron Model API Manager + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include "project.h" + +#include "base.h" +#include "kdrv_ipc.h" /*for NCPU triggering */ +#include "kdrv_clock.h" /* for kdrv_delay_us() */ +#include "kdev_flash.h" + +#include "kmdw_ipc.h" +#include "kmdw_model.h" +#include "kmdw_console.h" /*for dbg_msg */ +#include "kmdw_memxfer.h" /*for flash access */ +#include "kmdw_memory.h" +#include "kmdw_utils_crc.h" + +#define DEBUG 0 +#define OUTPUT_MEM_ADDR2_SIZE 0x100000 /* 1MB, for DME parallel buffer */ +#define OUTPUT_MEM_ADDR3_SIZE 0x5000 /* for MBSSD anchor data */ + +#define FLAG_KMDW_MODEL_ABORT BIT(29) // Event flag to notify abort +#define FLAG_KMDW_MODEL_FROM_NCPU BIT(30) // Event flag to know NCPU is done +#define FLAG_KMDW_MODEL_FROM_NPU BIT(28) // Event flag to know NPU is done + +#define MODEL_INF_TIMEOUT (2000) // timeout milli-secs for waiting npcu response + +#define KDP_FLASH_FW_INFO_SIZE 0x1000 + +#ifdef EMBED_CMP_NPU + /* the following is for specific dense model wt/cmd mem modification */ + /*================================================*/ + #define WT_DATA_SIZE_BYTE 272 + + #define CONF_QUEUE 0 + #define GETW_QUEUE 3 + + #define CONF_GETW0_CMD_OFFSET 0x0038 + #define CONF_WDMA0_DST0_CMD_OFFSET 0x00f0 + + #define ACL_NPU_GETW0 0x2e + #define ACH_NPU_GETW0 0x2f + #define ACL_NPU_WDMA0_DST0 0x36 + #define ACH_NPU_WDMA0_DST0 0x37 + + #define MASK_2 0x0003 + #define MASK_10 0x03FF + #define MASK_16 0x00FFFF + + #define VAL_ACL(x) (((x)&0xffff)) + #define VAL_ACH(x) (((x) >> 16) & 0xffff) + + #define SetBitsVal(tgt, val, mask, offset) \ + ((tgt) &= ~((mask) << (offset))); \ + ((tgt) |= (((val) & (mask)) << (offset))) + + /*================================================*/ +#endif // EMBED_CMP_NPU + + +extern const struct s_kdp_memxfer kdp_memxfer_module; + +/* Type of Operations */ +enum { + NODE_TYPE_IN, + NODE_TYPE_CPU, + NODE_TYPE_OUTPUT, + NODE_TYPE_DATA, + NODE_TYPE_SUPER, + NODE_TYPE_INPUT +}; + +/* Structures of Data Nodes */ +struct super_node_s { + uint32_t node_id; + uint32_t addr; + uint32_t row_start; + uint32_t col_start; + uint32_t ch_start; + uint32_t row_length; + uint32_t col_length; + uint32_t ch_length; +}; + +struct data_node_s { + uint32_t node_id; + uint32_t supernum; + uint32_t data_format; + uint32_t data_radix; + uint32_t data_scale; + uint32_t row_start; + uint32_t col_start; + uint32_t ch_start; + uint32_t row_length; + uint32_t col_length; + uint32_t ch_length; + struct super_node_s node_list[1]; +}; + +/* Structure of Input Operation */ +struct in_node_s { + uint32_t node_id; + uint32_t next_npu; +}; + +/* Structure of Output Operation */ +struct out_node_s { + uint32_t node_id; + uint32_t supernum; + uint32_t data_format; + uint32_t row_start; + uint32_t col_start; + uint32_t ch_start; + uint32_t row_length; + uint32_t col_length; + uint32_t ch_length; + uint32_t output_index; + uint32_t output_radix; + uint32_t output_scale; + struct super_node_s node_list[1]; +}; + +/* Structure of CPU Operation */ +struct cpu_node_s { + uint32_t node_id; + uint32_t input_datanode_num; + uint32_t op_type; + /* There will be more parameter here for cpu operation */ + uint32_t in_num_row; + uint32_t in_num_col; + uint32_t in_num_ch; + uint32_t out_num_row; + uint32_t out_num_col; + uint32_t out_num_ch; + uint32_t h_pad; + uint32_t w_pad; + uint32_t kernel_h; + uint32_t kernel_w; + uint32_t stride_h; + uint32_t stride_w; + struct data_node_s output_datanode; + struct data_node_s input_datanode[1]; +}; + +/* Structure of CNN Header in setup.bin */ +struct cnn_header_s { + uint32_t crc; + uint32_t version; + uint32_t key_offset; + uint32_t model_type; + uint32_t app_type; + uint32_t dram_start; + uint32_t dram_size; + uint32_t input_row; + uint32_t input_col; + uint32_t input_channel; + uint32_t cmd_start; + uint32_t cmd_size; + uint32_t weight_start; + uint32_t weight_size; + uint32_t input_start; + uint32_t input_size; + uint32_t input_radix; + uint32_t output_nums; +}; + +typedef struct { + uint32_t n_model_source; // 0: not set, 1: from flash, 2: from ddr + uint32_t n_model_count; // model count + struct kdp_model_s p_model_info[KMDW_MODEL_MAX_MODEL_COUNT]; // save model info generated by compiler + uint8_t pn_is_model_loaded_table[KMDW_MODEL_MAX_MODEL_COUNT]; // flag table to indicate if model is loaded + uint32_t n_ddr_addr_model_end; // DDR address of model end = user data start + + int32_t n_model_slot_index; // scpu_to_ncpu->model_slot_index +} kmdw_model_data_t; + +static kmdw_model_data_t s_model_data = {0}; + +typedef struct { + int32_t raw_img_idx; + osEventFlagsId_t evt_caller; // event to know/control ncpu + uint32_t caller_e; + osEventFlagsId_t evt_result; // event to know/control npu + uint32_t result_e; +} kmdw_img_data_t; + +// ptr to the buf for uploaded fw info from host +static kmdw_model_fw_info_t *s_fw_info_buf_p = NULL; +// ptr to the buf for uploaded fw info from flash +static bool s_model_loaded_from_flash = false; + +static kmdw_img_data_t s_img_data[IPC_IMAGE_ACTIVE_MAX] = {0}; +static int32_t s_current_ipc_idx = 0; +static int32_t s_next_ipc_idx = 0; + +static bool ModelFromDDR = false; // check model is from flash : false, ddr : true + +/* ############################ + * ## Static Functions ## + * ############################ */ +/** + * @brief init ddr space for s_fw_info_buf_p + * + */ +static void _init_fw_info_buf(void) +{ + if (NULL == s_fw_info_buf_p) { + s_fw_info_buf_p = (kmdw_model_fw_info_t*)kmdw_ddr_reserve(KDP_FLASH_FW_INFO_SIZE); + + if (NULL == s_fw_info_buf_p) + critical_msg("insufficent memory for reading fw_info from flash\n"); + } +} + + +#ifdef EMBED_CMP_NPU +static inline void udt_conf_cmd(void *cmd_addr, int reg_idx, uint16_t val16b, int queue) +{ + uint32_t val = 0x80000000; + + SetBitsVal(val, queue, MASK_2, 26); + SetBitsVal(val, reg_idx, MASK_10, 16); + SetBitsVal(val, val16b, MASK_16, 0); + + memcpy(cmd_addr, &val, sizeof(val)); +} + +static void udt_npu_model_mem(uint32_t wt_addr, uint32_t out_addr, void *cmd_addr) +{ + uint32_t *dst = (uint32_t *)((char *)cmd_addr + CONF_GETW0_CMD_OFFSET); + udt_conf_cmd(dst, ACL_NPU_GETW0, VAL_ACL(wt_addr), GETW_QUEUE); + udt_conf_cmd(dst + 1, ACH_NPU_GETW0, VAL_ACH(wt_addr), GETW_QUEUE); + + dst = (uint32_t *)((char *)cmd_addr + CONF_WDMA0_DST0_CMD_OFFSET); + udt_conf_cmd(dst, ACL_NPU_WDMA0_DST0, VAL_ACL(out_addr), CONF_QUEUE); + udt_conf_cmd(dst + 1, ACH_NPU_WDMA0_DST0, VAL_ACH(out_addr), CONF_QUEUE); +} +#endif // EMBED_CMP_NPU + +/** + * @brief load fw info from flash + * @return 0: OK, -1: fail + * @note NULL means failed; non-zero ptr means OK + */ +static kmdw_model_fw_info_t* _load_flash_model_info(void) +{ + //load model from flash once and reuse loaded data, until reload + if (false == s_model_loaded_from_flash ) { + s_model_loaded_from_flash = true; + kdp_memxfer_module.flash_to_ddr((uint32_t)s_fw_info_buf_p, FLASH_MODEL_FW_INFO_ADDR, KDP_FLASH_FW_INFO_SIZE); + } + + return s_fw_info_buf_p; +} + + +/** + * @brief reset s_model_data + */ +static void _reset_model_data(void) +{ + s_model_data.n_model_count = 0; + s_model_data.n_model_source = 0; + memset( s_model_data.p_model_info, 0, sizeof(s_model_data.p_model_info)); + memset( s_model_data.pn_is_model_loaded_table, 0 , sizeof(s_model_data.pn_is_model_loaded_table)); + + //can't reset the following variable which maintains DDR boundary for model + //n_last_model_space_end_addr + return; +} + +/** + * @brief check flash read with timeout_ms + * @param timeout_ms timeout in ms + * @return flash ready ready time in ms + * -1 means timeout hit + */ +//static int32_t _flash_wait_ready(int timeout_ms) +//{ +// kdev_flash_status_t flash_status; +// int i; + +// for (i = 0; i < timeout_ms; i++) { +// flash_status = kdev_flash_get_status(); +// if (flash_status.busy == 0) break; +// kdrv_delay_us(1*1000); +// } +// if (i == timeout_ms) i = -1; // we have timed out +// return i; +//} + +/** + * @brief convert modeltype to modelInfo array index + * @param model_type_p: model type (defined in model_type.h) + * @return modelInfo model index (starts from 0) + * -1 means not such modeltype in flash + */ +static int8_t _get_model_info_array_index_by_model_type(uint32_t model_type_p) +{ + int i; + for(i=0 ; i < s_model_data.n_model_count; i++) { + if(s_model_data.p_model_info[i].model_type == model_type_p) + return i; + } + + return -1; +} + +/** + * @brief get fw info extension data from fw_info ptr + * @param[in] fw_info_p the ptr to fw_info + * @return the ptr to fw_info_ext + */ +static kmdw_model_fw_info_ext_t* +_get_fw_info_ext_by_fw_info(kmdw_model_fw_info_t* fw_info_p) +{ + if(NULL == fw_info_p) + return NULL; + else { + kmdw_model_fw_info_ext_t* ret = NULL; + uint32_t count; + uint32_t offset; + + count = fw_info_p->model_count; + offset = sizeof(struct kdp_model_s) * count; + ret = (kmdw_model_fw_info_ext_t *)((uint32_t)fw_info_p->models + offset); + return ret; + } +} + +/** + * @brief load model information generated by compiler + * @param [in] is_model_from_ddr: if model is from ddr/host command + * @param [in] is_reload : is force reload + * @return model count + * 0 means no model is loaded in this call + */ +static int32_t _load_model_info(bool from_ddr, bool reload) +{ + if (s_model_data.n_model_count && !reload) { + return s_model_data.n_model_count; + } + + if (reload) { + _reset_model_data(); + s_model_loaded_from_flash = false; + } + + kmdw_model_fw_info_t *model_info_p = NULL; + kmdw_model_fw_info_ext_t *model_info2_p = NULL; + + // load model Info + if (from_ddr) { + model_info_p = s_fw_info_buf_p; + model_info2_p = _get_fw_info_ext_by_fw_info(model_info_p); + + if((NULL == model_info_p) || (NULL == model_info2_p) ) { + s_model_data.n_model_count = 0; + return 0; + } + + // Use the version number for new fw_info structure. Model number is in use for dynamic model execution (DME) + //if (*(uint32_t*)(base_addr + 8) == 0) { + // return 0; //error, model_info is not ready + //} + + // get model count + s_model_data.n_model_count = model_info_p->model_count; + dbg_msg("[DBG] model info: model count:%d\n", s_model_data.n_model_count); + + if(0 == s_model_data.n_model_count) { + info_msg("[info] model is not in DDR!!\n"); + return 0; + } else if (s_model_data.n_model_count > KMDW_MODEL_MAX_MODEL_COUNT) { + info_msg("[ERR] model count is over MAX limit=%d!!\n", KMDW_MODEL_MAX_MODEL_COUNT); + s_model_data.n_model_count = 0; + return 0; + } else { + dbg_msg("[DBG] model info: model count:%d\n", s_model_data.n_model_count); + } + + // get model info + memcpy(s_model_data.p_model_info, (const void*)model_info_p->models, + sizeof(struct kdp_model_s)*s_model_data.n_model_count); + + // get ddr model end addr + s_model_data.n_ddr_addr_model_end = model_info2_p->model_dram_addr_end; + if (s_model_data.n_ddr_addr_model_end >= kmdw_ddr_get_heap_tail()) { + err_msg("modelInfo: DDR end address: 0x%x over (>=) boundary 0x%x\n", s_model_data.n_ddr_addr_model_end, kmdw_ddr_get_heap_tail()); + return 0; + } else { + dbg_msg("modelInfo: DDR end address: 0x%x\n", s_model_data.n_ddr_addr_model_end); + } + + // set model source + s_model_data.n_model_source = 2; // from ddr + + } else { // models are stored in flash + + model_info_p = _load_flash_model_info(); // this function updates data on s_fw_info_buf_p + model_info2_p = _get_fw_info_ext_by_fw_info(model_info_p); + + if((NULL == model_info_p) || (NULL == model_info2_p) ) { + s_model_data.n_model_count = 0; + return 0; + } + + // get model count + s_model_data.n_model_count = model_info_p->model_count; + dbg_msg("[DBG] model info: model count:%d\n", s_model_data.n_model_count); + + if (s_model_data.n_model_count == 0xFFFFFFFF) { + err_msg("[info] model is not in flash!!\n"); + s_model_data.n_model_count = 0; + return 0; + } else if (s_model_data.n_model_count > KMDW_MODEL_MAX_MODEL_COUNT) { + info_msg("[ERR] model count is over MAX limit=%d!!\n", KMDW_MODEL_MAX_MODEL_COUNT); + s_model_data.n_model_count = 0; + return 0; + } else { + dbg_msg("[DBG] model info: model count:%d\n", s_model_data.n_model_count); + } + + // get model info + //FIXME, why need to clone to s_fw_info_buf_p + //memcpy(s_fw_info_buf_p, (void *)model_info_p, KDP_FLASH_FW_INFO_SIZE); + + memcpy(s_model_data.p_model_info, model_info_p->models, sizeof(struct kdp_model_s)*s_model_data.n_model_count); + + // get ddr model end addr + s_model_data.n_ddr_addr_model_end = model_info2_p->model_dram_addr_end; + + if (s_model_data.n_ddr_addr_model_end >= kmdw_ddr_get_heap_tail()) { + err_msg("modelInfo: DDR end address: 0x%x over (>=) boundary 0x%x\n", s_model_data.n_ddr_addr_model_end, kmdw_ddr_get_heap_tail()); + return 0; + } else { + dbg_msg("modelInfo: DDR end address: 0x%x\n", s_model_data.n_ddr_addr_model_end); + } + + // set model source + s_model_data.n_model_source = 1; // from flash + } + + // for support of dynamic model execution + *(uint32_t*)(((char*)s_fw_info_buf_p) + 8) = 0; //trick: we will check the work to see if model_info is uploaded + + return s_model_data.n_model_count; +} + +/** + * @brief load specific model by model info index (the order in flash) + * @param model_index_p: model info index + * @return 0: model not ready, 1: model is loaded + */ +static int32_t _load_model(uint8_t model_index_p/*starts from 0*/) +{ + uint32_t ddr_addr_models_head; //start point = the 1st model's cmd.bin + uint32_t ddr_addr_offset; + uint32_t flash_addr; + uint32_t len_to_load; + + struct kdp_model_s *p_model; + + if(s_model_data.n_model_count == 0) + return 0; // model info is not ready + + if(s_model_data.pn_is_model_loaded_table[model_index_p] == 1 ) + return 1; //model has been loaded + else + s_model_data.pn_is_model_loaded_table[model_index_p] = 1; + + //load model with (index=model_index_p) from flash to DDR + ddr_addr_models_head = s_model_data.p_model_info[0].cmd_mem_addr; //start point = the 1st model's cmd.bin + + //load cmd + weight + setup together + p_model = &(s_model_data.p_model_info[model_index_p]); + ddr_addr_offset = p_model->cmd_mem_addr - ddr_addr_models_head; + + flash_addr = FLASH_MODEL_ALL_ADDR + ddr_addr_offset; + + len_to_load = ALIGN16(p_model->cmd_mem_len) + + ALIGN16(p_model->weight_mem_len) + + ALIGN16(p_model->setup_mem_len); + + //model from flash to ddr + kdp_memxfer_module.flash_to_ddr(p_model->cmd_mem_addr, flash_addr, len_to_load); + + return 1; +} + +/** + * @brief prepare ouptut_mem_addr2 for ncpu/npu parallel mode inference + * + * @return 0:OK, -1:Fail + */ +static int32_t _prepare_output_mem_addr2(void) +{ + /* Allocate parallel output buffer , if caller not provide buf*/ + struct scpu_to_ncpu_s* comm_out = kmdw_ipc_get_output(); + uint32_t addr_parallel = comm_out->output_mem_addr2; + + if (addr_parallel == 0) { + //TODO, dynamic allocate memory for output_mem_addr2 + //uint32_t addr1 = comm_out->models[model_idx].output_mem_addr; + //uint32_t addr2 = comm_out->models[model_idx].buf_addr; + //uint32_t len = comm_out->models[model_idx].output_mem_len; + //if (addr1 == addr2) { + // // Old memory layout, use working buffer length + // len = comm_out->models[model_idx].buf_len; + //} + + // reserve more space for larger model output (ty_608x608 need 620160) + uint32_t len = OUTPUT_MEM_ADDR2_SIZE; + + addr_parallel = kmdw_ddr_reserve(len); + if (addr_parallel == 0) { + err_msg("Error ddr allocation ncpu/npu parallel buffer, len %d\n", len); + return -1; //error + } + comm_out->output_mem_addr2 = addr_parallel; + comm_out->output_mem_len2 = len; + + dbg_msg("allocated Parallel buffer: len %d, addr 0x%x", len, addr_parallel); + } + return 0; +} + +#ifdef KL520 +/** + * @brief prepare ouptut_mem_addr3 for MBSSD network + * + * @param [in] model_type model id + * @return 0:OK, -1:Fail + */ +static int32_t _prepare_output_mem_addr3(uint32_t model_type) +{ + + if (model_type == KNERON_FD_MBSSD_200_200_3 || + model_type == KNERON_FD_MASK_MBSSD_200_200_3 || + model_type == KNERON_OD_MBSSD || + model_type == KNERON_PD_MBSSD || + model_type == KNERON_CAR_DETECTION_MBSSD_224_416_3) { + + uint32_t *pMemAddr3; + uint32_t len = OUTPUT_MEM_ADDR3_SIZE; + struct scpu_to_ncpu_s* comm_out = kmdw_ipc_get_output(); + + switch (model_type) { + case KNERON_FD_MBSSD_200_200_3 : + case KNERON_FD_MASK_MBSSD_200_200_3 : + { + static uint32_t mem_addr3_fdssd = 0; + pMemAddr3 = &mem_addr3_fdssd; + break; + } + case KNERON_OD_MBSSD : + { + static uint32_t mem_addr3_odssd = 0; + pMemAddr3 = &mem_addr3_odssd; + break; + } + case KNERON_PD_MBSSD : + { + static uint32_t mem_addr3_pdssd = 0; + pMemAddr3 = &mem_addr3_pdssd; + break; + } + case KNERON_CAR_DETECTION_MBSSD_224_416_3 : + { + static uint32_t mem_addr3_vdssd = 0; + pMemAddr3 = &mem_addr3_vdssd; + break; + } + default : + break; + } + if (*pMemAddr3 == 0) { + *pMemAddr3 = kmdw_ddr_reserve(len*sizeof(uint32_t)); + if (*pMemAddr3 == 0) { + err_msg("Error ddr allocation fail for MBSSD network, mem_addr3 len %d\n", len); + return -1; //error + } + *(uint32_t*)(*pMemAddr3) = 0; + } + comm_out->output_mem_addr3 = *pMemAddr3; + } + return 0; +} +#endif + +/** + * @brief specify model information, load model info, load model + * @param [in] model_type_p: model unique ID defined by Kneron + * @param [in] model_from_ddr: is model from ddr or host command + * @return model_slot_index(requested by NCPU/NPU) + * -1 : model not found + */ +static int32_t _config_model(uint32_t model_type, bool model_from_ddr) +{ + int model_info_idx; //limitation (hard coded in flash) + int model_idx; + + //check if model info is loaded + if( 0 == _load_model_info(model_from_ddr, false/*reload*/)) { + return -1; + } + + if( model_from_ddr == 0 ) { + //FIXME, should remove application related code + /* Special model not in DDR but in ncpu */ + if (model_type == KNERON_2D_LIVENESS_224_224_3) { + model_idx = 3; + model_info_idx = 4; + + goto model_common; + } + + model_info_idx = _get_model_info_array_index_by_model_type(model_type); + if(model_info_idx == -1) { + err_msg("[ERR] model_type[%d] is not found in flash\n", model_type); + return -1; + } + _load_model(model_info_idx); + + // FIXME: need to remove the following hard code + model_idx = model_info_idx; + + } else { + model_info_idx = _get_model_info_array_index_by_model_type(model_type); + if(model_info_idx == -1) { + err_msg("[ERR] model_type[%d] is not found in DDR\n", model_type); + return -1; + } + model_idx = model_info_idx; + } + +model_common: + s_model_data.n_model_slot_index = model_idx; + + kmdw_ipc_set_model(s_model_data.p_model_info, model_info_idx, model_idx); + + + struct kdp_img_raw_s *raw_img = kmdw_model_get_raw_img(s_img_data[s_current_ipc_idx].raw_img_idx); + + if (raw_img->inf_format & IMAGE_FORMAT_PARALLEL_PROC) { + if (-1 == _prepare_output_mem_addr2() ) { + return -1; + } + } + +#ifdef KL520 + if ( -1 == _prepare_output_mem_addr3(model_type) ) { + return -1; + } + +#else + struct scpu_to_ncpu_s* p_comm_out = kmdw_ipc_get_output(); + + if (NULL == p_comm_out->output_mem_addr3) { + uint32_t len = 0x5000; + p_comm_out->output_mem_addr3 = kmdw_ddr_reserve(len*sizeof(uint32_t)); + if(NULL == p_comm_out->output_mem_addr3) { + critical_msg("kmdw_model: failed to malloc comm_out->output_mem_addr3\n"); + return -1; + } + } + + if (NULL == p_comm_out->output_mem_addr4) { + uint32_t len = 8 * (1 << 20); + p_comm_out->output_mem_addr4 = kmdw_ddr_reserve(len); + if (NULL == p_comm_out->output_mem_addr4) { + critical_msg("kmdw_model: failed to malloc comm_out->output_mem_addr4\n"); + return -1; + } + } +#endif + + kmdw_ipc_set_model_active(model_idx); + + return model_idx; +} + + +/** + * @brief run model according to config settings + * @return status defined in NCPU + * @note !!! must be called after kapp_config_model_image() + */ +static int32_t _run_model(void) +{ + int active_idx = s_current_ipc_idx; + int raw_img_idx = s_img_data[active_idx].raw_img_idx; + struct kdp_img_raw_s *p_raw_image = kmdw_model_get_raw_img(raw_img_idx); + uint32_t flags, wait_evt; + uint32_t is_abort = 0; + + // Start time for ncpu/npu round trip + p_raw_image->tick_start = osKernelGetTickCount(); + + if (s_img_data[active_idx].evt_caller == NULL) + s_img_data[active_idx].evt_caller = osEventFlagsNew(0); + + if(!s_img_data[active_idx].evt_caller) + err_msg(" active_idx=%d, osEventFlagsNew evt_caller failure\n",active_idx); + + // set notify for job done + if (s_img_data[active_idx].evt_result) { + /* Result event already set. Let's do local event for parallel. */ + wait_evt = FLAG_KMDW_MODEL_FROM_NPU; + } else { + wait_evt = FLAG_KMDW_MODEL_FROM_NCPU; + } + + dbg_msg(" wait %d[%d] evt %x\n", raw_img_idx, active_idx, wait_evt); + + //assign caller event before triggering ncpu/npu + s_img_data[active_idx].caller_e = wait_evt; + + //trigger ncpu/npu + kmdw_ipc_trigger_int(CMD_RUN_NPU); + + //check abort signal + flags = osEventFlagsWait(s_img_data[active_idx].evt_caller, + FLAG_KMDW_MODEL_ABORT, + osFlagsWaitAll, 0); + if( flags != osFlagsErrorResource ) { + osEventFlagsClear(s_img_data[active_idx].evt_caller, FLAG_KMDW_MODEL_ABORT); + is_abort = 1; + } + + uint32_t wait_timeout = (kmdw_ipc_get_output()->kp_dbg_checkpoinots == 0x0) ? MODEL_INF_TIMEOUT : osWaitForever; + + //wait for finish of current task + flags = osEventFlagsWait(s_img_data[active_idx].evt_caller, + wait_evt, + osFlagsNoClear, wait_timeout); + + if(flags == osFlagsErrorTimeout){ + err_msg("[%s] osEventFlagsWait flag 0x%08x timeout\n", __FUNCTION__, wait_evt); + return IMAGE_STATE_TIMEOUT; + } else if (flags != wait_evt) + dbg_msg("[%s] 1+ events 0x%08x (%d[%d] expected)\n", __FUNCTION__, flags, wait_evt, active_idx); + else + dbg_msg("[DBG][%s] got: raw_img_idx[active_idx]=%d[%d]\n", __FUNCTION__, raw_img_idx, active_idx); + + osEventFlagsClear(s_img_data[active_idx].evt_caller, wait_evt); + + if( 1 == is_abort ) { + dbg_msg("[DBG][%s] abort after n_model_slot_index = %d\n", __FUNCTION__, s_model_data.n_model_slot_index); + return KMDW_MODEL_RUN_RC_ABORT; //abort + } + + return kmdw_ipc_get_input()->result.postproc.img_result.status; +} + +__weak osStatus_t kmdw_fifoq_manager_result_enqueue(void *result_buf, int buf_size, bool preempt) +{ + return osOK; +} + +static void _ipc_handler(struct kdp_img_raw_s *p_raw_image, int state) +{ + int ipc_idx; + + if(state == 0x999) // FIXME, very workaround + { + kmdw_ipc_get_input()->kp_dbg_status = 0x0; + osStatus_t sts = kmdw_fifoq_manager_result_enqueue(kmdw_ipc_get_output()->kp_dbg_buffer, 0, false); + if(sts != osOK) + kmdw_printf("send dbg data failed in ipc, err %d\n", sts); + } + else if (state == IMAGE_STATE_RECEIVING) { + ipc_idx = p_raw_image->ref_idx; + + // End time for ncpu/npu round trip + p_raw_image->tick_end = osKernelGetSysTimerCount(); + + if (s_img_data[ipc_idx].evt_result) { + dbg_msg("[done: post: P] ipc_idx: %d, result_e: %d (ram %x)\n", ipc_idx, s_img_data[ipc_idx].result_e, p_raw_image); + osEventFlagsSet(s_img_data[ipc_idx].evt_result, s_img_data[ipc_idx].result_e); + } else { + dbg_msg("[done: post: S] ipc_idx: %d, caller_e: %x.\n", ipc_idx, s_img_data[ipc_idx].caller_e); + osEventFlagsSet(s_img_data[ipc_idx].evt_caller, s_img_data[ipc_idx].caller_e); + } + } else if (state == IMAGE_STATE_ACTIVE){ + ipc_idx = s_current_ipc_idx; + dbg_msg("[done: npu: P] ipc_idx: %d, caller_e: %x\n", ipc_idx, s_img_data[ipc_idx].caller_e); + osEventFlagsSet(s_img_data[ipc_idx].evt_caller, s_img_data[ipc_idx].caller_e); + } else { + err_msg("[ERR] wrong state: %d (ipc_idx %d)\n", state, ipc_idx); + } +} + +/* ############################ + * ## Public Functions ## + * ############################ */ + +void kmdw_model_init(void) +{ + kmdw_ipc_initialize(_ipc_handler); + + _init_fw_info_buf(); + s_fw_info_buf_p->model_count = 0; +} + +int32_t kmdw_model_load_model(int8_t model_info_index_p) +{ + int32_t ret = 0; + + if(1 != s_model_data.n_model_source || // check if s_model_data is not according to flash + 0 == s_model_data.n_model_count) { + if(0 == _load_model_info(false/*from ddr*/, true/*reload*/)) + return 0; //error, no model is loaded + } + + // load all models + if (KMDW_MODEL_ALL_MODELS == model_info_index_p) { + uint8_t i; + for (i = 0 ; i < s_model_data.n_model_count ; i++) { + ret = _load_model(i); + if( 0 == ret) { + err_msg("[ERR] %s : failed to load model array index:%d\n", __FUNCTION__, i); + return 0; + } + } + +// Very slow if turn it on. Maybe hardware support is needed. +// Add a new compiler directive if CRC32 method is also used in other scenarios (ex: check FW image) +#if ENABLE_CRC32 + // check CRC value of all_models.bin + kmdw_model_fw_info_t *model_info_p = _load_flash_model_info(); + kmdw_model_fw_info_ext_t *model_info2_p = _get_fw_info_ext_by_fw_info(model_info_p); + + // cmd_mem_addr of first model is the start address of all_models.bin + uint8_t *addr = (uint8_t *)s_model_data.p_model_info[0].cmd_mem_addr; + + uint32_t crc32 = kmdw_utils_crc_gen_crc32(addr, model_info2_p->model_total_size); + + dbg_msg("[%s] crc32 calculated: 0x%x\n", __FUNCTION__, crc32); + dbg_msg("[%s] crc32 read from flash: 0x%x\n", __FUNCTION__, model_info2_p->model_checksum); + dbg_msg("[%s] model start address: 0x%x\n", __FUNCTION__, s_model_data.p_model_info[0].cmd_mem_addr); + dbg_msg("[%s] model total size: %d\n", __FUNCTION__, model_info2_p->model_total_size); + + if (crc32 != model_info2_p->model_checksum) + { + err_msg("[ERR] %s: all models.bin CRC check failed\n", __FUNCTION__); + return 0; + } +#endif + + return s_model_data.n_model_count; + } else { // load specific model + ret = _load_model(model_info_index_p); + return ret; + } +} + +int32_t kmdw_model_reload_model_info(bool from_ddr) +{ + return _load_model_info(from_ddr, true/*reload*/); +} + +int32_t kmdw_model_refresh_models(void) // reload all the models from flash again +{ + uint8_t i; + + // forcedly update s_model_data which might be poluted by model upload from host + if(0 == _load_model_info(false/*from ddr*/, true/*reload*/)) + return 0; //error, no model is loaded + + int ret; + for (i = 0 ; i < s_model_data.n_model_count ; i++) { + if (s_model_data.pn_is_model_loaded_table[i]) { // if previously loaded + s_model_data.pn_is_model_loaded_table[i] = 0; + ret = _load_model(i); // reload the model again + if ( 0 == ret) { + err_msg("[ERR] %s : failed to load model array index:%d\n", __FUNCTION__, i); + return 0; + } + } + } + return s_model_data.n_model_count; +} + +int32_t kmdw_model_config_result(osEventFlagsId_t result_evt, uint32_t result_evt_flag) +{ + int active_idx = s_current_ipc_idx; + + s_img_data[active_idx].evt_result = result_evt; + s_img_data[active_idx].result_e = result_evt_flag; + + return 0; +} + +void kmdw_model_config_img(struct kdp_img_cfg *img_cfg, void *ext_param) +{ + int act_img_idx = img_cfg->image_buf_active_index; + struct kdp_img_raw_s *raw_img = kmdw_model_get_raw_img(act_img_idx); + + s_current_ipc_idx = s_next_ipc_idx; + + if (img_cfg->inf_format & IMAGE_FORMAT_PARALLEL_PROC) + s_next_ipc_idx = !s_next_ipc_idx; + + kmdw_ipc_set_image_active(act_img_idx); + s_img_data[s_current_ipc_idx].raw_img_idx = act_img_idx; + + raw_img->state = IMAGE_STATE_ACTIVE; + raw_img->seq_num = act_img_idx; + + raw_img->ref_idx = s_current_ipc_idx; + raw_img->num_image = img_cfg->num_image; + raw_img->inf_format = img_cfg->inf_format; + + for (int i = 0; i < img_cfg->num_image; i++) { + raw_img->image_list[i].input_row = img_cfg->image_list[i].input_row; + raw_img->image_list[i].input_col = img_cfg->image_list[i].input_col; + raw_img->image_list[i].input_channel = img_cfg->image_list[i].input_channel; + raw_img->image_list[i].format = img_cfg->image_list[i].format; + raw_img->image_list[i].image_mem_addr = img_cfg->image_list[i].image_mem_addr; + raw_img->image_list[i].image_mem_len = img_cfg->image_list[i].image_mem_len; + + memcpy(&(raw_img->image_list[i].params_s), &(img_cfg->image_list[i].params_s), sizeof(parameter_t)); + } + + if (ext_param == NULL) { + memset(raw_img->ext_params, 0, MAX_PARAMS_LEN * 4); + } else { + memcpy(raw_img->ext_params, ext_param, MAX_PARAMS_LEN * 4); + } +} + +struct kdp_img_raw_s* kmdw_model_get_raw_img(int idx) +{ + struct scpu_to_ncpu_s *comm_out = kmdw_ipc_get_output(); + return &(comm_out->raw_images[idx]); +} + +int kmdw_model_run(const char *tag, void *output, uint32_t model_type, bool model_from_ddr) +{ + int model_idx = _config_model(model_type, model_from_ddr); + if (model_idx < 0) { + return KMDW_MODEL_RUN_RC_ABORT; + } + + int img_idx = s_img_data[s_current_ipc_idx].raw_img_idx; + struct kdp_img_raw_s *raw_img = kmdw_model_get_raw_img(img_idx); + + raw_img->results[model_idx].result_mem_addr = (uint32_t)output; + + dbg_msg("[INFO] %s:\n", tag); + dbg_msg(" model_idx = %d\n", model_idx); + dbg_msg(" model type = %d\n", model_type); + dbg_msg(" ref_idx = %d\n", raw_img->ref_idx); + dbg_msg(" inf_format = 0x%X\n", raw_img->inf_format); + dbg_msg(" output addr = 0x%x\n", raw_img->results[model_idx].result_mem_addr); + dbg_msg(" ext_params(first 4)= %d/%d/%d/%d\n", raw_img->ext_params[0], raw_img->ext_params[1], + raw_img->ext_params[2], raw_img->ext_params[3]); + + for (int i = 0; i < raw_img->num_image; i++) { + dbg_msg(" image index: %d\n", i); + dbg_msg(" (row/col/ch) = %d/%d/%d\n", raw_img->image_list[i].input_row, + raw_img->image_list[i].input_col, + raw_img->image_list[i].input_channel); + dbg_msg(" image format = 0x%x\n", raw_img->image_list[i].format); + dbg_msg(" crop(tp/bt/lf/rt) = %d/%d/%d/%d\n", raw_img->image_list[i].params_s.crop_top, + raw_img->image_list[i].params_s.crop_bottom, + raw_img->image_list[i].params_s.crop_left, + raw_img->image_list[i].params_s.crop_right); + dbg_msg(" image addr = 0x%x\n", raw_img->image_list[i].image_mem_addr); + } + + return _run_model(); +} + +void kmdw_model_abort(void) +{ + int active_idx = s_current_ipc_idx; + + if( 0 == s_img_data[active_idx].evt_caller) + return; + + osEventFlagsSet(s_img_data[active_idx].evt_caller, FLAG_KMDW_MODEL_ABORT); +} + +struct kdp_model_s* kmdw_model_get_model_info(int model_idx_p) +{ + if (s_model_data.n_model_count == 0) { + return NULL; + } else if (model_idx_p >= s_model_data.n_model_count) { + return NULL; + } else { + return &(s_model_data.p_model_info[model_idx_p]); + } +} + +void kmdw_model_get_run_time(int img_idx, kmdw_model_run_time_t *run_time/*out*/) +{ + struct kdp_img_raw_s *p_raw_image; + + if (run_time == NULL) + return; + + p_raw_image = kmdw_model_get_raw_img(img_idx); + + run_time->round_trip_time = p_raw_image->tick_end - p_raw_image->tick_start; + run_time->pre_proc_time = p_raw_image->tick_end_pre - p_raw_image->tick_start_pre; + run_time->npu_proc_time = p_raw_image->tick_end_npu - p_raw_image->tick_start_npu; + run_time->post_proc_time = p_raw_image->tick_end_post - p_raw_image->tick_start_post; +} + + + +int kmdw_model_is_model_loaded(uint32_t model_type) +{ + if (_get_model_info_array_index_by_model_type(model_type) == -1) + return 0; + else + return 1; +} + +uint32_t *kmdw_model_get_all_model_info(bool trust_ddr_data) +{ + static uint32_t *s_p_model_id_list = NULL; //[model_count, id0, id1, id2 ...] + + kmdw_model_fw_info_t *fw_info_ptr = NULL; + + fw_info_ptr = kmdw_model_get_fw_info(trust_ddr_data); + + if (fw_info_ptr) { + + if (NULL == s_p_model_id_list) + s_p_model_id_list = (uint32_t *)calloc(1+KMDW_MODEL_MAX_MODEL_COUNT, sizeof(uint32_t)); + + if (NULL == s_p_model_id_list) { + err_msg("[ERR] insufficent memory for model id list\n"); + } else { + int i; + uint32_t model_id; + + s_p_model_id_list[0] = fw_info_ptr->model_count; + dbg_msg("%s:\n", __FUNCTION__); + dbg_msg("Model Count = %d\n", s_p_model_id_list[0]); + + for (i = 0 ; i < s_p_model_id_list[0]; i++) { + model_id = fw_info_ptr->models[i].model_type; + dbg_msg("Extract Model ID %d\n", model_id); + + s_p_model_id_list[i+1] = model_id; + } + } + return s_p_model_id_list; + } else { + return NULL; + } + +} + +uint32_t kmdw_model_get_crc(bool trust_ddr_data) +{ + uint32_t ret = 0; + kmdw_model_fw_info_t *fw_info_ptr; + kmdw_model_fw_info_ext_t *fw_info_ext_ptr; + + fw_info_ptr = kmdw_model_get_fw_info(trust_ddr_data); + fw_info_ext_ptr = _get_fw_info_ext_by_fw_info(fw_info_ptr); + + if (fw_info_ext_ptr) { + ret = fw_info_ext_ptr->model_checksum; + } + + dbg_msg("%s = 0x%x\n", __FUNCTION__, ret); + + return ret; +} + + +kmdw_model_fw_info_t *kmdw_model_get_fw_info(bool trust_ddr_data) +{ + uint32_t model_cnt; + kmdw_model_fw_info_t *fw_info_ptr = s_fw_info_buf_p; + + if (false == trust_ddr_data) { + if ((0 >= s_model_data.n_model_count) || + ((1 != s_model_data.n_model_source) && (2 != s_model_data.n_model_source))) { + fw_info_ptr = NULL; + } else { + model_cnt = fw_info_ptr->model_count; + + if ((0 == model_cnt) || (model_cnt > KMDW_MODEL_MAX_MODEL_COUNT)) { + fw_info_ptr = NULL; + } + } + } + + return fw_info_ptr; +} + +uint32_t kmdw_model_get_model_end_addr(bool trust_ddr_data) +{ + uint32_t ret = 0; + kmdw_model_fw_info_t* fw_info_ptr; + kmdw_model_fw_info_ext_t* fw_info_ext_ptr = NULL; + + if (0 != s_model_data.n_ddr_addr_model_end) { + ret = s_model_data.n_ddr_addr_model_end; + goto FUNC_OUT; + } + + fw_info_ptr = kmdw_model_get_fw_info(trust_ddr_data); + fw_info_ext_ptr = _get_fw_info_ext_by_fw_info(fw_info_ptr); + + if (fw_info_ext_ptr) { + ret = fw_info_ext_ptr->model_dram_addr_end; + } + +FUNC_OUT: + + dbg_msg("%s = 0x%x\n", __FUNCTION__, ret); + + return ret; +} + +void kmdw_model_set_location(bool model_inddr) +{ + ModelFromDDR = model_inddr; +} + +bool kmdw_model_get_location(void) +{ + return ModelFromDDR; +} + +int kmdw_model_get_input_tensor_num(uint32_t model_type) +{ + int model_idx = 0; + + model_idx = _get_model_info_array_index_by_model_type(model_type); + if (model_idx >= 0) { + /****************************************************************** + * KL520 only support single input model + ******************************************************************/ + return 1; + } else { + err_msg("[%s] invalid model id %d\n", __FUNCTION__, model_type); + return 0; + } +} + +int kmdw_model_get_input_tensor_info(uint32_t model_type, uint32_t tensor_idx, kmdw_model_tensor_descriptor_t *tensor_info) +{ + int ret = 1; + int model_idx = 0; + uint32_t p_setup_bin = 0; + struct cnn_header_s *target_input_node = NULL; + + if (NULL == tensor_info) { + err_msg("[%s] NULL tensor_info pointer\n", __FUNCTION__); + ret = 0; + goto FUNC_OUT; + } + + model_idx = _get_model_info_array_index_by_model_type(model_type); + if (model_idx >= 0) { + struct kdp_model_s *p_model_info = kmdw_model_get_model_info(model_idx); + + if (NULL != p_model_info) { + p_setup_bin = p_model_info->setup_mem_addr; + } else { + err_msg("[%s] NULL model info pointer %d\n", __FUNCTION__); + return 0; + } + } else { + err_msg("[%s] invalid model id %d\n", __FUNCTION__, model_type); + ret = 0; + goto FUNC_OUT; + } + + if (tensor_idx >= 1) { + err_msg("[%s] tensor index out of range %d\n", __FUNCTION__, tensor_idx); + ret = 0; + goto FUNC_OUT; + } + + target_input_node = (struct cnn_header_s *)p_setup_bin; + + tensor_info->index = 1; + tensor_info->shape_npu_len = 4; + tensor_info->shape_npu[0] = 1; + tensor_info->shape_npu[1] = target_input_node->input_channel; + tensor_info->shape_npu[2] = target_input_node->input_row; + tensor_info->shape_npu[3] = target_input_node->input_col; + tensor_info->data_layout = DATA_FMT_4W4C8B; + tensor_info->scale = 1.0; + tensor_info->radix = target_input_node->input_radix; + +FUNC_OUT: + return ret; +} + +int kmdw_model_get_output_tensor_num(uint32_t model_type) +{ + int model_idx = 0; + struct kdp_model_s *p_model_info = NULL; + + model_idx = _get_model_info_array_index_by_model_type(model_type); + if (model_idx >= 0) { + p_model_info = kmdw_model_get_model_info(model_idx); + } else { + err_msg("[%s] invalid model id %d\n", __FUNCTION__, model_type); + return 0; + } + + /****************************************************************** + * legacy setup.bin model + ******************************************************************/ + if (NULL != p_model_info) { + return ((struct cnn_header_s *)p_model_info->setup_mem_addr)->output_nums; + } else { + err_msg("[%s] NULL model info pointer %d\n", __FUNCTION__); + return 0; + } +} + +int kmdw_model_get_output_tensor_info(uint32_t model_type, uint32_t tensor_idx, kmdw_model_tensor_descriptor_t *tensor_info) +{ + int ret = 1; + int model_idx = 0; + uint32_t p_setup_bin = 0; + uint32_t node_num = 0; + uint32_t setup_buff_offset = sizeof(struct cnn_header_s); + uint32_t setup_buff_size = 0; + struct out_node_s *target_output_node = NULL; + struct out_node_s *output_node = NULL; + + if (NULL == tensor_info) { + err_msg("[%s] NULL tensor_info pointer\n", __FUNCTION__); + ret = 0; + goto FUNC_OUT; + } + + model_idx = _get_model_info_array_index_by_model_type(model_type); + if (model_idx >= 0) { + struct kdp_model_s *p_model_info = kmdw_model_get_model_info(model_idx); + + if (NULL != p_model_info) { + p_setup_bin = p_model_info->setup_mem_addr; + setup_buff_size = p_model_info->setup_mem_len; + } else { + err_msg("[%s] NULL model info pointer %d\n", __FUNCTION__); + return 0; + } + } else { + err_msg("[%s] invalid model id %d\n", __FUNCTION__, model_type); + ret = 0; + goto FUNC_OUT; + } + + node_num = ((struct cnn_header_s *)p_setup_bin)->output_nums; + + if (tensor_idx >= node_num) { + err_msg("[%s] tensor index out of range %d\n", __FUNCTION__, tensor_idx); + ret = 0; + goto FUNC_OUT; + } + + while ((setup_buff_offset < setup_buff_size) && (NULL == target_output_node)) { + uintptr_t node_buff = (uintptr_t)p_setup_bin + setup_buff_offset; + uint32_t node_id = *(uint32_t *)node_buff; + uint32_t node_offset = 0; + + switch (node_id) { + case NODE_TYPE_IN: + // NPU IN Signal NODE + dbg_msg("current node is an NPU IN Signal NODE\n"); + node_offset = sizeof(struct in_node_s); + break; + case NODE_TYPE_CPU: + // CPU NODE + dbg_msg("current node is a CPU NODE\n"); + node_offset = sizeof(struct cpu_node_s) - (2 * sizeof(struct data_node_s)); + break; + case NODE_TYPE_OUTPUT: + // OUTPUT NODE + dbg_msg("current node is a output NODE\n"); + output_node = (struct out_node_s *)node_buff; + node_offset = sizeof(struct out_node_s) - (sizeof(struct super_node_s)); + + if (output_node->output_index == tensor_idx) + target_output_node = output_node; + break; + case NODE_TYPE_DATA: + // NPU DATA NODE + dbg_msg("current node is an network data NODE\n"); + node_offset = sizeof(struct data_node_s) - sizeof(struct super_node_s); + break; + case NODE_TYPE_SUPER: + // NPU SUPER NODE + dbg_msg("current node is an network super NODE\n"); + node_offset = sizeof(struct super_node_s); + break; + default: + // Unknown NODE + err_msg("[%s] unknown node type: %d\n", __FUNCTION__, node_id); + ret = 0; + goto FUNC_OUT; + } + + setup_buff_offset += node_offset; + } + + if (NULL == target_output_node) { + err_msg("[%s] can not find target index node %d\n", __FUNCTION__, tensor_idx); + ret = 0; + goto FUNC_OUT; + } + + tensor_info->index = target_output_node->output_index; + tensor_info->shape_npu_len = 4; + tensor_info->shape_npu[0] = 1; + tensor_info->shape_npu[1] = target_output_node->ch_length; + tensor_info->shape_npu[2] = target_output_node->row_length; + tensor_info->shape_npu[3] = target_output_node->col_length; + tensor_info->data_layout = target_output_node->data_format; + tensor_info->scale = *(float *)&(target_output_node->output_scale); + tensor_info->radix = target_output_node->output_radix; + +FUNC_OUT: + return ret; +} + +#ifdef EMBED_CMP_NPU + +int8_t kmdw_model_add_update_model(uint32_t model_type, + int cmd_len, int wt_len, int input_len, int output_len, int setup_len, + uint32_t cmd_mem_addr, uint32_t wt_mem_addr, + uint32_t input_mem_addr, uint32_t output_mem_addr, uint32_t setup_mem_addr) +{ + int model_info_idx = _get_model_info_array_index_from_model_type(model_type); + + if (model_info_idx < 0) { + int model_count = s_model_data.n_model_count + 1; + s_model_data.n_model_count = model_count; + model_info_idx = model_count - 1; + + s_model_data.p_model_info[model_info_idx].model_type = model_type; + + s_model_data.p_model_info[model_info_idx].cmd_mem_addr = cmd_mem_addr; + s_model_data.p_model_info[model_info_idx].cmd_mem_len = cmd_len; + + s_model_data.p_model_info[model_info_idx].weight_mem_len = wt_len; + + s_model_data.p_model_info[model_info_idx].input_mem_addr = input_mem_addr; + s_model_data.p_model_info[model_info_idx].input_mem_len = input_len; + + s_model_data.p_model_info[model_info_idx].output_mem_len = output_len; + s_model_data.p_model_info[model_info_idx].buf_len = output_len; + + s_model_data.p_model_info[model_info_idx].setup_mem_addr = setup_mem_addr; + s_model_data.p_model_info[model_info_idx].setup_mem_len = setup_len; + + s_model_data.pn_is_model_loaded_table[model_info_idx] = 1; + } + + s_model_data.p_model_info[model_info_idx].weight_mem_addr = wt_mem_addr; + s_model_data.p_model_info[model_info_idx].output_mem_addr = output_mem_addr; + s_model_data.p_model_info[model_info_idx].buf_addr = output_mem_addr; + + dbg_msg("[%s] model cmd addr: 0x%x\n", __func__, s_model_data.p_model_info[model_info_idx].cmd_mem_addr); + dbg_msg("[%s] model wt addr: 0x%x\n", __func__, s_model_data.p_model_info[model_info_idx].weight_mem_addr); + dbg_msg("[%s] model input addr: 0x%x\n", __func__, s_model_data.p_model_info[model_info_idx].input_mem_addr); + dbg_msg("[%s] model output addr: 0x%x\n", __func__, s_model_data.p_model_info[model_info_idx].output_mem_addr); + dbg_msg("[%s] model buf addr: 0x%x\n", __func__, s_model_data.p_model_info[model_info_idx].buf_addr); + dbg_msg("[%s] model setup addr: 0x%x\n", __func__, s_model_data.p_model_info[model_info_idx].setup_mem_addr); + + udt_npu_model_mem(wt_mem_addr, output_mem_addr, (void *)cmd_mem_addr); + + return 0; +} + +#endif // EMBED_CMP_NPU + +#if DEBUG + +void kmdw_model_dump_model_info(void) +{ + struct kdp_model_s *p_modelInfo = 0; + uint8_t i; + + dbg_msg("Model info Count = %d\n", s_model_data.n_model_count); + + for (i = 0 ; i < s_model_data.n_model_count ; i++) { + p_modelInfo = &(kmdw_model_data.p_model_info[i]); + dbg_msg("Model(%2d) model_type(%3d)/version(%5d):\n", + (i+1), + p_modelInfo->model_type, p_modelInfo->model_version); + + dbg_msg("input[%x](sz:%d) -> cmd[%x](sz:%d),weight[%x](sz:%d),setup[%x](sz:%d),buf[%x](sz:%d) -> out[%x](sz:%d)\n", + (i+1), + p_modelInfo->input_mem_addr, p_modelInfo->input_mem_len, + p_modelInfo->cmd_mem_addr, p_modelInfo->cmd_mem_len, + p_modelInfo->weight_mem_addr,p_modelInfo->weight_mem_len, + p_modelInfo->setup_mem_addr, p_modelInfo->setup_mem_len, + p_modelInfo->buf_addr, p_modelInfo->buf_len, + p_modelInfo->output_mem_addr,p_modelInfo->output_mem_len); + } + + return; +} + +#endif // DEBUG diff --git a/mdw/power/kmdw_power_manager.c b/mdw/power/kmdw_power_manager.c new file mode 100644 index 0000000..07de8f0 --- /dev/null +++ b/mdw/power/kmdw_power_manager.c @@ -0,0 +1,571 @@ +/* + * Kneron Power Manager driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" +#include "os_tick.h" +#include "RTX_Config.h" +#include "kmdw_power_manager.h" +#include "kdrv_scu.h" +#include "kdrv_power.h" +#include "kdrv_clock.h" +#include "kdrv_system.h" +#include "kmdw_system.h" +#include "rtc.h" // TODO: need to rewrite to kdrv_rtc.h +#include "kdrv_ddr.h" +#include "kmdw_console.h" +#include "kdrv_cmsis_core.h" + +#define FLAG_SYSTEM_RESET BIT0 +#define FLAG_SYSTEM_NAP BIT1 +#define FLAG_SYSTEM_NAP2 BIT2 +#define FLAG_SYSTEM_SLEEP BIT3 +#define FLAG_SYSTEM_DEEP_SLEEP BIT4 +#define FLAG_SYSTEM_TIMER BIT5 +#define FLAG_SYSTEM_SHUTDOWN BIT6 +#define FLAG_SYSTEM_ERROR BIT8 +#define FLAG_SYSTEM_PWRBTN_FALL BIT16 +#define FLAG_SYSTEM_PWRBTN_RISE BIT17 + +#define FLAGS_ALL (FLAG_SYSTEM_RESET | FLAG_SYSTEM_SHUTDOWN \ + | FLAG_SYSTEM_NAP | FLAG_SYSTEM_NAP2 \ + | FLAG_SYSTEM_SLEEP | FLAG_SYSTEM_DEEP_SLEEP \ + | FLAG_SYSTEM_TIMER | FLAG_SYSTEM_ERROR \ + | FLAG_SYSTEM_PWRBTN_FALL | FLAG_SYSTEM_PWRBTN_RISE) + +#define PERIOD_PRINT (3 * OS_TICK_FREQ) // 3 secs +#define PERIOD_COUNT (PERIOD_PRINT + PERIOD_PRINT/100) // add 1% margin + +/* SCU_REG_INT_EN & SCU_REG_INT_STS */ +#define SCU_INT_RTC_PERIODIC BIT17 +#define SCU_INT_RTC_ALARM BIT16 +#define SCU_INT_PLL_UPDATE BIT8 +#define SCU_INT_FCS BIT6 +#define SCU_INT_BUSSPEED BIT5 +#define SCU_INT_WAKEUP BIT3 +#define SCU_INT_PWRBTN_RISE BIT1 +#define SCU_INT_PWRBTN_FALL BIT0 + +/* Inactivity timers in seconds */ +#define NAP_TIME_1 30 +#define NAP_TIME_2 60 + +osThreadId_t power_tid; +uint32_t cpu_idle_counter = 0; + +uint32_t idle_entry_time_in_secs; +uint32_t idle_exit_time_in_secs; +uint32_t sleep_state; + +kmdw_power_manager_ptn_handler ptn_cb; + +static struct pm_device_func_s { + enum kmdw_power_manager_device_id dev_id; + int inuse; + struct kmdw_power_manager_s pm; +} _pm_dev_fns[KMDW_POWER_MANAGER_DEVICE_MAX]; + +static void scu_system_isr(void) +{ + static int pwr_button_wakeup = 1; // = 1 for cold boot by PWR button + uint32_t status; + + status = inw(SCU_REG_INT_STS); + + if (status & SCU_INT_RTC_ALARM) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_NAP); + if (status & SCU_INT_RTC_PERIODIC) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_TIMER); + if (status & SCU_INT_PWRBTN_FALL) { + if (pwr_button_wakeup) { + pwr_button_wakeup = 0; + } else { + osThreadFlagsSet(power_tid, FLAG_SYSTEM_PWRBTN_FALL); + } + } + if (status & SCU_INT_PWRBTN_RISE) { + if (sleep_state == 1) { + pwr_button_wakeup = 1; + } else { + pwr_button_wakeup = 0; + osThreadFlagsSet(power_tid, FLAG_SYSTEM_PWRBTN_RISE); + } + } + + outw(SCU_REG_INT_STS, status); + NVIC_ClearPendingIRQ(SYS_SYSTEM_IRQ); +} + +static void _scu_system_init(void) +{ + NVIC_DisableIRQ(SYS_SYSTEM_IRQ); + + rtc_init(NULL, NULL); + outw(SCU_REG_INT_STS, 0xffffffff); // Clear all old ones + + /* Enable PWR button interrupt and wakeup */ + outw(SCU_REG_INT_EN, SCU_INT_PWRBTN_FALL | SCU_INT_PWRBTN_RISE | SCU_INT_WAKEUP); + + /* Enable nap alarm interrupt */ + uint32_t nap_time = NAP_TIME_1; + rtc_alarm_enable(ALARM_IN_SECS, &nap_time, NULL); + masked_outw(SCU_REG_INT_EN, SCU_INT_RTC_ALARM, SCU_INT_RTC_ALARM); + + NVIC_SetVector(SYS_SYSTEM_IRQ, (uint32_t)scu_system_isr); + NVIC_EnableIRQ(SYS_SYSTEM_IRQ); +} + +#define MMFAR 0xE000ED34 +#define FLAG_WAIT_FOREVER 0x40000000 +static void _scpu_wait_reset(void) +{ + osThreadId_t calling_tid = osThreadGetId(); + if ((calling_tid == 0) || (calling_tid == power_tid)){ // no os or if power mgmnt thread is in trouble +#if 0 + kdrv_power_sw_reset(); +#else + for (;;); +#endif + } + else // let power mgmnt thread handles the reset + osThreadFlagsWait((u32)calling_tid , FLAG_WAIT_FOREVER, osWaitForever); +} + +register unsigned int _msp __asm("msp"); +register unsigned int _psp __asm("psp"); +register unsigned int _lr __asm("lr"); +static unsigned int stack, pc; + +static void _scpu_hard_fault(void) +{ + if (_lr & 4) { + stack = _psp; + pc = stack + 24; + } + else { + stack = _msp; + pc = stack + 40; + } + + err_msg("scpu: hard fault @ %08X, PC = %08X, LR = %08X, SP = %08X\n", *(u32*)MMFAR, + *(u32*)pc, *(u32*)(pc-4), (u32)pc+8); + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_ERROR); + *(u32*)pc = (u32)&_scpu_wait_reset; // modify stack to go to the wait forever loop +} + +static void _scpu_mem_mnmt(void) +{ + if (_lr & 4) { + stack = _psp; + pc = stack + 24; + } + else { + stack = _msp; + pc = stack + 40; + } + + err_msg("scpu: memory fault @ %08X, PC = %08X, LR = %08X, SP = %08X\n", *(u32*)MMFAR, + *(u32*)pc, *(u32*)(pc-4), (u32)pc+8); + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_ERROR); + *(u32*)pc = (u32)&_scpu_wait_reset; // modify stack to go to the wait forever loop +} + +static void _scpu_bus_fault(void) +{ + err_msg("scpu: _scpu_bus_fault !\n"); + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_ERROR); +} + +static void _scpu_usage_fault(void) +{ + err_msg("scpu: _scpu_usage_fault !\n"); + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_ERROR); +} + +void kmdw_power_manager_error_notify(uint32_t code, void *object_id) +{ + err_msg("scpu: exception: code=%d, object_id=0x%p\n", code, object_id); + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_ERROR); +} + +void kmdw_power_manager_reset(void) +{ + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_RESET); +} + +void kmdw_power_manager_sleep(void) +{ + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_SLEEP); +} + +void kmdw_power_manager_deep_sleep(void) +{ + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_DEEP_SLEEP); +} + +void kmdw_power_manager_shutdown(void) +{ + if (power_tid) + osThreadFlagsSet(power_tid, FLAG_SYSTEM_SHUTDOWN); +} + +static void _power_mgr_cpu_usage(void) +{ + static uint32_t last_record=0, print_count=0, diff; + + diff = (cpu_idle_counter - last_record); + last_record = cpu_idle_counter; + + if (diff > PERIOD_COUNT) + diff = PERIOD_COUNT; + + info_msg("#%04d cpu loading %d %%\n", ++print_count, + (PERIOD_COUNT - diff) * 100 / PERIOD_COUNT); +} + +__NO_RETURN void kmdw_power_manager_cpu_idle(void) +{ + uint32_t tick_start, tick_end, tick_idle; + + while(1) { + rtc_get_date_time_in_secs(&idle_entry_time_in_secs); + tick_start = osKernelGetTickCount(); + __WFI(); + tick_end = osKernelGetTickCount(); + tick_idle = tick_end - tick_start; + cpu_idle_counter += tick_idle; + rtc_get_date_time_in_secs(&idle_exit_time_in_secs); + } +} + +static void _power_manager_do_nap(void) +{ + int i; + + for (i = KMDW_POWER_MANAGER_DEVICE_MAX - 1; i >= 0; i--) { + if (_pm_dev_fns[i].inuse && _pm_dev_fns[i].pm.nap) + { + if(_pm_dev_fns[i].pm.nap(_pm_dev_fns[i].dev_id) < 0) + { + info_msg("Can't take a nap\n"); + return; + } + } + } + dbg_msg("Take a nap\n"); + /* Disable npu/ncpu clocks */ + kdrv_clock_disable(CLK_NPU); + kdrv_clock_disable(CLK_NCPU); + __WFI(); + kdrv_clock_enable(CLK_NCPU); + kdrv_clock_enable(CLK_NPU); + + for (i = 0; i < KMDW_POWER_MANAGER_DEVICE_MAX; i++) { + if (_pm_dev_fns[i].inuse && _pm_dev_fns[i].pm.wakeup_nap) + _pm_dev_fns[i].pm.wakeup_nap(_pm_dev_fns[i].dev_id); + } +} + +static void _power_manager_do_deep_nap(void) +{ + int i; + + for (i = KMDW_POWER_MANAGER_DEVICE_MAX - 1; i >= 0; i--) { + if (_pm_dev_fns[i].inuse && _pm_dev_fns[i].pm.deep_nap) + { + if(_pm_dev_fns[i].pm.deep_nap(_pm_dev_fns[i].dev_id) < 0) + { + info_msg("Can't take a deep nap\n"); + return; + } + } + } + dbg_msg("Take a deep nap\n"); + /* Disable npu/ncpu clocks + DDR self refresh */ + kdrv_clock_disable(CLK_NPU); + kdrv_clock_disable(CLK_NCPU); + kdrv_ddr_self_refresh_enter(); + __WFI(); + kdrv_ddr_self_refresh_exit(); + kdrv_clock_enable(CLK_NCPU); + kdrv_clock_enable(CLK_NPU); + + for (i = 0; i < KMDW_POWER_MANAGER_DEVICE_MAX; i++) { + if (_pm_dev_fns[i].inuse && _pm_dev_fns[i].pm.wakeup_deep_nap) + _pm_dev_fns[i].pm.wakeup_deep_nap(_pm_dev_fns[i].dev_id); + } +} + +static void _power_manager_do_sleep(void) +{ + int i; + + for (i = KMDW_POWER_MANAGER_DEVICE_MAX - 1; i >= 0; i--) { + if (_pm_dev_fns[i].inuse && _pm_dev_fns[i].pm.sleep) + { + if(_pm_dev_fns[i].pm.sleep(_pm_dev_fns[i].dev_id) < 0) + { + info_msg("Can't sleep\n"); + return; + } + } + } + dbg_msg("!!! sleep\n"); + + sleep_state = 1; + + /* Retention: NPU power domain off */ + kdrv_clock_disable(CLK_NPU); + kdrv_clock_disable(CLK_NCPU); + kdrv_ddr_self_refresh_enter(); + __WFI(); + kdrv_ddr_self_refresh_exit(); +// kdrv_clock_enable(CLK_NCPU); // these are done in system_wakeup_ncpu(); +// kdrv_clock_enable(CLK_NPU); + load_ncpu_fw(0); // reload ncpu fw but don't start it yet + system_wakeup_ncpu(0, 1); + // ddr doesn't seemed correct, reload default models for testing ??? + + sleep_state = 0; + dbg_msg("!!! sleep -> wakeup\n"); + + for (i = 0; i < KMDW_POWER_MANAGER_DEVICE_MAX; i++) { + if (_pm_dev_fns[i].inuse && _pm_dev_fns[i].pm.wakeup_sleep) + _pm_dev_fns[i].pm.wakeup_sleep(_pm_dev_fns[i].dev_id); + } +} + +static void _power_manager_do_deep_sleep(void) +{ + int i; + + for (i = KMDW_POWER_MANAGER_DEVICE_MAX - 1; i >= 0; i--) { + if (_pm_dev_fns[i].inuse && _pm_dev_fns[i].pm.deep_sleep) + { + if(_pm_dev_fns[i].pm.deep_sleep(_pm_dev_fns[i].dev_id) < 0) + { + info_msg("Can't deep sleep\n"); + return; + } + } + } + + dbg_msg("!!! deep sleep\n\n"); + + /* Deep Retention: NPU+Default domain off */ + kdrv_power_softoff(POWER_MODE_DEEP_RETENTION); + __WFI(); + + err_msg("!!! deep sleep failed!\n"); + + /* TODO: resume here */ + for (i = 0; i < KMDW_POWER_MANAGER_DEVICE_MAX; i++) { + if (_pm_dev_fns[i].inuse && _pm_dev_fns[i].pm.wakeup_deep_sleep) + _pm_dev_fns[i].pm.wakeup_deep_sleep(_pm_dev_fns[i].dev_id); + } +} + +static void _power_manager_do_shutdown(void) +{ + dbg_msg("!!! shutdown ...\n\n"); + + /* Disable alarm */ + rtc_alarm_disable(ALARM_IN_SECS); + + /* Power off everything except RTC */ + kdrv_power_softoff(POWER_MODE_RTC); + __WFI(); + + err_msg("!!! shutdown failed!\n"); + for (;;); +} + +//#define PRINT_CPU_USAGE + +void _kmdw_power_manager_thread(void *arg) +{ + uint32_t status, timeout; + uint32_t current_time, elapsed_time, nap_time, pwrbtn_press_time, pwrbtn_release_time; + + /* Init system/power/rtc control on SCU */ + _scu_system_init(); + +#ifdef PRINT_CPU_USAGE + timeout = PERIOD_PRINT; +#else + timeout = osWaitForever; +#endif + + while(1) + { + status = osThreadFlagsWait(FLAGS_ALL, osFlagsWaitAny, timeout); + + if (status == osFlagsErrorTimeout) { + _power_mgr_cpu_usage(); + continue; + } + + if (status & FLAG_SYSTEM_SLEEP) { + _power_manager_do_sleep(); + } + + if (status & FLAG_SYSTEM_DEEP_SLEEP) { + _power_manager_do_deep_sleep(); + } + + if (status & FLAG_SYSTEM_RESET) { + info_msg("!!! reset\r\n"); + // will not come back + kdrv_delay_us(50*1000); + kdrv_power_sw_reset(); + } + + if (status & FLAG_SYSTEM_SHUTDOWN) { + // will not come back + _power_manager_do_shutdown(); + } + + if (status & FLAG_SYSTEM_NAP) { + + if (idle_exit_time_in_secs > idle_entry_time_in_secs) + elapsed_time = idle_exit_time_in_secs - idle_entry_time_in_secs; + else + elapsed_time = 0; + + /* update */ + rtc_get_date_time_in_secs(&idle_entry_time_in_secs); + + /* set next alarm */ + if (elapsed_time < NAP_TIME_1) { + nap_time = NAP_TIME_1; + rtc_alarm_enable(ALARM_IN_SECS, &nap_time, NULL); + } else if (elapsed_time < NAP_TIME_2) { + //rtc_current_time_info(); + dbg_msg("Idle: %d seconds -> nap\n", elapsed_time); + /* Set longer nap time */ + nap_time = NAP_TIME_2; + rtc_alarm_enable(ALARM_IN_SECS, &nap_time, NULL); + /* Take nap */ + _power_manager_do_nap(); + /* regular nap time upon wakeup */ + nap_time = NAP_TIME_1; + rtc_alarm_enable(ALARM_IN_SECS, &nap_time, NULL); + } else { + //rtc_current_time_info(); + dbg_msg("Idle: %d seconds -> deep nap\n", elapsed_time); + /* Set even longer nap time */ + nap_time = NAP_TIME_2 * 10; + rtc_alarm_enable(ALARM_IN_SECS, &nap_time, NULL); + /* Take deep nap */ + _power_manager_do_deep_nap(); + /* regular nap time upon wakeup */ + nap_time = NAP_TIME_1; + rtc_alarm_enable(ALARM_IN_SECS, &nap_time, NULL); + } + } + + if (status & FLAG_SYSTEM_TIMER) { + rtc_current_time_info(); + + rtc_get_date_time_in_secs(¤t_time); + elapsed_time = current_time - idle_entry_time_in_secs; + + dbg_msg("Idle: %d\n", elapsed_time); + } + + if (status & FLAG_SYSTEM_ERROR) { + err_msg("!!! scpu: error\n"); +#if 0 + kdrv_power_sw_reset(); +#else + // for debug + for (;;) + osDelay(10); +#endif + } + + if (status & FLAG_SYSTEM_PWRBTN_FALL) { + rtc_get_date_time_in_secs(&pwrbtn_release_time); + elapsed_time = pwrbtn_release_time - pwrbtn_press_time; + info_msg("!!! PWR Button pressed for %d seconds:\n", elapsed_time); + if (elapsed_time > 6) + _power_manager_do_shutdown(); + else if (ptn_cb) + ptn_cb(1); + } + + if (status & FLAG_SYSTEM_PWRBTN_RISE) { + rtc_get_date_time_in_secs(&pwrbtn_press_time); + info_msg("!!! PWR Button Press&Hold 7+ seconds for shutdown (RTC mode)\n"); + } + } +} + +/* Registration APIs */ +int kmdw_power_manager_register(enum kmdw_power_manager_device_id dev_id, struct kmdw_power_manager_s *pm_p) +{ + int i; + + if (dev_id >= KMDW_POWER_MANAGER_DEVICE_MAX || pm_p == NULL) + return -1; + + for (i = 0; i < KMDW_POWER_MANAGER_DEVICE_MAX; i++) { + if (_pm_dev_fns[i].inuse == 0) { + memcpy(&_pm_dev_fns[i].pm, pm_p, sizeof(struct kmdw_power_manager_s)); + _pm_dev_fns[i].dev_id = dev_id; + _pm_dev_fns[i].inuse = 1; + break; + } + } + + return 0; +} + +void kmdw_power_manager_unregister(enum kmdw_power_manager_device_id dev_id, struct kmdw_power_manager_s *pm_p) +{ + int i; + + if (dev_id >= KMDW_POWER_MANAGER_DEVICE_MAX || pm_p == NULL) + return; + + for (i = 0; i < KMDW_POWER_MANAGER_DEVICE_MAX; i++) { + if (_pm_dev_fns[i].dev_id == dev_id && _pm_dev_fns[i].pm.sleep == pm_p->sleep && _pm_dev_fns[i].inuse) { + memset(&_pm_dev_fns[i].pm, 0, sizeof(struct kmdw_power_manager_s)); + _pm_dev_fns[i].dev_id = KMDW_POWER_MANAGER_DEVICE_NONE; + _pm_dev_fns[i].inuse = 0; + return; + } + } +} + +void kmdw_power_manager_power_button_register(kmdw_power_manager_ptn_handler button_handler) +{ + ptn_cb = button_handler; +} + +void kmdw_power_manager_init(void) +{ + osThreadAttr_t attr; + + memset(&attr, 0, sizeof(attr)); + attr.stack_size = 512; + attr.priority = osPriorityRealtime7; + power_tid = osThreadNew(_kmdw_power_manager_thread, NULL, &attr); + + NVIC_SetVector(HardFault_IRQn, (uint32_t)_scpu_hard_fault); + NVIC_SetVector(MemoryManagement_IRQn, (uint32_t)_scpu_mem_mnmt); + NVIC_SetVector(BusFault_IRQn, (uint32_t)_scpu_bus_fault); + NVIC_SetVector(UsageFault_IRQn, (uint32_t)_scpu_usage_fault); +} diff --git a/mdw/system/kmdw_system.c b/mdw/system/kmdw_system.c new file mode 100644 index 0000000..3b854c1 --- /dev/null +++ b/mdw/system/kmdw_system.c @@ -0,0 +1,120 @@ +/* + * Kneron System driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include "cmsis_os2.h" +#include "board.h" +#include "project.h" + +#include "kdrv_system.h" +#include "kdrv_scu.h" +#include "kdrv_scu_ext.h" +#include "kdrv_power.h" +#include "kdrv_clock.h" +#include "kdrv_ddr.h" +#include "kdrv_pwm.h" +#include "kdrv_mpu.h" + +#include "kmdw_console.h" +#include "kmdw_memxfer.h" +#include "kmdw_dfu.h" +#include "kmdw_utils_crc.h" +#include "kmdw_system.h" + +extern const struct s_kdp_memxfer kdp_memxfer_module; + +void system_wakeup_ncpu(int32_t boot_loader_flag, uint8_t wakeup_all) +{ + if (boot_loader_flag) + kdrv_pwmtimer_delay_ms(200); + + if (1 == wakeup_all) { + kdrv_clock_enable(CLK_SCPU_TRACE); + kdrv_clock_enable(CLK_NCPU); + kdrv_clock_enable(CLK_NPU); + kdrv_system_reset(SUBSYS_PD_NPU); + kdrv_system_reset(SUBSYS_NPU); + } + + SCU_EXTREG_CM4_NCPU_CTRL_SET_wakeup(1); +} + + + +/** + * @brief RELOAD_NCPU_FW(), Reload NCPU firmware from flash + */ +void reload_ncpu_fw(void) +{ + kdrv_mpu_niram_enable(); + int dfu_active_sts = kmdw_dfu_get_active_ncpu_partition(); + kdp_memxfer_module.init(MEMXFER_OPS_DMA, MEMXFER_OPS_DMA); + kdp_memxfer_module.flash_to_niram(dfu_active_sts); + kdrv_mpu_niram_disable(); + kdrv_system_reset(SUBSYS_NCPU); +} + +/** +* flag = 0, just launch ncpu +* flag <> 0, load and launch ncpu +* flag < 0, not using mpu +* +* @retVal: 0, new sum32 value matches with another one in FLASH +* >0, return wrong new sum32 value +*/ +u32 load_ncpu_fw(int32_t reset_flag) +{ + uint32_t ret = 0; + SCU_EXTREG_CM4_NCPU_CTRL_SET_wakeup(0); // stop ncpu first + if (reset_flag) { + if (reset_flag > 0) + kdrv_mpu_niram_enable(); + /* initialize flash first for kmdw_dfu_get_active_ncpu_partition() */ + kdp_memxfer_module.init(MEMXFER_OPS_DMA, MEMXFER_OPS_DMA); + int dfu_active_sts = kmdw_dfu_get_active_ncpu_partition(); + kdp_memxfer_module.flash_to_niram(dfu_active_sts); + /*ncpu may change its interrupt vector in NiRAM, which may fail the image check. + So ncpu check should be done before ncput is waken up and run*/ + ret = system_check_fw_image(NCPU_FW); + if (reset_flag > 0) + kdrv_mpu_niram_disable(); + } + SCU_EXTREG_CM4_NCPU_CTRL_SET_wakeup(1); // restart ncpu + return ret; +} + +/** + * @brief Calculate sum32 of scpu/ncpu fw and compare to the value which resides at the end of flash + * N-iRAM(64KB) 0x28000000 ~ 0x2800FFFF + * S-iRAM(88KB) 0x10102000 ~ 0x10117FFF + * + * If sums are the same, return 0 (Note: check value could be zero) + * Else return wrong calculated value, if value is zero, return 0xffffffff + */ +uint32_t system_check_fw_image(int32_t fw_type) +{ + uint8_t *pBase; + uint32_t sum32_cal, sum32_in_flash; + uint32_t size; + + if(fw_type == SCPU_FW) { + pBase = (u8 *)SCPU_START_ADDRESS; + size = (SCPU_IMAGE_SIZE - 4); + } + else if(fw_type == NCPU_FW){ + pBase = (u8 *)NCPU_START_ADDRESS; + size = (NCPU_IMAGE_SIZE - 4); + } + + sum32_cal = kmdw_utils_crc_gen_sum32(pBase, size); + sum32_in_flash = *(u32 *)(pBase + size); + if (sum32_cal == sum32_in_flash) + return 0; + if (sum32_cal == 0) + sum32_cal--; + return sum32_cal; +} + diff --git a/mdw/usb_companion/kdp2_cmd_handler_520.c b/mdw/usb_companion/kdp2_cmd_handler_520.c new file mode 100644 index 0000000..11f286d --- /dev/null +++ b/mdw/usb_companion/kdp2_cmd_handler_520.c @@ -0,0 +1,828 @@ +// #define FIFO_CMD_DBG + +#include +#include + +#include "cmsis_os2.h" +#include "version.h" +#include "project.h" + +#include "usbd_hal.h" +#include "kdrv_scu_ext.h" +#include "kdrv_power.h" +#include "kdrv_clock.h" +#include "kdp_system.h" + +#include "kmdw_dfu.h" +#include "kmdw_console.h" +#include "kmdw_model.h" +#include "kmdw_memxfer.h" + + + +#include "kmdw_ipc.h" // for kp inference debug +#include "kdp2_ipc_cmd.h" +#include "kdp2_inf_generic_raw.h" +#include "kmdw_fifoq_manager.h" + +#ifdef FIFO_CMD_DBG +#define fifo_cmd_dbg(__format__, ...) kmdw_printf("[fifoCmd]"__format__, ##__VA_ARGS__) +#else +#define fifo_cmd_dbg(__format__, ...) +#endif + +#define USB_NORMAL_TIMEOUT (2 * 1000) // 2 secs +#define KP_DEBUG_BUF_SIZE (8 * 1024 * 1024) // FIXME, max is 1920x1080 RGB565 + +typedef struct +{ + /* Model type */ + uint32_t model_type; //defined in model_type.h + + /* Model version */ + uint32_t model_version; + + /* Input in memory */ + uint32_t input_mem_addr; + int32_t input_mem_len; + + /* Output in memory */ + uint32_t output_mem_addr; + int32_t output_mem_len; + + /* Working buffer */ + uint32_t buf_addr; + int32_t buf_len; + + /* command.bin in memory */ + uint32_t cmd_mem_addr; + int32_t cmd_mem_len; + + /* weight.bin in memory */ + uint32_t weight_mem_addr; + int32_t weight_mem_len; + + /* setup.bin in memory */ + uint32_t setup_mem_addr; + int32_t setup_mem_len; +} _fw_info_t; // == kdp_model_t + +/* Structure of CNN Header in setup.bin - copy from kdpio.h */ +struct cnn_header_s +{ + uint32_t crc; + uint32_t version; + uint32_t key_offset; + uint32_t model_type; + uint32_t app_type; + uint32_t dram_start; + uint32_t dram_size; + uint32_t input_row; + uint32_t input_col; + uint32_t input_channel; + uint32_t cmd_start; + uint32_t cmd_size; + uint32_t weight_start; + uint32_t weight_size; + uint32_t input_start; + uint32_t input_size; + uint32_t input_radix; + uint32_t output_nums; +}; + +extern int kdp_memxfer_flash_to_ddr(uint32_t dst, uint32_t src, size_t bytes); +extern int kdp_memxfer_ddr_to_flash(u32 dst, u32 src, size_t bytes); + +static uint32_t _flash_read_callback(uint32_t addr, uint32_t img_size) +{ + fifo_cmd_dbg("[%s]\n", __FUNCTION__); + + int usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (void *)addr, &img_size, USB_NORMAL_TIMEOUT); + + if (KDRV_STATUS_OK != usb_sts) { + fifo_cmd_dbg("[%s] receive fw data failed, sts %d\n", __FUNCTION__, usb_sts); + + return 0; + } + + fifo_cmd_dbg("[%s] received fw data %d bytes\n", __FUNCTION__, img_size); + + return img_size; +} + +static int _load_model(kdp2_ipc_cmd_load_model_t *cmd_lmd) +{ + fifo_cmd_dbg("[%s] model_size %d fw_info_size %d\n", __FUNCTION__, cmd_lmd->model_size, cmd_lmd->fw_info_size); + fifo_cmd_dbg("[%s] num_model = %d\n", __FUNCTION__, cmd_lmd->fw_info[0]); + + _fw_info_t *first_fwinfo = (_fw_info_t *)(cmd_lmd->fw_info + 4); + + kmdw_model_fw_info_t *fw_info_p = kmdw_model_get_fw_info(true); + memcpy(fw_info_p, (void *)cmd_lmd->fw_info, cmd_lmd->fw_info_size); + fifo_cmd_dbg("fw_info_p = 0x%x, fw_info_size = %d, sizeof(_fw_info_t) = %d\n", + fw_info_p, cmd_lmd->fw_info_size, sizeof(_fw_info_t)); + + uint32_t reload_model_info_sts = kmdw_model_reload_model_info(true); + uint32_t return_code = (0 < reload_model_info_sts) ? KP_SUCCESS : KP_FW_LOAD_MODEL_FAILED_104; + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&return_code, sizeof(uint32_t), USB_NORMAL_TIMEOUT); + + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] send reload model info statsus failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + if (return_code != KP_SUCCESS) + { + fifo_cmd_dbg("[%s] reload model info failed, sts %d\n", __FUNCTION__, reload_model_info_sts); + return -1; + } + + fifo_cmd_dbg("[%s] receiving model and writing to addr 0x%x\n", __FUNCTION__, first_fwinfo->cmd_mem_addr); + + uint32_t txLen = cmd_lmd->model_size; // should be acceptable + + fifo_cmd_dbg("[%s] max model buf size %d\n", __FUNCTION__, txLen); + + usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (void *)first_fwinfo->cmd_mem_addr, &txLen, 20 * 1000); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] receive model failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + fifo_cmd_dbg("[%s] received model done %d bytes\n", __FUNCTION__, txLen); + + return 0; +} + +static uint8_t ack_packet[] = {0x35, 0x8A, 0xC, 0, 0x4, 0, 0x8, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +static int _update_firmware(kdp_firmware_update_cmd_t *kdp_cmd) +{ + kdrv_status_t usb_sts; + uint32_t txLen, txLen2; + int fw_id = kdp_cmd->fw_id; + bool reboot_after_update = (1 == kdp_cmd->auto_reboot); + int dfu_update_sts = -1; + + fifo_cmd_dbg("[%s] recognized KDP KDP_CMD_UPDATE_FW\n", __FUNCTION__); + + if ((KDP_UPDATE_MODULE_SCPU == fw_id) || (KDP_UPDATE_MODULE_NCPU == fw_id)) + { + txLen = sizeof(ack_packet); + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)ack_packet, txLen, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] send error ack failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + } + else + { + fifo_cmd_dbg("[%s] error fw_id %d\n", __FUNCTION__, fw_id); + + // send some error ack back to host + txLen = 16; + memset((void *)kdp_cmd, 0, txLen); + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)kdp_cmd, txLen, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] send ack failed, sts %d\n", __FUNCTION__, usb_sts); + } + + return -1; + } + + // now receive fw content + fifo_cmd_dbg("[%s] received fw data %d bytes\n", __FUNCTION__, txLen); + + if (fw_id == KDP_UPDATE_MODULE_SCPU) + { + fifo_cmd_dbg("[%s] updateing scpu fw\n", __FUNCTION__); + dfu_update_sts = kmdw_dfu_update_scpu(); + } + else if (fw_id == KDP_UPDATE_MODULE_NCPU) + { + fifo_cmd_dbg("[%s] updateing ncpu fw\n", __FUNCTION__); + dfu_update_sts = kmdw_dfu_update_ncpu(); + } + + // so far so good, give a response to host + kdp_firmware_update_response_t kdp_resp = {KDP_MSG_HDR_RSP, 0xc, KDP_CMD_UPDATE_FW_RESPONSE, 8, dfu_update_sts, fw_id}; + + txLen2 = sizeof(kdp_resp); + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&kdp_resp, txLen2, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] send response failed, sts %d\n", __FUNCTION__, usb_sts); + } + + osDelay(1000); + + if (true == reboot_after_update) + kdrv_power_sw_reset(); + + return 0; +} + +static int _update_model(kdp_model_update_cmd_t *kdp_cmd) +{ + kdrv_status_t usb_sts; + uint32_t txLen, txLen2; + int fw_info_size = kdp_cmd->fw_info_size; + int all_models_size = kdp_cmd->all_models_size; + bool reboot_after_update = (1 == kdp_cmd->auto_reboot); + + fifo_cmd_dbg("[%s] recognized KDP KDP_CMD_UPDATE_MODEL\n", __FUNCTION__); + + txLen = sizeof(ack_packet); + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)ack_packet, txLen, USB_NORMAL_TIMEOUT); + + if (KDRV_STATUS_OK != usb_sts) { + fifo_cmd_dbg("[%s] send error ack failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + int ret = kmdw_dfu_update_model(fw_info_size, all_models_size); + + if (0 != ret) { + fifo_cmd_dbg("[%s] write model to flash failed, sts %d\n", __FUNCTION__, ret); + } + + // so far so good, give a response to host + kdp_model_update_response_t kdp_resp = {KDP_MSG_HDR_RSP, 0xc, KDP_CMD_UPDATE_MODEL_RESPONSE, 8, ret, ret}; + + txLen2 = sizeof(kdp_resp); + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&kdp_resp, txLen2, USB_NORMAL_TIMEOUT); + + if (KDRV_STATUS_OK != usb_sts) { + fifo_cmd_dbg("[%s] send response failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + fifo_cmd_dbg("[%s] update model done, sts: %d\n", __FUNCTION__, ret); + + osDelay(1000); + + if (true == reboot_after_update) { + kdrv_power_sw_reset(); + } + + return 0; +} + +static uint8_t _dfu_buf[4 * 1024]; // kmdw_dfu_init() says it need at least 4KB buffer, and it cannot use DDR, really sucks +int kdp2_cmd_handler_initialize() +{ + fifo_cmd_dbg("[%s]\n", __FUNCTION__); + + if(FLASH_TYPE != FLASH_TYPE_NULL) { + kmdw_dfu_init(_dfu_buf, _flash_read_callback); // TODO: waste of memory + } + + return 0; +} + +static int _memory_read_write(kdp2_ipc_cmd_memory_read_write_t *cmd_buf) +{ + kdrv_status_t usb_sts; + + if (cmd_buf->command_id == KDP2_COMMAND_MEMORY_READ) // read mode + { + fifo_cmd_dbg("[%s] read mode\n", __FUNCTION__); + + uint32_t return_code = KP_SUCCESS; // FIXME: error handling + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&return_code, sizeof(uint32_t), USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] memory read failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)cmd_buf->start_address, cmd_buf->length, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] memory read failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + } + else if (cmd_buf->command_id == KDP2_COMMAND_MEMORY_WRITE) // write mode + { + fifo_cmd_dbg("[%s] write mode\n", __FUNCTION__); + + uint32_t rxLen = cmd_buf->length; + usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (void *)cmd_buf->start_address, &rxLen, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] memory write failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + uint32_t return_code = KP_SUCCESS; + if (rxLen != cmd_buf->length) + { + return_code = KP_ERROR_RECEIVE_SIZE_MISMATCH_31; + fifo_cmd_dbg("[%s] received buffer length is not the same with the length specified in the command, return code %d\n", __FUNCTION__, return_code); + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&return_code, sizeof(uint32_t), USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] memory write failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + } + else + fifo_cmd_dbg("[%s] unsupported command, should not be here\n", __FUNCTION__); + + return 0; +} + +static int _get_system_info() +{ + kdrv_status_t usb_sts; + kdp2_ipc_response_get_system_info_t response_buf; + + response_buf.return_code = KP_SUCCESS; // FIXME: error handling + + response_buf.system_info.kn_number = kdp_sys_get_kn_number(); + + response_buf.system_info.firmware_version.reserved = 0; + response_buf.system_info.firmware_version.major = IMG_FW_MAJOR; + response_buf.system_info.firmware_version.minor = IMG_FW_MINOR; + response_buf.system_info.firmware_version.update = IMG_FW_UPDATE; + response_buf.system_info.firmware_version.build = IMG_FW_BUILD; + + fifo_cmd_dbg("[%s] kn_number 0x%8X\n", __FUNCTION__, response_buf.system_info.kn_number); + + fifo_cmd_dbg("[%s] FW: %d.%d.%d-build.%d\n", + __FUNCTION__, + response_buf.system_info.firmware_version.major, + response_buf.system_info.firmware_version.minor, + response_buf.system_info.firmware_version.update, + response_buf.system_info.firmware_version.build); + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&response_buf, sizeof(response_buf), USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] get system info failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + return 0; +} + +static int _load_model_from_flash() +{ + int32_t load_model_sts = kmdw_model_load_model(-1); + uint32_t return_code = (0 < load_model_sts) ? KP_SUCCESS : KP_FW_LOAD_MODEL_FAILED_104; + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&return_code, sizeof(uint32_t), USB_NORMAL_TIMEOUT); + + if (KDRV_STATUS_OK != usb_sts) { + fifo_cmd_dbg("[%s] send reload model info statsus failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + if (KP_SUCCESS != return_code) { + fifo_cmd_dbg("[%s] reload model info failed, sts %d\n", __FUNCTION__, load_model_sts); + return -1; + } + + return 0; +} + +static int _read_flash(kdp2_ipc_cmd_read_flash_t *cmd_buf) +{ + kdrv_status_t usb_sts; + int32_t return_code = KP_SUCCESS; // FIXME: error handling + uint32_t buffer = (uint32_t)cmd_buf; + uint32_t flash_addr = cmd_buf->flash_offset; + uint32_t length = cmd_buf->length; + + fifo_cmd_dbg("[%s] Read flash on addr %d\n", __FUNCTION__, flash_addr); + + kdp_memxfer_flash_to_ddr(buffer, flash_addr, length); + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&return_code, sizeof(uint32_t), USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) { + fifo_cmd_dbg("[%s] memory read failed, sts %d\n", __FUNCTION__, usb_sts); + return_code = -1; + goto FUNC_OUT; + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)buffer, length, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) { + fifo_cmd_dbg("[%s] memory read failed, sts %d\n", __FUNCTION__, usb_sts); + return_code = -1; + goto FUNC_OUT; + } + +FUNC_OUT: + + return return_code; +} + +static int _write_flash(kdp2_ipc_cmd_write_flash_t *cmd_buf) +{ + kdrv_status_t usb_sts; + int32_t return_code = KP_SUCCESS; // FIXME: error handling + uint32_t buffer = (uint32_t)cmd_buf; + uint32_t flash_addr = cmd_buf->flash_offset; + uint32_t length = cmd_buf->length; + + fifo_cmd_dbg("[%s] Write flash on addr %d\n", __FUNCTION__, flash_addr); + + usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (void *)buffer, &length, USB_NORMAL_TIMEOUT); + + if (usb_sts != KDRV_STATUS_OK) { + fifo_cmd_dbg("[%s] receive data failed, sts %d\n", __FUNCTION__, usb_sts); + return_code = -1; + goto FUNC_OUT; + } + + kdp_memxfer_ddr_to_flash(flash_addr, buffer, length); + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&return_code, sizeof(uint32_t), USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) { + fifo_cmd_dbg("[%s] send return code failed, sts %d\n", __FUNCTION__, usb_sts); + return_code = -1; + goto FUNC_OUT; + } + +FUNC_OUT: + + return return_code; +} + +#define OUT_NODE_HEAD_SIZE 20 // node's width, height, channel, radix, scale + +static int _get_model_info(kdp2_ipc_cmd_get_model_info_t *cmd_buf) +{ + kdrv_status_t usb_sts; + + kdp2_ipc_response_get_model_info_fw_info_t fw_info_response_buf = {0}; + kmdw_model_fw_info_t *fw_info_buf_p = kmdw_model_get_fw_info(false); + + if (NULL == fw_info_buf_p) + { + fw_info_response_buf.return_code = KP_FW_GET_MODEL_INFO_FAILED_109; + fw_info_response_buf.fw_info_size = 0; + fw_info_response_buf.target_chip = KP_MODEL_TARGET_CHIP_KL520; + } + else + { + fw_info_response_buf.return_code = KP_SUCCESS; + fw_info_response_buf.fw_info_size = sizeof(kmdw_model_fw_info_t) - sizeof(struct kdp_model_s) + (fw_info_buf_p->model_count * sizeof(struct kdp_model_s)) + sizeof(kmdw_model_fw_info_ext_t); + fw_info_response_buf.target_chip = KP_MODEL_TARGET_CHIP_KL520; + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&fw_info_response_buf, sizeof(fw_info_response_buf), USB_NORMAL_TIMEOUT); + if ((usb_sts != KDRV_STATUS_OK) || (fw_info_response_buf.return_code != KP_SUCCESS)) + { + fifo_cmd_dbg("[%s] get model info send fw_info response failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)fw_info_buf_p, fw_info_response_buf.fw_info_size, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] get model info send fw_info data failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + kdp2_ipc_response_get_model_info_setup_t all_setup_response_buf = {0}; + kdp2_ipc_response_get_model_info_setup_t single_setup_response_buf = {0}; + struct kdp_model_s *model_info = NULL; + + all_setup_response_buf.setup_size = 0; + all_setup_response_buf.return_code = KP_SUCCESS; + + for (int i = 0; i < fw_info_buf_p->model_count; i++) { + model_info = kmdw_model_get_model_info(i); + + if (NULL != model_info) { + all_setup_response_buf.setup_size += model_info->setup_mem_len; + } else { + all_setup_response_buf.return_code = KP_FW_GET_MODEL_INFO_FAILED_109; + fifo_cmd_dbg("[%s] get model info failed, invalid model info in ddr\n", __FUNCTION__); + break; + } + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&all_setup_response_buf, sizeof(all_setup_response_buf), USB_NORMAL_TIMEOUT); + if ((usb_sts != KDRV_STATUS_OK) || (all_setup_response_buf.return_code != KP_SUCCESS)) + { + fifo_cmd_dbg("[%s] get model info send all setup response failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + for (int i = 0; i < fw_info_buf_p->model_count; i++) { + model_info = kmdw_model_get_model_info(i); + + if (NULL != model_info) { + single_setup_response_buf.setup_size = model_info->setup_mem_len; + single_setup_response_buf.return_code = KP_SUCCESS; + } else { + single_setup_response_buf.setup_size = 0; + single_setup_response_buf.return_code = KP_FW_GET_MODEL_INFO_FAILED_109; + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&single_setup_response_buf, sizeof(single_setup_response_buf), USB_NORMAL_TIMEOUT); + if ((usb_sts != KDRV_STATUS_OK) || (single_setup_response_buf.return_code != KP_SUCCESS)) + { + fifo_cmd_dbg("[%s] get model info send single setup response failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)model_info->setup_mem_addr, model_info->setup_mem_len, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] get model info send setup data entry %d failed, sts %d\n", __FUNCTION__, i, usb_sts); + return -1; + } + } + + return 0; +} + +#define NCPU_IRAM_ADDR (0x28000000) +#define NCPU_IRAM_SIZE (64 * 1024) + +static int _load_firmware(kdp2_ipc_cmd_upload_firmware_t *cmd_buf) +{ + uint32_t txLen = NCPU_IRAM_SIZE; + uint32_t recv_buf; + + static bool isNCPU_loaded = false; + + if (isNCPU_loaded == false) + recv_buf = NCPU_IRAM_ADDR; + else + // useless, just to recv it + recv_buf = (uint32_t)cmd_buf + sizeof(kdp2_ipc_cmd_upload_firmware_t); + + kdrv_status_t usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (uint32_t *)recv_buf, &txLen, USB_NORMAL_TIMEOUT); + if (usb_sts != KDRV_STATUS_OK) + { + fifo_cmd_dbg("[%s] receive fw failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + if (isNCPU_loaded) + return 0; + + kmdw_printf("recv ncpu fw %d\n", txLen); + osDelay(10); + SCU_EXTREG_CM4_NCPU_CTRL_SET_wakeup(1); // restart ncpu + + isNCPU_loaded = true; + + return 0; +} + +static int _set_ckey(kdp2_ipc_cmd_set_ckey_t *cmd_buf) +{ + kdrv_status_t usb_sts; + uint32_t ckey = cmd_buf->ckey; + uint32_t status = 0; + int32_t resp = 0; + + fifo_cmd_dbg("[%s] set ckey : 0x%08X\n", __FUNCTION__, ckey); + + status = kdp_sys_program_key(ckey); + + switch (status) + { + case 0x1: + resp = KP_FW_EFUSE_CAN_NOT_BURN_300; + break; + case 0x2: + resp = KP_FW_EFUSE_PROTECTED_301; + break; + case 0x0: + resp = KP_SUCCESS; + break; + default: + resp = KP_FW_EFUSE_OTHER_302; + break; + } + + usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&resp, sizeof(int32_t), USB_NORMAL_TIMEOUT); + + if (KDRV_STATUS_OK != usb_sts) { + fifo_cmd_dbg("[%s] send response failed, sts %d\n", __FUNCTION__, usb_sts); + return -1; + } + + fifo_cmd_dbg("[%s] set ckey done, sts: %d\n", __FUNCTION__, resp); + + return 0; +} + +static int _set_dbg_checkpoint(kdp2_ipc_cmd_set_dbg_checkpoint_t *cmd_buf) +{ + // kp inference debug code + struct scpu_to_ncpu_s *out_comm = kmdw_ipc_get_output(); + int32_t return_code = KP_SUCCESS; + + if (out_comm->kp_dbg_buffer == NULL) + { + out_comm->kp_dbg_buffer = (void *)kmdw_ddr_reserve(KP_DEBUG_BUF_SIZE); + if (out_comm->kp_dbg_buffer == NULL) + { + return_code = KP_FW_DDR_MALLOC_FAILED_102; + } + } + + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&return_code, sizeof(uint32_t), USB_NORMAL_TIMEOUT); + if (KDRV_STATUS_OK != usb_sts) + fifo_cmd_dbg("[%s] send ack failed, sts %d\n", __FUNCTION__, usb_sts); + + uint32_t checkponit_flags = out_comm->kp_dbg_checkpoinots; + + if (cmd_buf->enable) + checkponit_flags |= cmd_buf->checkpoint_flags; + else + checkponit_flags &= ~cmd_buf->checkpoint_flags; + + out_comm->kp_dbg_checkpoinots = checkponit_flags; + + return 0; +} + +static int _set_dbg_profile(kdp2_ipc_cmd_set_profile_enable_t *cmd_buf) +{ + struct scpu_to_ncpu_s *out_comm = kmdw_ipc_get_output(); + + out_comm->kp_dbg_enable_profile = (cmd_buf->enable) ? 1 : 0; + if (cmd_buf->enable) + { + kp_model_profile_t *profile_recs = (kp_model_profile_t *)out_comm->kp_model_profile_records; + memset(profile_recs, 0, MULTI_MODEL_MAX * sizeof(kp_model_profile_t)); + } + + int32_t return_code = KP_SUCCESS; + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&return_code, sizeof(uint32_t), USB_NORMAL_TIMEOUT); + if (KDRV_STATUS_OK != usb_sts) + fifo_cmd_dbg("[%s] send ack failed, sts %d\n", __FUNCTION__, usb_sts); + + return 0; +} + +static int _get_dbg_profile(kdp2_ipc_cmd_get_profile_statics_t *cmd_buf) +{ + struct scpu_to_ncpu_s *out_comm = kmdw_ipc_get_output(); + + kp_profile_data_t pd = {0}; + + kp_model_profile_t *profile_recs = (kp_model_profile_t *)out_comm->kp_model_profile_records; + for (int i = 0; i < MULTI_MODEL_MAX; i++) + { + if (profile_recs[i].model_id == 0) + break; + + pd.num_model_profiled++; + pd.model_st[i].model_id = profile_recs[i].model_id; + pd.model_st[i].inf_count = profile_recs[i].sum_frame_count; + pd.model_st[i].cpu_op_count = profile_recs[i].sum_cpu_op_count / profile_recs[i].sum_frame_count; + pd.model_st[i].avg_pre_process_ms = (float)profile_recs[i].sum_ticks_preprocess / profile_recs[i].sum_frame_count; + pd.model_st[i].avg_inference_ms = (float)profile_recs[i].sum_ticks_inference / profile_recs[i].sum_frame_count; + pd.model_st[i].avg_cpu_op_ms = (float)profile_recs[i].sum_ticks_cpu_op / profile_recs[i].sum_frame_count; + pd.model_st[i].avg_cpu_op_per_cpu_node_ms = (float)profile_recs[i].sum_ticks_cpu_op / (0 == profile_recs[i].sum_cpu_op_count ? 1 : profile_recs[i].sum_cpu_op_count); + pd.model_st[i].avg_post_process_ms = (float)profile_recs[i].sum_ticks_postprocess / profile_recs[i].sum_frame_count; + } + + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&pd, sizeof(kp_profile_data_t), USB_NORMAL_TIMEOUT); + if (KDRV_STATUS_OK != usb_sts) + fifo_cmd_dbg("[%s] send ack failed, sts %d\n", __FUNCTION__, usb_sts); + + return 0; +} + +static int _get_ddr_config(kdp2_ipc_cmd_get_available_ddr_config_t *cmd_buf) +{ + kp_available_ddr_config_t ddr_config = {0}; + + ddr_config.ddr_available_begin = DDR_BEGIN; + ddr_config.ddr_available_end = kmdw_ddr_get_heap_tail(); + ddr_config.ddr_model_end = kmdw_model_get_model_end_addr(true); + ddr_config.ddr_fifoq_allocated = (true == kmdw_fifoq_manager_get_fifoq_allocated()) ? 1 : 0; + + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&ddr_config, sizeof(kp_available_ddr_config_t), USB_NORMAL_TIMEOUT); + if (KDRV_STATUS_OK != usb_sts) + fifo_cmd_dbg("[%s] send ack failed, sts %d\n", __FUNCTION__, usb_sts); + + return 0; +} + +static int _get_fifo_queue_config(kdp2_ipc_cmd_get_fifo_queue_config_t *cmd_buf) +{ + kp_fifo_queue_config_t fifo_queue_config = {0}; + + if (true == kmdw_fifoq_manager_get_fifoq_allocated()) { + kmdw_fifoq_manager_get_fifoq_config(&fifo_queue_config.fifoq_input_buf_count, &fifo_queue_config.fifoq_input_buf_size, + &fifo_queue_config.fifoq_result_buf_count, &fifo_queue_config.fifoq_result_buf_size); + } + + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&fifo_queue_config, sizeof(kp_fifo_queue_config_t), USB_NORMAL_TIMEOUT); + if (KDRV_STATUS_OK != usb_sts) + fifo_cmd_dbg("[%s] send ack failed, sts %d\n", __FUNCTION__, usb_sts); + + return 0; +} + +int kdp2_cmd_handle_kp_command(uint32_t command_buffer) +{ + int ret = -1; + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)command_buffer; + + uint32_t command_id = header_stamp->job_id; + + switch (command_id) + { + case KDP2_COMMAND_LOAD_MODEL: + ret = _load_model((kdp2_ipc_cmd_load_model_t *)command_buffer); + break; + case KDP2_COMMAND_MEMORY_READ: + case KDP2_COMMAND_MEMORY_WRITE: + ret = _memory_read_write((kdp2_ipc_cmd_memory_read_write_t *)command_buffer); + break; + case KDP2_COMMAND_GET_SYSTEM_INFO: + ret = _get_system_info(); // no need to pass argument since we already parsed all useful info + break; + case KDP2_COMMAND_LOAD_MODEL_FROM_FLASH: + ret = _load_model_from_flash(); // no need to pass argument since we already parsed all useful info + break; + case KDP2_COMMAND_READ_FLASH: + ret = _read_flash((kdp2_ipc_cmd_read_flash_t *)command_buffer); + break; + case KDP2_COMMAND_WRITE_FLASH: + ret = _write_flash((kdp2_ipc_cmd_write_flash_t *)command_buffer); + break; + case KDP2_COMMAND_GET_MODEL_INFO: + ret = _get_model_info((kdp2_ipc_cmd_get_model_info_t *)command_buffer); + break; + case KDP2_COMMAND_LOAD_FIRMWARE: + ret = _load_firmware((kdp2_ipc_cmd_upload_firmware_t *)command_buffer); + break; + case KDP2_COMMAND_SET_CKEY: + ret = _set_ckey((kdp2_ipc_cmd_set_ckey_t *)command_buffer); + break; + case KDP2_COMMAND_SET_DBG_CHECKPOINT: + ret = _set_dbg_checkpoint((kdp2_ipc_cmd_set_dbg_checkpoint_t *)command_buffer); + break; + case KDP2_COMMAND_SET_PROFILE_ENABLE: + ret = _set_dbg_profile((kdp2_ipc_cmd_set_profile_enable_t *)command_buffer); + break; + case KDP2_COMMAND_GET_PROFILE_STATISTICS: + ret = _get_dbg_profile((kdp2_ipc_cmd_get_profile_statics_t *)command_buffer); + break; + case KDP2_COMMAND_GET_DDR_CONFIG: + ret = _get_ddr_config((kdp2_ipc_cmd_get_available_ddr_config_t *)command_buffer); + break; + case KDP2_COMMAND_GET_FIFOQ_CONFIG: + ret = _get_fifo_queue_config((kdp2_ipc_cmd_get_fifo_queue_config_t *)command_buffer); + break; + default: + kmdw_printf("error ! unknown command id %d\n", command_id); + break; + } + + return ret; +} + +int kdp2_cmd_handle_legend_kdp_command(uint32_t command_buffer) +{ + fifo_cmd_dbg("[%s]\n", __FUNCTION__); + + int Ret = -1; + uint16_t cmd = *((uint16_t *)command_buffer + 2); + fifo_cmd_dbg("kdp_cmd->cmd: %d\n", cmd); + + switch (cmd) + { + case KDP_CMD_UPDATE_FW: + Ret = _update_firmware((kdp_firmware_update_cmd_t *)command_buffer); + break; + case KDP_CMD_UPDATE_MODEL: + Ret = _update_model((kdp_model_update_cmd_t *)command_buffer); + break; + default: + fifo_cmd_dbg("[%s] not recognized KDP command %d, refused to handle it !\n", __FUNCTION__, cmd); + + // send some error ack back to host + uint32_t txLen = 16; + memset((void *)command_buffer, 0, txLen); + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)command_buffer, txLen, USB_NORMAL_TIMEOUT); + + if (KDRV_STATUS_OK != usb_sts) { + fifo_cmd_dbg("[%s] send ack failed, sts %d\n", __FUNCTION__, usb_sts); + } + + break; + } + + return Ret; +} diff --git a/mdw/usb_companion/kdp2_usb_companion.c b/mdw/usb_companion/kdp2_usb_companion.c new file mode 100644 index 0000000..2ffc7d6 --- /dev/null +++ b/mdw/usb_companion/kdp2_usb_companion.c @@ -0,0 +1,516 @@ +// #define ENABLE_DBG_LOG + +#include +#include "cmsis_os2.h" +#include "kmdw_power_manager.h" + +#include "kmdw_console.h" +#include "kdrv_power.h" +#include "kdrv_scu_ext.h" +#include "kdp_system.h" + +#include "usbd_hal.h" + +#include "buffer_object.h" + +#include "kmdw_fifoq_manager.h" +#include "kdp2_usb_companion.h" +#include "kdp2_ipc_cmd.h" + +#ifdef ENABLE_DBG_LOG +#define dbg_log(__format__, ...) kmdw_printf("[kp companion]"__format__, ##__VA_ARGS__) +#else +#define dbg_log(__format__, ...) +#endif + +#define FLAG_WAIT_USB_CONNECTION 0x1 + +static osThreadId_t result_thread_id = NULL; +static osThreadId_t image_thread_id = NULL; + +static bool _do_reset_queue = false; +static bool _enable_inf_droppable = false; + +static bool allocate_memory_for_inference_queue(uint32_t image_count, uint32_t image_size, uint32_t result_count, uint32_t result_size) +{ + if (true == kmdw_fifoq_manager_get_fifoq_allocated()) + return false; // already inited + + uint32_t total_need_size = (image_count * image_size) + (result_count * result_size); + + kmdw_printf("allocating memory for fifoq: image %d x %d, result %d x %d, total %u bytes\n", image_count, image_size, result_count, result_size, total_need_size); + + uint32_t buf_addr = kmdw_ddr_reserve(total_need_size); + if (buf_addr > 0) + { + dbg_log("allocated fifoq buffers OK\n"); + + kmdw_fifoq_manager_store_fifoq_config(image_count, image_size, result_count, result_size); + + osStatus_t sts; + + // queue image and result buffers into queues correspondingly + for (uint32_t i = 0; i < image_count; i++) + { + sts = kmdw_fifoq_manager_image_put_free_buffer(buf_addr, (int)image_size, 0); + if (sts != osOK) + { + dbg_log("kmdw_fifoq_manager_image_put_free_buffer error = %d\n", sts); + } + + buf_addr += image_size; + } + for (uint32_t i = 0; i < result_count; i++) + { + sts = kmdw_fifoq_manager_result_put_free_buffer(buf_addr, (int)result_size, 0); + if (sts != osOK) + { + dbg_log("kmdw_fifoq_manager_image_put_free_buffer error = %d\n", sts); + } + + buf_addr += result_size; + } + + return true; + } + else + { + kmdw_printf("error ! not enough memory for inference queue buffers\n"); + return false; + } +} + +// usb link status notify +void usb_link_status_callback(usbd_hal_link_status_t link_status) +{ + switch (link_status) + { + case USBD_STATUS_DISCONNECTED: + kmdw_printf("USB is disconnected\n"); + break; + + case USBD_STATUS_CONFIGURED: + kmdw_printf("USB is connected\n"); + osThreadFlagsSet(image_thread_id, FLAG_WAIT_USB_CONNECTION); + break; + } +} + +// vendor-specific control transfer setup packet notify +static bool usb_user_control_callback(usbd_hal_setup_packet_t *setup) +{ + bool ret = false; + + dbg_log("control bRequest = 0x%x\n", setup->bRequest); + + switch (setup->bRequest) + { + case KDP2_CONTROL_REBOOT: + { + dbg_log("control reboot\n"); + kdrv_power_sw_reset(); + break; + } + case KDP2_CONTROL_SHUTDOWN: + { + dbg_log("control shutdown\n"); + kmdw_power_manager_shutdown(); + break; + } + case KDP2_CONTROL_FIFOQ_RESET: + { + dbg_log("control fifoq reset\n"); + + if (true == kmdw_fifoq_manager_get_fifoq_allocated()) + { + _do_reset_queue = true; + + // also reset any inf defaults + _enable_inf_droppable = false; + + usbd_hal_terminate_all_endpoint(); + } + + ret = true; + break; + } + case KDP2_CONTROL_FIFOQ_CONFIGURE: + { + if (true == kmdw_fifoq_manager_get_fifoq_allocated()) + break; // already inited + + uint16_t arg1_image = setup->wValue; + uint16_t arg2_result = setup->wIndex; + + uint32_t image_count = (arg1_image & 0x7) + 1; // lower 3 bits for number of image, 1~8 + uint32_t image_size = (10 * 1024) * (uint32_t)((arg1_image >> 3) + 1); // higher 13 bits for image buffer size in 10KB, 10KB~80MB + + uint32_t result_count = (arg2_result & 0x7) + 1; // lower 3 bits for number of image, 1~8 + uint32_t result_size = (10 * 1024) * (uint32_t)((arg2_result >> 3) + 1); // higher 13 bits for image buffer size in 10KB, 10KB~80MB + + ret = allocate_memory_for_inference_queue(image_count, image_size, result_count, result_size); + + break; + } + case KDP2_CONTROL_FIFOQ_ENABLE_DROPPABLE: + { + _enable_inf_droppable = (setup->wValue == 1); + ret = true; + break; + } + case KDP2_CONTROL_DDR_HEAP_BOUNDARY_ADJUST: + { + uint32_t arg1 = (uint32_t)setup->wValue; + uint32_t arg2 = (uint32_t)setup->wIndex; + uint32_t boundary_addr = (arg1 << 16) | arg2; + + ret = (0 == kmdw_ddr_set_ddr_boundary(boundary_addr)); + break; + } + case KDP2_CONTROL_REBOOT_SYSTEM: + { + dbg_log("control reboot system\n"); + kdrv_power_sw_reset(); + break; + } + + default: + ret = false; + break; + } + + return ret; +} + +static void process_plus_command(uint32_t cmd_buf) +{ + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)cmd_buf; + + if (header_stamp->magic_type == KDP2_MAGIC_TYPE_COMMAND) + { + dbg_log("handle kdp2 command = 0x%x\n", header_stamp->job_id); + // handle kdp2 commands ... + kdp2_cmd_handle_kp_command(cmd_buf); + } + else if ((header_stamp->magic_type & 0xFFFF) == KDP_MSG_HDR_CMD) // very speical case for old arch. fw update + { + // handle legendary kdp commands, should be as few as possible + dbg_log("handle legendary kdp command = 0x%x\n", header_stamp->job_id); + kdp2_cmd_handle_legend_kdp_command(cmd_buf); + } + else + { + dbg_log("[%s] error ! received un-recognized buffer beginning with incorrect magic_type 0x%x\n", __FUNCTION__, header_stamp->magic_type); + } +} + +enum +{ + RECV_TYPE_INF_IMAGE = 1, + RECV_TYPE_COMMAND = 2, + RECV_TYPE_UNKNOWN = 3, +}; + +void kdp2_usb_companion_image_thread(void *arg) +{ + dbg_log("[%s] starting ..\n", __FUNCTION__); + + uint32_t temp_cmd_buffer = 0; + uint32_t temp_cmd_buffer_size = 0; + + kmdw_ddr_get_system_reserve(&temp_cmd_buffer, &temp_cmd_buffer_size); + + // this is due to "static thread allocation", refer to task_handler.h + image_thread_id = osThreadGetId(); + if (image_thread_id == NULL) + kmdw_printf("%s creation failed !\n", __FUNCTION__); + + // wait until usb connection is established + osThreadFlagsWait(FLAG_WAIT_USB_CONNECTION, osFlagsWaitAny, osWaitForever); + + // run infinitely + while (1) + { + uint32_t buf_addr; // contains a inference image or a command + int buf_size; // buffer size should bigger than inference image size + + // take a free buffer to receive a inf image or a command + if (true == kmdw_fifoq_manager_get_fifoq_allocated()) { + osStatus_t sts = kmdw_fifoq_manager_image_get_free_buffer(&buf_addr, &buf_size, osWaitForever, _enable_inf_droppable); + + while (_enable_inf_droppable && osErrorResource == sts) + { + sts = kmdw_fifoq_manager_image_get_free_buffer(&buf_addr, &buf_size, osWaitForever, _enable_inf_droppable); + } + } else { + buf_addr = temp_cmd_buffer; + buf_size = temp_cmd_buffer_size; + dbg_log("[%s] got system reserve buffer: 0x%X size %d\n", __FUNCTION__, buf_addr, buf_size); + } + + dbg_log("[%s] free queue --> buf 0x%X size %d\n", __FUNCTION__, buf_addr, buf_size); + + uint32_t total_recv_len = 0; + uint32_t total_wanted_len = 0; + int recv_type = RECV_TYPE_UNKNOWN; + uint32_t total_image_count = 0; + uint32_t image_index = 0; + + // loop done when receiving size-matched data + while (1) + { + uint32_t txLen = buf_size - total_recv_len; + kdrv_status_t usb_sts = usbd_hal_bulk_receive(KDP2_USB_ENDPOINT_DATA_OUT, (uint32_t *)(buf_addr + total_recv_len), &txLen, osWaitForever); + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + { + dbg_log("[%s] bulk receive is terminated, sts %d\n", __FUNCTION__, usb_sts); + + // guess this is good time to clear/reset queue + if (_do_reset_queue) + { + dbg_log("[%s] do reset fifo queue !!!\n", __FUNCTION__); + + _do_reset_queue = false; + + // abandon all unprocessed data + kmdw_fifoq_manager_clean_queues(); + + // sending enpoint may still hold a buffer, terminate it + usbd_hal_terminate_all_endpoint(); + + recv_type = RECV_TYPE_UNKNOWN; + + break; + } + } + + if (total_recv_len == 0) // buffer should begin with header stamp 'magic_type' + { + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)buf_addr; + + if (header_stamp->magic_type == KDP2_MAGIC_TYPE_INFERENCE) + { + recv_type = RECV_TYPE_INF_IMAGE; // indicate this buffer contains inf image + total_wanted_len = header_stamp->total_size; + total_image_count = header_stamp->total_image; + image_index = header_stamp->image_index; + + if ((buf_addr == temp_cmd_buffer) && (true == kmdw_fifoq_manager_get_fifoq_allocated())) { + osStatus_t sts = kmdw_fifoq_manager_image_get_free_buffer(&buf_addr, &buf_size, osWaitForever, _enable_inf_droppable); + + while (_enable_inf_droppable && osErrorResource == sts) { + sts = kmdw_fifoq_manager_image_get_free_buffer(&buf_addr, &buf_size, osWaitForever, _enable_inf_droppable); + } + + memcpy((void *)buf_addr, (void *)temp_cmd_buffer, txLen); + + dbg_log("[%s] swap data from system reserve buffer to fifoq buffer: 0x%X\n", __FUNCTION__, buf_addr); + } + + if (header_stamp->total_size > buf_size) { + // FIXME, serious error, make host SW pending (timeout) + // reboot and configure bigger buffer !!!! + kmdw_printf("[%s] error !! inf image size (%d) is bigger than buffer size (%d)\n", __FUNCTION__, total_wanted_len, buf_size); + return; // a way to inform host SW ? + } + } + else + { + recv_type = RECV_TYPE_COMMAND; // indicate this buffer contains a command (if no failuire) + total_wanted_len = txLen; // assume this is a command (or not if failure) + } + } + else + { + // extra check for inference image data + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)(buf_addr + total_recv_len); + if (header_stamp->magic_type == KDP2_MAGIC_TYPE_COMMAND || + header_stamp->magic_type == KDP2_MAGIC_TYPE_COMMAND) + { + // this should not happen + kmdw_printf("[%s] error !! receiving inf image corrupted ! start over.\n", __FUNCTION__); + recv_type = RECV_TYPE_UNKNOWN; + } + } + + total_recv_len += txLen; + + dbg_log("[%s] host -- usb --> buf 0x%x len %d (total %d)\n", __FUNCTION__, (void *)buf_addr, txLen, total_recv_len); + + if (total_recv_len == total_wanted_len) + break; // recv done + else if (total_recv_len > total_wanted_len) + { + kmdw_printf("[%s] warning !! actual received size (%d) is bigger than expected size (%d)\n", __FUNCTION__, total_recv_len, total_wanted_len); + break; + } + } + + if (recv_type == RECV_TYPE_INF_IMAGE) + { + dbg_log("[%s] buf 0x%x -- > inference queue\n", __FUNCTION__, (void *)buf_addr); + kmdw_fifoq_manager_image_enqueue(total_image_count, image_index, buf_addr, buf_size, osWaitForever, false); + } + else if (recv_type == RECV_TYPE_COMMAND) + { + dbg_log("[%s] buf 0x%x -- > command handler\n", __FUNCTION__, (void *)buf_addr); + process_plus_command(buf_addr); + // as the buffer is not put into inference queue, return it back to free buffer queue + if (temp_cmd_buffer != buf_addr) + kmdw_fifoq_manager_image_put_free_buffer(buf_addr, buf_size, osWaitForever); + } + else + { + // invalid data !! ignore it ! + dbg_log("[%s] XXXXXX buf 0x%x -- > free buffer queue\n", __FUNCTION__, (void *)buf_addr); + if (temp_cmd_buffer != buf_addr) + kmdw_fifoq_manager_image_put_free_buffer(buf_addr, buf_size, osWaitForever); + } + } +} + +void kdp2_usb_companion_result_thread(void *arg) +{ + bool bRunning_dbg = false; + + dbg_log("[%s] starting ..\n", __FUNCTION__); + + result_thread_id = osThreadGetId(); + if (result_thread_id == NULL) + kmdw_printf("%s creation failed !\n", __FUNCTION__); + + while (1) + { + uint32_t buf_addr; + int buf_size; + + // get result data from queue blocking wait + kmdw_fifoq_manager_result_dequeue(&buf_addr, &buf_size, osWaitForever); + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)buf_addr; + + dbg_log("[%s] buf 0x%x len %d -- usb --> host\n", __FUNCTION__, (void *)buf_addr, header_stamp->total_size); + + // kp inference debug code + if(bRunning_dbg && header_stamp->magic_type != KDP2_MAGIC_TYPE_CHECKPOINT_DATA) + { + // send a signal notify the end of dbg process + kp_inference_header_stamp_t dbg_ending; + dbg_ending.magic_type = KDP2_MAGIC_TYPE_CHECKPOINT_DATA; + dbg_ending.total_size = sizeof(kp_inference_header_stamp_t); + dbg_ending.job_id = 0; + dbg_ending.status_code = KP_SUCCESS; + usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)&dbg_ending, dbg_ending.total_size, osWaitForever); + bRunning_dbg = false; + } + + // send result to the host, blocking wait + kdrv_status_t usb_sts = usbd_hal_bulk_send(KDP2_USB_ENDPOINT_DATA_IN, (void *)buf_addr, header_stamp->total_size, osWaitForever); + + if (usb_sts != KDRV_STATUS_OK) // KDRV_STATUS_USBD_TRANSFER_TERMINATED or KDRV_STATUS_USBD_TRANSFER_DISCONNECTED + { + dbg_log("[%s] bulk send is terminated, sts %d\n", __FUNCTION__, usb_sts); + } + + // kp inference debug code + if(header_stamp->magic_type == KDP2_MAGIC_TYPE_CHECKPOINT_DATA) + { + bRunning_dbg = true; + header_stamp->status_code = 1; // to let ncpu go on + continue; + } + +#ifdef AUTOTEST /* CI_PACK_REMOVE_START */ + if(header_stamp->magic_type == KDP2_MAGIC_TYPE_JSON) + { + // FIXME: figure out a better way to find offset from kdp2_ipc_json_result_t + uint32_t offset = *(uint32_t *)(buf_addr + sizeof(kp_inference_header_stamp_t) + 8); + buf_addr -= offset; + } +#endif /* CI_PACK_REMOVE_END */ + + // return free buf back to queue + kmdw_fifoq_manager_result_put_free_buffer(buf_addr, buf_size, osWaitForever); + } +} + +//////////////////////////////////////////////////////////// +// for usb-boot, flash-boot, jtag-boot, kdp2 loader + +#define JTAG_MAGIC_ADDRESS 0x10100000 +#define CONTROL_BYPASS_ADDRESS 0x10100004 +#define KDP2_BOOT_CONFIG_ADDRESS 0x10100100 +#define RECOVERY_MARK_POS (SdRAM_MEM_BASE + SdRAM_MEM_SIZE - 64) + +#define JTAG_MAGIC_VALUE 0xFEDCBA01 +#define BOOT_FROM_FLASH 0xA + +typedef struct +{ + uint32_t boot_type; // 0xA = flash-boot, others = usb-boot + uint8_t loader_ver[4]; // fw loader version numbers + uint8_t scpu_fw_ver[4]; // SCPU fw version numbers + uint8_t ncpu_fw_ver[4]; // NCPU fw version numbers +} kdp2_boot_config_t; + +//////////////////////////////////////////////////////////// + +int kdp2_usb_companion_init() +{ + // retrieve real serial number here from efuse + // then convert it to hex string format + + uint32_t uid = 0; + + uid = kdp_sys_get_kn_number(); + + int32_t sidx = 0; + uint8_t kn_num_string[32] = {0}; + for (int i = 7; i >= 0; i--) + { + uint32_t hex = (uid >> i * 4) & 0xF; + kn_num_string[sidx] = (hex < 10) ? '0' + hex : 'A' + (hex - 10); + sidx += 2; + } + + // Companion Mode + uint16_t bcdDevice = KP_KDP2_FW_COMPANION_MODE; + + if (*((uint32_t *)JTAG_MAGIC_ADDRESS) == JTAG_MAGIC_VALUE) + { + kmdw_printf("FW is running in JTAG mode\n"); + bcdDevice |= KP_KDP2_FW_JTAG_TYPE; + } + else + { + kdp2_boot_config_t *bConfig = (kdp2_boot_config_t *)KDP2_BOOT_CONFIG_ADDRESS; + if (bConfig->boot_type == BOOT_FROM_FLASH) + { + kmdw_printf("KDP2 FW is running in flash-boot mode\n"); + bcdDevice |= KP_KDP2_FW_FLASH_TYPE; + + kmdw_printf("boot ncpu fw from flash\n"); + SCU_EXTREG_CM4_NCPU_CTRL_SET_wakeup(1); // run ncpu + } + else + { + kmdw_printf("KDP2 FW is running in usb-boot mode\n"); + bcdDevice |= KP_KDP2_FW_USB_TYPE; + } + } + + // this is about recovery mode + *(uint32_t *)RECOVERY_MARK_POS = 0; + + usbd_hal_initialize(kn_num_string, bcdDevice, usb_link_status_callback, usb_user_control_callback); + usbd_hal_set_enable(true); + + // wow ! fifoq can also handle command + kdp2_cmd_handler_initialize(); + +#ifdef FIFIOQ_LOG_VIA_USB + kdp2_usb_log_initialize(); +#endif + + return 0; +} diff --git a/mdw/usb_companion/kdp2_usb_log.c b/mdw/usb_companion/kdp2_usb_log.c new file mode 100644 index 0000000..a93c5f3 --- /dev/null +++ b/mdw/usb_companion/kdp2_usb_log.c @@ -0,0 +1,44 @@ +//#define FIFO_CMD_DBG + +#ifdef FIFIOQ_LOG_VIA_USB + +#include + +#include "cmsis_os2.h" + +#include "kmdw_console.h" + +#include "usbd_hal.h" + +static char *s_usb_log_buf = NULL; +static int s_usb_log_buf_write_pos = 0; + +void fifoq_log_send_usb(const char *str); + +int kdp2_usb_log_initialize() +{ + s_usb_log_buf = (char *)kmdw_ddr_reserve(1024); + if (s_usb_log_buf == NULL) + return KMDW_STATUS_ERROR; + + kmdw_console_hook_callback(&fifoq_log_send_usb); + return KMDW_STATUS_OK; +} + +// Print log through interrupt endpoint, only called from logger_thread +void fifoq_log_send_usb(const char *str) +{ + if (usbd_hal_interrupt_send_check_buffer_empty(KDP2_USB_ENDPOINT_LOG_IN)) + s_usb_log_buf_write_pos = 0; + + // Reset write pos + if (s_usb_log_buf_write_pos + strlen(str) + 1 > 1000) + s_usb_log_buf_write_pos = 0; + + memcpy(s_usb_log_buf + s_usb_log_buf_write_pos, str, strlen(str) + 1); + s_usb_log_buf_write_pos += strlen(str); + + usbd_hal_interrupt_send(KDP2_USB_ENDPOINT_LOG_IN, (void *)(s_usb_log_buf), s_usb_log_buf_write_pos + 1, 1); +} + +#endif diff --git a/mdw/usb_companion/usbd_hal_520.c b/mdw/usb_companion/usbd_hal_520.c new file mode 100644 index 0000000..86c0b0e --- /dev/null +++ b/mdw/usb_companion/usbd_hal_520.c @@ -0,0 +1,193 @@ +#include "usbd_hal.h" +#include "kdrv_usbd2v.h" + +#include + +#include "kmdw_console.h" + +#ifdef FIFIOQ_LOG_VIA_USB +#define NUM_ENDPOINT 3 +#else +#define NUM_ENDPOINT 2 +#endif + +static kdrv_usbd2v_endpoint_descriptor_t hs_enp_data_out = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = KDP2_USB_ENDPOINT_DATA_OUT, // + .bmAttributes = 0x02, // TransferType = Bulk + .wMaxPacketSize = 512, // max 512 bytes + .bInterval = 0x00, // never NAKs +}; + +static kdrv_usbd2v_endpoint_descriptor_t hs_enp_data_in = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = KDP2_USB_ENDPOINT_DATA_IN, // + .bmAttributes = 0x02, // TransferType = Bulk + .wMaxPacketSize = 512, // max 512 bytes + .bInterval = 0x00, // never NAKs +}; + +#ifdef FIFIOQ_LOG_VIA_USB +static kdrv_usbd2v_endpoint_descriptor_t hs_enp_log_in = + { + .bLength = 0x07, // 7 bytes + .bDescriptorType = 0x05, // Endpoint Descriptor + .bEndpointAddress = KDP2_USB_ENDPOINT_LOG_IN, // + .bmAttributes = 0x03, // TransferType = Interrupt + .wMaxPacketSize = 1024, // max 1024 bytes + .bInterval = 1, // interval +}; +#endif + +kdrv_usbd2v_interface_descriptor_t intf_desc = + { + .bLength = 0x9, // 9 bytes + .bDescriptorType = 0x04, // Inteface Descriptor + .bInterfaceNumber = 0x0, // Interface Number + .bAlternateSetting = 0x0, // + .bNumEndpoints = NUM_ENDPOINT, // 4 endpoints + .bInterfaceClass = 0xFF, // Vendor specific + .bInterfaceSubClass = 0x0, // 3rd party uses 0x01 + .bInterfaceProtocol = 0x0, // 3rd party uses 0x50 + .iInterface = 0x0, // No String Descriptor + .endpoint[0] = &hs_enp_data_out, // receive image or command from host + .endpoint[1] = &hs_enp_data_in, // send command response back to host +#ifdef FIFIOQ_LOG_VIA_USB + .endpoint[2] = &hs_enp_log_in, // send logs to host +#endif +}; + +kdrv_usbd2v_config_descriptor_t confg_desc = + { + .bLength = 0x09, // 9 bytes + .bDescriptorType = 0x02, // Type: Configuration Descriptor + .wTotalLength = (9 + 9 + NUM_ENDPOINT * sizeof(kdrv_usbd2v_endpoint_descriptor_t)), // stotal bytes including config/interface/endpoint descriptors + .bNumInterfaces = 0x1, // Number of interfaces + .bConfigurationValue = 0x1, // Configuration number + .iConfiguration = 0x0, // No String Descriptor + .bmAttributes = 0xC0, // Self-powered, no Remote wakeup + .MaxPower = 0x0, // 0 syould be ok for self-powered device + .interface = &intf_desc, +}; + +kdrv_usbd2v_device_descriptor_t dev_desc = + { + .bLength = 0x12, // 18 bytes + .bDescriptorType = 0x01, // Type : Device Descriptor + .bcdUSB = 0x200, // USB 2.0 + .bDeviceClass = 0x00, // Device class, 0x0: defined by the interface descriptors + .bDeviceSubClass = 0x00, // Device sub-class + .bDeviceProtocol = 0x00, // Device protocol + .bMaxPacketSize0 = 0x40, // Max EP0 packet size: 64 bytes + .idVendor = 0x3231, // Vendor ID + .idProduct = 0x0100, // Product ID + .bcdDevice = 0x00B0, // Device release number + .iManufacturer = 0x01, // Manufacture string index, FIXME + .iProduct = 0x02, // Product string index, FIXME + .iSerialNumber = 0x3, // Serial number string index + .bNumConfigurations = 1, // Number of configurations, FIXME + .config = &confg_desc, // configuration descriptor +}; + +#define USB_MANUFACTURER_STRING \ + { \ + 'K', 0, 'n', 0, 'e', 0, 'r', 0, 'o', 0, 'n', 0 \ + } +#define USB_PRODUCT_STRING \ + { \ + 'K', 0, 'n', 0, 'e', 0, 'r', 0, 'o', 0, 'n', 0, ' ', 0, 'K', 0, 'L', 0, '5', 0, '2', 0, '0', 0 \ + } +#define USB_SERIAL_STRING \ + { \ + '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0, '0', 0 \ + } + +static kdrv_usbd2v_prd_string_descriptor_t str_desc_mun = + { + .bLength = (2 + 12), + .bDescriptorType = 0x03, + .bString = USB_MANUFACTURER_STRING, +}; + +static kdrv_usbd2v_prd_string_descriptor_t str_desc_prd = + { + .bLength = (2 + 24), + .bDescriptorType = 0x03, + .bString = USB_PRODUCT_STRING, +}; + +static kdrv_usbd2v_prd_string_descriptor_t str_desc_serial = + { + .bLength = (2 + 16), + .bDescriptorType = 0x03, + .bString = USB_SERIAL_STRING, +}; + +static kdrv_usbd2v_string_descriptor_t str_desc = + { + .bLength = 4, + .bDescriptorType = 0x03, + .bLanguageID = 0x0409, + .desc[0] = &str_desc_mun, + .desc[1] = &str_desc_prd, + .desc[2] = &str_desc_serial, +}; + +kdrv_status_t usbd_hal_initialize( + uint8_t *serial_string, + uint16_t bcdDevice, + usbd_hal_user_link_status_callback_t usr_link_isr_cb, + usbd_hal_user_control_callback_t usr_cx_isr_cb) +{ + memcpy((void *)str_desc_serial.bString, (void *)serial_string, sizeof(str_desc_serial.bString)); + + dev_desc.bcdDevice = bcdDevice; + + return kdrv_usbd2v_initialize(&dev_desc, &str_desc, (kdrv_usbd2v_link_status_callback_t)usr_link_isr_cb, (kdrv_usbd2v_user_control_callback_t)usr_cx_isr_cb); +} + +kdrv_status_t usbd_hal_set_enable(bool enable) +{ + return kdrv_usbd2v_set_enable(true); +} + +kdrv_status_t usbd_hal_bulk_send(uint32_t endpoint, uint32_t *buf, uint32_t txLen, uint32_t timeout_ms) +{ + return kdrv_usbd2v_bulk_send(endpoint, buf, txLen, timeout_ms); +} + +kdrv_status_t usbd_hal_bulk_receive(uint32_t endpoint, uint32_t *buf, uint32_t *blen, uint32_t timeout_ms) +{ + return kdrv_usbd2v_bulk_receive(endpoint, buf, blen, timeout_ms); +} + +bool usbd_hal_interrupt_send_check_buffer_empty(uint32_t endpoint) +{ + return kdrv_usbd2v_interrupt_send_check_buffer_empty(endpoint); +} + +kdrv_status_t usbd_hal_interrupt_send(uint32_t endpoint, uint32_t *buf, uint32_t txLen, uint32_t timeout_ms) +{ + return kdrv_usbd2v_interrupt_send(endpoint, buf, txLen, timeout_ms); +} + +kdrv_status_t usbd_hal_terminate_all_endpoint(void) +{ + return kdrv_usbd2v_terminate_all_endpoint(); +} + +usbd_hal_link_status_t usbd_hal_get_link_status(){ + kdrv_usbd2v_link_status_t t = kdrv_usbd2v_get_link_status(); + usbd_hal_link_status_t ret = USBD_STATUS_DISCONNECTED; + if(t == USBD2_STATUS_DISCONNECTED){ + ret = USBD_STATUS_DISCONNECTED; + } + else if(t == USBD2_STATUS_CONFIGURED){ + ret = USBD_STATUS_CONFIGURED; + } + return ret; +} diff --git a/mdw/usbh/kmdw_usbh.c b/mdw/usbh/kmdw_usbh.c new file mode 100644 index 0000000..36110ce --- /dev/null +++ b/mdw/usbh/kmdw_usbh.c @@ -0,0 +1,665 @@ +#ifndef __USBH_MDW_H__ +#define __USBH_MDW_H__ + +#ifndef KNERON_USBH_MDW +#error "Please define 'KNERON_USBH_MDW' in global scope, it is necessary for Kneron USBH middleware." +// stop compliation +#endif + +//#define USBH_MDW_DBG // turn on this can help trace code, a lot of code-size needed +//#define USBH_MDW_ERR // turn on this can add some more error checking, slightly code-size needed + +#include "kmdw_usbh.h" +#include "Driver_USBH.h" +#include "kmdw_memory.h" +#include +#include + +#if defined(USBH_MDW_DBG) | defined(USBH_MDW_ERR) +#include "kdrv_uart.h" +#endif + +#define USBH_EVENT_QUEUE_LEN 16 // number of Message Queue Objects + +typedef enum +{ + USBH_STM_INITED = 0, + USBH_STM_CONNECTED_FS, + USBH_STM_DISCONNECTED, + USBH_STM_RESET_HS_DONE, // reset and at high-speed + USBH_STM_RESET_HS_DONE_2, // reset and at high-speed, 2nd + USBH_STM_CUSTOM_CONFIGURE, + USBH_STM_CUSTOM_INITIALIZE, + USBH_STM_CUSTOM_INITIALIZE_DONE, + USBH_STM_FAILED = 0x100, +} USBH_STM_t; + +typedef struct +{ // object data type + uint8_t type; // 0x11 = port, 0x22 = pipe + uint8_t port; // for port event + //uint32_t pipe; // for pipe event + uint32_t event; // for both port and pipe events +} USBH_Event_t; + +// below record what thread is running what pipe +typedef struct +{ + USBH_PIPE_HANDLE pipe; + osThreadId_t thread; +} USBH_PIPE_TID_t; + +#define MAX_PIPE_NUM 6 // FIXME +#define USER_FLAG_XFER_COMPLETE 0x100U +#define MDW_FLAG_MESSAGE 0x1000U +#define MDW_FLAG_ITD_WORK 0x2000U + +#define DEV_ADDR 0x3 // FIXME: constant value ? + +static osThreadId_t usbh_mdw_tid; +static int usbh_state; // state machine control + +static uint32_t cur_pipe_num = 0; +static USBH_PIPE_TID_t dev_pipetid[MAX_PIPE_NUM] = {0}; // if pipe is not 0, it is in use +static osMessageQueueId_t usbh_msgq = NULL; +static ARM_USBH_PORT_STATE port_st; + +ARM_USBH_ISOCH_ITD_WORK_FUNC itd_work_func = 0; // this will point to a callback from USBH driver + +static USB_DEVICE_DESCRIPTOR dev_descp; +static USB_CONFIGURATION_DESCRIPTOR config_descp; + +__weak uint8_t USBH_CustomClass_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc) +{ + return 0; +} + +__weak usbStatus USBH_CustomClass_Initialize(uint8_t instance) +{ + return usbUnknownError; +} + +__weak usbStatus USBH_CustomClass_Disconnected(uint8_t instance) +{ + return usbUnknownError; +} + +static void usbh_port_event_cb(uint8_t port, uint32_t event) +{ + // dont take too much time here, because it is invoked from ISR + USBH_Event_t uevent; + uevent.type = 0x11; + uevent.port = port; + uevent.event = event; + osMessageQueuePut(usbh_msgq, &uevent, 0U, 0U); + osThreadFlagsSet(usbh_mdw_tid, MDW_FLAG_MESSAGE); +} + +static void usbh_pipe_event_cb(ARM_USBH_PIPE_HANDLE pipe_hndl, uint32_t event) +{ + // dont take too much time here, because it is invoked from ISR + +#ifdef USBH_MDW_ERR + if (event != ARM_USBH_EVENT_TRANSFER_COMPLETE) + kmdw_printf("@@ %s() error: event is not transfer_complete !!\n", __FUNCTION__); +#endif + + // there must be a pipe transfer waiting for this + + for (int i = 0; i < MAX_PIPE_NUM; i++) + { + if (pipe_hndl == dev_pipetid[i].pipe) + { + osThreadFlagsSet(dev_pipetid[i].thread, USER_FLAG_XFER_COMPLETE); + } + } +} + +static void usbh_handle_port_evnet(uint8_t port, uint32_t event) +{ + switch (event) + { + case ARM_USBH_EVENT_CONNECT: + { + // NOTE: we support only high-speed + port_st = Driver_USBH0.PortGetState(0); + +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() Connect: isCnt 0x%x, speed 0x%x\n", __FUNCTION__, port_st.connected, port_st.speed); +#endif + + if (port_st.connected && port_st.speed == ARM_USB_SPEED_FULL) + { + // here make sure state is connected and FULL speed (pre state for high-speed) + usbh_state = USBH_STM_CONNECTED_FS; + } + else if (port_st.connected && port_st.speed == ARM_USB_SPEED_HIGH && usbh_state == USBH_STM_DISCONNECTED) + { + // here make sure state is connected and FULL speed (pre state for high-speed) + usbh_state = USBH_STM_CONNECTED_FS; + } + else + { +#ifdef USBH_MDW_ERR + kmdw_printf("@@ %s() Connect: state is incorrect\n", __FUNCTION__); +#endif + usbh_state = USBH_STM_FAILED; + } + } + break; + + case ARM_USBH_EVENT_DISCONNECT: + { + port_st = Driver_USBH0.PortGetState(0); + +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() Disconnect: isCnt 0x%x, speed 0x%x\n", __FUNCTION__, port_st.connected, port_st.speed); +#endif + + if (port_st.speed == ARM_USB_SPEED_HIGH) + { + usbh_state = USBH_STM_DISCONNECTED; + } + else + { +#ifdef USBH_MDW_ERR + kmdw_printf("@@ %s() Reset: error connection or speed\n", __FUNCTION__); +#endif + usbh_state = USBH_STM_FAILED; + } + } + break; + + + case ARM_USBH_EVENT_RESET: + { + port_st = Driver_USBH0.PortGetState(0); + +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() Reset: isCnt 0x%x, speed 0x%x\n", __FUNCTION__, port_st.connected, port_st.speed); +#endif + + if (port_st.connected && port_st.speed == ARM_USB_SPEED_HIGH) + { + if (usbh_state == USBH_STM_RESET_HS_DONE) + usbh_state = USBH_STM_RESET_HS_DONE_2; + else + usbh_state = USBH_STM_RESET_HS_DONE; + } + else + { +#ifdef USBH_MDW_ERR + kmdw_printf("@@ %s() Reset: error connection or speed\n", __FUNCTION__); +#endif + usbh_state = USBH_STM_FAILED; + } + } + break; + + default: +#ifdef USBH_MDW_ERR + kmdw_printf("@@ %s() error: this event is not handled\n", __FUNCTION__); +#endif + break; + } +} + +static void usbh_protocol_stm() +{ + switch (usbh_state) + { + case USBH_STM_CONNECTED_FS: // connected at FS + { +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() doing USBH_STM_CONNECTED_FS\n", __FUNCTION__); +#endif + // reset it to see if it can be HS + osDelay(500); // FIXME + Driver_USBH0.PortReset(0); + } + break; + + case USBH_STM_DISCONNECTED: + { +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() doing USBH_STM_DISCONNECTED_FS\n", __FUNCTION__); +#endif + USBH_CustomClass_Disconnected(0); + // osDelay(500); // FIXME + // usbh_state = USBH_STM_INITED; + } + break; + + case USBH_STM_RESET_HS_DONE: // state is after reset, at HS + { +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() doing USBH_STM_RESET_HS_DONE\n", __FUNCTION__); +#endif + + // suspend & resume port + Driver_USBH0.PortSuspend(0); + osDelay(200); // FIXME + + Driver_USBH0.PortResume(0); + osDelay(200); // FIXME + + Driver_USBH0.PortReset(0); + } + break; + + case USBH_STM_RESET_HS_DONE_2: // state is after reset, at HS, 2nd + { + +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() doing USBH_STM_RESET_HS_DONE_2\n", __FUNCTION__); +#endif + uint8_t *config_buf = 0; + // modify pipe to be HS pipe + Driver_USBH0.PipeModify(dev_pipetid[0].pipe, 0x0, ARM_USB_SPEED_HIGH, 0x0, 0x0, 64); + + uint8_t data[64]; + USB_SETUP_PACKET setup; + + // GET_DESCRIPTOR - device, 64 bytes + { + setup.bmRequestType.Recipient = USB_REQUEST_TO_DEVICE; + setup.bmRequestType.Type = USB_REQUEST_STANDARD; + setup.bmRequestType.Dir = USB_REQUEST_DEVICE_TO_HOST; + setup.bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup.wValue = USB_DEVICE_DESCRIPTOR_TYPE << 8; + setup.wIndex = 0; + setup.wLength = 64; + + USBH_ControlTransfer(0, &setup, data, 64); + } + + // SET_ADDRESS (set adrees to DEV_ADDR) + { + setup.bmRequestType.Recipient = USB_REQUEST_TO_DEVICE; + setup.bmRequestType.Type = USB_REQUEST_STANDARD; + setup.bmRequestType.Dir = USB_REQUEST_HOST_TO_DEVICE; + setup.bRequest = USB_REQUEST_SET_ADDRESS; + setup.wValue = DEV_ADDR; + setup.wIndex = 0; + setup.wLength = 0; + + USBH_ControlTransfer(0, &setup, NULL, 0); + } + + // update dev address of the pipe + Driver_USBH0.PipeModify(dev_pipetid[0].pipe, DEV_ADDR, ARM_USB_SPEED_HIGH, 0x0, 0x0, 64); + + // GET_DESCRIPTOR - device, actual bytes with new address + { + setup.bmRequestType.Recipient = USB_REQUEST_TO_DEVICE; + setup.bmRequestType.Type = USB_REQUEST_STANDARD; + setup.bmRequestType.Dir = USB_REQUEST_DEVICE_TO_HOST; + setup.bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup.wValue = USB_DEVICE_DESCRIPTOR_TYPE << 8; + setup.wIndex = 0; + setup.wLength = 18; + + USBH_ControlTransfer(0, &setup, data, 64); + memcpy(&dev_descp, data, sizeof(USB_DEVICE_DESCRIPTOR)); + } + + // GET_DESCRIPTOR - configuration, first 9 bytes + { + setup.bmRequestType.Recipient = USB_REQUEST_TO_DEVICE; + setup.bmRequestType.Type = USB_REQUEST_STANDARD; + setup.bmRequestType.Dir = USB_REQUEST_DEVICE_TO_HOST; + setup.bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup.wValue = USB_CONFIGURATION_DESCRIPTOR_TYPE << 8; + setup.wIndex = 0; + setup.wLength = 9; + + USBH_ControlTransfer(0, &setup, data, 64); + memcpy(&config_descp, data, sizeof(USB_CONFIGURATION_DESCRIPTOR)); + } + + // GET_DESCRIPTOR - configuration, full length + { + + if (0 == (config_buf = malloc(config_descp.wTotalLength))) + while (1) {}; + memset(config_buf, 0,config_descp.wTotalLength); + setup.bmRequestType.Recipient = USB_REQUEST_TO_DEVICE; + setup.bmRequestType.Type = USB_REQUEST_STANDARD; + setup.bmRequestType.Dir = USB_REQUEST_DEVICE_TO_HOST; + setup.bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup.wValue = USB_CONFIGURATION_DESCRIPTOR_TYPE << 8; + setup.wIndex = 0; + setup.wLength = config_descp.wTotalLength; + + USBH_ControlTransfer(0, &setup, config_buf, config_descp.wTotalLength); + + } + + // SET_CONFIGURATION - 0x1 + { + setup.bmRequestType.Recipient = USB_REQUEST_TO_DEVICE; + setup.bmRequestType.Type = USB_REQUEST_STANDARD; + setup.bmRequestType.Dir = USB_REQUEST_HOST_TO_DEVICE; + setup.bRequest = USB_REQUEST_SET_CONFIGURATION; + setup.wValue = 1; + setup.wIndex = 0; + setup.wLength = 0; + + USBH_ControlTransfer(0, &setup, NULL, 0); + } + + usbh_state = USBH_STM_CUSTOM_CONFIGURE; // FIXME + + // next : callback user's USBH_CustomClass_Configure() + + USBH_CustomClass_Configure(0, &dev_descp, (const USB_CONFIGURATION_DESCRIPTOR *)config_buf); + memset(config_buf, 0,config_descp.wTotalLength); + free(config_buf); + + usbh_state = USBH_STM_CUSTOM_INITIALIZE; // FIXME + + // next : callback user's USBH_CustomClass_Initialize() + USBH_CustomClass_Initialize(0); + + usbh_state = USBH_STM_CUSTOM_INITIALIZE_DONE; // FIXME + } + break; + + default: +#ifdef USBH_MDW_ERR + kmdw_printf("@@ %s() error: invalid state\n", __FUNCTION__); +#endif + break; + } +} + +static void usbh_mdw_thread(void *argument) +{ +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s(), start USBH middleware thread.....\n", __FUNCTION__); +#endif + + while (1) + { + uint32_t flags = osThreadFlagsWait(MDW_FLAG_MESSAGE | MDW_FLAG_ITD_WORK, osFlagsWaitAny, osWaitForever); + + if (flags & MDW_FLAG_MESSAGE) + { + USBH_Event_t uevent; + osStatus_t status = osMessageQueueGet(usbh_msgq, &uevent, NULL, osWaitForever); // wait for message + if (status == osOK) + { + if (uevent.type == 0x11) + usbh_handle_port_evnet(uevent.port, uevent.event); + + // state machine + usbh_protocol_stm(); + } + } + if (flags & MDW_FLAG_ITD_WORK) + { + // here do the bottom-half iTD work + itd_work_func(); + } + } +} + +usbStatus USBH_Initialize(uint8_t ctrl) +{ +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s()\n", __FUNCTION__); +#endif + + // need a message queue + usbh_msgq = osMessageQueueNew(USBH_EVENT_QUEUE_LEN, sizeof(USBH_Event_t), NULL); + +#ifdef USBH_MDW_ERR + if (usbh_msgq == NULL) + { + kmdw_printf("@@ osMessageQueueNew() failed\n"); + } +#endif + + Driver_USBH0.Initialize(&usbh_port_event_cb, &usbh_pipe_event_cb); + Driver_USBH0.PowerControl(ARM_POWER_FULL); + dev_pipetid[cur_pipe_num++].pipe = Driver_USBH0.PipeCreate(0x0, ARM_USB_SPEED_LOW, 0x0, 0x0, 0x0, 0x0, 8, 0); + Driver_USBH0.PortVbusOnOff(0, true); + + usbh_state = USBH_STM_INITED; + + // first, we need a thread + usbh_mdw_tid = osThreadNew(usbh_mdw_thread, NULL, NULL); + osThreadSetPriority(usbh_mdw_tid, osPriorityHigh); // FIXME: what priority is proper ? + + return usbOK; +} + +USBH_PIPE_HANDLE USBH_PipeCreate(uint8_t device, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_max_packet_size, uint8_t ep_interval) +{ + USBH_PIPE_HANDLE pipe_h; + + pipe_h = Driver_USBH0.PipeCreate(DEV_ADDR, ARM_USB_SPEED_HIGH, 0x0, 0x0, ep_addr, ep_type, ep_max_packet_size, ep_interval); + + dev_pipetid[cur_pipe_num++].pipe = pipe_h; + +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() ep_addr 0x%x ep_type %d max_packet %d ep_interval %d, pipe 0x%p\n", + __FUNCTION__, ep_addr, ep_type, ep_max_packet_size, ep_interval, pipe_h); +#endif + + return pipe_h; +} + +static usbStatus _usbh_transfer_payload(USBH_PIPE_HANDLE pipe_hndl, uint8_t *buf, uint32_t len, bool isSend) +{ + // look up the pipe index from the pipetid table + int i; + for (i = 0; i < MAX_PIPE_NUM; i++) + if (pipe_hndl == dev_pipetid[i].pipe) + { + dev_pipetid[i].thread = osThreadGetId(); // register thread id for thread flag notification + break; + } + +#ifdef USBH_MDW_ERR + if (i >= MAX_PIPE_NUM) + { + kmdw_printf("-- pipe 0x%p is invalid\n", pipe_hndl); + return usbInvalidParameter; + } +#endif + + int32_t sts = Driver_USBH0.PipeTransfer(pipe_hndl, isSend ? ARM_USBH_PACKET_OUT : ARM_USBH_PACKET_IN, buf, len); + + uint32_t flags = osThreadFlagsWait(USER_FLAG_XFER_COMPLETE, osFlagsWaitAny, 5000); // 5 secs timeout, should be long enough + +#ifdef USBH_MDW_ERR + if (flags == osFlagsErrorTimeout) + { + kmdw_printf("-- pipe 0x%p transfer timeout\n", pipe_hndl); + return usbTimeout; + } +#endif + +#ifdef USBH_MDW_ERR + if (sts != ARM_DRIVER_OK) + { + kmdw_printf("-- pipe 0x%p error, sts = %d\n", pipe_hndl, sts); + return usbTransferError; + } +#endif + + return usbOK; +} + +usbStatus USBH_PipeSend(USBH_PIPE_HANDLE pipe_hndl, const uint8_t *buf, uint32_t len) +{ +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() pipe_hndl 0x%p buf 0x%p len %d\n", __FUNCTION__, pipe_hndl, buf, len); +#endif + + return _usbh_transfer_payload(pipe_hndl, (uint8_t *)buf, len, true); +} + +usbStatus USBH_PipeReceive(USBH_PIPE_HANDLE pipe_hndl, uint8_t *buf, uint32_t len) +{ +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() pipe_hndl 0x%p buf 0x%p len %d\n", __FUNCTION__, pipe_hndl, buf, len); +#endif + + return _usbh_transfer_payload(pipe_hndl, buf, len, false); +} + +static uint32_t _usbh_get_txfer_bytes(USBH_PIPE_HANDLE pipe_hndl) +{ + uint32_t txfer_bytes = Driver_USBH0.PipeTransferGetResult(pipe_hndl); + +#ifdef USBH_MDW_DBG + kmdw_printf("@@ pipe_hndl txfered %d bytes\n", pipe_hndl, txfer_bytes); +#endif + + return txfer_bytes; +} + +uint32_t USBH_PipeSendGetResult(USBH_PIPE_HANDLE pipe_hndl) +{ + return _usbh_get_txfer_bytes(pipe_hndl); +} + +uint32_t USBH_PipeReceiveGetResult(USBH_PIPE_HANDLE pipe_hndl) +{ + return _usbh_get_txfer_bytes(pipe_hndl); +} + +usbStatus USBH_ControlTransfer(uint8_t device, const USB_SETUP_PACKET *setup_packet, uint8_t *data, uint32_t len) +{ +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() device %d, setup_packet : 0x ", __FUNCTION__, device); + uint8_t *sp = (uint8_t *)setup_packet; + for (int i = 0; i < 8; i++) + kmdw_printf("%02x ", sp[i]); + kmdw_printf(", data ptr 0x%p, len %u\n", data, len); +#endif + + ARM_USBH_PIPE_HANDLE ctrl_pipe = dev_pipetid[0].pipe; + dev_pipetid[0].thread = osThreadGetId(); + uint32_t packet; + uint8_t *payload; + uint32_t txfer_len; + + // three stages + for (int stage = 0; stage < 3; stage++) + { + switch (stage) + { + case 0: // Setup stage + + packet = ARM_USBH_PACKET_DATA0 | ARM_USBH_PACKET_SETUP; + payload = (uint8_t *)setup_packet; + txfer_len = 8; + + break; + case 1: // Data stage (optional) + + // skeip Data stage if wLength is 0 + if (setup_packet->wLength == 0) + continue; + + // Contorl IN or OUT + packet = ARM_USBH_PACKET_DATA1 | + ((setup_packet->bmRequestType.Dir) ? ARM_USBH_PACKET_IN : ARM_USBH_PACKET_OUT); + payload = data; + txfer_len = len; + + break; + case 2: // Status stage + + packet = ARM_USBH_PACKET_DATA1 | + ((setup_packet->bmRequestType.Dir) ? ARM_USBH_PACKET_OUT : ARM_USBH_PACKET_IN); + payload = NULL; + txfer_len = 0; + + break; + } + + Driver_USBH0.PipeTransfer(ctrl_pipe, packet, payload, txfer_len); + + uint32_t flags = osThreadFlagsWait(USER_FLAG_XFER_COMPLETE, osFlagsWaitAny, 5000); // 5 secs timeout, should be long enough +#ifdef USBH_MDW_ERR + if (flags == osFlagsErrorTimeout) + { + kmdw_printf("@@ %s() control transfer timeout\n", __FUNCTION__); + return usbTimeout; + } +#endif + } + + return usbOK; +} + +USBH_PIPE_HANDLE USBH_Pipe_ISOCH_PipeDelete(USBH_PIPE_HANDLE pipe_hndl) +{ + Driver_USBH0.PipeDelete(pipe_hndl); + return usbOK; + +} + +USBH_PIPE_HANDLE USBH_Pipe_ISOCH_PipeCreate(uint8_t device, uint8_t ep_addr, uint32_t wMaxPacketSize, uint8_t bInterval, uint8_t *buf, uint32_t buf_size) +{ + USBH_PIPE_HANDLE pipe_h; + + uint16_t max_packet_size = wMaxPacketSize & 0x7FF; + uint8_t mult = (wMaxPacketSize >> 11) + 1; + + pipe_h = Driver_USBH0.PipeCreate_ISOCH(DEV_ADDR, ep_addr, max_packet_size, mult, bInterval, buf, buf_size); + + dev_pipetid[cur_pipe_num++].pipe = pipe_h; + +#ifdef USBH_MDW_DBG + kmdw_printf("@@ %s() ep_addr 0x%x ep_type 'isoch' wMaxPacketSize 0x%x bInterval %d buf 0x%p buf_size %u pipe 0x%p\n", + __FUNCTION__, ep_addr, wMaxPacketSize, bInterval, buf, buf_size, pipe_h); +#endif + + return pipe_h; +} + +static uint32_t handle_itd_cb() +{ + // wake up bottom-half thread + osThreadFlagsSet(usbh_mdw_tid, MDW_FLAG_ITD_WORK); + return 1; +} + +usbStatus USBH_Pipe_ISOCH_Start(USBH_PIPE_HANDLE pipe_hndl, USBH_CB_ISR_Isoch_transfer user_isoch_cb) +{ + // enable bottom-half mechanism + itd_work_func = Driver_USBH0.PipeEnableBH_ISOCH(pipe_hndl, handle_itd_cb); + + // start isoch transfer with user data callback + Driver_USBH0.PipeStart_ISOCH(pipe_hndl, user_isoch_cb); + + return usbOK; +} + +usbStatus USBH_Pipe_ISOCH_Stop(USBH_PIPE_HANDLE pipe_hndl) +{ + Driver_USBH0.PipeStop_ISOCH(pipe_hndl); + return usbOK; +} + +usbStatus USBH_DeviceRequest_SetInterface(uint8_t device, uint8_t index, uint8_t alternate) +{ + USB_SETUP_PACKET setup; + + setup.bmRequestType.Recipient = USB_REQUEST_TO_INTERFACE; + setup.bmRequestType.Type = USB_REQUEST_STANDARD; + setup.bmRequestType.Dir = USB_REQUEST_HOST_TO_DEVICE; + setup.bRequest = USB_REQUEST_SET_INTERFACE; + setup.wValue = alternate; + setup.wIndex = index; + setup.wLength = 0; + + return USBH_ControlTransfer(device, &setup, NULL, 0); +} + +#endif diff --git a/mdw/usbh/kmdw_uvc.c b/mdw/usbh/kmdw_uvc.c new file mode 100644 index 0000000..7c49da2 --- /dev/null +++ b/mdw/usbh/kmdw_uvc.c @@ -0,0 +1,317 @@ +#include "kmdw_usbh.h" +#include "kmdw_uvc.h" +#include "kmdw_memory.h" +#include "kdrv_gdma.h" +#include "kmdw_camera.h" +#include "kmdw_console.h" +#ifdef USBH_UVC_ERR +#include "kmdw_console.h" +#endif + +#define UVC_MAX_FRAME 10 + +typedef struct _UVC_FRAME_LINK +{ + uint32_t *user_frame; + uint32_t size; + uint8_t in_use; // 1: in use, 0: not in use + struct _UVC_FRAME_LINK *next; +} UVC_FRAME_LINK; + +static UVC_FRAME_LINK uvc_block_list[UVC_MAX_FRAME] = {0}; +static UVC_FRAME_LINK *frame_head = NULL; +static UVC_FRAME_LINK *frame_last = NULL; +#ifdef KDP_UVC +typedef struct write_frame +{ + uint32_t buffer; + uint32_t size; + int index; + +} write_frame_t; + +static write_frame_t curr_write_frame = {0, 0, -1}; + +extern uint32_t ping_pong_buf_addr[2]; +#endif + +// GDMA handle +static kdrv_gdma_handle_t dma_handle; + +__weak uint8_t USBH_UVC_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc) +{ + return 0; +} + +__weak usbStatus USBH_UVC_Initialize(uint8_t instance) +{ + return usbUnknownError; +} + + +__weak usbStatus USBH_UVC_Disconnected(uint8_t instance) +{ + return usbUnknownError; +} + +#ifdef KDP_UVC +__weak void USBH_UVC_Get_Frame(uint32_t *frame_ptr, uint32_t *frame_size, int *index) +{ + return; +} +#else +__weak void USBH_UVC_Get_Frame(uint32_t *frame_ptr, uint32_t frame_size) +{ + return; +} +#endif +// callback from usbh middleware +uint8_t USBH_CustomClass_Configure(uint8_t device, const USB_DEVICE_DESCRIPTOR *ptr_dev_desc, const USB_CONFIGURATION_DESCRIPTOR *ptr_cfg_desc) +{ + // can do something for UVC + return USBH_UVC_Configure(device, ptr_dev_desc, ptr_cfg_desc); +} + +// callback from usbh middleware +usbStatus USBH_CustomClass_Initialize(uint8_t instance) +{ + // UVC internal initialization + + // can do something for UVC + return USBH_UVC_Initialize(instance); +} + +usbStatus USBH_CustomClass_Disconnected(uint8_t instance) +{ + // UVC internal initialization + + // can do something for UVC + return USBH_UVC_Disconnected(instance); +} + +usbStatus USBH_UVC_VS_Control(uint8_t device, UVC_VS_Request_t vs_req, UVC_VS_ControlSelector_t cs, UVC_PROBE_COMMIT_CONTROL *upc_ctrl) +{ + USB_SETUP_PACKET setup; + + setup.bmRequestType.Recipient = 0x1; // interface + setup.bmRequestType.Type = 0x1; // class + setup.bmRequestType.Dir = (vs_req == SET_CUR) ? 0 : 1; + setup.bRequest = vs_req; + setup.wValue = cs; + setup.wIndex = 1; // zero and interface + setup.wLength = 26; + + return USBH_ControlTransfer(device, &setup, (uint8_t *)upc_ctrl, 26); +} + +USBH_PIPE_HANDLE USBH_UVC_PipeCreate_Isoch(uint8_t device, uint8_t ep_addr, uint32_t wMaxPacketSize, uint8_t bInterval) +{ +#define ITD_BUF_SIZE (4 * 1024 * 1024) + static uint8_t *buf = NULL; + if (NULL == buf) + buf = (uint8_t *)kmdw_ddr_reserve(ITD_BUF_SIZE); + return USBH_Pipe_ISOCH_PipeCreate(device, ep_addr, wMaxPacketSize, bInterval, buf, ITD_BUF_SIZE); +} + +#define UVC_HEADER_SIZE 12 +#define USBH_UVC_Send_Frame USBH_UVC_Get_Frame // uvc middleware send frames and uvc user get frames + +#ifdef KDP_UVC +#define ty_msg(fmt, ...) info_msg(fmt, ##__VA_ARGS__) + +void uvc_isoch_cb(uint32_t *payload, uint32_t length) +{ + static uint32_t frame_cur_offset = 0; + static uint32_t pay_load_num =0; + static uint32_t pay_load_size =0; + if (curr_write_frame.index == -1) + USBH_UVC_Get_Frame(&curr_write_frame.buffer, &curr_write_frame.size, &curr_write_frame.index); + + if ((2 >= length ) || (0 == payload )) + return; + + uint32_t *frame_buf_offset = (uint32_t *)((uint32_t)(curr_write_frame.buffer) + frame_cur_offset); + uint8_t *uv_header = (uint8_t *)payload; + uint32_t *img_body = (uint32_t *)((uint32_t)payload + UVC_HEADER_SIZE); + int32_t payload_size = (length - UVC_HEADER_SIZE); + uint16_t *p = (uint16_t *)img_body; + + if (payload_size > 0) { + pay_load_num++; + pay_load_size +=payload_size; + + for (int i = 0; i < (payload_size >> 1) + (payload_size & 0x1); i++) + p[i] = p[i] >> 8 | p[i] << 8; + + if ((frame_cur_offset + payload_size) <= ITD_BUF_SIZE) + { + kdrv_status_t dma_sts = kdrv_gdma_transfer(dma_handle, (uint32_t)frame_buf_offset, (uint32_t)img_body, payload_size); + +#ifdef USBH_UVC_ERR + if (dma_sts != KDRV_STATUS_OK) + kmdw_printf("UVC: DMA failed, dst 0x%x src 0x%x size %d\n", (uint32_t)frame_buf_offset, (uint32_t)img_body, payload_size); +#endif + } + else + { +#ifdef USBH_UVC_ERR + kmdw_printf("UVC: detect frame size overrun\n"); +#endif + frame_cur_offset = 0; + kdrv_status_t dma_sts = kdrv_gdma_transfer(dma_handle, (uint32_t)frame_buf_offset, (uint32_t)img_body, payload_size); + } + } + if (uv_header[1] & 0x2) // check bit D1:End of Frame, UVC SPEC 1.0 Table 2-5 + { + pay_load_num = 0; + pay_load_size = 0; + + // FIXME: temp solution (ping pong buffer) to remove kdrv_fb_mgr, need to test if 520 uvc device is ready + if (curr_write_frame.buffer == ping_pong_buf_addr[0]) + curr_write_frame.buffer = ping_pong_buf_addr[1]; + else + curr_write_frame.buffer = ping_pong_buf_addr[0]; + + frame_cur_offset = 0; + } + else { + frame_cur_offset += payload_size; + + } + +} +#else +void uvc_isoch_cb(uint32_t *payload, uint32_t length) +{ + static uint32_t frame_cur_offset = 0; + + if (frame_head == NULL || frame_head->user_frame == NULL) + { +#ifdef USBH_UVC_ERR + kmdw_printf("UVC: no available frame buffer to write\n"); +#endif + return; + } + if ((0 == length ) || (0 == payload )) + return; + + uint32_t *frame_buf_offset = (uint32_t *)((uint32_t)(frame_head->user_frame) + frame_cur_offset); + uint8_t *uv_header = (uint8_t *)payload; + uint32_t *img_body = (uint32_t *)((uint32_t)payload + UVC_HEADER_SIZE); + uint32_t payload_size = (length - UVC_HEADER_SIZE); + uint16_t *p = (uint16_t *)img_body; + + for (int i = 0; i < (payload_size >> 1) + (payload_size & 0x1); i++) + p[i] = p[i] >> 8 | p[i] << 8; + + if ((frame_cur_offset + payload_size) <= frame_head->size) + { + kdrv_status_t dma_sts = kdrv_gdma_transfer(dma_handle, (uint32_t)frame_buf_offset, (uint32_t)img_body, payload_size); + +#ifdef USBH_UVC_ERR + if (dma_sts != KDRV_STATUS_OK) + kmdw_printf("UVC: DMA failed, dst 0x%x src 0x%x size %d\n", (uint32_t)frame_buf_offset, (uint32_t)img_body, payload_size); +#endif + } +#ifdef USBH_UVC_ERR + else + { + frame_cur_offset = 0; + kdrv_status_t dma_sts = kdrv_gdma_transfer(dma_handle, (uint32_t)frame_buf_offset, (uint32_t)img_body, payload_size); + } +#endif + if (uv_header[1] & 0x2) // check bit D1:End of Frame, UVC SPEC 1.0 Table 2-5 + { + // send completed frame to user and advacne to the next frame + USBH_UVC_Send_Frame(frame_head->user_frame, frame_head->size); + + frame_head->in_use = 0; + frame_head = frame_head->next; + if (frame_head == NULL) + frame_last = NULL; + + frame_cur_offset = 0; + } + else { + frame_cur_offset += payload_size; + + } +} +#endif +usbStatus USBH_UVC_PipeStart_Isoch(USBH_PIPE_HANDLE pipe_hndl) +{ + // acquire a DMA channel here and configure it in advance + + // this is to make sure GDMA initialization + kdrv_gdma_initialize(); + + kdrv_status_t sts = kdrv_gdma_acquire_handle(&dma_handle); +#ifdef USBH_UVC_ERR + if (sts != KDRV_STATUS_OK) + { + kmdw_printf("UVC: acquire GDMA handle failed\n"); + return usbUnknownError; + } +#endif + + gdma_setting_t dma_setting; + dma_setting.dst_width = GDMA_TXFER_WIDTH_32_BITS; + dma_setting.src_width = GDMA_TXFER_WIDTH_32_BITS; + dma_setting.burst_size = GDMA_BURST_SIZE_16; + dma_setting.dst_addr_ctrl = GDMA_INCREMENT_ADDRESS; + dma_setting.src_addr_ctrl = GDMA_INCREMENT_ADDRESS; + dma_setting.dma_mode = GDMA_NORMAL_MODE; + dma_setting.dma_dst_req = 0; + dma_setting.dma_src_req = 0; + + kdrv_gdma_configure_setting(dma_handle, &dma_setting); + + // then start ISOCH transfer + return USBH_Pipe_ISOCH_Start(pipe_hndl, uvc_isoch_cb); +} + +usbStatus USBH_UVC_PipeStop_Isoch(USBH_PIPE_HANDLE pipe_hndl) +{ + kdrv_gdma_release_handle(dma_handle); + return USBH_Pipe_ISOCH_Stop(pipe_hndl); +} + +usbStatus USBH_UVC_Queue_Frame(USBH_PIPE_HANDLE pipe, uint32_t *frame_ptr, uint32_t size) +{ + // FIXME : pipe ? + + UVC_FRAME_LINK *new_frame; + + // find a free one + int i; + for (i = 0; i < UVC_MAX_FRAME; i++) + if (uvc_block_list[i].in_use == 0) + { + new_frame = &uvc_block_list[i]; + new_frame->in_use = 1; + break; + }; + +#ifdef USBH_UVC_ERR + if (i >= UVC_MAX_FRAME) + { + kmdw_printf("UVC: no available UVC block to queue\n"); + } +#endif + + new_frame->user_frame = frame_ptr; + new_frame->size = size; // it should match image size + new_frame->next = NULL; + + if (frame_head) + { + frame_last->next = new_frame; + frame_last = new_frame; + } + else + { + frame_head = frame_last = new_frame; + } + + return usbOK; +} diff --git a/mdw/utils/kdp_sha1.h b/mdw/utils/kdp_sha1.h new file mode 100644 index 0000000..eb51ed5 --- /dev/null +++ b/mdw/utils/kdp_sha1.h @@ -0,0 +1,73 @@ +/* + * sha1.h + * + * Description: + * This is the header file for code which implements the Secure + * Hashing Algorithm 1 as defined in FIPS PUB 180-1 published + * April 17, 1995. + * + * Many of the variable names in this code, especially the + * single character names, were used because those were the names + * used in the publication. + * + * Please read the file sha1.c for more information. + * + */ + +#ifndef _SHA1_H_ +#define _SHA1_H_ + +#include +/* + * If you do not have the ISO standard stdint.h header file, then you + * must typdef the following: + * name meaning + * uint32_t unsigned 32 bit integer + * uint8_t unsigned 8 bit integer (i.e., unsigned char) + * int_least16_t integer of >= 16 bits + * + */ + +#ifndef _SHA_enum_ +#define _SHA_enum_ +enum +{ + shaSuccess = 0, + shaNull, /* Null pointer parameter */ + shaInputTooLong, /* input data too long */ + shaStateError /* called Input after Result */ +}; +#endif +#define SHA1HashSize 20 + +/* + * This structure will hold context information for the SHA-1 + * hashing operation + */ +typedef struct SHA1Context +{ + uint32_t Intermediate_Hash[SHA1HashSize/4]; /* Message Digest */ + + uint32_t Length_Low; /* Message length in bits */ + uint32_t Length_High; /* Message length in bits */ + + /* Index into message block array */ + int_least16_t Message_Block_Index; + uint8_t Message_Block[64]; /* 512-bit message blocks */ + + int Computed; /* Is the digest computed? */ + int Corrupted; /* Is the message digest corrupted? */ +} SHA1Context; + +/* + * Function Prototypes + */ + +int SHA1Reset( SHA1Context *); +int SHA1Input( SHA1Context *, + const uint8_t *, + unsigned int); +int SHA1Result( SHA1Context *, + uint8_t Message_Digest[SHA1HashSize]); + +#endif diff --git a/mdw/utils/kmdw_utils_crc.c b/mdw/utils/kmdw_utils_crc.c new file mode 100644 index 0000000..0b20a98 --- /dev/null +++ b/mdw/utils/kmdw_utils_crc.c @@ -0,0 +1,523 @@ +/* + * Kneron crc, checksum & sha1 integrity check value generation + * + * Copyright (C) 2018 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "kdp_sha1.h" +#include "kmdw_utils_crc.h" +#include "kmdw_console.h" + + +#define SHA1CircularShift(bits,word) \ + (((word) << (bits)) | ((word) >> (32-(bits)))) + +/* Local Function Prototyptes */ +void SHA1PadMessage(SHA1Context *); +void SHA1ProcessMessageBlock(SHA1Context *); + +int SHA1Reset(SHA1Context *context) +{ + if (!context) + { + return shaNull; + } + + context->Length_Low = 0; + context->Length_High = 0; + context->Message_Block_Index = 0; + + context->Intermediate_Hash[0] = 0x67452301; + context->Intermediate_Hash[1] = 0xEFCDAB89; + context->Intermediate_Hash[2] = 0x98BADCFE; + context->Intermediate_Hash[3] = 0x10325476; + context->Intermediate_Hash[4] = 0xC3D2E1F0; + + context->Computed = 0; + context->Corrupted = 0; + + return shaSuccess; +} + +/* + * SHA1Result + * + * Description: + * This function will return the 160-bit message digest into the + * Message_Digest array provided by the caller. + * NOTE: The first octet of hash is stored in the 0th element, + * the last octet of hash in the 19th element. + * + * Parameters: + * context: [in/out] + * The context to use to calculate the SHA-1 hash. + * Message_Digest: [out] + * Where the digest is returned. + * + * Returns: + * sha Error Code. + * + */ +int SHA1Result( SHA1Context *context, + uint8_t Message_Digest[SHA1HashSize]) +{ + int i; + + if (!context || !Message_Digest) + { + return shaNull; + } + + if (context->Corrupted) + { + return context->Corrupted; + } + + if (!context->Computed) + { + SHA1PadMessage(context); + for(i=0; i<64; ++i) + { + /* message may be sensitive, clear it out */ + context->Message_Block[i] = 0; + } + context->Length_Low = 0; /* and clear length */ + context->Length_High = 0; + context->Computed = 1; + + } + + for(i = 0; i < SHA1HashSize; ++i) + { + Message_Digest[i] = context->Intermediate_Hash[i>>2] + >> 8 * ( 3 - ( i & 0x03 ) ); + } + + return shaSuccess; +} + +/* + * SHA1Input + * + * Description: + * This function accepts an array of octets as the next portion + * of the message. + * + * Parameters: + * context: [in/out] + * The SHA context to update + * message_array: [in] + * An array of characters representing the next portion of + * the message. + * length: [in] + * The length of the message in message_array + * + * Returns: + * sha Error Code. + * + */ +int SHA1Input( SHA1Context *context, + const uint8_t *message_array, + unsigned length) +{ + if (!length) + { + return shaSuccess; + } + + if (!context || !message_array) + { + return shaNull; + } + + if (context->Computed) + { + context->Corrupted = shaStateError; + + return shaStateError; + } + + if (context->Corrupted) + { + return context->Corrupted; + } + while(length-- && !context->Corrupted) + { + context->Message_Block[context->Message_Block_Index++] = + (*message_array & 0xFF); + + context->Length_Low += 8; + if (context->Length_Low == 0) + { + context->Length_High++; + if (context->Length_High == 0) + { + /* Message is too long */ + context->Corrupted = 1; + } + } + + if (context->Message_Block_Index == 64) + { + SHA1ProcessMessageBlock(context); + } + + message_array++; + } + + return shaSuccess; +} + +/* + * SHA1ProcessMessageBlock + * + * Description: + * This function will process the next 512 bits of the message + * stored in the Message_Block array. + * + * Parameters: + * None. + * + * Returns: + * Nothing. + * + * Comments: + + * Many of the variable names in this code, especially the + * single character names, were used because those were the + * names used in the publication. + * + * + */ +void SHA1ProcessMessageBlock(SHA1Context *context) +{ + const uint32_t K[] = { /* Constants defined in SHA-1 */ + 0x5A827999, + 0x6ED9EBA1, + 0x8F1BBCDC, + 0xCA62C1D6 + }; + int t; /* Loop counter */ + uint32_t temp; /* Temporary word value */ + uint32_t W[80]; /* Word sequence */ + uint32_t A, B, C, D, E; /* Word buffers */ + + /* + * Initialize the first 16 words in the array W + */ + for(t = 0; t < 16; t++) + { + W[t] = context->Message_Block[t * 4] << 24; + W[t] |= context->Message_Block[t * 4 + 1] << 16; + W[t] |= context->Message_Block[t * 4 + 2] << 8; + W[t] |= context->Message_Block[t * 4 + 3]; + } + + for(t = 16; t < 80; t++) + { + W[t] = SHA1CircularShift(1,W[t-3] ^ W[t-8] ^ W[t-14] ^ W[t-16]); + } + + A = context->Intermediate_Hash[0]; + B = context->Intermediate_Hash[1]; + C = context->Intermediate_Hash[2]; + D = context->Intermediate_Hash[3]; + E = context->Intermediate_Hash[4]; + + for(t = 0; t < 20; t++) + { + temp = SHA1CircularShift(5,A) + + ((B & C) | ((~B) & D)) + E + W[t] + K[0]; + E = D; + D = C; + C = SHA1CircularShift(30,B); + + B = A; + A = temp; + } + + for(t = 20; t < 40; t++) + { + temp = SHA1CircularShift(5,A) + (B ^ C ^ D) + E + W[t] + K[1]; + E = D; + D = C; + C = SHA1CircularShift(30,B); + B = A; + A = temp; + } + + for(t = 40; t < 60; t++) + { + temp = SHA1CircularShift(5,A) + + ((B & C) | (B & D) | (C & D)) + E + W[t] + K[2]; + E = D; + D = C; + C = SHA1CircularShift(30,B); + B = A; + A = temp; + } + + for(t = 60; t < 80; t++) + { + temp = SHA1CircularShift(5,A) + (B ^ C ^ D) + E + W[t] + K[3]; + E = D; + D = C; + C = SHA1CircularShift(30,B); + B = A; + A = temp; + } + + context->Intermediate_Hash[0] += A; + context->Intermediate_Hash[1] += B; + context->Intermediate_Hash[2] += C; + context->Intermediate_Hash[3] += D; + context->Intermediate_Hash[4] += E; + + context->Message_Block_Index = 0; +} + +/* + * SHA1PadMessage + * + + * Description: + * According to the standard, the message must be padded to an even + * 512 bits. The first padding bit must be a '1'. The last 64 + * bits represent the length of the original message. All bits in + * between should be 0. This function will pad the message + * according to those rules by filling the Message_Block array + * accordingly. It will also call the ProcessMessageBlock function + * provided appropriately. When it returns, it can be assumed that + * the message digest has been computed. + * + * Parameters: + * context: [in/out] + * The context to pad + * ProcessMessageBlock: [in] + * The appropriate SHA*ProcessMessageBlock function + * Returns: + * Nothing. + * + */ + +void SHA1PadMessage(SHA1Context *context) +{ + /* + * Check to see if the current message block is too small to hold + * the initial padding bits and length. If so, we will pad the + * block, process it, and then continue padding into a second + * block. + */ + if (context->Message_Block_Index > 55) + { + context->Message_Block[context->Message_Block_Index++] = 0x80; + while(context->Message_Block_Index < 64) + { + context->Message_Block[context->Message_Block_Index++] = 0; + } + + SHA1ProcessMessageBlock(context); + + while(context->Message_Block_Index < 56) + { + context->Message_Block[context->Message_Block_Index++] = 0; + } + } + else + { + context->Message_Block[context->Message_Block_Index++] = 0x80; + while(context->Message_Block_Index < 56) + { + + context->Message_Block[context->Message_Block_Index++] = 0; + } + } + + /* + * Store the message length as the last 8 octets + */ + context->Message_Block[56] = context->Length_High >> 24; + context->Message_Block[57] = context->Length_High >> 16; + context->Message_Block[58] = context->Length_High >> 8; + context->Message_Block[59] = context->Length_High; + context->Message_Block[60] = context->Length_Low >> 24; + context->Message_Block[61] = context->Length_Low >> 16; + context->Message_Block[62] = context->Length_Low >> 8; + context->Message_Block[63] = context->Length_Low; + + SHA1ProcessMessageBlock(context); +} + +struct SHA1Context sha_core; + +uint32_t kmdw_utils_crc_gen_sha32(uint8_t *data, uint32_t size) +{ + uint32_t *sram, *ddr, i, j; + ddr = (uint32_t*)data; + sram = (uint32_t*)(sha_core.Message_Block); + SHA1Reset(&sha_core); + for (i = 0; i < size; i += 64) + { +#if 0 + memcpy(sram, ddr, 64); + ddr += 16; +#else + for (j = 0; j < 16; j++) // copy one block over + sram[j] = *ddr++; +#endif + SHA1ProcessMessageBlock(&sha_core); + } + if (size & 0x03F) // pad partial block with zero's + { + i -= 64; // point to the start of partial block + memset(sha_core.Message_Block, 0, 64); + memcpy(sha_core.Message_Block, &data[i], size & 0x03F); + SHA1ProcessMessageBlock(&sha_core); + } + j = 0; + for (i = 0; i < 5; i++) + j ^= sha_core.Intermediate_Hash[i]; + return(j); +} + +/* Calculate the 32-bit checksum of object using 32-bit size block +** If address is not 32-bit aligned, use the fraction of the block w/ zero's +** replacing excluded bytes. (Note: we use Little Endian) +*/ +uint32_t kmdw_utils_crc_gen_sum32(uint8_t *data, uint32_t size) +{ + uint32_t sum, *ddr, i = (uint32_t)data & 0x03; + ddr = (uint32_t*) ((uint32_t)data & 0xFFFFFFFC); // point to the first 32-bit aligned block + if (i) { // starting address misaligned ? + size = size + i - 4; + sum = *ddr; + sum >>= i*8; + sum <<= i*8; + ddr++; + } + else + sum = 0; + for (i = 0; i < (size & 0xFFFFFFFC); i += 4) { + sum += *ddr; + ddr++; + } + i = size & 3; + if (i) // ending address misaligned ? + { + size = *ddr; + size <<= (4-i)*8; + size >>= (4-i)*8; + sum += size; + } + return(sum); +} + +#if ENABLE_CRC32 +static const uint32_t crc32_tab[] = { + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, + 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, + 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, + 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, + 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, + 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, + 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, + 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, + 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, + 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, + 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, + 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, + 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, + 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, + 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, + 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, + 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, + 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, + 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d +}; + +uint32_t kmdw_utils_crc_gen_crc32(uint8_t *data, uint32_t size) +{ + const uint8_t *p = data; + uint32_t crc; + + crc = ~0U; + while (size--) + crc = crc32_tab[(crc ^ *p++) & 0xFF] ^ (crc >> 8); + return crc ^ ~0U; +} + +uint16_t kmdw_utils_crc_gen_crc16(uint8_t *data, uint32_t size) +{ + uint16_t out = 0; + int bits_read = 0, bit_flag, i; + + /* Sanity check: */ + if (data == NULL) + return 0; + + while (size > 0) + { + bit_flag = out >> 15; + + /* Get next bit: */ + out <<= 1; + out |= (*data >> bits_read) & 1; + bits_read++; + if (bits_read > 7) + { + bits_read = 0; + data++; + size--; + } + + /* Cycle check: */ + if (bit_flag) + out ^= CRC16_CONSTANT; + + } + + // push out the last 16 bits + for (i = 0; i < 16; ++i) { + bit_flag = out >> 15; + out <<= 1; + if (bit_flag) + out ^= CRC16_CONSTANT; + } + + // reverse the bits + uint16_t crc = 0; + i = 0x8000; + int j = 0x0001; + for (; i != 0; i >>= 1, j <<= 1) { + if (i & out) crc |= j; + } + + return crc; +} +#endif diff --git a/platform/board/board_sn52096/board.h b/platform/board/board_sn52096/board.h new file mode 100644 index 0000000..3f22e2e --- /dev/null +++ b/platform/board/board_sn52096/board.h @@ -0,0 +1,318 @@ +#ifndef __BOARD_H__ +#define __BOARD_H__ + +/* Common definitions for all boards with KL520 */ + +#define YES 1 +#define NO 0 + +//Protocol +#define COMM_SUPPORT_I2C 0 +#define COMM_SUPPORT_SPI 1 +#define COMM_SUPPORT_UART 2 +#define COMM_SUPPORT_I2S 3 + +#define COMM_PORT_ID_0 0 +#define COMM_PORT_ID_1 1 +#define COMM_PORT_ID_2 2 +#define COMM_PORT_ID_3 3 +#define COMM_PORT_ID_4 4 + +#define COMM_I2CSPEED_100K 0 +#define COMM_I2CSPEED_200K 1 +#define COMM_I2CSPEED_400K 2 +#define COMM_I2CSPEED_1000K 3 + +#define COMM_I2CMODE_SLAVE 0 +#define COMM_I2CMODE_MASTER 1 + + +#define COMM_SPIMODE_MODE_0 0 +#define COMM_SPIMODE_MODE_1 1 +#define COMM_SPIMODE_MODE_2 2 +#define COMM_SPIMODE_MODE_3 3 + +#define COMM_UART_BAUDRATE_1200 0 +#define COMM_UART_BAUDRATE_2400 1 +#define COMM_UART_BAUDRATE_4800 2 +#define COMM_UART_BAUDRATE_9600 3 +#define COMM_UART_BAUDRATE_14400 4 +#define COMM_UART_BAUDRATE_19200 5 +#define COMM_UART_BAUDRATE_38400 6 +#define COMM_UART_BAUDRATE_57600 7 +#define COMM_UART_BAUDRATE_115200 8 +#define COMM_UART_BAUDRATE_460800 9 +#define COMM_UART_BAUDRATE_921600 10 + +//flash +//flash manufacturer +#define FLASH_TYPE_NULL 0x00 /**< No flash */ +#define FLASH_TYPE_WINBOND_NOR 0X01 +#define FLASH_TYPE_WINBOND_NAND 0X02 +#define FLASH_TYPE_MXIC_NOR 0X11 +#define FLASH_TYPE_MXIC_NAND 0X12 +#define FLASH_TYPE_GIGADEVICE_NOR 0X21 +#define FLASH_TYPE_GIGADEVICE_NAND 0X22 + +//flash SIZE +#define FLASH_SIZE_64MBIT 1 //8MBYTES +#define FLASH_SIZE_128MBIT 2 //16MBYTES +#define FLASH_SIZE_256MBIT 3 //32MBYTES + +//speed(25MHZ/50MHZ/100MHZ) +#define FLASH_COMM_SPEED_25MHZ 1 +#define FLASH_COMM_SPEED_50MHZ 2 +#define FLASH_COMM_SPEED_100MHZ 3 + +//IO pin DRIVING STRENGTH +#define FLASH_DRV_NORMAL_MODE 1 +#define FLASH_DRV_DUAL_IO_MODE 2 +#define FLASH_DRV_DUAL_OUTPUT_MODE 3 +#define FLASH_DRV_QUAD_IO_MODE 4 +#define FLASH_DRV_QUAD_OUTPUT_MODE 5 + + +#define SENSOR_ID_HMX2056 0 +#define SENSOR_ID_OV9286 1 +#define SENSOR_ID_HMXRICA 2 +#define SENSOR_ID_GC2145 3 +#define SENSOR_ID_SC132GS 4 +#define SENSOR_ID_MAX 5 +#define SENSOR_ID_EXTERN 0xFE +#define SENSOR_ID_NONE 0xFF + +#define IMGSRC_IN_PORT_NONE 0 +#define IMGSRC_IN_PORT_MIPI 1 +#define IMGSRC_IN_PORT_DPI 2 //DVP port +#define IMGSRC_IN_PORT_UVC 3 + +#define SENSOR_RES_640_480 0 +#define SENSOR_RES_480_640 1 +#define SENSOR_RES_480_272 2 +#define SENSOR_RES_272_480 3 +/* align with 720, use SENSOR_RES_xxx instead of RES_XXX +#define RES_640_480 0 +#define RES_480_640 1 +#define RES_480_272 2 +#define RES_272_480 3 +*/ +#define IMG_FORMAT_RGB565 0 +#define IMG_FORMAT_RAW10 1 +#define IMG_FORMAT_RAW8 2 +#define IMG_FORMAT_YCBCR 3 + +#define IMG_TYPE_RGB 0 +#define IMG_TYPE_IR 1 +/* align with 720, use IMG_XXX instead of IMAGE_XXX +#define IMAGE_FORMAT_RGB565 0 +#define IMAGE_FORMAT_RAW10 1 +#define IMAGE_FORMAT_RAW8 2 +#define IMAGE_FORMAT_YCBCR 3 + +#define IMAGE_TYPE_RGB 0 +#define IMAGE_TYPE_IR 1 +*/ +#define DISPLAY_DEVICE_LCDC 0 +#define DISPLAY_DEVICE_LCM 1 + +#define PANEL_MZT_480X272 1 +#define PANEL_ST7789_240X320 2 + +#define SENSOR_RES_RGB SENSOR_RES_640_480 +#define SENSOR_RES_NIR SENSOR_RES_480_640 +#define IMGSRC_FORMAT_RGB IMG_FORMAT_RGB565 +#define IMGSRC_FORMAT_NIR IMG_FORMAT_RAW8 + +#define CFG_AI_3D_LIVENESS_IN_NONE 0 +#define CFG_AI_3D_LIVENESS_IN_SCPU 1 +#define CFG_AI_3D_LIVENESS_IN_NCPU 2 + +/* Specific definitions for each board */ +#ifndef BOARD_DVP_EXAMPLE + +/* original board_kl520_96.h*/ +#define IMGSRC_IN_0 YES +#define IMGSRC_IN_1 YES + +#if (IMGSRC_IN_0 == YES) +#define IMGSRC_IN_0_PORT IMGSRC_IN_PORT_MIPI +#define IMGSRC_0_SENSORID SENSOR_ID_GC2145 +#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 +#else +#define IMGSRC_IN_0_PORT IMGSRC_IN_PORT_NONE +#define IMGSRC_0_SENSORID SENSOR_ID_NONE +#define IMGSRC_0_FORMAT IMG_FORMAT_RGB565 +#define IMGSRC_0_TYPE IMG_TYPE_RGB +#define IMGSRC_0_RES SENSOR_RES_640_480 +#define IMGSRC_0_WIDTH 640 +#define IMGSRC_0_HEIGHT 480 +#define IMGSRC_0_TILE_AVG 0 +#define IMGSRC_0_MIPI_LANE 2 +#endif + +#if (IMGSRC_IN_1 == YES) +#define IMGSRC_IN_1_PORT IMGSRC_IN_PORT_MIPI +#define IMGSRC_1_SENSORID SENSOR_ID_SC132GS +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 +#else +#define IMGSRC_IN_1_PORT IMGSRC_IN_PORT_NONE +#define IMGSRC_1_SENSORID SENSOR_ID_NONE +#define IMGSRC_1_FORMAT IMG_FORMAT_RAW8 +#define IMGSRC_1_TYPE IMG_TYPE_IR +#define IMGSRC_1_RES SENSOR_RES_480_640 +#define IMGSRC_1_WIDTH 480 +#define IMGSRC_1_HEIGHT 640 +#define IMGSRC_1_TILE_AVG 1 +#define IMGSRC_1_MIPI_LANE 2 +#endif + +#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_MIPI || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_MIPI) +#define IMGSRC_IN_HAS_MIPI +#define MIPI_LANE_RGB 2 +#define MIPI_LANE_NIR 2 +#endif + +#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_DPI || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_DPI) +#define IMGSRC_IN_HAS_DPI +#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_DPI) +#define IMAGE_DVP_PORT_NO 0 +#else +#define IMAGE_DVP_PORT_NO 1 +#endif +#endif + +#if (IMGSRC_IN_0_PORT == IMGSRC_IN_PORT_UVC || IMGSRC_IN_1_PORT == IMGSRC_IN_PORT_UVC) +#define IMGSRC_IN_HAS_UVC +#endif + +#if (IMGSRC_IN_0 && IMGSRC_IN_1 && IMGSRC_IN_2) +#define CAM_ID_MAX 3 +#elif (IMGSRC_IN_0 && IMGSRC_IN_1) +#define CAM_ID_MAX 2 +#elif (IMGSRC_IN_0 || IMGSRC_IN_1) +#define CAM_ID_MAX 1 +#else +#define CAM_ID_MAX 0 +#endif + +#define IMGSRC_NUM CAM_ID_MAX +#define MIPI_CAM_RGB 0 +#define MIPI_CAM_NIR 1 + +#define LCDC_WIDTH 640 +#define LCDC_HEIGHT 480 + +#define RGB_IMG_SOURCE_W IMGSRC_0_WIDTH +#define RGB_IMG_SOURCE_H IMGSRC_0_HEIGHT +#define NIR_IMG_SOURCE_W IMGSRC_1_WIDTH +#define NIR_IMG_SOURCE_H IMGSRC_1_HEIGHT + +#define PANEL_TYPE PANEL_MZT_480X272 +#define DISPLAY_DEVICE DISPLAY_DEVICE_LCDC + +#define CAM_CLK_MS 2 +#define CAM_CLK_NS 242 +#define CAM_CLK_PS 2 +#define CSI0_TXESC 4 +#define CSI0_CSI 11 +#define CSI0_VC0 5 +#define CSI1_TXESC 4 +#define CSI1_CSI 7 +#define CSI1_VC0 1 + +/* original board_cfg_96.h*/ +#define CFG_V2K_TYPE 8 +#define CFG_PANEL_TYPE 1 +#define CFG_DISPLAY_DMA_ENABLE 0 +#define CFG_PREFER_DISPLAY 1 +#define CFG_I2C_0_ENABLE 1 +#define CFG_I2C_1_ENABLE 0 +#define CFG_I2C_2_ENABLE 0 +#define CFG_I2C_3_ENABLE 0 +#define CFG_UART0_ENABLE 1 +#define CFG_UART1_ENABLE 0 +#define CFG_UART1_TX_DMA_ENABLE 0 +#define CFG_UART1_RX_DMA_ENABLE 0 +#define CFG_UART2_ENABLE 0 +#define CFG_UART2_TX_DMA_ENABLE 0 +#define CFG_UART2_RX_DMA_ENABLE 0 +#define CFG_UART3_ENABLE 0 +#define CFG_UART3_TX_DMA_ENABLE 0 +#define CFG_UART3_RX_DMA_ENABLE 0 +#define CFG_UART4_ENABLE 0 +#define CFG_UART4_TX_DMA_ENABLE 0 +#define CFG_UART4_RX_DMA_ENABLE 0 +#define CFG_ADC0_ENABLE 0 +#define CFG_ADC0_DMA_ENABLE 0 +#define CFG_ADC1_ENABLE 0 +#define CFG_ADC1_DMA_ENABLE 0 +#define CFG_ADC2_ENABLE 0 +#define CFG_ADC2_DMA_ENABLE 0 +#define CFG_ADC3_ENABLE 0 +#define CFG_ADC3_DMA_ENABLE 0 +#define CFG_PWM1_DMA_ENABLE 0 +#define CFG_PWM2_DMA_ENABLE 0 +#define CFG_PWM3_DMA_ENABLE 0 +#define CFG_PWM4_DMA_ENABLE 0 +#define CFG_PWM5_DMA_ENABLE 0 +#define CFG_PWM6_DMA_ENABLE 0 +#define CFG_SSP0_ENABLE 0 +#define CFG_SSP0_TX_DMA_ENABLE 0 +#define CFG_SSP0_RX_DMA_ENABLE 0 +#define CFG_SSP1_ENABLE 1 +#define CFG_SSP1_TX_DMA_ENABLE 1 +#define CFG_SSP1_RX_DMA_ENABLE 1 +#define CFG_SPI_ENABLE 1 +#define CFG_SPI_DMA_ENABLE 0 +#define CFG_SD_ENABLE 1 +#define CFG_SD_DMA_ENABLE 0 +#define CFG_USBD_ENABLE 0 +#define CFG_USBH_ENABLE 0 +#define CFG_AI_USE_FIXED_IMG 0 +#define CFG_AI_3D_ENABLE 1 +#define CFG_AI_3D_LIVENESS_IN 2 +#define CFG_UI_USR_IMG 1 +#define CFG_CONSOLE_MODE 1 +#define CFG_TOUCH_ENABLE 1 +#define CFG_USE_FRAME_BUFFER_DRIVER 1 +#define CFG_SNAPSHOT_ENABLE 1 +#define CFG_SNAPSHOT_NUMS 10 +#define CFG_DFU_FLASH_BUF_ENABLE 1 +#define CFG_DFU_IMAGE_BUF_ENABLE 1 +#define CFG_KDP_SETTINGS_ENABLE 1 +#define CFG_KDP_SETTINGS_SIZE 8192 +#define CFG_USR_SETTINGS_ENABLE 1 +#define CFG_USR_SETTINGS_SIZE 4096 + +#else +#include "board_kl520_dvp_example.h" +#endif + +/* original board_uvc.h*/ +#define YCBCR422_IMG_SOURCE_W 640 +#define YCBCR422_IMG_SOURCE_H 480 + +// #ifdef BOARD_96 +// #include "board_kl520_96.h" +// #include "board_cfg_96.h" +// #elif BOARD_DVP_EXAMPLE +// #include "board_kl520_dvp_example.h" +// #else +// #include "board_kl520_evb.h" +// #endif +// #ifdef KDP_UVC +// #include "board_uvc.h" +// #endif +#endif // __BOARD_KDP520_H__ diff --git a/platform/dev/flash/kdev_flash_gd.c b/platform/dev/flash/kdev_flash_gd.c new file mode 100644 index 0000000..4274649 --- /dev/null +++ b/platform/dev/flash/kdev_flash_gd.c @@ -0,0 +1,922 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. +* +* The information contained herein is property of Kneron, Inc. +* Terms and conditions of usage are described in detail in Kneron +* STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. +* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed +* from the file. +*/ + +/****************************************************************************** +* Filename: +* --------- +* kdev_flash_gd.c +* +* Project: +* -------- +* KL520 +* +* Description: +* ------------ +* This SPI Flash driver is specific for GigaDevice SPI Flash Access +* HW: Faraday FTSPI020 +* +* Author: +* ------- +* Teresa Chen +** +******************************************************************************/ +#include "kdev_flash_gd.h" +#include "kdrv_spif.h" +#include "kdev_flash.h" +#include "io.h" +//#define FLASH_GB_DBG +#ifdef FLASH_GB_DBG +#include "kmdw_console.h" +#define flash_msg(fmt, ...) info_msg("[GD_FLASH] " fmt, ##__VA_ARGS__) +#else +#define flash_msg(fmt, ...) +#endif + +spi_flash_t flash_info; +kdev_spif_parameter_t st_flash_info; + +#if FLASH_4BYTES_CMD_EN +bool kdev_flash_is_4byte_address(uint32_t addr) +{ + bool ret = false; + + if( addr > FLASH_3BYTE_ADDR_MAX ) + ret = true; + return ret; +} +#endif + +void kdev_flash_4Bytes_ctrl(uint8_t enable) +{ +#if FLASH_4BYTES_CMD_EN + //if (kdev_flash_is_4byte_address()) + { + if (enable) { + kdrv_spif_set_commands(SPI020_B7_CMD0, SPI020_B7_CMD1, SPI020_B7_CMD2, SPI020_B7_CMD3); + } else { + kdrv_spif_set_commands(SPI020_E9_CMD0, SPI020_E9_CMD1, SPI020_E9_CMD2, SPI020_E9_CMD3); + } + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + } +#endif +} + +void kdev_flash_write_control(uint8_t enable) +{ + /* fill in command 0~3 */ + if (enable) { + kdrv_spif_set_commands(SPI020_06_CMD0, SPI020_06_CMD1, SPI020_06_CMD2, SPI020_06_CMD3); + } else { + kdrv_spif_set_commands(SPI020_04_CMD0, SPI020_04_CMD1, SPI020_04_CMD2, SPI020_04_CMD3); + } + /* wait for command complete */ + kdrv_spif_wait_command_complete(); +} + +void kdev_flash_write_control_volatile(uint8_t enable) +{ + /* fill in command 0~3 */ + if (enable) { + kdrv_spif_set_commands(SPI020_50_CMD0, SPI020_50_CMD1, SPI020_50_CMD2, SPI020_50_CMD3); + } else { + kdrv_spif_set_commands(SPI020_04_CMD0, SPI020_04_CMD1, SPI020_04_CMD2, SPI020_04_CMD3); + } + /* wait for command complete */ + kdrv_spif_wait_command_complete(); +} + +void kdev_flash_64kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_64K) return 1; */ + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_DC_CMD1, SPI020_DC_CMD2, SPI020_DC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_D8_CMD1, SPI020_D8_CMD2, SPI020_D8_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_D8_CMD1, SPI020_D8_CMD2, SPI020_D8_CMD3); + #endif + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +void kdev_flash_32kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_64K) return 1; */ + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + kdrv_spif_set_commands(offset, SPI020_52_CMD1, SPI020_52_CMD2, SPI020_52_CMD3); + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); +} + +void kdev_flash_4kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_4K) return 1; */ + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_21_CMD1, SPI020_21_CMD2, SPI020_21_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_20_CMD1, SPI020_20_CMD2, SPI020_20_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_20_CMD1, SPI020_20_CMD2, SPI020_20_CMD3); + #endif + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +uint32_t kdev_flash_probe(spi_flash_t *flash) +{ + uint32_t chip_id=0; + + uint32_t probe_90_instruction=0; + /* fill in command 0~3 */ + //Read Manufacturer and Device Identification by JEDEC ID(0x9F) + kdrv_spif_set_commands(SPI020_9F_CMD0, SPI020_9F_CMD1, SPI020_9F_CMD2, SPI020_9F_CMD3); + /* read data */ + kdrv_spif_read_data(/*(uint8_t *)*/&chip_id, 0x3); + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + + //flash->manufacturer = (chip_id>>24); + flash->manufacturer = (uint8_t )chip_id; + if (flash->manufacturer == 0x00 || flash->manufacturer == 0xFF) { + /* fill in command 0~3 */ + //Read Manufacturer and Device Identification by 0x90 + kdrv_spif_set_commands(SPI020_90_CMD0, SPI020_90_CMD1, SPI020_90_CMD2, SPI020_90_CMD3); + /* read data */ + kdrv_spif_read_data(/*(uint8_t *)*/&chip_id, 0x02/*0x4*/); + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + //flash->manufacturer = (chip_id>>24); + flash->manufacturer = (uint8_t )chip_id; + probe_90_instruction=1; + } + flash->flash_id = (chip_id>>8); + return probe_90_instruction; +} + +/* =================================== + * Init SPI controller and flash device. + * Init flash information and register functions. + * =================================== */ +void kdev_flash_read_flash_id(void) +{ + uint32_t probe_90_instruction; + uint32_t sizeId; + + probe_90_instruction=kdev_flash_probe(&flash_info); + +#ifdef FLASH_GB_DBG + char *flash_manu; + switch (flash_info.manufacturer) { + case FLASH_WB_DEV: + flash_manu = "WINBOND"; + break; + case FLASH_MXIC_DEV: + flash_manu = "MXIC"; + break; + case FLASH_Micron_DEV: + flash_manu = "Micron"; + break; + case FLASH_GD_DEV: + flash_manu = "GigaDevice"; + break; + case FLASH_ZBIT_DEV: + flash_manu = "Zbit"; + break; + default: + flash_manu = "Unknown"; + break; + } +#endif + if(probe_90_instruction) + { + sizeId = flash_info.flash_id & 0x00FF; + if(sizeId >= FLASH_SIZE_1MB_ID) + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID+1)); + } + else + { + sizeId = (flash_info.flash_id & 0xFF00)>>8; + if(sizeId >= FLASH_SIZE_512MB_ID) { + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID-FLASH_SIZE_SHIFT)); + flash_msg("flash_size 0x%2X >= 512MB = %d kbytes\n",sizeId, flash_info.flash_size); + } + else if(sizeId >= FLASH_SIZE_1MB_ID) { + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID)); + flash_msg("flash_size 0x%2X = %d kbytes\n",sizeId, flash_info.flash_size); + } + } + + flash_msg("Manufacturer ID = 0x%02X (%s)\n", flash_info.manufacturer,flash_manu); + flash_msg("Device ID = 0x"); + if(probe_90_instruction) + flash_msg("%02X\n", flash_info.flash_id); + else + flash_msg("%04X\n", flash_info.flash_id); + + flash_msg("Flash Size = "); + if((flash_info.flash_size%1024)==0x00) { + flash_msg("%dkByte(%dMByte)\n", flash_info.flash_size,flash_info.flash_size>>10); + } else { + flash_msg("%dkByte\n", flash_info.flash_size); + } + + st_flash_info.ID = flash_info.manufacturer; + st_flash_info.erase_4K_support = 1; + st_flash_info.flash_size_KByte = flash_info.flash_size; + st_flash_info.sector_size_Bytes = SPI020_SECTOR_SIZE; + st_flash_info.total_sector_numbers = (st_flash_info.flash_size_KByte * 1024) / st_flash_info.sector_size_Bytes; +} + +/* GD Flash */ +void kdev_flash_read_status(void) +{ + uint16_t nrx_buff_word_index = 0; + uint32_t RDSR1=0; //05h + uint32_t RDSR2=0; //35h + uint32_t RDSR3=0; //15h + + kdrv_spif_set_commands( SPI020_05_CMD0_w , SPI020_05_CMD1_w, SPI020_05_CMD2_w, SPI020_05_CMD3_w ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR1, &nrx_buff_word_index, 0x01 ); + flash_msg("SPI020_05_CMD RDSR1=0x%2X\n", (uint8_t)RDSR1 ); + kdrv_spif_wait_command_complete(); + + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3 ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR2, &nrx_buff_word_index, 0x01 ); + flash_msg("SPI020_35_CMD RDSR2=0x%2X\n", (uint8_t)RDSR2 ); + kdrv_spif_wait_command_complete(); + + kdrv_spif_set_commands(SPI020_15_CMD0, SPI020_15_CMD1, SPI020_15_CMD2, SPI020_15_CMD3 ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR3, &nrx_buff_word_index, 0x01 ); + flash_msg("SPI020_15_CMD RDSR3=0x%2X\n", (uint8_t)RDSR3 ); + kdrv_spif_wait_command_complete(); + + flash_msg("Manufacturer ID = 0x%02X \n", flash_info.manufacturer); + + RDSR1 &= ~0xFC; /* disable Block protect bit6,5,4,3,2*/ + if( (RDSR3 & 0x0C) ) /* check Program/Erase Error bits */ + { + kdev_flash_write_control(1); + flash_msg("need to clean program/erase error 0x%2X \n", RDSR3&~0x0C ); + kdrv_spif_set_commands(SPI020_30_CMD0, SPI020_30_CMD1, SPI020_30_CMD2, SPI020_30_CMD3 ); + flash_msg("SPI020_30_CMD0 done\n"); + kdrv_spif_wait_command_complete(); + } + RDSR3 &= ~0x70; /* driver output strength 00 100% & clear ADP bit*/ + + RDSR2 &= ~0x40; /* clear Status Register Protect 1 bit6 */ + #if defined(FLASH_QUAD_IO_EN) && (FLASH_QUAD_IO_EN == 1) + flash_msg("Set QE enabled \n"); + RDSR2 |= BIT1; + #endif + + flash_msg("RDSR1(%4X) RDSR2(%4X) RDSR3(%4X) \n", (uint8_t)RDSR1, (uint8_t)RDSR2, (uint8_t)RDSR3); + + kdev_flash_write_control_volatile(1); + kdrv_spif_set_commands(SPI020_01_CMD0, SPI020_01_CMD1, 1, SPI020_01_CMD3 ); + kdrv_spif_write_data((uint8_t*)&RDSR1, 1); + kdrv_spif_check_status_till_ready(); + + kdev_flash_write_control_volatile(1); + kdrv_spif_set_commands(SPI020_31_CMD0, SPI020_31_CMD1, SPI020_31_CMD2, SPI020_31_CMD3 ); + kdrv_spif_write_data((uint8_t*)(&RDSR2), 1); + kdrv_spif_check_status_till_ready(); + #if defined(FLASH_QUAD_IO_EN) && (FLASH_QUAD_IO_EN == 1) + flash_msg("FLASH_WB/GD/ZBIT Set QE OK!! \n"); + #endif + + kdev_flash_write_control_volatile(1); + kdrv_spif_set_commands(SPI020_11_CMD0, SPI020_11_CMD1, SPI020_11_CMD2, SPI020_11_CMD3 ); + kdrv_spif_write_data((uint8_t*)&RDSR3, 1); + kdrv_spif_check_status_till_ready(); +} + +kdev_status_t kdev_flash_read_SFDP(void) +{ + #define SPI_Rx_SIZE (5) + uint16_t nrx_buff_word_index = 0; + uint32_t nrx_buff_word[ SPI_Rx_SIZE ]; + uint32_t ntemp =0; + + kdrv_spif_switch_low_speed(); + //check status + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x00 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.signature = nrx_buff_word[nrx_buff_word_index-1];//FLASH_SIGNATURE; + + //check + if( nrx_buff_word[nrx_buff_word_index-1] != FLASH_SIGNATURE ) + { + st_flash_info.ID = flash_info.manufacturer; + st_flash_info.erase_4K_support = 1; + st_flash_info.flash_size_KByte = flash_info.flash_size; + st_flash_info.sector_size_Bytes = SPI020_SECTOR_SIZE; + st_flash_info.total_sector_numbers = (st_flash_info.flash_size_KByte * 1024) / st_flash_info.sector_size_Bytes; + return KDEV_STATUS_ERROR; + } + + //get ptr + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x0C , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.PTP = nrx_buff_word[nrx_buff_word_index-1] & 0XFF; + + //get ID + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x10 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.ID = nrx_buff_word[nrx_buff_word_index-1] & 0XFFFFFFFF; + + if( st_flash_info.ID== 0x00 || st_flash_info.ID==0xFF ) + { + nrx_buff_word_index =0; + kdrv_spif_set_commands( SPI020_9F_CMD0 , SPI020_9F_CMD1, SPI020_9F_CMD2, SPI020_9F_CMD3 ); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, SPI020_9F_CMD2 ); + kdrv_spif_wait_command_complete(); + st_flash_info.ID = nrx_buff_word[nrx_buff_word_index-1] & 0xFF; + } + + //get 4K erase support + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP + 0, SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.erase_4K_support = nrx_buff_word[nrx_buff_word_index-1] & 0x3; + + //get size + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+4 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.flash_size_KByte = (nrx_buff_word[nrx_buff_word_index-1]>>10)>>3; + ntemp = nrx_buff_word[nrx_buff_word_index-1]>>3; + + //get sector size 0x1C + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x1C , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.sector_size_Bytes = 1<<(nrx_buff_word[ nrx_buff_word_index-1 ]&0xFF); + st_flash_info.total_sector_numbers = (ntemp / st_flash_info.sector_size_Bytes)+1; + + //get sector size 0x20 + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x20 , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.block_size_Bytes = ( 1<<( nrx_buff_word[ nrx_buff_word_index-1 ] & 0xFF ) )/st_flash_info.sector_size_Bytes ; + + //get page size + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x28 , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + ntemp = nrx_buff_word[nrx_buff_word_index-1]&0xFF; + + #if 0 + //20191219 add + nrx_buff_word_index =0; + kdrv_spif_set_commands(SPI020_15_CMD0, SPI020_15_CMD1, SPI020_15_CMD2, SPI020_15_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + nrx_buff_word_index =0; + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3);//bessel:wait interrupt instead of delay + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + + + #endif + + kdrv_spif_switch_org(); + + if( (ntemp>>4) == FLASH_PAGE_SIZE_256_CODE ) + { + st_flash_info.page_size_Bytes = 256; + } + else + { + st_flash_info.page_size_Bytes = 0; + return KDEV_STATUS_ERROR; + } + + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_initialize(void)//ARM_Flash_SignalEvent_t cb_event) +{ + #if defined(FLASH_COMM) && (FLASH_COMM == FLASH_COMM_SPEED_100MHZ) + kdrv_spif_initialize(SPI_CLK_DIVIDER_2);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_2; // SCPU:200MHz, Flash: 100MHz + #elif defined(FLASH_COMM) && (FLASH_COMM == FLASH_COMM_SPEED_50MHZ) + kdrv_spif_initialize(SPI_CLK_DIVIDER_4);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_4; // SCPU:200MHz, Flash: 50MHz + #else + kdrv_spif_initialize(SPI_CLK_DIVIDER_8);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_8; // SCPU:200MHz, Flash: 25MHz + #endif + //kdrv_spif_initialize(); + kdev_flash_read_flash_id(); + kdev_flash_read_status(); + #if FLASH_4BYTES_CMD_EN + //kdev_flash_4Bytes_ctrl(1); + #endif + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_uninitialize(void) +{ + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_power_control(ARM_POWER_STATE state) +{ + switch (state) { + case ARM_POWER_OFF: + break; + + case ARM_POWER_LOW: + break; + + case ARM_POWER_FULL: + break; + + default: + return KDEV_STATUS_ERROR; + } + return KDEV_STATUS_OK; +} + +uint32_t kdev_flash_read_compare(uint8_t type, uint32_t offset, uint32_t len, void *buf) +{ + uint32_t *read_buf;//uint8_t *read_buf; + uint32_t ret=0; + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + if (type & FLASH_DMA_READ) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + } + + /* fill in command 0~3 */ + if (type & FLASH_DTR_RW) { + if (type & FLASH_DUAL_READ) + kdrv_spif_set_commands(offset, SPI020_BD_CMD1, len, SPI020_BD_CMD3); + else if(type & FLASH_QUAD_RW) + kdrv_spif_set_commands(offset, SPI020_ED_CMD1, len, SPI020_ED_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0D_CMD1, len, SPI020_0D_CMD3); + } else if (type & FLASH_DUAL_READ) { + if(type & FLASH_IO_RW) { + //fLib_printf("Daul (0xBB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_BC_CMD1, len, SPI020_BC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #endif + } else { + //fLib_printf("Daul (0x3B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_3C_CMD1, len, SPI020_3C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #endif + } + } else if(type & FLASH_QUAD_RW) { + if(type & FLASH_IO_RW) { + //fLib_printf("Quad (0xEB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_EC_CMD1, len, SPI020_EC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #endif + } else { + //fLib_printf("Quad (0x6B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_6C_CMD1, len, SPI020_6C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #endif + } + } else if(type & FLASH_FAST_READ) { + //fLib_printf("Fast (0x0B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_0C_CMD1, len, SPI020_0C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #endif + } else {/* normal read */ + //fLib_printf("Normal (0x03) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_13_CMD1, len, SPI020_13_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + } + + if (type & FLASH_DMA_READ) { + return 0; + } + + read_buf = (uint32_t *)buf; + ret = kdrv_spif_read_compare(read_buf, len);/* read data */ + kdrv_spif_wait_command_complete();/* wait for command complete */ + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif + return ret; +} + +void kdev_flash_read(uint8_t type, uint32_t offset, uint32_t len, void *buf) +{ + uint32_t *read_buf;//uint8_t *read_buf; + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + if (type & FLASH_DMA_READ) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + } + + /* fill in command 0~3 */ + if (type & FLASH_DTR_RW) { /* Please check flash datasheet which can support DTR or not */ + if (type & FLASH_DUAL_READ) + kdrv_spif_set_commands(offset, SPI020_BD_CMD1, len, SPI020_BD_CMD3); + else if(type & FLASH_QUAD_RW) + kdrv_spif_set_commands(offset, SPI020_ED_CMD1, len, SPI020_ED_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0D_CMD1, len, SPI020_0D_CMD3); + } else if (type & FLASH_DUAL_READ) { + if(type & FLASH_IO_RW) { + //fLib_printf("Daul (0xBB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_BC_CMD1, len, SPI020_BC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #endif + } else { + //fLib_printf("Daul (0x3B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_3C_CMD1, len, SPI020_3C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #endif + } + } else if(type & FLASH_QUAD_RW) { + if(type & FLASH_IO_RW) { + //fLib_printf("Quad (0xEB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_EC_CMD1, len, SPI020_EC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #endif + } else { + //fLib_printf("Quad (0x6B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_6C_CMD1, len, SPI020_6C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #endif + } + } else if(type & FLASH_FAST_READ) { + //fLib_printf("Fast (0x0B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_0C_CMD1, len, SPI020_0C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #endif + } else {/* normal read */ /* Please be noted that 03h command only can support max. 50MHz */ + //fLib_printf("Normal (0x03) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_13_CMD1, len, SPI020_13_CMD3); + else + #if defined(SPI_BUS_SPEED) && (SPI_BUS_SPEED == SPI_BUS_SPEED_100MHZ) + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + #else + #if defined(SPI_BUS_SPEED) && (SPI_BUS_SPEED == SPI_BUS_SPEED_100MHZ) + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + #endif + } + + if (type & FLASH_DMA_READ) { + return; + } + + read_buf = (uint32_t *)buf; + kdrv_spif_read_data(read_buf, len);/* read data */ + kdrv_spif_wait_command_complete();/* wait for command complete */ + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +void kdev_flash_dma_read_stop(void) +{ + kdrv_spif_wait_command_complete();/* wait for command complete */ + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en;/* disable DMA function */ +} + +void kdev_flash_dma_write_stop(void) +{ + kdrv_spif_wait_command_complete();/* savecodesize, move into spi020_check_status_til_ready */ + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en;/* disable DMA function */ + kdrv_spif_check_status_till_ready_2(); +} + +uint8_t kdev_flash_r_state_OpCode_35(void) +{ + uint16_t nrx_buff_word_index = 0; + uint32_t RDSR2=0; //35h + /* fill in command 0~3 */ + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3 ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR2, &nrx_buff_word_index, 0x01 ); + //fLib_printf("SPI020_35_CMD1 buf[0]=0x%2X\n", RDSR2 ); + kdrv_spif_wait_command_complete(); + return (uint8_t)RDSR2; +} + +void kdev_flash_write(uint8_t type, uint32_t offset, uint32_t len, void *buf, uint32_t buf_offset) +{ + uint8_t *write_buf; + + /* This function does not take care about 4 bytes alignment */ + /* if ((uint32_t )(para->buf) % 4) return 1; */ + kdrv_spif_switch_org(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + //fLib_printf("write: offset:%x\n", offset); + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + if(type & FLASH_QUAD_RW) { + //fLib_printf("Quad (0x32) write\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_34_CMD1, len, SPI020_34_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_32_CMD1, len, SPI020_32_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_32_CMD1, len, SPI020_32_CMD3); + #endif + } else { + //fLib_printf("Normal (0x02) write\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_12_CMD1, len, SPI020_12_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_02_CMD1, len, SPI020_02_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_02_CMD1, len, SPI020_02_CMD3); + #endif + } + + if (type & FLASH_DMA_WRITE) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + return; + } + + write_buf = (uint8_t *)buf+buf_offset; + //fLib_printf("write_buf:%x, len=%x\n",write_buf, len); + kdrv_spif_write_data(write_buf, len); + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif + return; +} + +kdev_status_t kdev_flash_readdata(uint32_t addr, void *data, uint32_t cnt) +{ + uint8_t Option; + + Option = FLASH_OP_MODE; + kdev_flash_read(Option, addr , cnt , data); + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_programming(uint8_t Option, uint32_t addr, const void *data, uint32_t cnt) +{ + uint16_t wloop = 0; + uint16_t i = 0; + uint16_t final = 0; + + if (cnt % FLASH_PAGE_SIZE == 0) + wloop = (cnt / FLASH_PAGE_SIZE); + else + wloop = (cnt / FLASH_PAGE_SIZE) + 1; + + for(i=0; i nstart_index ) + { + nend_index --; + } + flash_msg("_flash_erase_multi_sectors start_addr = %X! end_addr = %X!", start_addr, end_addr); + flash_msg("_flash_erase_multi_sectors start_index = %d! end_index = %d!", nstart_index, nend_index); + if( (nstart_index <= nend_index) || (nend_index < st_flash_info.total_sector_numbers) ) + { + for(i=nstart_index; i<=nend_index; i++) + { + flash_msg("_flash_erase_multi_sectors addr = %d*%d=0x%X!", i, st_flash_info.sector_size_Bytes, i*st_flash_info.sector_size_Bytes); + kdev_flash_4kErase(i*st_flash_info.sector_size_Bytes); + flash_msg("_flash_erase_multi_sectors addr = %d*%d=0x%X done!", i, st_flash_info.sector_size_Bytes, i*st_flash_info.sector_size_Bytes); + } + return KDEV_STATUS_OK; + } + return KDEV_STATUS_ERROR; +} + +kdev_status_t kdev_flash_erase_chip(void) +{ + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + kdrv_spif_set_commands(SPI020_C7_CMD0, SPI020_C7_CMD1, SPI020_C7_CMD2, SPI020_C7_CMD3); + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + return KDEV_STATUS_OK; +} + +kdev_flash_status_t kdev_flash_get_status(void) +{ + kdev_flash_status_t status; + uint32_t flash_status; + + kdrv_spif_set_commands(SPI020_05_CMD0, SPI020_05_CMD1, SPI020_05_CMD2, SPI020_05_CMD3); + kdrv_spif_wait_command_complete(); + /* read data */ + flash_status = regSPIF_irq->st.bf.kdrv_spif_spisr.SPI_read_status; + *(uint32_t*)&status = flash_status; + return status; +} + +kdev_status_t kdev_flash_get_info(void) +{ + kdev_status_t status; + status = kdev_flash_read_SFDP(); + flash_msg("Read Flash SFDP %s", (status==KDEV_STATUS_OK ? "PASS" : "FAIL")); + return status; +} + diff --git a/platform/dev/flash/kdev_flash_mxic.c b/platform/dev/flash/kdev_flash_mxic.c new file mode 100644 index 0000000..69b34f6 --- /dev/null +++ b/platform/dev/flash/kdev_flash_mxic.c @@ -0,0 +1,894 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. +* +* The information contained herein is property of Kneron, Inc. +* Terms and conditions of usage are described in detail in Kneron +* STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. +* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed +* from the file. +*/ + +/****************************************************************************** +* Filename: +* --------- +* kdev_flash_mxic.c +* +* Project: +* -------- +* KL520 +* +* Description: +* ------------ +* This SPI Flash driver is specific for Mxic SPI Flash Access +* HW: Faraday FTSPI020 +* +* Author: +* ------- +* Teresa Chen +** +******************************************************************************/ +#include "kdev_flash_mxic.h" +#include "kdrv_spif.h" +#include "kdev_flash.h" +#include "io.h" +//#define FLASH_MXIC_DBG +#ifdef FLASH_MXIC_DBG +#include "kmdw_console.h" +#define flash_msg(fmt, ...) info_msg("[MXIC_FLASH] " fmt, ##__VA_ARGS__) +#else +#define flash_msg(fmt, ...) +#endif + +spi_flash_t flash_info; +kdev_spif_parameter_t st_flash_info; + +#if FLASH_4BYTES_CMD_EN +bool kdev_flash_is_4byte_address(uint32_t addr) +{ + bool ret = false; + + if( addr > FLASH_3BYTE_ADDR_MAX ) + ret = true; + return ret; +} +#endif + +void kdev_flash_4Bytes_ctrl(uint8_t enable) +{ +#if FLASH_4BYTES_CMD_EN + //if (kdev_flash_is_4byte_address()) + { + if (enable) { + kdrv_spif_set_commands(SPI020_B7_CMD0, SPI020_B7_CMD1, SPI020_B7_CMD2, SPI020_B7_CMD3); + } else { + kdrv_spif_set_commands(SPI020_E9_CMD0, SPI020_E9_CMD1, SPI020_E9_CMD2, SPI020_E9_CMD3); + } + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + } +#endif +} + +void kdev_flash_write_control(uint8_t enable) +{ + /* fill in command 0~3 */ + if (enable) { + kdrv_spif_set_commands(SPI020_06_CMD0, SPI020_06_CMD1, SPI020_06_CMD2, SPI020_06_CMD3); + } else { + kdrv_spif_set_commands(SPI020_04_CMD0, SPI020_04_CMD1, SPI020_04_CMD2, SPI020_04_CMD3); + } + /* wait for command complete */ + kdrv_spif_wait_command_complete(); +} + +void kdev_flash_64kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_64K) return 1; */ + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_DC_CMD1, SPI020_DC_CMD2, SPI020_DC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_D8_CMD1, SPI020_D8_CMD2, SPI020_D8_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_D8_CMD1, SPI020_D8_CMD2, SPI020_D8_CMD3); + #endif + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +void kdev_flash_32kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_64K) return 1; */ + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + kdrv_spif_set_commands(offset, SPI020_52_CMD1, SPI020_52_CMD2, SPI020_52_CMD3); + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); +} + +void kdev_flash_4kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_4K) return 1; */ + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_21_CMD1, SPI020_21_CMD2, SPI020_21_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_20_CMD1, SPI020_20_CMD2, SPI020_20_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_20_CMD1, SPI020_20_CMD2, SPI020_20_CMD3); + #endif + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +uint32_t kdev_flash_probe(spi_flash_t *flash) +{ + uint32_t chip_id=0; + + uint32_t probe_90_instruction=0; + /* fill in command 0~3 */ + //Read Manufacturer and Device Identification by JEDEC ID(0x9F) + kdrv_spif_set_commands(SPI020_9F_CMD0, SPI020_9F_CMD1, SPI020_9F_CMD2, SPI020_9F_CMD3); + /* read data */ + kdrv_spif_read_data(/*(uint8_t *)*/&chip_id, 0x3); + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + + //flash->manufacturer = (chip_id>>24); + flash->manufacturer = (uint8_t )chip_id; + if (flash->manufacturer == 0x00 || flash->manufacturer == 0xFF) { + /* fill in command 0~3 */ + //Read Manufacturer and Device Identification by 0x90 + kdrv_spif_set_commands(SPI020_90_CMD0, SPI020_90_CMD1, SPI020_90_CMD2, SPI020_90_CMD3); + /* read data */ + kdrv_spif_read_data(/*(uint8_t *)*/&chip_id, 0x02/*0x4*/); + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + //flash->manufacturer = (chip_id>>24); + flash->manufacturer = (uint8_t )chip_id; + probe_90_instruction=1; + } + flash->flash_id = (chip_id>>8); + return probe_90_instruction; +} + +/* =================================== + * Init SPI controller and flash device. + * Init flash information and register functions. + * =================================== */ +void kdev_flash_read_flash_id(void) +{ + uint32_t probe_90_instruction; + uint32_t sizeId; + + probe_90_instruction=kdev_flash_probe(&flash_info); + +#ifdef FLASH_MXIC_DBG + char *flash_manu; + switch (flash_info.manufacturer) { + case FLASH_WB_DEV: + flash_manu = "WINBOND"; + break; + case FLASH_MXIC_DEV: + flash_manu = "MXIC"; + break; + case FLASH_Micron_DEV: + flash_manu = "Micron"; + break; + case FLASH_GD_DEV: + flash_manu = "GigaDevice"; + break; + case FLASH_ZBIT_DEV: + flash_manu = "Zbit"; + break; + default: + flash_manu = "Unknown"; + break; + } +#endif + if(probe_90_instruction) + { + sizeId = flash_info.flash_id & 0x00FF; + if(sizeId >= FLASH_SIZE_1MB_ID) + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID+1)); + } + else + { + sizeId = (flash_info.flash_id & 0xFF00)>>8; + if(sizeId >= FLASH_SIZE_512MB_ID) { + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID-FLASH_SIZE_SHIFT)); + flash_msg("flash_size 0x%2X >= 512MB = %d kbytes\n",sizeId, flash_info.flash_size); + } + else if(sizeId >= FLASH_SIZE_1MB_ID) { + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID)); + flash_msg("flash_size 0x%2X = %d kbytes\n",sizeId, flash_info.flash_size); + } + } + + flash_msg("Manufacturer ID = 0x%02X (%s)\n", flash_info.manufacturer,flash_manu); + flash_msg("Device ID = 0x"); + if(probe_90_instruction) + flash_msg("%02X\n", flash_info.flash_id); + else + flash_msg("%04X\n", flash_info.flash_id); + + flash_msg("Flash Size = "); + if((flash_info.flash_size%1024)==0x00) { + flash_msg("%dkByte(%dMByte)\n", flash_info.flash_size,flash_info.flash_size>>10); + } else { + flash_msg("%dkByte\n", flash_info.flash_size); + } + + st_flash_info.ID = flash_info.manufacturer; + st_flash_info.erase_4K_support = 1; + st_flash_info.flash_size_KByte = flash_info.flash_size; + st_flash_info.sector_size_Bytes = SPI020_SECTOR_SIZE; + st_flash_info.total_sector_numbers = (st_flash_info.flash_size_KByte * 1024) / st_flash_info.sector_size_Bytes; +} + +/* Mxic Flash */ +void kdev_flash_read_status(void) +{ + uint16_t nrx_buff_word_index = 0; + uint32_t RDSR1=0; //05h + uint32_t RDCR=0; //15h + uint8_t buf[2]; + + kdrv_spif_set_commands( SPI020_05_CMD0_w , SPI020_05_CMD1_w, SPI020_05_CMD2_w, SPI020_05_CMD3_w ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR1, &nrx_buff_word_index, 0x01 ); + flash_msg("SPI020_05_CMD buf[0]=0x%2X\n", RDSR1 ); + kdrv_spif_wait_command_complete(); + + kdrv_spif_set_commands(SPI020_15_CMD0, SPI020_15_CMD1, SPI020_15_CMD2, SPI020_15_CMD3 ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDCR, &nrx_buff_word_index, 0x01 ); + flash_msg("SPI020_15_CMD1 buf[0]=0x%2X\n", RDCR ); + kdrv_spif_wait_command_complete(); + + flash_msg("Manufacturer ID = 0x%02X \n", flash_info.manufacturer); + + //enable volatile bit + kdrv_spif_set_commands(SPI020_50_CMD0, SPI020_50_CMD1, SPI020_50_CMD2, SPI020_50_CMD3); + kdrv_spif_wait_command_complete(); + flash_msg("SPI020_50_CMD0 done\n"); + RDSR1 &= ~0x3C; /* disable Block protect bit5,4,3,2*/ + RDCR &= ~0x08; /* disable Top/Bottom protect */ + RDCR |= 0x07; /* driver output strength 111 30Ohms(25L512) / 15Ohms(25L256) */ + + /* check Quad mode */ + if(FLASH_OP_MODE & FLASH_QUAD_RW) + { + /* need to use command 01h */ + flash_msg("Set FLASH_MXIC_DEV QE enabled \n"); + RDSR1 |= BIT6; //QE enabled + } + + buf[0] = (uint8_t)RDSR1; + buf[1] = (uint8_t)RDCR; + flash_msg("RDSR1(%4X) RDCR(%4X) \n", buf[0], buf[1] ); + + kdev_flash_write_control(1); + flash_msg("kdev_flash_write_control done\n"); + kdrv_spif_set_commands(SPI020_01_CMD0, SPI020_01_CMD1, SPI020_01_CMD2, SPI020_01_CMD3 ); + kdrv_spif_write_data(buf, 2); + flash_msg("spi020_check_status_til_ready\n"); + kdrv_spif_wait_command_complete();//kdrv_spif_check_status_till_ready(); +} + +kdev_status_t kdev_flash_read_SFDP(void) +{ + #define SPI_Rx_SIZE (5) + uint16_t nrx_buff_word_index = 0; + uint32_t nrx_buff_word[ SPI_Rx_SIZE ]; + uint32_t ntemp =0; + + kdrv_spif_switch_low_speed(); + //check status + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x00 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.signature = nrx_buff_word[nrx_buff_word_index-1];//FLASH_SIGNATURE; + + //check + if( nrx_buff_word[nrx_buff_word_index-1] != FLASH_SIGNATURE ) + { + st_flash_info.ID = flash_info.manufacturer; + st_flash_info.erase_4K_support = 1; + st_flash_info.flash_size_KByte = flash_info.flash_size; + st_flash_info.sector_size_Bytes = SPI020_SECTOR_SIZE; + st_flash_info.total_sector_numbers = (st_flash_info.flash_size_KByte * 1024) / st_flash_info.sector_size_Bytes; + return KDEV_STATUS_ERROR; + } + + //get ptr + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x0C , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.PTP = nrx_buff_word[nrx_buff_word_index-1] & 0XFF; + + //get ID + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x10 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.ID = nrx_buff_word[nrx_buff_word_index-1] & 0XFFFFFFFF; + + if( st_flash_info.ID== 0x00 || st_flash_info.ID==0xFF ) + { + nrx_buff_word_index =0; + kdrv_spif_set_commands( SPI020_9F_CMD0 , SPI020_9F_CMD1, SPI020_9F_CMD2, SPI020_9F_CMD3 ); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, SPI020_9F_CMD2 ); + kdrv_spif_wait_command_complete(); + st_flash_info.ID = nrx_buff_word[nrx_buff_word_index-1] & 0xFF; + } + + //get 4K erase support + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP + 0, SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.erase_4K_support = nrx_buff_word[nrx_buff_word_index-1] & 0x3; + + //get size + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+4 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.flash_size_KByte = (nrx_buff_word[nrx_buff_word_index-1]>>10)>>3; + ntemp = nrx_buff_word[nrx_buff_word_index-1]>>3; + + //get sector size 0x1C + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x1C , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.sector_size_Bytes = 1<<(nrx_buff_word[ nrx_buff_word_index-1 ]&0xFF); + st_flash_info.total_sector_numbers = (ntemp / st_flash_info.sector_size_Bytes)+1; + + //get sector size 0x20 + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x20 , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.block_size_Bytes = ( 1<<( nrx_buff_word[ nrx_buff_word_index-1 ] & 0xFF ) )/st_flash_info.sector_size_Bytes ; + + //get page size + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x28 , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + ntemp = nrx_buff_word[nrx_buff_word_index-1]&0xFF; + + #if 0 + //20191219 add + nrx_buff_word_index =0; + kdrv_spif_set_commands(SPI020_15_CMD0, SPI020_15_CMD1, SPI020_15_CMD2, SPI020_15_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + nrx_buff_word_index =0; + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3);//bessel:wait interrupt instead of delay + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + + + #endif + + kdrv_spif_switch_org(); + + if( (ntemp>>4) == FLASH_PAGE_SIZE_256_CODE ) + { + st_flash_info.page_size_Bytes = 256; + } + else + { + st_flash_info.page_size_Bytes = 0; + return KDEV_STATUS_ERROR; + } + + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_initialize(void)//ARM_Flash_SignalEvent_t cb_event) +{ + #if defined(FLASH_COMM) && (FLASH_COMM == FLASH_COMM_SPEED_100MHZ) + kdrv_spif_initialize(SPI_CLK_DIVIDER_2);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_2; // SCPU:200MHz, Flash: 100MHz + #elif defined(FLASH_COMM) && (FLASH_COMM == FLASH_COMM_SPEED_50MHZ) + kdrv_spif_initialize(SPI_CLK_DIVIDER_4);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_4; // SCPU:200MHz, Flash: 50MHz + #else + kdrv_spif_initialize(SPI_CLK_DIVIDER_8);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_8; // SCPU:200MHz, Flash: 25MHz + #endif + //kdrv_spif_initialize(); + kdev_flash_read_flash_id(); + kdev_flash_read_status(); + #if FLASH_4BYTES_CMD_EN + //kdev_flash_4Bytes_ctrl(1); + #endif + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_uninitialize(void) +{ + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_power_control(ARM_POWER_STATE state) +{ + switch (state) { + case ARM_POWER_OFF: + break; + + case ARM_POWER_LOW: + break; + + case ARM_POWER_FULL: + break; + + default: + return KDEV_STATUS_ERROR; + } + return KDEV_STATUS_OK; +} + +uint32_t kdev_flash_read_compare(uint8_t type, uint32_t offset, uint32_t len, void *buf) +{ + uint32_t *read_buf;//uint8_t *read_buf; + uint32_t ret=0; + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + if (type & FLASH_DMA_READ) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + } + + /* fill in command 0~3 */ + if (type & FLASH_DTR_RW) { + if (type & FLASH_DUAL_READ) + kdrv_spif_set_commands(offset, SPI020_BD_CMD1, len, SPI020_BD_CMD3); + else if(type & FLASH_QUAD_RW) + kdrv_spif_set_commands(offset, SPI020_ED_CMD1, len, SPI020_ED_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0D_CMD1, len, SPI020_0D_CMD3); + } else if (type & FLASH_DUAL_READ) { + if(type & FLASH_IO_RW) { + //fLib_printf("Daul (0xBB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_BC_CMD1, len, SPI020_BC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #endif + } else { + //fLib_printf("Daul (0x3B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_3C_CMD1, len, SPI020_3C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #endif + } + } else if(type & FLASH_QUAD_RW) { + if(type & FLASH_IO_RW) { + //fLib_printf("Quad (0xEB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_EC_CMD1, len, SPI020_EC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #endif + } else { + //fLib_printf("Quad (0x6B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_6C_CMD1, len, SPI020_6C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #endif + } + } else if(type & FLASH_FAST_READ) { + //fLib_printf("Fast (0x0B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_0C_CMD1, len, SPI020_0C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #endif + } else {/* normal read */ + //fLib_printf("Normal (0x03) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_13_CMD1, len, SPI020_13_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + } + + if (type & FLASH_DMA_READ) { + return 0; + } + + read_buf = (uint32_t *)buf; + ret = kdrv_spif_read_compare(read_buf, len);/* read data */ + kdrv_spif_wait_command_complete();/* wait for command complete */ + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif + return ret; +} + +void kdev_flash_read(uint8_t type, uint32_t offset, uint32_t len, void *buf) +{ + uint32_t *read_buf;//uint8_t *read_buf; + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + if (type & FLASH_DMA_READ) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + } + + /* fill in command 0~3 */ + if (type & FLASH_DTR_RW) { /* Please check flash datasheet which can support DTR or not */ + if (type & FLASH_DUAL_READ) + kdrv_spif_set_commands(offset, SPI020_BD_CMD1, len, SPI020_BD_CMD3); + else if(type & FLASH_QUAD_RW) + kdrv_spif_set_commands(offset, SPI020_ED_CMD1, len, SPI020_ED_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0D_CMD1, len, SPI020_0D_CMD3); + } else if (type & FLASH_DUAL_READ) { + if(type & FLASH_IO_RW) { + //fLib_printf("Daul (0xBB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_BC_CMD1, len, SPI020_BC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #endif + } else { + //fLib_printf("Daul (0x3B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_3C_CMD1, len, SPI020_3C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #endif + } + } else if(type & FLASH_QUAD_RW) { + if(type & FLASH_IO_RW) { + //fLib_printf("Quad (0xEB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_EC_CMD1, len, SPI020_EC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #endif + } else { + //fLib_printf("Quad (0x6B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_6C_CMD1, len, SPI020_6C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #endif + } + } else if(type & FLASH_FAST_READ) { + //fLib_printf("Fast (0x0B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_0C_CMD1, len, SPI020_0C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #endif + } else {/* normal read */ /* Please be noted that 03h command only can support max. 50MHz */ + //fLib_printf("Normal (0x03) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_13_CMD1, len, SPI020_13_CMD3); + else + #if defined(SPI_BUS_SPEED) && (SPI_BUS_SPEED == SPI_BUS_SPEED_100MHZ) + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + #else + #if defined(SPI_BUS_SPEED) && (SPI_BUS_SPEED == SPI_BUS_SPEED_100MHZ) + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + #endif + } + + if (type & FLASH_DMA_READ) { + return; + } + + read_buf = (uint32_t *)buf; + kdrv_spif_read_data(read_buf, len);/* read data */ + kdrv_spif_wait_command_complete();/* wait for command complete */ + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +void kdev_flash_dma_read_stop(void) +{ + kdrv_spif_wait_command_complete();/* wait for command complete */ + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en;/* disable DMA function */ +} + +void kdev_flash_dma_write_stop(void) +{ + kdrv_spif_wait_command_complete();/* savecodesize, move into spi020_check_status_til_ready */ + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en;/* disable DMA function */ + kdrv_spif_check_status_till_ready_2(); +} + +uint8_t kdev_flash_r_state_OpCode_35(void) +{ + uint16_t nrx_buff_word_index = 0; + uint32_t RDSR2=0; //35h + /* fill in command 0~3 */ + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3 ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR2, &nrx_buff_word_index, 0x01 ); + //fLib_printf("SPI020_35_CMD1 buf[0]=0x%2X\n", RDSR2 ); + kdrv_spif_wait_command_complete(); + return (uint8_t)RDSR2; +} + +void kdev_flash_write(uint8_t type, uint32_t offset, uint32_t len, void *buf, uint32_t buf_offset) +{ + uint8_t *write_buf; + + /* This function does not take care about 4 bytes alignment */ + /* if ((uint32_t )(para->buf) % 4) return 1; */ + kdrv_spif_switch_org(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + //fLib_printf("write: offset:%x\n", offset); + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + if(type & FLASH_QUAD_RW) { + //fLib_printf("Quad (0x32) write\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_34_CMD1, len, SPI020_34_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_32_CMD1, len, SPI020_32_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_32_CMD1, len, SPI020_32_CMD3); + #endif + } else { + //fLib_printf("Normal (0x02) write\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_12_CMD1, len, SPI020_12_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_02_CMD1, len, SPI020_02_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_02_CMD1, len, SPI020_02_CMD3); + #endif + } + + if (type & FLASH_DMA_WRITE) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + return; + } + + write_buf = (uint8_t *)buf+buf_offset; + //fLib_printf("write_buf:%x, len=%x\n",write_buf, len); + kdrv_spif_write_data(write_buf, len); + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif + return; +} + +kdev_status_t kdev_flash_readdata(uint32_t addr, void *data, uint32_t cnt) +{ + uint8_t Option; + + Option = FLASH_OP_MODE; + kdev_flash_read(Option, addr , cnt , data); + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_programming(uint8_t Option, uint32_t addr, const void *data, uint32_t cnt) +{ + uint16_t wloop = 0; + uint16_t i = 0; + uint16_t final = 0; + + if (cnt % FLASH_PAGE_SIZE == 0) + wloop = (cnt / FLASH_PAGE_SIZE); + else + wloop = (cnt / FLASH_PAGE_SIZE) + 1; + + for(i=0; i nstart_index ) + { + nend_index --; + } + flash_msg("_flash_erase_multi_sectors start_addr = %X! end_addr = %X!", start_addr, end_addr); + flash_msg("_flash_erase_multi_sectors start_index = %d! end_index = %d!", nstart_index, nend_index); + if( (nstart_index <= nend_index) || (nend_index < st_flash_info.total_sector_numbers) ) + { + for(i=nstart_index; i<=nend_index; i++) + { + flash_msg("_flash_erase_multi_sectors addr = %d*%d=0x%X!", i, st_flash_info.sector_size_Bytes, i*st_flash_info.sector_size_Bytes); + kdev_flash_4kErase(i*st_flash_info.sector_size_Bytes); + flash_msg("_flash_erase_multi_sectors addr = %d*%d=0x%X done!", i, st_flash_info.sector_size_Bytes, i*st_flash_info.sector_size_Bytes); + } + return KDEV_STATUS_OK; + } + return KDEV_STATUS_ERROR; +} + +kdev_status_t kdev_flash_erase_chip(void) +{ + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + kdrv_spif_set_commands(SPI020_C7_CMD0, SPI020_C7_CMD1, SPI020_C7_CMD2, SPI020_C7_CMD3); + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + return KDEV_STATUS_OK; +} + +kdev_flash_status_t kdev_flash_get_status(void) +{ + kdev_flash_status_t status; + uint32_t flash_status; + + kdrv_spif_set_commands(SPI020_05_CMD0, SPI020_05_CMD1, SPI020_05_CMD2, SPI020_05_CMD3); + kdrv_spif_wait_command_complete(); + /* read data */ + flash_status = regSPIF_irq->st.bf.kdrv_spif_spisr.SPI_read_status; + *(uint32_t*)&status = flash_status; + return status; +} + +kdev_status_t kdev_flash_get_info(void) +{ + kdev_status_t status; + status = kdev_flash_read_SFDP(); + flash_msg("Read Flash SFDP %s", (status==KDEV_STATUS_OK ? "PASS" : "FAIL")); + return status; +} + diff --git a/platform/dev/flash/kdev_flash_winbond.c b/platform/dev/flash/kdev_flash_winbond.c new file mode 100644 index 0000000..85d1815 --- /dev/null +++ b/platform/dev/flash/kdev_flash_winbond.c @@ -0,0 +1,916 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. +* +* The information contained herein is property of Kneron, Inc. +* Terms and conditions of usage are described in detail in Kneron +* STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. +* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed +* from the file. +*/ + +/****************************************************************************** +* Filename: +* --------- +* kdev_flash_winbond.c +* +* Project: +* -------- +* KL520 +* +* Description: +* ------------ +* This SPI Flash driver is specific for Winbond SPI Flash Access +* HW: Faraday FTSPI020 +* +* Author: +* ------- +* Teresa Chen +** +******************************************************************************/ +#include "project.h" +#include "kdev_flash_winbond.h" +#include "kdrv_spif.h" +#include "kdev_flash.h" +#include "io.h" +//#define FLASH_WB_DBG +#ifdef FLASH_WB_DBG +#include "kmdw_console.h" +#define flash_msg(fmt, ...) info_msg("[WINBOND_FLASH] " fmt, ##__VA_ARGS__) +#else +#define flash_msg(fmt, ...) +#endif + +spi_flash_t flash_info; +kdev_spif_parameter_t st_flash_info; + +#if FLASH_4BYTES_CMD_EN +bool kdev_flash_is_4byte_address(uint32_t addr) +{ + bool ret = false; + + if( addr > FLASH_3BYTE_ADDR_MAX ) + ret = true; + return ret; +} +#endif + +void kdev_flash_4Bytes_ctrl(uint8_t enable) +{ +#if FLASH_4BYTES_CMD_EN + //if (kdev_flash_is_4byte_address()) + { + if (enable) { + kdrv_spif_set_commands(SPI020_B7_CMD0, SPI020_B7_CMD1, SPI020_B7_CMD2, SPI020_B7_CMD3); + } else { + kdrv_spif_set_commands(SPI020_E9_CMD0, SPI020_E9_CMD1, SPI020_E9_CMD2, SPI020_E9_CMD3); + } + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + } +#endif +} + +void kdev_flash_write_control(uint8_t enable) +{ + /* fill in command 0~3 */ + if (enable) { + kdrv_spif_set_commands(SPI020_06_CMD0, SPI020_06_CMD1, SPI020_06_CMD2, SPI020_06_CMD3); + } else { + kdrv_spif_set_commands(SPI020_04_CMD0, SPI020_04_CMD1, SPI020_04_CMD2, SPI020_04_CMD3); + } + /* wait for command complete */ + kdrv_spif_wait_command_complete(); +} + +void kdev_flash_write_control_volatile(uint8_t enable) +{ + /* fill in command 0~3 */ + if (enable) { + kdrv_spif_set_commands(SPI020_50_CMD0, SPI020_50_CMD1, SPI020_50_CMD2, SPI020_50_CMD3); + } else { + kdrv_spif_set_commands(SPI020_04_CMD0, SPI020_04_CMD1, SPI020_04_CMD2, SPI020_04_CMD3); + } + /* wait for command complete */ + kdrv_spif_wait_command_complete(); +} + +void kdev_flash_64kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_64K) return 1; */ + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_DC_CMD1, SPI020_DC_CMD2, SPI020_DC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_D8_CMD1, SPI020_D8_CMD2, SPI020_D8_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_D8_CMD1, SPI020_D8_CMD2, SPI020_D8_CMD3); + #endif + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +void kdev_flash_32kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_64K) return 1; */ + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + kdrv_spif_set_commands(offset, SPI020_52_CMD1, SPI020_52_CMD2, SPI020_52_CMD3); + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); +} + +void kdev_flash_4kErase(uint32_t offset) +{ + /* The start offset should be in 64K boundary */ + /* if(offset % SPI020_4K) return 1; */ + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_21_CMD1, SPI020_21_CMD2, SPI020_21_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_20_CMD1, SPI020_20_CMD2, SPI020_20_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_20_CMD1, SPI020_20_CMD2, SPI020_20_CMD3); + #endif + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +uint32_t kdev_flash_probe(spi_flash_t *flash) +{ + uint32_t chip_id=0; + + uint32_t probe_90_instruction=0; + /* fill in command 0~3 */ + //Read Manufacturer and Device Identification by JEDEC ID(0x9F) + kdrv_spif_set_commands(SPI020_9F_CMD0, SPI020_9F_CMD1, SPI020_9F_CMD2, SPI020_9F_CMD3); + /* read data */ + kdrv_spif_read_data(/*(uint8_t *)*/&chip_id, 0x3); + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + + //flash->manufacturer = (chip_id>>24); + flash->manufacturer = (uint8_t )chip_id; + if (flash->manufacturer == 0x00 || flash->manufacturer == 0xFF) { + /* fill in command 0~3 */ + //Read Manufacturer and Device Identification by 0x90 + kdrv_spif_set_commands(SPI020_90_CMD0, SPI020_90_CMD1, SPI020_90_CMD2, SPI020_90_CMD3); + /* read data */ + kdrv_spif_read_data(/*(uint8_t *)*/&chip_id, 0x02/*0x4*/); + /* wait for command complete */ + kdrv_spif_wait_command_complete(); + //flash->manufacturer = (chip_id>>24); + flash->manufacturer = (uint8_t )chip_id; + probe_90_instruction=1; + } + flash->flash_id = (chip_id>>8); + return probe_90_instruction; +} + +/* =================================== + * Init SPI controller and flash device. + * Init flash information and register functions. + * =================================== */ +void kdev_flash_read_flash_id(void) +{ + uint32_t probe_90_instruction; + uint32_t sizeId; + + probe_90_instruction=kdev_flash_probe(&flash_info); + +#ifdef FLASH_WB_DBG + char *flash_manu; + switch (flash_info.manufacturer) { + case FLASH_WB_DEV: + flash_manu = "WINBOND"; + break; + case FLASH_MXIC_DEV: + flash_manu = "MXIC"; + break; + case FLASH_Micron_DEV: + flash_manu = "Micron"; + break; + case FLASH_GD_DEV: + flash_manu = "GigaDevice"; + break; + case FLASH_ZBIT_DEV: + flash_manu = "Zbit"; + break; + default: + flash_manu = "Unknown"; + break; + } +#endif + if(probe_90_instruction) + { + sizeId = flash_info.flash_id & 0x00FF; + if(sizeId >= FLASH_SIZE_1MB_ID) + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID+1)); + } + else + { + sizeId = (flash_info.flash_id & 0xFF00)>>8; + if(sizeId >= FLASH_SIZE_512MB_ID) { + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID-FLASH_SIZE_SHIFT)); + flash_msg("flash_size 0x%2X >= 512MB = %d kbytes\n",sizeId, flash_info.flash_size); + } + else if(sizeId >= FLASH_SIZE_1MB_ID) { + flash_info.flash_size = 0x400 * (1<<(sizeId-FLASH_SIZE_1MB_ID)); + flash_msg("flash_size 0x%2X = %d kbytes\n",sizeId, flash_info.flash_size); + } + } + + flash_msg("Manufacturer ID = 0x%02X (%s)\n", flash_info.manufacturer,flash_manu); + flash_msg("Device ID = 0x"); + if(probe_90_instruction) + flash_msg("%02X\n", flash_info.flash_id); + else + flash_msg("%04X\n", flash_info.flash_id); + + flash_msg("Flash Size = "); + if((flash_info.flash_size%1024)==0x00) { + flash_msg("%dkByte(%dMByte)\n", flash_info.flash_size,flash_info.flash_size>>10); + } else { + flash_msg("%dkByte\n", flash_info.flash_size); + } + + st_flash_info.ID = flash_info.manufacturer; + st_flash_info.erase_4K_support = 1; + st_flash_info.flash_size_KByte = flash_info.flash_size; + st_flash_info.sector_size_Bytes = SPI020_SECTOR_SIZE; + st_flash_info.total_sector_numbers = (st_flash_info.flash_size_KByte * 1024) / st_flash_info.sector_size_Bytes; +} + +/* WB Flash */ +void kdev_flash_read_status(void) +{ + uint16_t nrx_buff_word_index = 0; + uint32_t RDSR1=0; //05h + uint32_t RDSR2=0; //35h + uint32_t RDSR3=0; //15h + + kdrv_spif_set_commands( SPI020_05_CMD0_w , SPI020_05_CMD1_w, SPI020_05_CMD2_w, SPI020_05_CMD3_w ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR1, &nrx_buff_word_index, 0x01 ); + flash_msg("SPI020_05_CMD RDSR1=0x%2X\n", (uint8_t)RDSR1 ); + kdrv_spif_wait_command_complete(); + + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3 ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR2, &nrx_buff_word_index, 0x01 ); + flash_msg("SPI020_35_CMD RDSR2=0x%2X\n", (uint8_t)RDSR2 ); + kdrv_spif_wait_command_complete(); + + kdrv_spif_set_commands(SPI020_15_CMD0, SPI020_15_CMD1, SPI020_15_CMD2, SPI020_15_CMD3 ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR3, &nrx_buff_word_index, 0x01 ); + flash_msg("SPI020_15_CMD RDSR3=0x%2X\n", (uint8_t)RDSR3 ); + kdrv_spif_wait_command_complete(); + + flash_msg("Manufacturer ID = 0x%02X \n", flash_info.manufacturer); + + flash_msg("RDSR1(%4X) RDSR2(%4X) RDSR3(%4X) \n", (uint8_t)RDSR1, (uint8_t)RDSR2, (uint8_t)RDSR3); + RDSR1 &= ~0xFC; /* disable Status Register & Block protect bit7,6,5,4,3,2 */ + kdev_flash_write_control_volatile(1); + kdrv_spif_set_commands(SPI020_01_CMD0, SPI020_01_CMD1, 1, SPI020_01_CMD3 ); + kdrv_spif_write_data((uint8_t*)&RDSR1, 1); + kdrv_spif_check_status_till_ready(); + + RDSR2 &= ~BIT6; /* clear CMP */ + #if defined(FLASH_QUAD_IO_EN) && (FLASH_QUAD_IO_EN == 1) + flash_msg("Set QE enabled \n"); + RDSR2 |= BIT1; + #endif + + kdev_flash_write_control_volatile(1); + kdrv_spif_set_commands(SPI020_31_CMD0, SPI020_31_CMD1, SPI020_31_CMD2, SPI020_31_CMD3 ); + kdrv_spif_write_data((uint8_t*)(&RDSR2), 1); + kdrv_spif_check_status_till_ready(); + #if defined(FLASH_QUAD_IO_EN) && (FLASH_QUAD_IO_EN == 1) + flash_msg("FLASH_WB/GD/ZBIT Set QE OK!! \n"); + #endif + + RDSR3 &= ~0x06; /* clear WPS & ADP bit */ + RDSR3 &= ~0x60; /* driver output strength 00 100% */ + flash_msg("need to set driver strength 0x%2X \n", (uint8_t)RDSR3 ); + + kdev_flash_write_control_volatile(1); + kdrv_spif_set_commands(SPI020_11_CMD0, SPI020_11_CMD1, SPI020_11_CMD2, SPI020_11_CMD3 ); + kdrv_spif_write_data((uint8_t*)&RDSR3, 1); + kdrv_spif_check_status_till_ready(); + flash_msg("RDSR1(%4X) RDSR2(%4X) RDSR3(%4X) \n", (uint8_t)RDSR1, (uint8_t)RDSR2, (uint8_t)RDSR3); +} + +kdev_status_t kdev_flash_read_SFDP(void) +{ + #define SPI_Rx_SIZE (5) + uint16_t nrx_buff_word_index = 0; + uint32_t nrx_buff_word[ SPI_Rx_SIZE ]; + uint32_t ntemp =0; + + kdrv_spif_switch_low_speed(); + //check status + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x00 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.signature = nrx_buff_word[nrx_buff_word_index-1];//FLASH_SIGNATURE; + + //check + if( nrx_buff_word[nrx_buff_word_index-1] != FLASH_SIGNATURE ) + { + st_flash_info.ID = flash_info.manufacturer; + st_flash_info.erase_4K_support = 1; + st_flash_info.flash_size_KByte = flash_info.flash_size; + st_flash_info.sector_size_Bytes = SPI020_SECTOR_SIZE; + st_flash_info.total_sector_numbers = (st_flash_info.flash_size_KByte * 1024) / st_flash_info.sector_size_Bytes; + return KDEV_STATUS_ERROR; + } + + //get ptr + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x0C , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.PTP = nrx_buff_word[nrx_buff_word_index-1] & 0XFF; + + //get ID + nrx_buff_word_index =0; + kdrv_spif_set_commands( 0x10 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.ID = nrx_buff_word[nrx_buff_word_index-1] & 0XFFFFFFFF; + + if( st_flash_info.ID== 0x00 || st_flash_info.ID==0xFF ) + { + nrx_buff_word_index =0; + kdrv_spif_set_commands( SPI020_9F_CMD0 , SPI020_9F_CMD1, SPI020_9F_CMD2, SPI020_9F_CMD3 ); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, SPI020_9F_CMD2 ); + kdrv_spif_wait_command_complete(); + st_flash_info.ID = nrx_buff_word[nrx_buff_word_index-1] & 0xFF; + } + + //get 4K erase support + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP + 0, SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.erase_4K_support = nrx_buff_word[nrx_buff_word_index-1] & 0x3; + + //get size + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+4 , SPI020_5A_CMD1, 0x04, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x04 ); + kdrv_spif_wait_command_complete(); + st_flash_info.flash_size_KByte = (nrx_buff_word[nrx_buff_word_index-1]>>10)>>3; + ntemp = nrx_buff_word[nrx_buff_word_index-1]>>3; + + //get sector size 0x1C + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x1C , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.sector_size_Bytes = 1<<(nrx_buff_word[ nrx_buff_word_index-1 ]&0xFF); + st_flash_info.total_sector_numbers = (ntemp / st_flash_info.sector_size_Bytes)+1; + + //get sector size 0x20 + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x20 , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + st_flash_info.block_size_Bytes = ( 1<<( nrx_buff_word[ nrx_buff_word_index-1 ] & 0xFF ) )/st_flash_info.sector_size_Bytes ; + + //get page size + nrx_buff_word_index =0; + kdrv_spif_set_commands( st_flash_info.PTP+0x28 , SPI020_5A_CMD1, 0x01, SPI020_5A_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + ntemp = nrx_buff_word[nrx_buff_word_index-1]&0xFF; + + #if 0 + //20191219 add + nrx_buff_word_index =0; + kdrv_spif_set_commands(SPI020_15_CMD0, SPI020_15_CMD1, SPI020_15_CMD2, SPI020_15_CMD3); + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + nrx_buff_word_index =0; + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3);//bessel:wait interrupt instead of delay + kdrv_spif_read_Rx_FIFO( nrx_buff_word, &nrx_buff_word_index, 0x01 ); + kdrv_spif_wait_command_complete(); + + + #endif + + kdrv_spif_switch_org(); + + if( (ntemp>>4) == FLASH_PAGE_SIZE_256_CODE ) + { + st_flash_info.page_size_Bytes = 256; + } + else + { + st_flash_info.page_size_Bytes = 0; + return KDEV_STATUS_ERROR; + } + + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_initialize(void)//ARM_Flash_SignalEvent_t cb_event) +{ + #if defined(FLASH_COMM) && (FLASH_COMM == FLASH_COMM_SPEED_100MHZ) + kdrv_spif_initialize(SPI_CLK_DIVIDER_2);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_2; // SCPU:200MHz, Flash: 100MHz + #elif defined(FLASH_COMM) && (FLASH_COMM == FLASH_COMM_SPEED_50MHZ) + kdrv_spif_initialize(SPI_CLK_DIVIDER_4);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_4; // SCPU:200MHz, Flash: 50MHz + #else + kdrv_spif_initialize(SPI_CLK_DIVIDER_8);//reg |= SPI_CLK_MODE0 | SPI_CLK_DIVIDER_8; // SCPU:200MHz, Flash: 25MHz + #endif + kdev_flash_read_flash_id(); + kdev_flash_read_status(); + #if FLASH_4BYTES_CMD_EN + //kdev_flash_4Bytes_ctrl(1); + #endif + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_uninitialize(void) +{ + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_power_control(ARM_POWER_STATE state) +{ + switch (state) { + case ARM_POWER_OFF: + break; + + case ARM_POWER_LOW: + break; + + case ARM_POWER_FULL: + break; + + default: + return KDEV_STATUS_ERROR; + } + return KDEV_STATUS_OK; +} + +uint32_t kdev_flash_read_compare(uint8_t type, uint32_t offset, uint32_t len, void *buf) +{ + uint32_t *read_buf;//uint8_t *read_buf; + uint32_t ret=0; + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + if (type & FLASH_DMA_READ) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + } + + /* fill in command 0~3 */ + if (type & FLASH_DTR_RW) { + if (type & FLASH_DUAL_READ) + kdrv_spif_set_commands(offset, SPI020_BD_CMD1, len, SPI020_BD_CMD3); + else if(type & FLASH_QUAD_RW) + kdrv_spif_set_commands(offset, SPI020_ED_CMD1, len, SPI020_ED_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0D_CMD1, len, SPI020_0D_CMD3); + } else if (type & FLASH_DUAL_READ) { + if(type & FLASH_IO_RW) { + //fLib_printf("Daul (0xBB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_BC_CMD1, len, SPI020_BC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #endif + } else { + //fLib_printf("Daul (0x3B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_3C_CMD1, len, SPI020_3C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #endif + } + } else if(type & FLASH_QUAD_RW) { + if(type & FLASH_IO_RW) { + //fLib_printf("Quad (0xEB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_EC_CMD1, len, SPI020_EC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #endif + } else { + //fLib_printf("Quad (0x6B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_6C_CMD1, len, SPI020_6C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #endif + } + } else if(type & FLASH_FAST_READ) { + //fLib_printf("Fast (0x0B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_0C_CMD1, len, SPI020_0C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #endif + } else {/* normal read */ + //fLib_printf("Normal (0x03) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_13_CMD1, len, SPI020_13_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + } + + if (type & FLASH_DMA_READ) { + return 0; + } + + read_buf = (uint32_t *)buf; + ret = kdrv_spif_read_compare(read_buf, len);/* read data */ + kdrv_spif_wait_command_complete();/* wait for command complete */ + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif + return ret; +} + +void kdev_flash_read(uint8_t type, uint32_t offset, uint32_t len, void *buf) +{ + uint32_t *read_buf;//uint8_t *read_buf; + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + if (type & FLASH_DMA_READ) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + } + + /* fill in command 0~3 */ + if (type & FLASH_DTR_RW) { /* Please check flash datasheet which can support DTR or not */ + if (type & FLASH_DUAL_READ) + kdrv_spif_set_commands(offset, SPI020_BD_CMD1, len, SPI020_BD_CMD3); + else if(type & FLASH_QUAD_RW) + kdrv_spif_set_commands(offset, SPI020_ED_CMD1, len, SPI020_ED_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0D_CMD1, len, SPI020_0D_CMD3); + } else if (type & FLASH_DUAL_READ) { + if(type & FLASH_IO_RW) { + //fLib_printf("Daul (0xBB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_BC_CMD1, len, SPI020_BC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_BB_CMD1, len, SPI020_BB_CMD3); + #endif + } else { + //fLib_printf("Daul (0x3B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_3C_CMD1, len, SPI020_3C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_3B_CMD1, len, SPI020_3B_CMD3); + #endif + } + } else if(type & FLASH_QUAD_RW) { + if(type & FLASH_IO_RW) { + //fLib_printf("Quad (0xEB) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_EC_CMD1, len, SPI020_EC_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_EB_CMD1, len, SPI020_EB_CMD3); + #endif + } else { + //fLib_printf("Quad (0x6B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_6C_CMD1, len, SPI020_6C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_6B_CMD1, len, SPI020_6B_CMD3); + #endif + } + } else if(type & FLASH_FAST_READ) { + //fLib_printf("Fast (0x0B) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_0C_CMD1, len, SPI020_0C_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #endif + } else {/* normal read */ /* Please be noted that 03h command only can support max. 50MHz */ + //fLib_printf("Normal (0x03) read\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_13_CMD1, len, SPI020_13_CMD3); + else + #if defined(SPI_BUS_SPEED) && (SPI_BUS_SPEED == SPI_BUS_SPEED_100MHZ) + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + #else + #if defined(SPI_BUS_SPEED) && (SPI_BUS_SPEED == SPI_BUS_SPEED_100MHZ) + kdrv_spif_set_commands(offset, SPI020_0B_CMD1, len, SPI020_0B_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_03_CMD1, len, SPI020_03_CMD3); + #endif + #endif + } + + if (type & FLASH_DMA_READ) { + return; + } + + read_buf = (uint32_t *)buf; + kdrv_spif_read_data(read_buf, len);/* read data */ + kdrv_spif_wait_command_complete();/* wait for command complete */ + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif +} + +void kdev_flash_dma_read_stop(void) +{ + kdrv_spif_wait_command_complete();/* wait for command complete */ + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en;/* disable DMA function */ +} + +void kdev_flash_dma_write_stop(void) +{ + kdrv_spif_wait_command_complete();/* savecodesize, move into spi020_check_status_til_ready */ + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en;/* disable DMA function */ + kdrv_spif_check_status_till_ready_2(); +} + +uint8_t kdev_flash_r_state_OpCode_35(void) +{ + uint16_t nrx_buff_word_index = 0; + uint32_t RDSR2=0; //35h + /* fill in command 0~3 */ + kdrv_spif_set_commands(SPI020_35_CMD0, SPI020_35_CMD1, SPI020_35_CMD2, SPI020_35_CMD3 ); + nrx_buff_word_index = 0; + kdrv_spif_read_Rx_FIFO( &RDSR2, &nrx_buff_word_index, 0x01 ); + //fLib_printf("SPI020_35_CMD1 buf[0]=0x%2X\n", RDSR2 ); + kdrv_spif_wait_command_complete(); + return (uint8_t)RDSR2; +} + +void kdev_flash_write(uint8_t type, uint32_t offset, uint32_t len, void *buf, uint32_t buf_offset) +{ + uint8_t *write_buf; + + /* This function does not take care about 4 bytes alignment */ + /* if ((uint32_t )(para->buf) % 4) return 1; */ + kdrv_spif_switch_org(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(1); + #endif + + //fLib_printf("write: offset:%x\n", offset); + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + if(type & FLASH_QUAD_RW) { + //fLib_printf("Quad (0x32) write\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_34_CMD1, len, SPI020_34_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_32_CMD1, len, SPI020_32_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_32_CMD1, len, SPI020_32_CMD3); + #endif + } else { + //fLib_printf("Normal (0x02) write\n"); + #if FLASH_4BYTES_CMD_EN + if (kdev_flash_is_4byte_address(offset)) + kdrv_spif_set_commands(offset, SPI020_12_CMD1, len, SPI020_12_CMD3); + else + kdrv_spif_set_commands(offset, SPI020_02_CMD1, len, SPI020_02_CMD3); + #else + kdrv_spif_set_commands(offset, SPI020_02_CMD1, len, SPI020_02_CMD3); + #endif + } + + if (type & FLASH_DMA_WRITE) { + regSPIF_irq->st.dw.kdrv_spif_icr = SPI020_cmd_cmplt_intr_en | SPI020_DMA_EN;/* enable DMA function */ + return; + } + + write_buf = (uint8_t *)buf+buf_offset; + //fLib_printf("write_buf:%x, len=%x\n",write_buf, len); + kdrv_spif_write_data(write_buf, len); + kdrv_spif_check_status_till_ready(); + + #if FLASH_4BYTES_CMD_EN + if(kdev_flash_is_4byte_address(offset)) + kdev_flash_4Bytes_ctrl(0); + #endif + return; +} + +kdev_status_t kdev_flash_readdata(uint32_t addr, void *data, uint32_t cnt) +{ + uint8_t Option; + + Option = FLASH_OP_MODE; + kdev_flash_read(Option, addr , cnt , data); + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_flash_programming(uint8_t Option, uint32_t addr, const void *data, uint32_t cnt) +{ + uint16_t wloop = 0; + uint16_t i = 0; + uint16_t final = 0; + + if (cnt % FLASH_PAGE_SIZE == 0) + wloop = (cnt / FLASH_PAGE_SIZE); + else + wloop = (cnt / FLASH_PAGE_SIZE) + 1; + + for(i=0; i nstart_index ) + { + nend_index --; + } + flash_msg("_flash_erase_multi_sectors start_addr = %X! end_addr = %X!", start_addr, end_addr); + flash_msg("_flash_erase_multi_sectors start_index = %d! end_index = %d!", nstart_index, nend_index); + if( (nstart_index <= nend_index) || (nend_index < st_flash_info.total_sector_numbers) ) + { + for(i=nstart_index; i<=nend_index; i++) + { + flash_msg("_flash_erase_multi_sectors addr = %d*%d=0x%X!", i, st_flash_info.sector_size_Bytes, i*st_flash_info.sector_size_Bytes); + kdev_flash_4kErase(i*st_flash_info.sector_size_Bytes); + flash_msg("_flash_erase_multi_sectors addr = %d*%d=0x%X done!", i, st_flash_info.sector_size_Bytes, i*st_flash_info.sector_size_Bytes); + } + return KDEV_STATUS_OK; + } + return KDEV_STATUS_ERROR; +} + +kdev_status_t kdev_flash_erase_chip(void) +{ + kdev_flash_write_control(1);/* send write enabled */ + + /* fill in command 0~3 */ + kdrv_spif_set_commands(SPI020_C7_CMD0, SPI020_C7_CMD1, SPI020_C7_CMD2, SPI020_C7_CMD3); + /* wait for command complete */ + kdrv_spif_check_status_till_ready(); + return KDEV_STATUS_OK; +} + +kdev_flash_status_t kdev_flash_get_status(void) +{ + kdev_flash_status_t status; + uint32_t flash_status; + + kdrv_spif_set_commands(SPI020_05_CMD0, SPI020_05_CMD1, SPI020_05_CMD2, SPI020_05_CMD3); + kdrv_spif_wait_command_complete(); + /* read data */ + flash_status = regSPIF_irq->st.bf.kdrv_spif_spisr.SPI_read_status; + *(uint32_t*)&status = flash_status; + return status; +} + +kdev_status_t kdev_flash_get_info(void) +{ + kdev_status_t status; + status = kdev_flash_read_SFDP(); + flash_msg("Read Flash SFDP %s", (status==KDEV_STATUS_OK ? "PASS" : "FAIL")); + return status; +} + diff --git a/platform/dev/include/kdev_flash.h b/platform/dev/include/kdev_flash.h new file mode 100644 index 0000000..dd7ff23 --- /dev/null +++ b/platform/dev/include/kdev_flash.h @@ -0,0 +1,227 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. +* +* The information contained herein is property of Kneron, Inc. +* Terms and conditions of usage are described in detail in Kneron +* STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. +* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed +* from the file. +*/ + +/* History: + * Version 2.00 + * Renamed driver NOR -> Flash (more generic) + * Non-blocking operation + * Added Events, Status and Capabilities + * Linked Flash information (GetInfo) + * Version 1.11 + * Changed prefix ARM_DRV -> ARM_DRIVER + * Version 1.10 + * Namespace prefix ARM_ added + * Version 1.00 + * Initial release + */ + +/**@addtogroup KDEV_FLASH KDEV_FLASH + * @{ + * @brief Kneron flash device + * @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. + */ +#ifndef __KDEV_FLASH_H +#define __KDEV_FLASH_H + +#include "Driver_Common.h" +#include "kdrv_SPI020.h" +#include "kdev_status.h" +#include "project.h" +#if defined(FLASH_DRV) && (FLASH_DRV == FLASH_DRV_QUAD_OUTPUT_MODE) +#define FLASH_OP_MODE FLASH_QUAD_RW +#elif defined(FLASH_DRV) && (FLASH_DRV == FLASH_DRV_QUAD_IO_MODE) +#define FLASH_OP_MODE (FLASH_QUAD_RW|FLASH_IO_RW) +#elif defined(FLASH_DRV) && (FLASH_DRV == FLASH_DRV_DUAL_OUTPUT_MODE) +#define FLASH_OP_MODE FLASH_DUAL_READ +#elif defined(FLASH_DRV) && (FLASH_DRV == FLASH_DRV_DUAL_IO_MODE) +#define FLASH_OP_MODE (FLASH_DUAL_READ|FLASH_IO_RW) +#elif defined(FLASH_DRV) && (FLASH_DRV == FLASH_DRV_NORMAL_MODE) +#define FLASH_OP_MODE FLASH_NORMAL +#else +#error "FLASH_DRV doesn't defined in project.h" +#endif + +#if defined (FLASH_SIZE) && (FLASH_SIZE < FLASH_SIZE_256MBIT) +#define FLASH_4BYTES_CMD_EN 0x00 +#else +#define FLASH_4BYTES_CMD_EN 0x01 +#endif + +#define SPI020_SECTOR_SIZE 4096 +#define SPI020_BLOCK_64SIZE 65536 + +#define FLASH_CODE_OPT (YES) +#define FLASH_CODING_GET_INFO_EN (YES) + +/** +* @brief Flash Sector index struct +*/ +typedef struct { + uint32_t start; /**< Sector Start address */ + uint32_t end; /**< Sector End address (start+size-1) */ +}kdev_flash_sector_t; + +/** +* @brief Flash information struct +*/ +typedef struct { + kdev_flash_sector_t *sector_info; /**< Sector layout information (NULL=Uniform sectors) */ + uint32_t sector_count; /**< Number of sectors */ + uint32_t sector_size; /**< Uniform sector size in bytes (0=sector_info used) */ + uint32_t page_size; /**< Optimal programming page size in bytes */ + uint32_t program_unit; /**< Smallest programmable unit in bytes */ + uint8_t erased_value; /**< Contents of erased memory (usually 0xFF) */ + uint32_t flash_size; +} kdev_flash_info_t; + +typedef struct _flash_paramter +{ + uint32_t signature; //0x00 + uint8_t PTP; //0x0C + uint8_t ID; //0x10 + uint8_t erase_4K_support; //0x00 => 0x30[1:0]; + uint32_t flash_size_KByte; //0x04~0x07 => 0x34~0x37 + uint16_t page_size_Bytes; //0x28 => 0x58[7:4]=0x8 + uint16_t sector_size_Bytes; + uint32_t block_size_Bytes; //how many sectors in one block + uint16_t total_sector_numbers; +} kdev_spif_parameter_t; + +/** +* @brief Flash Status struct +*/ +typedef struct { + uint32_t busy : 1; /**< Flash busy flag */ + uint32_t error : 1; /**< Read/Program/Erase error flag (cleared on start of next operation) */ +} kdev_flash_status_t; + + +extern uint32_t kdev_flash_probe(spi_flash_t *flash); + +// Function documentation +/** +* @fn kdev_status_t kdev_flash_initialize (void) +* @brief Initialize spi flash interface include hardware setting, get flash information and set to 4byte address +* if flash size is bigger than 16Mbytes +* @param[in] N/A +* @return @ref kdrv_status_t +* +* @note This API MUST be called before using the Read/write APIs for spi flash. +*/ +kdev_status_t kdev_flash_initialize(void);//ARM_Flash_SignalEvent_t cb_event); +/** +* @fn kdrv_status_t kdev_flash_uninitialize(void) +* @brief Uinitialize the spi flash interface. +* @return @ref kdrv_status_t +*/ +kdev_status_t kdev_flash_uninitialize(void); +/** +* @fn kdev_status_t kdev_flash_power_control(ARM_POWER_STATE state) +* @brief Power handling for spi flasg. +* @param[in] state Power state +* @return @ref kdev_status_t +*/ +kdev_status_t kdev_flash_power_control(ARM_POWER_STATE state); +/** +* @fn kdev_status_t kdev_flash_readdata(uint32_t addr, void *data, uint32_t cnt) +* @brief Read data from specific index of spi flash. +* @param[in] addr Data address. +* @param[out] data Pointer to a buffer storing the data read from Flash. +* @param[in] cnt Number of data items to read. +* @return number of data items read or @ref kdev_status_t +*/ +kdev_status_t kdev_flash_readdata(uint32_t addr, void *data, uint32_t cnt); +/** +* @fn void kdev_flash_read(uint8_t type, uint32_t offset, uint32_t len, void *buf) +* @brief Read data from specific index of spi flash. +* @param[in] type SPI operation type: standard/Dual/Quad mode. +* @param[in] offset Data address. +* @param[in] len Number of data items to read. +* @param[out] data Pointer to a buffer storing the data read from Flash. +* @return N/A +*/ +uint32_t kdev_flash_read_compare(uint8_t type, uint32_t offset, uint32_t len, void *buf); +void kdev_flash_read(uint8_t type, uint32_t offset, uint32_t len, void *buf); +/** +* @fn kdev_status_t kdev_flash_programdata (uint32_t addr, const void *data, uint32_t cnt) +* @brief Program data to specific index in spi flash +* @param[in] addr Data address. +* @param[in] data Pointer to a buffer containing the data to be programmed to Flash. +* @param[in] cnt Number of data items to program. +* @return number of data items programmed or @ref kdev_status_t +*/ +kdev_status_t kdev_flash_programdata (uint32_t addr, const void *data, uint32_t cnt); +void kdev_flash_write(uint8_t type, uint32_t offset, uint32_t len, void *buf, uint32_t buf_offset); +/** +* @fn kdev_status_t kdev_flash_programdata (uint32_t addr, const void *data, uint32_t cnt) +* @brief Program data to specific index in spi flash +* @param[in] addr Data address. +* @param[in] data Pointer to a buffer containing the data to be programmed to Flash. +* @param[in] cnt Number of data items to program. +* @return number of data items programmed or @ref kdev_status_t +*/ +kdev_status_t kdev_flash_programdata_memxfer(uint32_t addr, const void *data, uint32_t cnt); +/** +* @fn kdev_status_t kdev_flash_erase_sector(uint32_t addr) +* @brief Erase Flash by Sector(4k bytes). +* @param[in] addr Sector address +* @return @ref kdev_status_t +*/ +kdev_status_t kdev_flash_erase_sector(uint32_t addr); +/** +* @fn kdev_status_t kdev_flash_erase_multi_sector(uint32_t start_addr, uint32_t end_addr) +* @brief Erase multiple Flash Sectors(continuously). +* @param[in] addr Sector start address +* @param[in] addr Sector end address +* @return @ref kdev_status_t +*/ +kdev_status_t kdev_flash_erase_multi_sector(uint32_t start_addr, uint32_t end_addr); +/** +* @fn kdev_status_t kdev_flash_erase_chip(void) +* @brief Erase whole Flash at once. + Optional function for faster full chip erase. +* @return @ref kdev_status_t +*/ +kdev_status_t kdev_flash_erase_chip(void); +/** +* @fn kdev_flash_status_t kdev_flash_get_status(void) +* @brief Get Flash status. +* @return Flash status @ref kdev_flash_status_t +*/ +kdev_flash_status_t kdev_flash_get_status(void); +/** +* @fn kdev_status_t kdev_flash_get_info(void) +* @brief Get Flash information. +* @return @ref kdev_status_t +*/ +kdev_status_t kdev_flash_get_info(void); +/** +* @fn void kdev_flash_64kErase(uint32_t offset) +* @brief Block Erase to erase Flash 64K-bytes at once. + The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all FFh.. +* @param[in] offset Sector start address +* @return N/A +*/ +void kdev_flash_64kErase(uint32_t offset); +/** +* @fn void kdev_flash_64kErase(uint32_t offset) +* @brief Sector Erase to erase Flash 4K-bytes at once. + The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all FFh.. +* @param[in] offset Sector start address +* @return N/A +*/ +void kdev_flash_4kErase(uint32_t offset); + +#if FLASH_4BYTES_CMD_EN +bool kdev_flash_is_4byte_address(uint32_t address); +#endif +#endif /* __KDEV_FLASH_H */ +/** @}*/ diff --git a/platform/dev/include/kdev_flash_gd.h b/platform/dev/include/kdev_flash_gd.h new file mode 100644 index 0000000..b232ede --- /dev/null +++ b/platform/dev/include/kdev_flash_gd.h @@ -0,0 +1,56 @@ +#ifndef __KDEV_FLASH_GD_H__ +#define __KDEV_FLASH_GD_H__ + +#include "kdev_flash.h" + +/******************************************* + * for spi flash id definition + ********************************************/ +#define FLASH_WB_DEV 0xEF +#define FLASH_GD_DEV 0xC8 +#define FLASH_MXIC_DEV 0xC2 +#define FLASH_Micron_DEV 0x20 +#define FLASH_ZBIT_DEV 0x5E + +#define FLASH_IS_WB_DEV(x) ((x>>16)&0xFF == FLASH_WB_DEV) +#define FLASH_IS_MXIC_DEV(x) ((x>>16)&0xFF == FLASH_MXIC_DEV) +#define FLASH_IS_GD_DEV(x) ((x>>16)&0xFF == FLASH_GD_DEV) + +#define WB_W25Q01JV_ID 0x2140 //1G +#define WB_W25Q512JV_ID 0x2040 //512M bit +#define WB_W25L256JV_ID 0x1940 //256M bit +#define WB_W25Q128BVFG_ID 0x1840 //128M bit +#define WB_W25Q64CV_ID_9F 0x1740 +#define WB_W25Q32CV_ID_9F 0x1640 +#define WB_W25P80_ID_9F 0x1420 //8M bit +#define WB_W25P16_ID_9F 0x1520 //16M bit +#define WB_W25P32_ID_9F 0x1620 //32M bit +#define WB_W25P16_ID_90 0x14 +#define MX_MX25L51245G 0x1A20 +#define MX_MX25L25645G 0x1920 +#define MX_MX25L12845EM1 0x1820 +#define MX_MX25L6405D 0x1720 +#define GD_GD25Q64CSIG_ID 0x1740 +#define GD_GD25Q127CSIG_ID 0x1840 +#define GD_GD25Q256_ID 0x1940 +#define GD_GD25Q256_ID_9F 0x1940 +#define GD25Q512MC_ID_9F 0x2040 + +#define INVALID_CHIP_ID 0xFFFF +#define INVALID_MANU_ID 0xFF + +#define FLASH_SIZE_32MB_ID 0x19 +#define FLASH_SIZE_16MB_ID 0x18 +#define FLASH_SIZE_8MB_ID 0x17 +#define FLASH_SIZE_4MB_ID 0x16 +#define FLASH_SIZE_2MB_ID 0x15 +#define FLASH_SIZE_1MB_ID 0x14 +#define FLASH_SIZE_512MB_ID 0x20 +#define FLASH_SIZE_SHIFT (FLASH_SIZE_512MB_ID - 0x1A) + +#define FLASH_3BYTE_ADDR_MAX 0x00FFFFFF //16Mbytes +/******************************************* + * for function prototype definition + ********************************************/ +#endif/* __KDEV_FLASH_GD_H__ */ + diff --git a/platform/dev/include/kdev_flash_mxic.h b/platform/dev/include/kdev_flash_mxic.h new file mode 100644 index 0000000..d12faae --- /dev/null +++ b/platform/dev/include/kdev_flash_mxic.h @@ -0,0 +1,56 @@ +#ifndef __KDEV_FLASH_MXIC_H__ +#define __KDEV_FLASH_MXIC_H__ + +#include "kdev_flash.h" + +/******************************************* + * for spi flash id definition + ********************************************/ +#define FLASH_WB_DEV 0xEF +#define FLASH_GD_DEV 0xC8 +#define FLASH_MXIC_DEV 0xC2 +#define FLASH_Micron_DEV 0x20 +#define FLASH_ZBIT_DEV 0x5E + +#define FLASH_IS_WB_DEV(x) ((x>>16)&0xFF == FLASH_WB_DEV) +#define FLASH_IS_MXIC_DEV(x) ((x>>16)&0xFF == FLASH_MXIC_DEV) +#define FLASH_IS_GD_DEV(x) ((x>>16)&0xFF == FLASH_GD_DEV) + +#define WB_W25Q01JV_ID 0x2140 //1G +#define WB_W25Q512JV_ID 0x2040 //512M bit +#define WB_W25L256JV_ID 0x1940 //256M bit +#define WB_W25Q128BVFG_ID 0x1840 //128M bit +#define WB_W25Q64CV_ID_9F 0x1740 +#define WB_W25Q32CV_ID_9F 0x1640 +#define WB_W25P80_ID_9F 0x1420 //8M bit +#define WB_W25P16_ID_9F 0x1520 //16M bit +#define WB_W25P32_ID_9F 0x1620 //32M bit +#define WB_W25P16_ID_90 0x14 +#define MX_MX25L51245G 0x1A20 +#define MX_MX25L25645G 0x1920 +#define MX_MX25L12845EM1 0x1820 +#define MX_MX25L6405D 0x1720 +#define GD_GD25Q64CSIG_ID 0x1740 +#define GD_GD25Q127CSIG_ID 0x1840 +#define GD_GD25Q256_ID 0x1940 +#define GD_GD25Q256_ID_9F 0x1940 +#define GD25Q512MC_ID_9F 0x2040 + +#define INVALID_CHIP_ID 0xFFFF +#define INVALID_MANU_ID 0xFF + +#define FLASH_SIZE_32MB_ID 0x19 +#define FLASH_SIZE_16MB_ID 0x18 +#define FLASH_SIZE_8MB_ID 0x17 +#define FLASH_SIZE_4MB_ID 0x16 +#define FLASH_SIZE_2MB_ID 0x15 +#define FLASH_SIZE_1MB_ID 0x14 +#define FLASH_SIZE_512MB_ID 0x20 +#define FLASH_SIZE_SHIFT (FLASH_SIZE_512MB_ID - 0x1A) + +#define FLASH_3BYTE_ADDR_MAX 0x00FFFFFF //16Mbytes +/******************************************* + * for function prototype definition + ********************************************/ +#endif/* __KDEV_FLASH_MXIC_H__ */ + diff --git a/platform/dev/include/kdev_flash_null.h b/platform/dev/include/kdev_flash_null.h new file mode 100644 index 0000000..4dffdb7 --- /dev/null +++ b/platform/dev/include/kdev_flash_null.h @@ -0,0 +1,86 @@ +#ifndef _KDEV_FLASH_NULL_H_ +#define _KDEV_FLASH_NULL_H_ + +#include "Driver_Common.h" +#include "kdev_status.h" + +typedef struct { + uint32_t busy : 1; /**< Flash busy flag */ + uint32_t error : 1; /**< Read/Program/Erase error flag (cleared on start of next operation) */ +} kdev_flash_status_t; + +bool bGigaDeive_Fseries=0; + +__weak kdev_status_t kdev_flash_initialize(void) +{ + return KDEV_STATUS_OK; +} + +__weak kdev_status_t kdev_flash_uninitialize(void) +{ + return KDEV_STATUS_OK; +} + +__weak kdev_status_t kdev_flash_power_control(ARM_POWER_STATE state) +{ + return KDEV_STATUS_OK; +} + +__weak kdev_status_t kdev_flash_readdata(uint32_t addr, void *data, uint32_t cnt) +{ + return KDEV_STATUS_OK; +} + +__weak void kdev_flash_read(uint8_t type, uint32_t offset, uint32_t len, void *buf) +{ +} + +__weak kdev_status_t kdev_flash_programdata (uint32_t addr, const void *data, uint32_t cnt) +{ + return KDEV_STATUS_OK; +} + +__weak void kdev_flash_write(uint8_t type, uint32_t offset, uint32_t len, void *buf, uint32_t buf_offset) +{ +} + +__weak kdev_status_t kdev_flash_programdata_memxfer(uint32_t addr, const void *data, uint32_t cnt) +{ + return KDEV_STATUS_OK; +} + +__weak kdev_status_t kdev_flash_erase_sector(uint32_t addr) +{ + return KDEV_STATUS_OK; +} + +__weak kdev_status_t kdev_flash_erase_multi_sector(uint32_t start_addr, uint32_t end_addr) +{ + return KDEV_STATUS_OK; +} + +__weak kdev_status_t kdev_flash_erase_chip(void) +{ + return KDEV_STATUS_OK; +} + +__weak kdev_flash_status_t kdev_flash_get_status(void) +{ + kdev_flash_status_t tt; + return tt; +} + +__weak kdev_status_t kdev_flash_get_info(void) +{ + return KDEV_STATUS_OK; +} + +__weak void kdev_flash_128kErase(uint32_t offset) +{ +} + +__weak kdev_status_t kdev_memxfer_flash_to_ddr(uint32_t dst, uint32_t src, size_t bytes, uint8_t mode) +{ + return KDEV_STATUS_OK; +} +#endif diff --git a/platform/dev/include/kdev_flash_winbond.h b/platform/dev/include/kdev_flash_winbond.h new file mode 100644 index 0000000..8635020 --- /dev/null +++ b/platform/dev/include/kdev_flash_winbond.h @@ -0,0 +1,56 @@ +#ifndef __KDEV_FLASH_WINBOND_H__ +#define __KDEV_FLASH_WINBOND_H__ + +#include "kdev_flash.h" + +/******************************************* + * for spi flash id definition + ********************************************/ +#define FLASH_WB_DEV 0xEF +#define FLASH_GD_DEV 0xC8 +#define FLASH_MXIC_DEV 0xC2 +#define FLASH_Micron_DEV 0x20 +#define FLASH_ZBIT_DEV 0x5E + +#define FLASH_IS_WB_DEV(x) ((x>>16)&0xFF == FLASH_WB_DEV) +#define FLASH_IS_MXIC_DEV(x) ((x>>16)&0xFF == FLASH_MXIC_DEV) +#define FLASH_IS_GD_DEV(x) ((x>>16)&0xFF == FLASH_GD_DEV) + +#define WB_W25Q01JV_ID 0x2140 //1G +#define WB_W25Q512JV_ID 0x2040 //512M bit +#define WB_W25L256JV_ID 0x1940 //256M bit +#define WB_W25Q128BVFG_ID 0x1840 //128M bit +#define WB_W25Q64CV_ID_9F 0x1740 +#define WB_W25Q32CV_ID_9F 0x1640 +#define WB_W25P80_ID_9F 0x1420 //8M bit +#define WB_W25P16_ID_9F 0x1520 //16M bit +#define WB_W25P32_ID_9F 0x1620 //32M bit +#define WB_W25P16_ID_90 0x14 +#define MX_MX25L51245G 0x1A20 +#define MX_MX25L25645G 0x1920 +#define MX_MX25L12845EM1 0x1820 +#define MX_MX25L6405D 0x1720 +#define GD_GD25Q64CSIG_ID 0x1740 +#define GD_GD25Q127CSIG_ID 0x1840 +#define GD_GD25Q256_ID 0x1940 +#define GD_GD25Q256_ID_9F 0x1940 +#define GD25Q512MC_ID_9F 0x2040 + +#define INVALID_CHIP_ID 0xFFFF +#define INVALID_MANU_ID 0xFF + +#define FLASH_SIZE_32MB_ID 0x19 +#define FLASH_SIZE_16MB_ID 0x18 +#define FLASH_SIZE_8MB_ID 0x17 +#define FLASH_SIZE_4MB_ID 0x16 +#define FLASH_SIZE_2MB_ID 0x15 +#define FLASH_SIZE_1MB_ID 0x14 +#define FLASH_SIZE_512MB_ID 0x20 +#define FLASH_SIZE_SHIFT (FLASH_SIZE_512MB_ID - 0x1A) + +#define FLASH_3BYTE_ADDR_MAX 0x00FFFFFF //16Mbytes +/******************************************* + * for function prototype definition + ********************************************/ +#endif/* __KDEV_FLASH_WINBOND_H__ */ + diff --git a/platform/dev/include/kdev_panel.h b/platform/dev/include/kdev_panel.h new file mode 100644 index 0000000..43e8e3d --- /dev/null +++ b/platform/dev/include/kdev_panel.h @@ -0,0 +1,43 @@ +/******************************************************************** +* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. +* +* The information contained herein is property of Kneron, Inc. +* Terms and conditions of usage are described in detail in Kneron +* STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. +* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed +* from the file. +********************************************************************/ + +/**@addtogroup KDEV_PANEL KDEV_PANEL +* @{ +* @brief Kneron panel device interface for MZT_480x272 and ST778_240x320 driver +* +* @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. +*/ + +#ifndef __KDEV_PANEL_H__ +#define __KDEV_PANEL_H__ + +#include "kdrv_display.h" +#include "kdev_status.h" + +/** + * @brief Initializes kdev panel driver + * + * @param[in] display_drv see @ref kdrv_display_t + * @return kdrv_status_t see @ref kdrv_status_t + * + * @note This API MUST be called before using the Read/write APIs for I2C. + */ +kdev_status_t kdev_panel_initialize(kdrv_display_t *display_drv); + +kdev_status_t kdev_panel_clear(kdrv_display_t *display_drv, u32 color); + +uint16_t kdev_panel_read_display_id(kdrv_display_t *display_drv); + +kdev_status_t kdev_panel_refresh(kdrv_display_t* display_drv); + +#endif /* __KDEV_PANEL_H__ */ +/** @}*/ diff --git a/platform/dev/include/kdev_sensor.h b/platform/dev/include/kdev_sensor.h new file mode 100644 index 0000000..97554e4 --- /dev/null +++ b/platform/dev/include/kdev_sensor.h @@ -0,0 +1,44 @@ +/******************************************************************** +* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. +* +* The information contained herein is property of Kneron, Inc. +* Terms and conditions of usage are described in detail in Kneron +* STANDARD SOFTWARE LICENSE AGREEMENT. +* +* Licensees are granted free, non-transferable use of the information. +* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed +* from the file. +********************************************************************/ + +/**@addtogroup KDEV_SENSOR KDEV_SENSOR +* @{ +* @brief Kneron sensor device interface +* +* @copyright Copyright (C) 2020 Kneron, Inc. All rights reserved. +*/ + +#ifndef __KDEV_SENSOR_H__ +#define __KDEV_SENSOR_H__ + +#include "kdev_status.h" +#include "kmdw_sensor.h" + +struct sensor_ops { + kdev_status_t (*s_power) (uint32_t on); + kdev_status_t (*reset) (void); + kdev_status_t (*s_stream) (uint32_t enable); + kdev_status_t (*enum_fmt) (uint32_t index, uint32_t *fourcc); + kdev_status_t (*get_fmt) (struct cam_format *format); + kdev_status_t (*set_fmt) (struct cam_format *format); + kdev_status_t (*set_gain) (uint32_t gain1, uint32_t gain2); + kdev_status_t (*set_aec) (struct cam_sensor_aec *aec_p); + kdev_status_t (*set_exp_time)(uint32_t gain1, uint32_t gain2); + kdev_status_t (*get_lux) (uint16_t *expo, uint8_t *pre_gain, uint8_t *post_gain, uint8_t *global_gain, uint8_t *y_average); + kdev_status_t (*led_switch) (uint32_t on); + kdev_status_t (*set_mirror) (uint32_t enable); + kdev_status_t (*set_flip) (uint32_t enable); + uint32_t (*get_dev_id) (void); +}; + +#endif /* __KDEV_SENSOR_H__ */ +/** @}*/ diff --git a/platform/dev/include/kdev_status.h b/platform/dev/include/kdev_status.h new file mode 100644 index 0000000..3094bb1 --- /dev/null +++ b/platform/dev/include/kdev_status.h @@ -0,0 +1,23 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#ifndef __KDEV_STATUS_H__ +#define __KDEV_STATUS_H__ + +#include // for type 'bool', ture and false. +typedef enum +{ + KDEV_STATUS_OK = 0, /**< driver status OK */ + KDEV_STATUS_ERROR, /**< driver status error */ +} kdev_status_t; + +#endif /* __KDEV_STATUS_H__ */ diff --git a/platform/dev/include/utility.h b/platform/dev/include/utility.h new file mode 100644 index 0000000..c7bb846 --- /dev/null +++ b/platform/dev/include/utility.h @@ -0,0 +1,69 @@ +#ifndef UTILITY_H +#define UTILITY_H + + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "base.h" + +#define CMDLEN 50 +#define MAXARGS 20 + +#define divRoundDown(n,s) ((n) / (s)) +#define divRoundUp(n,s) ((n+s-1)/(s)) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) + +#define RoundUp(val, units) \ + ((((unsigned long)(val) + ((units) - 1)) / (units)) * (units)) +#define RoundDown(val, units) \ + (((unsigned long)(val)/(units))*(units)) + + +#define REG32(adr) *(volatile u32 *)(adr) +#define Min(a,b) (((a) < (b)) ? (a) : (b)) +#define Max(a,b) (((a) > (b)) ? (a) : (b)) + +#ifndef isblank +#define isblank(ch) (((ch) == ' ') || ((ch) == '\t')) +#endif + +int substring(char **ptr, char *string, char *pattern); +unsigned int atonum(char *val_str); + + +struct burnin_cmd +{ + char *string; /* command name */ + void (*burnin_routine)(); /* implementing routine */ +}; + +typedef struct cmd { //bessel:move from Drvftsdc021.h + s8 *name; + s8 *usage; + //bessel:For IAR, it's a error "a value of type "Us16 (*)(Us32, s8 **)" cannot be used to initialize an entity of type "s32 (*)(s32, s8 **)" + u16(*func) (u32 argc, s8 ** argv);// s32(*func) (s32 argc, s8 ** argv); +} cmd_t; + +extern int substring(char **ptr, char *string, char *pattern); +extern unsigned int atonum(char *val_str); +extern u32 get_dex(void); +extern void PrintWelcomeMsg(struct burnin_cmd * cmd, int col_width); +extern void ManualTesting(struct burnin_cmd * cmd, int col_width, int have_back); +extern void mem_dump(unsigned int addr, int size); +extern void DumpData(u8 *pp, u16 start_addr, u32 size); +extern u32 makeargs(s8 * cmd, s32 * argcptr, s8 *** argvptr); +extern s32 do_help(s32 argc, s8 ** argv,cmd_t *input_CmdTbl); +extern u32 ExecCmd(s8 * cmdline,cmd_t *input_CmdTbl); +extern unsigned int atonum(char *val_str); + +#ifdef __cplusplus +} +#endif + + + +#endif diff --git a/platform/dev/panel/kdev_mzt_480x272.c b/platform/dev/panel/kdev_mzt_480x272.c new file mode 100644 index 0000000..b6a80d6 --- /dev/null +++ b/platform/dev/panel/kdev_mzt_480x272.c @@ -0,0 +1,70 @@ +/* + * Kneron MZT Display Panel driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ +#include "kdev_panel.h" +#include "kdrv_lcdc.h" + +#ifdef KDP_UVC +#define MZT_PANEL_WIDTH 640 +#define MZT_PANEL_HEIGHT 800 +#else +#define MZT_PANEL_WIDTH TFT43_WIDTH +#define MZT_PANEL_HEIGHT TFT43_HEIGHT +#endif + +kdev_status_t kdev_panel_initialize(kdrv_display_t *display_drv) +{ + if(display_drv == NULL) + return KDEV_STATUS_ERROR; + + u16 hor_no_in = display_drv->vi_params.input_xres; + u16 ver_no_in = display_drv->vi_params.input_yres; + u16 hor_no_out = MZT_PANEL_WIDTH; + u16 ver_no_out = MZT_PANEL_HEIGHT; + + kdrv_lcdc_set_panel_type(KDRV_LCDC_6BIT_PER_CHANNEL); + kdrv_lcdc_set_bgrsw(KDRV_LCDC_OUTPUT_FMT_RGB); + + //serial panel pixel + kdrv_lcdc_set_auo052_mode(KDRV_LCDC_AUO052_OFF); + kdrv_lcdc_set_pixel_sr(KDRV_LCDC_SERIAL_PIX_RSR); + kdrv_lcdc_set_pixel_colorseq(KDRV_LCDC_SERIAL_PIX_COLORSEQ_GBR); + kdrv_lcdc_set_pixel_delta_type(KDRV_LCDC_SERIAL_PIX_DELTA_TYPE_SAME_SEQ); + kdrv_lcdc_set_pixel_serial_mode(KDRV_LCDC_SERIAL_PIX_RGB_PARALLEL_OUTPUT); + + kdrv_lcdc_set_framerate(60, hor_no_out, ver_no_out); + kdrv_lcdc_set_endian(KDRV_LCDC_FB_DATA_ENDIAN_LBLP); + kdrv_lcdc_set_image_color_params(0x2000, 0x2000, 0x0, 0x40000); + kdrv_lcdc_set_frame_buffer(0x00); + kdrv_lcdc_set_bus_bandwidth_ctrl(0x00); + kdrv_lcdc_down_scale(hor_no_in, hor_no_out, ver_no_in, ver_no_out); + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_panel_clear(kdrv_display_t *display_drv, u32 color) +{ + if(display_drv == NULL) + return KDEV_STATUS_ERROR; + + return KDEV_STATUS_OK; +} + +uint16_t kdev_panel_read_display_id(kdrv_display_t *display_drv) +{ + if(display_drv == NULL) + return 0xFFFF; + + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_panel_refresh(kdrv_display_t* display_drv) +{ + if(display_drv == NULL) + return KDEV_STATUS_ERROR; + + return KDEV_STATUS_OK; +} + diff --git a/platform/dev/panel/kdev_st7789_240x320.c b/platform/dev/panel/kdev_st7789_240x320.c new file mode 100644 index 0000000..c1b077e --- /dev/null +++ b/platform/dev/panel/kdev_st7789_240x320.c @@ -0,0 +1,382 @@ +/* + * KDP ST7789 Panel driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include "kdrv_gdma.h" +#include "kdrv_display.h" +#include "kdrv_lcm.h" +#include "kdrv_pwm.h" +#include "kl520_include.h" +#include "kdev_status.h" + + +osMutexId_t mutex_st7789 = NULL; +osMutexId_t mutex_snapshot = NULL; + +#define TE_ENABLE +#define PORTRAIT_DMA_ENABLE + +#define FRAME_RATE_60HZ 0 +#define FRAME_RATE_39HZ 1 +#define FRAME_RATE_CTRL FRAME_RATE_60HZ + +#define RAM_ENDIAN_MSB 0 +#define RAM_ENDIAN_LSB 1 +#define RAM_ENDIAN_TYPE RAM_ENDIAN_MSB + + +/* +This command is used to transfer data from MCU to frame memory. +-When this command is accepted, the column register and the page register are reset to the start column/start +page positions. +-The start column/start page positions are different in accordance with MADCTL setting. +-Sending any other command can stop frame write. +*/ +#define PANEL_REG_RAMWR 0x2C //Memory write +#define PANEL_REG_WRMEMC 0x3C //Write memory continue + +//#define ST7789_LANDSCAPE +#define ST7789_PORTRAIT + +#ifdef ST7789_PORTRAIT + //#define ST7789_PORTRAIT_PARTIAL + //#define ZOOM_IN_RATIO 3/2 +#endif + +#ifdef ST7789_LANDSCAPE +#define ST7789_PANEL_WIDTH QVGA_LANDSCAPE_WIDTH +#define ST7789_PANEL_HEIGHT QVGA_LANDSCAPE_HEIGHT +#else +#define ST7789_PANEL_WIDTH QVGA_PORTRAIT_WIDTH +#define ST7789_PANEL_HEIGHT QVGA_PORTRAIT_HEIGHT +#endif +#define ST7789_PANEL_TOTAL_PIXEL ST7789_PANEL_WIDTH * ST7789_PANEL_HEIGHT +#define OPEN_DOWN_SCALING +#define BYTES_PER_PIXEL 2 + +#ifdef PORTRAIT_DMA_ENABLE +#undef TE_ENABLE +#undef FRAME_RATE_CTRL +#undef RAM_ENDIAN_TYPE + +#define FRAME_RATE_CTRL FRAME_RATE_39HZ +#define RAM_ENDIAN_TYPE RAM_ENDIAN_LSB +#define TE_ENABLE + +#endif + +kdev_status_t kdev_panel_initialize(kdrv_display_t *display_drv) +{ + if(display_drv == NULL) + return KDEV_STATUS_ERROR; + + if(mutex_st7789 == NULL) + mutex_st7789 = osMutexNew(NULL); + + if(mutex_snapshot == NULL) + mutex_snapshot = osMutexNew(NULL); + + uint32_t base = display_drv->base; +// u16 hor_no_in = display_drv->vi_params.input_xres; +// u16 ver_no_in = display_drv->vi_params.input_yres; +// u16 hor_no_out = ST7789_PANEL_WIDTH;//MZT_PANEL_WIDTH; +// u16 ver_no_out = ST7789_PANEL_HEIGHT;//MZT_PANEL_HEIGHT; +// DSG("[%s] hor_no_in=%u ver_no_in=%u hor_no_out=%u ver_no_out=%u", +// __func__, hor_no_in, ver_no_in, hor_no_out, ver_no_out); + + kdrv_lcm_write_cmd(base, 0x11); //Exit Sleep + //kdrv_delay_us(100); + kdrv_pwmtimer_delay_ms(10); + + //-----------Display and color format setting-------------// + // Column Address Set + kdrv_lcm_write_cmd(base, 0x2A); + // XS + kdrv_lcm_write_data(base, 0x00); + kdrv_lcm_write_data(base, 0x00); + // XE +#ifdef ST7789_LANDSCAPE + kdrv_lcm_write_data(base, 0x01); + kdrv_lcm_write_data(base, 0x3F); +#else + kdrv_lcm_write_data(base, 0x00); + kdrv_lcm_write_data(base, 0xEF); +#endif + + // Row Address Set + kdrv_lcm_write_cmd(base, 0x2B); +#ifdef ST7789_LANDSCAPE + // YS + kdrv_lcm_write_data(base, 0x00); + kdrv_lcm_write_data(base, 0x00); + // YE + kdrv_lcm_write_data(base, 0x00); + kdrv_lcm_write_data(base, 0xEF); +#else + #ifdef ST7789_PORTRAIT_PARTIAL + // YS + kdrv_lcm_write_data(base, 0x00); + kdrv_lcm_write_data(base, 0x40); + // YE + kdrv_lcm_write_data(base, 0x01); + kdrv_lcm_write_data(base, 0x00); + #else + // YS + kdrv_lcm_write_data(base, 0x00); + kdrv_lcm_write_data(base, 0x00); + // YE + kdrv_lcm_write_data(base, 0x01); + kdrv_lcm_write_data(base, 0x3F); + #endif +#endif + +#ifdef ST7789_PORTRAIT_PARTIAL + kdrv_lcm_write_cmd(base, 0x13); + kdrv_lcm_write_data(base, 0x00); + kdrv_lcm_write_cmd(base, 0x12); + kdrv_lcm_write_data(base, 0xFF); + kdrv_lcm_write_cmd(base, 0x30); + kdrv_lcm_write_data(base, 0x00); + kdrv_lcm_write_data(base, 0x40); + kdrv_lcm_write_data(base, 0x01); + kdrv_lcm_write_data(base, 0x00); +#endif + +#ifdef TE_ENABLE + kdrv_lcm_write_cmd(base, 0x35); // Enable Tearing effect + kdrv_lcm_write_data(base, 0x00); +#endif + + kdrv_lcm_write_cmd(base, 0x36); // Memory Access Control +#ifdef ST7789_LANDSCAPE + // xy_exchange / y_inverse + //(Rotate positive 90 degrees) + //MY = 1, MX = 0, MV = 1, ML = 0 + kdrv_lcm_write_data(base, 0xA0); +#else + //MY = 1, MX = 1, MV = 0, ML = 0 + //0820,Tei/Jeff + { + //ops->write_data(base, 0x40); //image from camera + kdrv_lcm_write_data(base, 0x00); //image from flash + } +#endif + + // Interface Pixel Format + kdrv_lcm_write_cmd(base, 0x3a);//DPI=101 16bit RGB + kdrv_lcm_write_data(base, 0x55); + //ops->write_data(base, 0x05); + //-------------ST7789V Porch setting-----------// + kdrv_lcm_write_cmd(base, 0xb2); + kdrv_lcm_write_data(base, 0x0C); // Back porch (normal) + kdrv_lcm_write_data(base, 0x0C); // Front porch (normal) + kdrv_lcm_write_data(base, 0x00); // + kdrv_lcm_write_data(base, 0X33); // Back porch (idle) + Front porch (idle) + kdrv_lcm_write_data(base, 0X33); // Back porch (partial) + Front porch (partial) + + // Gate Control. 13.26, -10.43 + kdrv_lcm_write_cmd(base, 0xb7); + kdrv_lcm_write_data(base, 0x35);//(0x71); + + //Setting limitation: VCOMS+VCOMS offset+VDV=0.1V~1.675V. + // VCOMS Setting. used for feed through voltage compensation + // 1.175V + kdrv_lcm_write_cmd(base, 0xBB); + kdrv_lcm_write_data(base, 0x2b);//(0x25); + + // LCM Control ??? + kdrv_lcm_write_cmd(base, 0xC0); + kdrv_lcm_write_data(base, 0x2c); + + // VDV and VRH command enable + kdrv_lcm_write_cmd(base, 0xC2); + kdrv_lcm_write_data(base, 0x01); + + // VRH Set + kdrv_lcm_write_cmd(base, 0xC3); + kdrv_lcm_write_data(base, 0x11);//(0X14);// + + // VDVS Set + kdrv_lcm_write_cmd(base, 0xC4); + kdrv_lcm_write_data(base, 0x20); // 0 + + // Frame rate control in normal mode +#if FRAME_RATE_CTRL == FRAME_RATE_60HZ + kdrv_lcm_write_cmd(base, 0xC6); + kdrv_lcm_write_data(base, 0x0F); +#elif FRAME_RATE_CTRL == FRAME_RATE_39HZ + kdrv_lcm_write_cmd(base, 0xC6); + kdrv_lcm_write_data(base, 0x1F); +#endif + + // Power Control 1 + kdrv_lcm_write_cmd(base, 0xd0); + kdrv_lcm_write_data(base, 0xa4); + kdrv_lcm_write_data(base, 0xa1); // AVDD : 6.8V, AVCL : -4.6V, VDDS : 2.3 V + + //---------------ST7789V gamma setting-------------// + { // Positive Voltage gamma control + kdrv_lcm_write_cmd(base, 0xE0); + kdrv_lcm_write_data(base, 0xd0); + kdrv_lcm_write_data(base, 0x08); + kdrv_lcm_write_data(base, 0x0e); + kdrv_lcm_write_data(base, 0x0a); + kdrv_lcm_write_data(base, 0x0a); + kdrv_lcm_write_data(base, 0x06); + kdrv_lcm_write_data(base, 0x38); + kdrv_lcm_write_data(base, 0x44); + kdrv_lcm_write_data(base, 0x50); + kdrv_lcm_write_data(base, 0x29); + kdrv_lcm_write_data(base, 0x15); + kdrv_lcm_write_data(base, 0x16); + kdrv_lcm_write_data(base, 0x33); + kdrv_lcm_write_data(base, 0x36); + } + { // Negative Boltage gamma control + kdrv_lcm_write_cmd(base, 0XE1); + kdrv_lcm_write_data(base, 0xd0); + kdrv_lcm_write_data(base, 0x07); + kdrv_lcm_write_data(base, 0x0d); + kdrv_lcm_write_data(base, 0x09); + kdrv_lcm_write_data(base, 0x08); + kdrv_lcm_write_data(base, 0x06); + kdrv_lcm_write_data(base, 0x33); + kdrv_lcm_write_data(base, 0x33); + kdrv_lcm_write_data(base, 0x4d); + kdrv_lcm_write_data(base, 0x28); + kdrv_lcm_write_data(base, 0x16); + kdrv_lcm_write_data(base, 0x15); + kdrv_lcm_write_data(base, 0x33); + kdrv_lcm_write_data(base, 0x35); + } + + kdrv_lcm_write_cmd(base, 0x21); // Display Inversion On ?? + + // RAM Control +#if RAM_ENDIAN_TYPE == RAM_ENDIAN_MSB + kdrv_lcm_write_cmd(base, 0xB0); + kdrv_lcm_write_data(base, 0x00); // Ram access from MCU interface + kdrv_lcm_write_data(base, 0xd0); // Normal Endian (MSB first), 18 bit bus width +#elif RAM_ENDIAN_TYPE == RAM_ENDIAN_LSB + kdrv_lcm_write_cmd(base, 0xB0); + kdrv_lcm_write_data(base, 0x00); // Ram access from MCU interface + kdrv_lcm_write_data(base, 0xd8); // Normal Endian (MSB first), 18 bit bus width +#endif + + kdrv_lcm_write_cmd(base, 0x29); //Display on + //ops->write_cmd(base, 0x28); //Display off + + //_st7789_240x320_clear(display_drv, YELLOW);//WHITE); + + return KDEV_STATUS_OK; +} + +kdev_status_t kdev_panel_clear(kdrv_display_t *display_drv, u32 color) +{ + int i; + + if(display_drv == NULL) + return KDEV_STATUS_ERROR; + + kdrv_lcm_write_cmd(display_drv->base, PANEL_REG_WRMEMC); + for(i = 0; i < ST7789_PANEL_TOTAL_PIXEL; ++i) + { + kdrv_lcm_write_data(display_drv->base, (u8)((((color & 0xFF00) >>8 ) & 0xFF))); + kdrv_lcm_write_data(display_drv->base, (u8)(color & 0x00FF)); + } + return KDEV_STATUS_OK; +} + +uint16_t kdev_panel_read_display_id(kdrv_display_t *display_drv) +{ + uint32_t base; + uint16_t id = 0; + + if(display_drv == NULL) + return 0xFFFF; + + base = display_drv->base; + + kdrv_lcm_write_cmd(base, 0x04); + id = kdrv_lcm_read_data(base); //dummy read + id = kdrv_lcm_read_data(base); + id = ((kdrv_lcm_read_data(base) & 0xBF) << 8); + id |= kdrv_lcm_read_data(base); + return id; + +} + +kdev_status_t kdev_panel_refresh(kdrv_display_t* display_drv) +{ + uint32_t base; + uint32_t readAddr = kdrv_lcm_get_db_frame(); + uint16_t lcm_w = display_drv->vi_params.input_xres; + +#ifdef ST7789_PORTRAIT_PARTIAL + uint16_t lcm_h = 192;//ST7789_PANEL_HEIGHT; +#else + uint16_t lcm_h = display_drv->vi_params.input_yres; +#endif + + if(display_drv == NULL) + return KDEV_STATUS_ERROR; + + base = display_drv->base; +#if 0//ndef ST7789_PORTRAIT_PARTIAL + //home point : (0, 0) + kdrv_display_write_cmd(base, 0x2A); + kdrv_display_write_data(base, 0x00); + kdrv_display_write_data(base, 0x00); + kdrv_display_write_data(base, 0x00); + kdrv_display_write_data(base, 0xEF); + kdrv_display_write_cmd(base, 0x2B); + kdrv_display_write_data(base, 0x00); + kdrv_display_write_data(base, 0x00); + kdrv_display_write_data(base, 0x01); + kdrv_display_write_data(base, 0x3F); +#endif + osThreadId_t tid = osThreadGetId(); + osPriority_t save_pri = osThreadGetPriority(tid); + + kdrv_lcm_write_cmd(base, PANEL_REG_RAMWR); + + //kdp520_gpio_setedgemode( 1 << GPIO_16, 0); + + //osThreadSetPriority(tid, save_pri+1); + //TODO: (save_pri+1) is dangerous, below workaround is just to remove warning, + // programmer must fix this. + osThreadSetPriority(tid, (osPriority_t)((uint32_t)save_pri+1)); + + //kdp520_gpio_enableint( GPIO_16, GPIO_EDGE, false); + //kdp520_wait_gpio_int(1< +#include "utility.h" +#include "board.h" +#include "kdev_sensor.h" +#include "kdrv_i2c.h" + +//#define GC2145_DBG +#ifdef GC2145_DBG +#define sensor_msg(fmt, ...) info_msg("[%s] " fmt, __func__, ##__VA_ARGS__) +#else +#define sensor_msg(fmt, ...) +#endif + +static const struct sensor_datafmt_info gc2145_colour_fmts[] = { + { PIX_FMT_YCBCR, COLORSPACE_YUV }, + { PIX_FMT_RGB565, COLORSPACE_RGB }, +}; + +static struct sensor_device gc2145_dev = { + .addr = 0x3C, +}; + +struct sensor_init_seq gc2145_init_regs[] = { + //SENSORDB("GC2145MIPI_Sensor_Init"); + // reset : soft_reset, cm_reset, mipi_reset + {0xfe, 0xf0}, + {0xfe, 0xf0}, + {0xfe, 0xf0}, + + //pll / clock + {0xfc, 0x06}, // vpll_en, vpix_en, analog pwd enable=0 + {0xf6, 0x00}, // up_dn : not pull. PWD : pull down + {0xf7, 0x1d}, // PLL_mode1 [7]not dvp, serial_clk_double = 1, clk_double=1, div2_en=0, pll_en=1 + {0xf8, 0x84}, // PLL_mode2 [7]pll_dgdiv_en=1, [5:0]divx4 = 4 + {0xfa, 0x00}, // clk_div_mode [7:4]divide_by : 0, [3:0]clock_duty = 0 + {0xf9, 0x8e}, // regf clk enable, isp all clock enable, serial clk enable, re_lock_pll + {0xf2, 0x00}, + + ///////////////////////////////////////////////// + //////////////////ISP reg////////////////////// + //////////////////////////////////////////////////// + //reset release + {0xfe, 0x00}, + //Exposure : 1250 + {0x03, 0x04}, + {0x04, 0xe2}, + //Row Start + {0x09, 0x00}, + {0x0a, 0x00}, + //Col Start + {0x0b, 0x00}, + {0x0c, 0x00}, + //Window Height : 1216 , 4c0h + {0x0d, 0x04}, + {0x0e, 0xc0}, + //Window Width : 1618 + {0x0f, 0x06}, + {0x10, 0x52}, + + {0x12, 0x2e}, + + {0x17, 0x15}, //bit1: updown or bit0:mirror + {0x18, 0x22}, + {0x19, 0x0e}, + {0x1a, 0x01}, + {0x1b, 0x4b}, + {0x1c, 0x07}, + {0x1d, 0x10}, + {0x1e, 0x88}, + {0x1f, 0x78}, + {0x20, 0x03}, + {0x21, 0x40}, + {0x22, 0xa0}, + {0x24, 0x16}, + {0x25, 0x01}, + {0x26, 0x10}, + {0x2d, 0x60}, + {0x30, 0x01}, + {0x31, 0x90}, + {0x33, 0x06}, + {0x34, 0x01}, + ///////////////////////////////////////////////// + //////////////////ISP reg//////////////////// + ///////////////////////////////////////////////// + {0xfe, 0x00}, + {0x80, 0x7f}, + {0x81, 0x26}, + {0x82, 0xfa}, + {0x83, 0x00}, //special effect + +#if IMGSRC_FORMAT_RGB == IMG_FORMAT_YCBCR + {0x84, 0x02}, +#elif IMGSRC_FORMAT_RGB == IMG_FORMAT_RGB565 + {0x84, 0x06}, // RGB565:6;CbYCrY:0;CrYCbY:1;YCbYcr:2;YCrYcb:3; +#endif + + {0x86, 0x02}, + {0x88, 0x03}, + {0x89, 0x23}, + //{0x89, 0x20}, //eric version + {0x85, 0x08}, + {0x8a, 0x00}, + {0x8b, 0x00}, + {0xb0, 0x55}, + {0xc3, 0x00}, + {0xc4, 0x80}, + {0xc5, 0x90}, + {0xc6, 0x3b}, + {0xc7, 0x46}, + {0xec, 0x06}, + {0xed, 0x04}, + {0xee, 0x60}, + {0xef, 0x90}, + {0xb6, 0x01}, + {0x90, 0x01}, + {0x91, 0x00}, + {0x92, 0x00}, + {0x93, 0x00}, + {0x94, 0x00}, + {0x95, 0x04}, + {0x96, 0xb0}, + {0x97, 0x06}, + {0x98, 0x40}, + ///////////////////////////////////////// + /////////// BLK //////////////////////// + ///////////////////////////////////////// + {0xfe, 0x00}, + {0x40, 0x42}, + {0x41, 0x00}, + {0x43, 0x5b}, + {0x5e, 0x00}, + {0x5f, 0x00}, + {0x60, 0x00}, + {0x61, 0x00}, + {0x62, 0x00}, + {0x63, 0x00}, + {0x64, 0x00}, + {0x65, 0x00}, + {0x66, 0x20}, + {0x67, 0x20}, + {0x68, 0x20}, + {0x69, 0x20}, + {0x76, 0x00}, + {0x6a, 0x08}, + {0x6b, 0x08}, + {0x6c, 0x08}, + {0x6d, 0x08}, + {0x6e, 0x08}, + {0x6f, 0x08}, + {0x70, 0x08}, + {0x71, 0x08}, + {0x76, 0x00}, + {0x72, 0xf0}, + {0x7e, 0x3c}, + {0x7f, 0x00}, + {0xfe, 0x02}, + {0x48, 0x15}, + {0x49, 0x00}, + {0x4b, 0x0b}, + {0xfe, 0x00}, + //////////////////////////////////////// + /////////// AEC //////////////////////// + //////////////////////////////////////// + {0xfe, 0x01}, + {0x01, 0x04}, + {0x02, 0xc0}, + {0x03, 0x04}, + {0x04, 0x90}, + {0x05, 0x30}, + {0x06, 0x90}, + {0x07, 0x30}, + {0x08, 0x80}, + {0x09, 0x00}, + {0x0a, 0x82}, + {0x0b, 0x11}, + {0x0c, 0x10}, + {0x11, 0x10}, + {0x13, 0x7b}, + {0x17, 0x00}, + {0x1c, 0x11}, + {0x1e, 0x61}, + {0x1f, 0x35}, + {0x20, 0x40}, + {0x22, 0x40}, + {0x23, 0x20}, + {0xfe, 0x02}, + {0x0f, 0x04}, + {0xfe, 0x01}, + {0x12, 0x35}, + {0x15, 0xb0}, + {0x10, 0x31}, + {0x3e, 0x28}, + {0x3f, 0xb0}, + {0x40, 0x90}, + {0x41, 0x0f}, + + ///////////////////////////// + //////// INTPEE ///////////// + ///////////////////////////// + {0xfe, 0x02}, + {0x90, 0x6c}, + {0x91, 0x03}, + {0x92, 0xcb}, + {0x94, 0x33}, + {0x95, 0x84}, + {0x97, 0x65}, + {0xa2, 0x11}, + {0xfe, 0x00}, + ///////////////////////////// + //////// DNDD/////////////// + ///////////////////////////// + {0xfe, 0x02}, + {0x80, 0xc1}, + {0x81, 0x08}, + {0x82, 0x05}, + {0x83, 0x08}, + {0x84, 0x0a}, + {0x86, 0xf0}, + {0x87, 0x50}, + {0x88, 0x15}, + {0x89, 0xb0}, + {0x8a, 0x30}, + {0x8b, 0x10}, + ///////////////////////////////////////// + /////////// ASDE //////////////////////// + ///////////////////////////////////////// + {0xfe, 0x01}, + {0x21, 0x04}, + {0xfe, 0x02}, + {0xa3, 0x50}, + {0xa4, 0x20}, + {0xa5, 0x40}, + {0xa6, 0x80}, + {0xab, 0x40}, + {0xae, 0x0c}, + {0xb3, 0x46}, + {0xb4, 0x64}, + {0xb6, 0x38}, + {0xb7, 0x01}, + {0xb9, 0x2b}, + {0x3c, 0x04}, + {0x3d, 0x15}, + {0x4b, 0x06}, + {0x4c, 0x20}, + {0xfe, 0x00}, + ///////////////////////////////////////// + /////////// GAMMA //////////////////////// + ///////////////////////////////////////// + + ///////////////////gamma1//////////////////// + {0xfe, 0x02}, + {0x10, 0x09}, + {0x11, 0x0d}, + {0x12, 0x13}, + {0x13, 0x19}, + {0x14, 0x27}, + {0x15, 0x37}, + {0x16, 0x45}, + {0x17, 0x53}, + {0x18, 0x69}, + {0x19, 0x7d}, + {0x1a, 0x8f}, + {0x1b, 0x9d}, + {0x1c, 0xa9}, + {0x1d, 0xbd}, + {0x1e, 0xcd}, + {0x1f, 0xd9}, + {0x20, 0xe3}, + {0x21, 0xea}, + {0x22, 0xef}, + {0x23, 0xf5}, + {0x24, 0xf9}, + {0x25, 0xff}, + + {0xfe, 0x00}, + {0xc6, 0x20}, + {0xc7, 0x2b}, + ///////////////////gamma2//////////////////// + {0xfe, 0x02}, + {0x26, 0x0f}, + {0x27, 0x14}, + {0x28, 0x19}, + {0x29, 0x1e}, + {0x2a, 0x27}, + {0x2b, 0x33}, + {0x2c, 0x3b}, + {0x2d, 0x45}, + {0x2e, 0x59}, + {0x2f, 0x69}, + {0x30, 0x7c}, + {0x31, 0x89}, + {0x32, 0x98}, + {0x33, 0xae}, + {0x34, 0xc0}, + {0x35, 0xcf}, + {0x36, 0xda}, + {0x37, 0xe2}, + {0x38, 0xe9}, + {0x39, 0xf3}, + {0x3a, 0xf9}, + {0x3b, 0xff}, + /////////////////////////////////////////////// + ///////////YCP /////////////////////// + /////////////////////////////////////////////// + {0xfe, 0x02}, + {0xd1, 0x32}, + {0xd2, 0x32}, + {0xd3, 0x40}, + {0xd6, 0xf0}, + {0xd7, 0x10}, + {0xd8, 0xda}, + {0xdd, 0x14}, + {0xde, 0x86}, + {0xed, 0x80}, + {0xee, 0x00}, + {0xef, 0x3f}, + {0xd8, 0xd8}, + ///////////////////abs///////////////// + {0xfe, 0x01}, + {0x9f, 0x40}, + ///////////////////////////////////////////// + //////////////////////// LSC /////////////// + ////////////////////////////////////////// + {0xfe, 0x01}, + {0xc2, 0x14}, + {0xc3, 0x0d}, + {0xc4, 0x0c}, + {0xc8, 0x15}, + {0xc9, 0x0d}, + {0xca, 0x0a}, + {0xbc, 0x24}, + {0xbd, 0x10}, + {0xbe, 0x0b}, + {0xb6, 0x25}, + {0xb7, 0x16}, + {0xb8, 0x15}, + {0xc5, 0x00}, + {0xc6, 0x00}, + {0xc7, 0x00}, + {0xcb, 0x00}, + {0xcc, 0x00}, + {0xcd, 0x00}, + {0xbf, 0x07}, + {0xc0, 0x00}, + {0xc1, 0x00}, + {0xb9, 0x00}, + {0xba, 0x00}, + {0xbb, 0x00}, + {0xaa, 0x01}, + {0xab, 0x01}, + {0xac, 0x00}, + {0xad, 0x05}, + {0xae, 0x06}, + {0xaf, 0x0e}, + {0xb0, 0x0b}, + {0xb1, 0x07}, + {0xb2, 0x06}, + {0xb3, 0x17}, + {0xb4, 0x0e}, + {0xb5, 0x0e}, + {0xd0, 0x09}, + {0xd1, 0x00}, + {0xd2, 0x00}, + {0xd6, 0x08}, + {0xd7, 0x00}, + {0xd8, 0x00}, + {0xd9, 0x00}, + {0xda, 0x00}, + {0xdb, 0x00}, + {0xd3, 0x0a}, + {0xd4, 0x00}, + {0xd5, 0x00}, + {0xa4, 0x00}, + {0xa5, 0x00}, + {0xa6, 0x77}, + {0xa7, 0x77}, + {0xa8, 0x77}, + {0xa9, 0x77}, + {0xa1, 0x80}, + {0xa2, 0x80}, + + {0xfe, 0x01}, + {0xdf, 0x0d}, + {0xdc, 0x25}, + {0xdd, 0x30}, + {0xe0, 0x77}, + {0xe1, 0x80}, + {0xe2, 0x77}, + {0xe3, 0x90}, + {0xe6, 0x90}, + {0xe7, 0xa0}, + {0xe8, 0x90}, + {0xe9, 0xa0}, + {0xfe, 0x00}, + /////////////////////////////////////////////// + /////////// AWB//////////////////////// + /////////////////////////////////////////////// + {0xfe, 0x01}, + {0x4f, 0x00}, + {0x4f, 0x00}, + {0x4b, 0x01}, + {0x4f, 0x00}, + + {0x4c, 0x01}, // D75 + {0x4d, 0x71}, + {0x4e, 0x01}, + {0x4c, 0x01}, + {0x4d, 0x91}, + {0x4e, 0x01}, + {0x4c, 0x01}, + {0x4d, 0x70}, + {0x4e, 0x01}, + + {0x4c, 0x01}, // D65 + {0x4d, 0x90}, + {0x4e, 0x02}, + + + {0x4c, 0x01}, + {0x4d, 0xb0}, + {0x4e, 0x02}, + {0x4c, 0x01}, + {0x4d, 0x8f}, + {0x4e, 0x02}, + {0x4c, 0x01}, + {0x4d, 0x6f}, + {0x4e, 0x02}, + {0x4c, 0x01}, + {0x4d, 0xaf}, + {0x4e, 0x02}, + + {0x4c, 0x01}, + {0x4d, 0xd0}, + {0x4e, 0x02}, + {0x4c, 0x01}, + {0x4d, 0xf0}, + {0x4e, 0x02}, + {0x4c, 0x01}, + {0x4d, 0xcf}, + {0x4e, 0x02}, + {0x4c, 0x01}, + {0x4d, 0xef}, + {0x4e, 0x02}, + + {0x4c, 0x01},//D50 + {0x4d, 0x6e}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x8e}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0xae}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0xce}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x4d}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x6d}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x8d}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0xad}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0xcd}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x4c}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x6c}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x8c}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0xac}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0xcc}, + {0x4e, 0x03}, + + {0x4c, 0x01}, + {0x4d, 0xcb}, + {0x4e, 0x03}, + + {0x4c, 0x01}, + {0x4d, 0x4b}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x6b}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0x8b}, + {0x4e, 0x03}, + {0x4c, 0x01}, + {0x4d, 0xab}, + {0x4e, 0x03}, + + {0x4c, 0x01},//CWF + {0x4d, 0x8a}, + {0x4e, 0x04}, + {0x4c, 0x01}, + {0x4d, 0xaa}, + {0x4e, 0x04}, + {0x4c, 0x01}, + {0x4d, 0xca}, + {0x4e, 0x04}, + {0x4c, 0x01}, + {0x4d, 0xca}, + {0x4e, 0x04}, + {0x4c, 0x01}, + {0x4d, 0xc9}, + {0x4e, 0x04}, + {0x4c, 0x01}, + {0x4d, 0x8a}, + {0x4e, 0x04}, + {0x4c, 0x01}, + {0x4d, 0x89}, + {0x4e, 0x04}, + {0x4c, 0x01}, + {0x4d, 0xa9}, + {0x4e, 0x04}, + + {0x4c, 0x02},//tl84 + {0x4d, 0x0b}, + {0x4e, 0x05}, + {0x4c, 0x02}, + {0x4d, 0x0a}, + {0x4e, 0x05}, + + {0x4c, 0x01}, + {0x4d, 0xeb}, + {0x4e, 0x05}, + + {0x4c, 0x01}, + {0x4d, 0xea}, + {0x4e, 0x05}, + + {0x4c, 0x02}, + {0x4d, 0x09}, + {0x4e, 0x05}, + {0x4c, 0x02}, + {0x4d, 0x29}, + {0x4e, 0x05}, + + {0x4c, 0x02}, + {0x4d, 0x2a}, + {0x4e, 0x05}, + + {0x4c, 0x02}, + {0x4d, 0x4a}, + {0x4e, 0x05}, + + {0x4c, 0x02}, + {0x4d, 0x8a}, + {0x4e, 0x06}, + + {0x4c, 0x02}, + {0x4d, 0x49}, + {0x4e, 0x06}, + {0x4c, 0x02}, + {0x4d, 0x69}, + {0x4e, 0x06}, + {0x4c, 0x02}, + {0x4d, 0x89}, + {0x4e, 0x06}, + {0x4c, 0x02}, + {0x4d, 0xa9}, + {0x4e, 0x06}, + + {0x4c, 0x02}, + {0x4d, 0x48}, + {0x4e, 0x06}, + {0x4c, 0x02}, + {0x4d, 0x68}, + {0x4e, 0x06}, + {0x4c, 0x02}, + {0x4d, 0x69}, + {0x4e, 0x06}, + + {0x4c, 0x02},//H + {0x4d, 0xca}, + {0x4e, 0x07}, + {0x4c, 0x02}, + {0x4d, 0xc9}, + {0x4e, 0x07}, + {0x4c, 0x02}, + {0x4d, 0xe9}, + {0x4e, 0x07}, + {0x4c, 0x03}, + {0x4d, 0x09}, + {0x4e, 0x07}, + {0x4c, 0x02}, + {0x4d, 0xc8}, + {0x4e, 0x07}, + {0x4c, 0x02}, + {0x4d, 0xe8}, + {0x4e, 0x07}, + {0x4c, 0x02}, + {0x4d, 0xa7}, + {0x4e, 0x07}, + {0x4c, 0x02}, + {0x4d, 0xc7}, + {0x4e, 0x07}, + {0x4c, 0x02}, + {0x4d, 0xe7}, + {0x4e, 0x07}, + {0x4c, 0x03}, + {0x4d, 0x07}, + {0x4e, 0x07}, + + {0x4f, 0x01}, + {0x50, 0x80}, + {0x51, 0xa8}, + {0x52, 0x47}, + {0x53, 0x38}, + {0x54, 0xc7}, + {0x56, 0x0e}, + {0x58, 0x08}, + {0x5b, 0x00}, + {0x5c, 0x74}, + {0x5d, 0x8b}, + {0x61, 0xdb}, + {0x62, 0xb8}, + {0x63, 0x86}, + {0x64, 0xc0}, + {0x65, 0x04}, + + {0x67, 0xa8}, + {0x68, 0xb0}, + {0x69, 0x00}, + {0x6a, 0xa8}, + {0x6b, 0xb0}, + {0x6c, 0xaf}, + {0x6d, 0x8b}, + {0x6e, 0x50}, + {0x6f, 0x18}, + {0x73, 0xf0}, + {0x70, 0x0d}, + {0x71, 0x60}, + {0x72, 0x80}, + {0x74, 0x01}, + {0x75, 0x01}, + {0x7f, 0x0c}, + {0x76, 0x70}, + {0x77, 0x58}, + {0x78, 0xa0}, + {0x79, 0x5e}, + {0x7a, 0x54}, + {0x7b, 0x58}, + {0xfe, 0x00}, + ////////////////////////////////////////// + ///////////CC//////////////////////// + ////////////////////////////////////////// + {0xfe, 0x02}, + {0xc0, 0x01}, + {0xc1, 0x44}, + {0xc2, 0xfd}, + {0xc3, 0x04}, + {0xc4, 0xf0}, + {0xc5, 0x48}, + {0xc6, 0xfd}, + {0xc7, 0x46}, + {0xc8, 0xfd}, + {0xc9, 0x02}, + {0xca, 0xe0}, + {0xcb, 0x45}, + {0xcc, 0xec}, + {0xcd, 0x48}, + {0xce, 0xf0}, + {0xcf, 0xf0}, + {0xe3, 0x0c}, + {0xe4, 0x4b}, + {0xe5, 0xe0}, + ////////////////////////////////////////// + /////////// ABS //////////////////// + ////////////////////////////////////////// + {0xfe, 0x01}, + {0x9f, 0x40}, + {0xfe, 0x00}, + ////////////////////////////////////// + /////////// OUTPUT //////////////// + ////////////////////////////////////// + {0xfe, 0x00}, + {0xf2, 0x00}, + + //////////////frame rate 50Hz///////// + {0xfe, 0x00}, + {0x05, 0x01}, + {0x06, 0x56}, + {0x07, 0x00}, + {0x08, 0x32}, + {0xfe, 0x01}, + {0x25, 0x00}, + {0x26, 0xfa}, + {0x27, 0x04}, + {0x28, 0xe2}, //20fps + {0x29, 0x06}, + {0x2a, 0xd6}, //14fps + {0x2b, 0x07}, + {0x2c, 0xd0}, //12fps + {0x2d, 0x0b}, + {0x2e, 0xb8}, //8fps + {0xfe, 0x00}, + + ///////////////dark sun//////////////////// + {0xfe, 0x02}, + {0x40, 0xbf}, + {0x46, 0xcf}, + {0xfe, 0x00}, + ///////////////////////////////////////////////////// + ////////////////////// MIPI ///////////////////// + ///////////////////////////////////////////////////// + {0xfe, 0x03}, // P3 + {0x02, 0x22}, + {0x03, 0x10}, // 0x12 20140821 + {0x04, 0x10}, // 0x01 + {0x05, 0x00}, + {0x06, 0x88}, + +#if MIPI_LANE_RGB == 2 + {0x01, 0x87}, // clk lane_p2s_sel, phy_lane1_en, phy_lane0_en, phy_clk_en + {0x10, 0x95}, // lane_enable, MIPI_enable, RAW8, double_lane +#else + {0x01, 0x83}, // clk lane_p2s_sel, phy_lane0_en, phy_clk_en + {0x10, 0x94}, // lane_enable, MIPI_enable, RAW8 +#endif + +#if IMGSRC_FORMAT_RGB == IMG_FORMAT_YCBCR + {0x11, 0x1e}, +#elif IMGSRC_FORMAT_RGB == IMG_FORMAT_RGB565 + {0x11, 0x22}, +#endif + + {0x12, 0x80}, + {0x13, 0x0c}, + {0x15, 0x10}, + {0x17, 0xf0}, + + {0x21, 0x10}, + {0x22, 0x04}, + {0x23, 0x10}, + {0x24, 0x10}, + {0x25, 0x10}, + {0x26, 0x05}, + {0x29, 0x03}, + {0x2a, 0x0a}, + {0x2b, 0x06}, + + {0xfe, 0x00}, // P0 + //SENSORDB("GC2145MIPI_Sensor_SVGA"); + + {0xfe, 0x00}, // P0 + {0xfd, 0x01}, // column scalar mode + {0xfa, 0x00}, + //// crop window + {0xfe, 0x00}, + {0x90, 0x01}, + //out_win_y1 + {0x91, 0x00}, + {0x92, 0x00}, + //out_win_x1 + {0x93, 0x00}, + {0x94, 0x00}, + +#if SENSOR_RES_RGB == SENSOR_RES_640_480 + // 640X480 + // Out window height + {0x95, 0x01}, + {0x96, 0xe0}, + // Out window width + {0x97, 0x02}, + {0x98, 0x80}, +#elif SENSOR_RES_RGB == SENSOR_RES_480_272 + // 480x272 + // Out window height + {0x95, 0x01}, + {0x96, 0x10}, + // Out window width + {0x97, 0x01}, + {0x98, 0xe0}, +#endif + + {0x99, 0x11}, + {0x9a, 0x06}, + //// AWB + {0xfe, 0x00}, + {0xec, 0x02}, + {0xed, 0x02}, + {0xee, 0x30}, + {0xef, 0x48}, +#ifdef MIPI_EXAMPLE + {0x8c, 0x01}, // test pattern +#endif + {0xfe, 0x02}, + {0x9d, 0x08}, + {0xfe, 0x01}, + {0x74, 0x00}, + //// AEC + {0xfe, 0x01}, + {0x01, 0x04}, + {0x02, 0x60}, + {0x03, 0x02}, + {0x04, 0x48}, + {0x05, 0x18}, + {0x06, 0x50}, + {0x07, 0x10}, + {0x08, 0x38}, + {0x0a, 0x80}, + {0x21, 0x04}, + {0xfe, 0x00}, + {0x20, 0x03}, + //// mipi + {0xfe, 0x03}, //P3, CSI/PHY1.0 + +#if SENSOR_RES_RGB == SENSOR_RES_640_480 + {0x12, 0x00}, // LWC_set + {0x13, 0x05}, +#elif SENSOR_RES_RGB == SENSOR_RES_480_272 + {0x12, 0xc0}, // LWC_set + {0x13, 0x03}, +#endif + + //FIFO full level +#if MIPI_LANE_RGB == 2 + //400 + {0x04, 0x90}, + {0x05, 0x01}, +#elif MIPI_LANE_RGB == 1 + // 1 + {0x04, 0x01}, + {0x05, 0x00}, +#endif + + {0xfe, 0x00}, + + {0x00, 0x00}, +}; +static uint32_t kdev_sensor_get_dev_id(void); +static void rgb_set_aec_roi(struct cam_sensor_aec *aec_p) +{ + uint16_t dev_addr = gc2145_dev.addr; + + //set to page 1 + uint16_t reg = 0xfe; + uint8_t data = 0x01; + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, reg, 1, 1, &data); + + //set roi + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x01, 1, 1, &aec_p->x1); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x02, 1, 1, &aec_p->x2); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x03, 1, 1, &aec_p->y1); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x04, 1, 1, &aec_p->y2); + + //set center roi + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x05, 1, 1, &aec_p->center_x1); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x06, 1, 1, &aec_p->center_x2); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x07, 1, 1, &aec_p->center_y1); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x08, 1, 1, &aec_p->center_y2); +} + +static void rgb_get_lux(uint16_t* exposure, uint8_t* pre_gain, uint8_t* post_gain, uint8_t* global_gain, uint8_t* y_average) +{ + uint16_t dev_addr = gc2145_dev.addr; + + //set to page 0 + uint8_t data = 0x00; + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0xfe, 1, 1, &data); + + //get exposure + *exposure = 0; + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 0x03, 1, 1, &data); + *exposure |= (data << 8); + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 0x04, 1, 1, &data); + *exposure |= data; + + //get gain + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 0xb1, 1, 1, &data); + *pre_gain = data; + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 0xb2, 1, 1, &data); + *post_gain = data; + + // global gain + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 0xb0, 1, 1, &data); + *global_gain = data; + + //set to page 1 + data = 0x01; + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0xfe, 1, 1, &data); + + // y average + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 0x14, 1, 1, &data); + *y_average = data; + + return; +} + +static uint32_t gc2145_write_reg(struct sensor_device *sensor_dev, uint16_t reg, uint8_t data) +{ + uint32_t ret; + + ret = kdrv_i2c_write_register(KDRV_I2C_CTRL_0, sensor_dev->addr, reg, 1, 1, &data); + return ret; +} + +static uint32_t gc2145_read_reg(struct sensor_device *sensor_dev, uint16_t reg, uint8_t *data) +{ + uint32_t ret; + + ret = kdrv_i2c_read_register(KDRV_I2C_CTRL_0, sensor_dev->addr, reg, 1, 1, data); + return ret; +} + +uint32_t gc2145_init(struct sensor_device *sensor_dev, struct sensor_init_seq *seq) +{ + struct sensor_device *dev = sensor_dev; + struct sensor_init_seq *init_fnc_ptr; + + for (init_fnc_ptr = seq; ; ++init_fnc_ptr) + { + if(init_fnc_ptr->addr == 0 && init_fnc_ptr->value == 0) + break; + gc2145_write_reg(dev, init_fnc_ptr->addr , (uint8_t)(init_fnc_ptr->value & 0xFF)); + } + + uint32_t data = kdev_sensor_get_dev_id(); + sensor_msg("gc2145_init sensor id=%x\n", data); + return 0; +} + +static uint32_t gc2145_set_params(struct sensor_device *sensor_dev) +{ + sensor_msg(" <%s>\n", __func__); + /* initialize the sensor with default settings */ + gc2145_init(sensor_dev, gc2145_init_regs); + return 0; +} + +static kdev_status_t kdev_sensor_power(uint32_t on) +{ + sensor_msg(" <%s>\n", __func__); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_reset() +{ + sensor_msg(" <%s>\n", __func__); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_stream(uint32_t enable) +{ + sensor_msg(" <%s>\n", __func__); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_enum_fmt(uint32_t index, uint32_t *code) +{ + if (index >= ARRAY_SIZE(gc2145_colour_fmts)) + return KDEV_STATUS_ERROR; + + sensor_msg(" <%s>\n", __func__); + *code = gc2145_colour_fmts[index].fourcc; + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_get_fmt(struct cam_format *format) +{ + sensor_msg(" <%s>\n", __func__); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_set_fmt(struct cam_format *fmt) +{ + sensor_msg(" <%s>\n", __func__); + + return (kdev_status_t)gc2145_set_params(&gc2145_dev); +} + +static kdev_status_t kdev_sensor_set_aec(struct cam_sensor_aec *aec_p) +{ + sensor_msg(" <%s>\n", __func__); + + rgb_set_aec_roi(aec_p); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_get_lux(uint16_t *expo, uint8_t *pre_gain, uint8_t *post_gain, uint8_t* global_gain, uint8_t* y_average) +{ + sensor_msg(" <%s>\n", __func__); + + rgb_get_lux(expo, pre_gain, post_gain, global_gain, y_average); + + return KDEV_STATUS_OK; +} + +static uint32_t kdev_sensor_get_dev_id(void) +{ + uint8_t data = 0; + uint16_t id = 0; + + gc2145_read_reg(&gc2145_dev, 0xf0, &data); + id = data<<8; + gc2145_read_reg(&gc2145_dev, 0xf1, &data); + id += data; + + return (uint32_t)id; +} + +static struct sensor_ops gc2145_ops = { + .s_power = kdev_sensor_power, + .reset = kdev_sensor_reset, + .s_stream = kdev_sensor_stream, + .enum_fmt = kdev_sensor_enum_fmt, + .get_fmt = kdev_sensor_get_fmt, + .set_fmt = kdev_sensor_set_fmt, + .set_gain = NULL, + .set_aec = kdev_sensor_set_aec, + .set_exp_time = NULL, + .get_lux = kdev_sensor_get_lux, + .led_switch = NULL, + .set_mirror = NULL, + .set_flip = NULL, + .get_dev_id = kdev_sensor_get_dev_id, +}; + +struct sensor_ops* kdev_sensor_gc2145_get_ops(void) +{ + return &gc2145_ops; +} diff --git a/platform/dev/sensor/kdev_sensor_hmx2056.c b/platform/dev/sensor/kdev_sensor_hmx2056.c new file mode 100644 index 0000000..d85336e --- /dev/null +++ b/platform/dev/sensor/kdev_sensor_hmx2056.c @@ -0,0 +1,1326 @@ +#include "config/board_kdp520.h" +#if (V2K_ENABLE_TYPE == V2K_ENABLE_HMX2056) || (V2K_ENABLE_TYPE == V2K_ENABLE_HMX2056_OV9286) +#include +#include "framework/init.h" +#include "framework/v2k.h" +#include "framework/v2k_image.h" +#include "framework/framework_errno.h" + +#include "media/camera/sensor.h" +#include "media/camera/sys_camera.h" +#include "media/v2k_subdev.h" +#include "utility.h" +//#include "kmdw_console.h" + +#define RES_640x480 1 +#define RES_480x272 2 +#define HMX2056_RES RES_640x480 + + +struct hmx2056_context { + struct v2k_subdev subdev; + //const struct sensor_datafmt_info *fmt; +}; + +static const struct sensor_datafmt_info hmx2056_colour_fmts[] = { + { V2K_PIX_FMT_RGB565, V2K_COLORSPACE_RGB }, + { V2K_PIX_FMT_RAW8, V2K_COLORSPACE_RAW }, +}; + +static const struct sensor_win_size hmx2056_supported_win_sizes[] = { + { .width = TFT43_WIDTH, .height = TFT43_HEIGHT, }, + { .width = VGA_LANDSCAPE_WIDTH, .height = VGA_LANDSCAPE_HEIGHT, }, +}; + +#if HMX2056_RES == RES_640x480 + +struct sensor_init_seq INITDATA hmx2056_init_regs[] = { +{0x0022,0x00}, +{0x0020,0x00}, +{0x0025,0x00}, +//{0x0025,0x80}, +{0x0026,0x87}, //24mhz=0x87 +//{0x0026,0x83}, //12mhz=0x83 +{0x0027,0x40}, +{0x0028,0xC0}, +{0x002A,0x25},//228Mhz +{0x002B,0x00}, // divider for system clock 228/4=57, divider for mipi clock=228/2=114 +{0x002C,0x0A}, +{0x0004,0x10}, +//RDCFG - resolution param : 1 +{0x0006,0x01},//kay from 0 to 3 +//VREAD - resolution param : 2 +{0x000D,0x01}, +//{0x000D,0x11}, +//HREAD - resolution param : 3 +{0x000E,0x11}, + +{0x000F,0x00}, //variable frame rate +{0x0011,0x02}, +{0x0012,0x1C}, +{0x0013,0x01}, +{0x0015,0x02}, +{0x0016,0x80}, +{0x0018,0x00}, +{0x001D,0x40}, +{0x0040,0x20}, +{0x0053,0x0A}, +{0x0044,0x06}, +{0x0046,0xD8}, +{0x004A,0x0A}, +{0x004B,0x72}, +{0x0075,0x01}, +{0x0070,0x5F}, +{0x0071,0xFF}, +{0x0072,0x55}, +{0x0073,0x50}, +{0x0077,0x04}, +{0x0080,0xC8}, +{0x0082,0xA2}, +{0x0083,0xF0}, +{0x0085,0x11}, +{0x0086,0x02}, +{0x0087,0x80}, +{0x0088,0x6C}, +{0x0089,0x2E}, +{0x008A,0x6D}, +{0x008D,0x20}, +{0x0090,0x00}, +{0x0091,0x10}, +{0x0092,0x11}, +{0x0093,0x12}, +{0x0094,0x16}, +{0x0095,0x08}, +{0x0096,0x00}, +{0x0097,0x10}, +{0x0098,0x11}, +{0x0099,0x12}, +{0x009A,0x16}, +{0x009B,0x34}, +{0x00A0,0x00}, +{0x00A1,0x04}, +//ISPCTRL0 resolution param : 6 , Full mode +{0x011F,0x00}, +//{0x011F,0xF7}, +{0x0120,0x37}, +{0x0121,0x83}, +{0x0122,0x7B},//0114 +{0x0123,0xC2}, +{0x0124,0xDE}, +//ISPCTRL5 resolution param : 4 , Scaler - enable down-scaler +{0x0125,0xFF},//0114 +//ISPCTRL6 resolution param : 5 , Windowing Vsync width adjust +{0x0126,0x70}, +{0x0128,0x1F}, +{0x0132,0x10}, +{0x0136,0x0A}, +{0x0131,0xBD}, +{0x0140,0x14}, +{0x0141,0x0A}, +{0x0142,0x14}, +{0x0143,0x0A}, +{0x0144,0x06}, +{0x0145,0x00}, +{0x0146,0x20}, +{0x0147,0x0A}, +{0x0148,0x10}, +{0x0149,0x0C}, +{0x014A,0x80}, +{0x014B,0x80}, +{0x014C,0x2E}, +{0x014D,0x2E}, +{0x014E,0x05}, +{0x014F,0x05}, +{0x0150,0x0D}, +{0x0155,0x00}, +{0x0156,0x10}, +{0x0157,0x0A}, +{0x0158,0x0A}, +{0x0159,0x0A}, +{0x015A,0x05}, +{0x015B,0x05}, +{0x015C,0x05}, +{0x015D,0x05}, +{0x015E,0x08}, +{0x015F,0xFF}, +{0x0160,0x50}, +{0x0161,0x20}, +{0x0162,0x14}, +{0x0163,0x0A}, +{0x0164,0x10}, +{0x0165,0x08}, +{0x0166,0x0A}, +{0x018C,0x24}, +{0x018D,0x04}, +{0x018E,0x00}, +{0x018F,0x11}, +{0x0190,0x80}, +{0x0191,0x47}, +{0x0192,0x48}, +{0x0193,0x64}, +{0x0194,0x32}, +{0x0195,0xC8}, +{0x0196,0x96}, +{0x0197,0x64}, +{0x0198,0x32}, +{0x0199,0x14}, +{0x019A,0x20}, +{0x019B,0x14}, +{0x01BA,0x10}, +{0x01BB,0x04}, +{0x01D8,0x40}, +{0x01DE,0x60}, +{0x01E4,0x10}, +{0x01E5,0x10}, +{0x01F2,0x0C}, +{0x01F3,0x14}, +{0x01F8,0x04}, +{0x01F9,0x0C}, +{0x01FE,0x02}, +{0x01FF,0x04}, +{0x0220,0x00}, +{0x0221,0xB0}, +{0x0222,0x00}, +{0x0223,0x80}, +{0x0224,0x8E}, +{0x0225,0x00}, +{0x0226,0x88}, +{0x022A,0x88}, +{0x022B,0x00}, +{0x022C,0x88}, +{0x022D,0x13}, +{0x022E,0x0B}, +{0x022F,0x13}, +{0x0230,0x0B}, +{0x0233,0x13}, +{0x0234,0x0B}, +{0x0235,0x28}, +{0x0236,0x03}, +{0x0237,0x28}, +{0x0238,0x03}, +{0x023B,0x28}, +{0x023C,0x03}, +{0x023D,0x5C}, +{0x023E,0x02}, +{0x023F,0x5C}, +{0x0240,0x02}, +{0x0243,0x5C}, +{0x0244,0x02}, +{0x0251,0x0E}, +{0x0252,0x00}, +{0x0280,0x0A}, +{0x0282,0x14}, +{0x0284,0x2A}, +{0x0286,0x50}, +{0x0288,0x60}, +{0x028A,0x6D}, +{0x028C,0x79}, +{0x028E,0x82}, +{0x0290,0x8A}, +{0x0292,0x91}, +{0x0294,0x9C}, +{0x0296,0xA7}, +{0x0298,0xBA}, +{0x029A,0xCD}, +{0x029C,0xE0}, +{0x029E,0x2D}, +{0x02A0,0x06}, +{0x02E0,0x04}, +{0x02C0,0xB1}, +{0x02C1,0x01}, +{0x02C2,0x7D}, +{0x02C3,0x07}, +{0x02C4,0xD2}, +{0x02C5,0x07}, +{0x02C6,0xC4}, +{0x02C7,0x07}, +{0x02C8,0x79}, +{0x02C9,0x01}, +{0x02CA,0xC4}, +{0x02CB,0x07}, +{0x02CC,0xF7}, +{0x02CD,0x07}, +{0x02CE,0x3B}, +{0x02CF,0x07}, +{0x02D0,0xCF}, +{0x02D1,0x01}, +{0x0302,0x00}, +{0x0303,0x00}, +{0x0304,0x00}, +{0x02F0,0x5E}, +{0x02F1,0x07}, +{0x02F2,0xA0}, +{0x02F3,0x00}, +{0x02F4,0x02}, +{0x02F5,0x00}, +{0x02F6,0xC4}, +{0x02F7,0x07}, +{0x02F8,0x11}, +{0x02F9,0x00}, +{0x02FA,0x2A}, +{0x02FB,0x00}, +{0x02FC,0xA1}, +{0x02FD,0x07}, +{0x02FE,0xB8}, +{0x02FF,0x07}, +{0x0300,0xA7}, +{0x0301,0x00}, +{0x0305,0x00}, +{0x0306,0x00}, +{0x0307,0x7A}, +{0x032D,0x00}, +{0x032E,0x01}, +{0x032F,0x00}, +{0x0330,0x01}, +{0x0331,0x00}, +{0x0332,0x01}, +{0x0333,0x82}, +{0x0334,0x00}, +{0x0335,0x84}, +{0x0336,0x00}, +{0x0337,0x01}, +{0x0338,0x00}, +{0x0339,0x01}, +{0x033A,0x00}, +{0x033B,0x01}, +{0x0340,0x30}, +{0x0341,0x44}, +{0x0342,0x4A}, +{0x0343,0x42}, +{0x0344,0x74}, +{0x0345,0x4F}, +{0x0346,0x67}, +{0x0347,0x5C}, +{0x0348,0x59}, +{0x0349,0x67}, +{0x034A,0x4D}, +{0x034B,0x6E}, +{0x034C,0x44}, +{0x0350,0x80}, +{0x0351,0x80}, +{0x0352,0x18}, +{0x0353,0x18}, +{0x0354,0x6E}, +{0x0355,0x4A}, +{0x0356,0x7A}, +{0x0357,0xC6}, +{0x0358,0x06}, +{0x035A,0x06}, +{0x035B,0xA0}, +{0x035C,0x73}, +{0x035D,0x5A}, +{0x035E,0xC6}, +{0x035F,0xA0}, +{0x0360,0x02}, +{0x0361,0x18}, +{0x0362,0x80}, +{0x0363,0x6C}, +{0x0364,0x00}, +{0x0365,0xF0}, +{0x0366,0x20}, +{0x0367,0x0C}, +{0x0369,0x00}, +{0x036A,0x10}, +{0x036B,0x10}, +{0x036E,0x20}, +{0x036F,0x00}, +{0x0370,0x10}, +{0x0371,0x18}, +{0x0372,0x0C}, +{0x0373,0x38}, +{0x0374,0x3A}, +{0x0375,0x13}, +{0x0376,0x22}, +{0x0380,0xFF},//0114 +{0x0381,0x4A}, +{0x0382,0x36}, +{0x038A,0x40}, +{0x038B,0x08}, +{0x038C,0xC1}, +{0x038E,0x40}, +//{0x038F,0x09}, +//{0x0390,0xD0}, +{0x038F,0x02}, +{0x0390,0x80}, +{0x0391,0x05}, +{0x0393,0x80}, +{0x0395,0x21}, +{0x0398,0x02}, +{0x0399,0x74}, +{0x039A,0x03}, +{0x039B,0x11}, +{0x039C,0x03}, +{0x039D,0xAE}, +{0x039E,0x04}, +{0x039F,0xE8}, +{0x03A0,0x06}, +{0x03A1,0x22}, +{0x03A2,0x07}, +{0x03A3,0x5C}, +{0x03A4,0x09}, +{0x03A5,0xD0}, +{0x03A6,0x0C}, +{0x03A7,0x0E}, +{0x03A8,0x10}, +{0x03A9,0x18}, +{0x03AA,0x20}, +{0x03AB,0x28}, +{0x03AC,0x1E}, +{0x03AD,0x1A}, +{0x03AE,0x13}, +{0x03AF,0x0C}, +{0x03B0,0x0B}, +{0x03B1,0x09}, +{0x03B3,0x10}, +{0x03B4,0x00}, +{0x03B5,0x10}, +{0x03B6,0x00}, +{0x03B7,0xEA}, +{0x03B8,0x00}, +{0x03B9,0x3A}, +{0x03BA,0x01}, +{0x03BB,0x9F}, +{0x03BC,0xCF}, +{0x03BD,0xE7}, +{0x03BE,0xF3}, +{0x03BF,0x01}, +{0x03D0,0xF8}, +{0x03E0,0x04}, +{0x03E1,0x01}, +{0x03E2,0x04}, +{0x03E4,0x10}, +{0x03E5,0x12}, +{0x03E6,0x00}, +{0x03E8,0x21}, +{0x03E9,0x23}, +{0x03EA,0x01}, +{0x03EC,0x21}, +{0x03ED,0x23}, +{0x03EE,0x01}, +{0x03F0,0x20}, +{0x03F1,0x22}, +{0x03F2,0x00}, +{0x0420,0x84}, +{0x0421,0x00}, +{0x0422,0x00}, +{0x0423,0x83}, +{0x0430,0x08}, +{0x0431,0x28}, +{0x0432,0x10}, +{0x0433,0x08}, +{0x0435,0x0C}, +{0x0450,0xFF}, +{0x0451,0xE8}, +{0x0452,0xC4}, +{0x0453,0x88}, +{0x0454,0x00}, +{0x0458,0x98}, +{0x0459,0x03}, +{0x045A,0x00}, +{0x045B,0x28}, +{0x045C,0x00}, +{0x045D,0x68}, +{0x0466,0x14}, +{0x047A,0x00}, +{0x047B,0x00}, +{0x0480,0x58}, +{0x0481,0x06}, +{0x0482,0x0C}, +{0x04B0,0x50}, +{0x04B6,0x30}, +{0x04B9,0x10}, +{0x04B3,0x10}, +{0x04B1,0x8E}, +{0x04B4,0x20}, +{0x0540,0x00}, +{0x0541,0x9D}, +{0x0542,0x00}, +{0x0543,0xBC}, +{0x0580,0x01}, +{0x0581,0x0F}, +{0x0582,0x04}, +{0x0594,0x00}, +{0x0595,0x04}, +{0x05A9,0x03}, +{0x05AA,0x40}, +{0x05AB,0x80}, +{0x05AC,0x0A}, +{0x05AD,0x10}, +{0x05AE,0x0C}, +{0x05AF,0x0C}, +{0x05B0,0x03}, +{0x05B1,0x03}, +{0x05B2,0x1C}, +{0x05B3,0x02}, +{0x05B4,0x00}, +{0x05B5,0x0C}, +{0x05B8,0x80}, +{0x05B9,0x32}, +{0x05BA,0x00}, +{0x05BB,0x80}, +{0x05BC,0x03}, +{0x05BD,0x00}, +{0x05BF,0x05}, +{0x05C0,0x10}, +{0x05C3,0x00}, +{0x05C4,0x0C}, +{0x05C5,0x20}, +{0x05C7,0x01}, +{0x05C8,0x14}, +{0x05C9,0x54}, +{0x05CA,0x14}, +{0x05CB,0xE0}, +{0x05CC,0x20}, +{0x05CD,0x00}, +{0x05CE,0x08}, +{0x05CF,0x60}, +{0x05D0,0x10}, +{0x05D1,0x05}, +{0x05D2,0x03}, +{0x05D4,0x00}, +{0x05D5,0x05}, +{0x05D6,0x05}, +{0x05D7,0x05}, +{0x05D8,0x08}, +{0x05DC,0x0C}, +{0x05D9,0x00}, +{0x05DB,0x00}, +{0x05DD,0x0F}, +{0x05DE,0x00}, +{0x05DF,0x0A}, + + {0x05E0,0xA0}, + {0x05E1,0x00}, + {0x05E2,0xA0}, + {0x05E3,0x00}, + {0x05E4,0x04}, + {0x05E5,0x00}, + {0x05E6,0x83}, + {0x05E7,0x02}, + {0x05E8,0x06}, + {0x05E9,0x00}, + {0x05EA,0xE5}, + {0x05EB,0x01}, + +{0x0660,0x04}, +{0x0661,0x16}, +{0x0662,0x04}, +{0x0663,0x28}, +{0x0664,0x04}, +{0x0665,0x18}, +{0x0666,0x04}, +{0x0667,0x21}, +{0x0668,0x04}, +{0x0669,0x0C}, +{0x066A,0x04}, +{0x066B,0x25}, +{0x066C,0x00}, +{0x066D,0x12}, +{0x066E,0x00}, +{0x066F,0x80}, +{0x0670,0x00}, +{0x0671,0x0A}, +{0x0672,0x04}, +{0x0673,0x1D}, +{0x0674,0x04}, +{0x0675,0x1D}, +{0x0676,0x00}, +{0x0677,0x7E}, +{0x0678,0x01}, +{0x0679,0x47}, +{0x067A,0x00}, +{0x067B,0x73}, +{0x067C,0x04}, +{0x067D,0x14}, +{0x067E,0x04}, +{0x067F,0x28}, +{0x0680,0x00}, +{0x0681,0x22}, +{0x0682,0x00}, +{0x0683,0xA5}, +{0x0684,0x00}, +{0x0685,0x1E}, +{0x0686,0x04}, +{0x0687,0x1D}, +{0x0688,0x04}, +{0x0689,0x19}, +{0x068A,0x04}, +{0x068B,0x21}, +{0x068C,0x04}, +{0x068D,0x0A}, +{0x068E,0x04}, +{0x068F,0x25}, +{0x0690,0x04}, +{0x0691,0x15}, +{0x0698,0x20}, +{0x0699,0x20}, +{0x069A,0x01}, +{0x069C,0x22}, +{0x069D,0x10}, +{0x069E,0x10}, +{0x069F,0x08}, +{0x0B20,0xBE}, +//{0x007C,0x33}, +{0x007C,0x40}, +{0x0B02,0x04}, +{0x0B07,0x25}, + +{0x0B0E,0x1D}, +{0x0B0F,0x07}, +{0x0B22,0x02}, +{0x0B39,0x03}, +{0x0B11,0x7F}, +{0x0B12,0x7F}, +{0x0B17,0xE0}, +{0x0B30,0x0F}, +{0x0B31,0x02}, +{0x0B32,0x00}, +{0x0B33,0x00}, +{0x0B39,0x0F}, +{0x0B3B,0x12}, +{0x0B3F,0x01}, +{0x0024,0x40}, +//{0x0028,0x81},//test pattern enable +{0x0028,0xC0}, +{0x0000,0x01}, +{0x0100,0x01}, +{0x0101,0x01}, +{0x0005,0x01}, + +{ 0,0}, +}; + +#elif HMX2056_RES == RES_480x272 + +struct sensor_init_seq INITDATA hmx2056_init_regs[] = { +{0x0022,0x00}, +{0x0020,0x00}, +{0x0025,0x00}, +//{0x0025,0x80}, +{0x0026,0x87}, //24mhz=0x87 +//{0x0026,0x83}, //12mhz=0x83 +{0x0027,0x40}, +{0x0028,0xC0}, +{0x002A,0x25},//228Mhz +{0x002B,0x00}, // 0x06: mipi clk /4 +{0x002C,0x0A}, +{0x0004,0x10}, +{0x0006,0x01},//kay from 0 to 3 +{0x000D,0x11}, +{0x000E,0x11}, +{0x000F,0x00}, +{0x0011,0x02}, +{0x0012,0x1C}, +{0x0013,0x01}, +{0x0015,0x02}, +{0x0016,0x80}, +{0x0018,0x00}, +{0x001D,0x40}, +{0x0040,0x20}, +{0x0053,0x0A}, +{0x0044,0x06}, +{0x0046,0xD8}, +{0x004A,0x0A}, +{0x004B,0x72}, +{0x0075,0x01}, +{0x0070,0x5F}, +{0x0071,0xFF}, +{0x0072,0x55}, +{0x0073,0x50}, +{0x0077,0x04}, +{0x0080,0xC8}, +{0x0082,0xA2}, +{0x0083,0xF0}, +{0x0085,0x11}, +{0x0086,0x02}, +{0x0087,0x80}, +{0x0088,0x6C}, +{0x0089,0x2E}, +{0x008A,0x6D}, +{0x008D,0x20}, +{0x0090,0x00}, +{0x0091,0x10}, +{0x0092,0x11}, +{0x0093,0x12}, +{0x0094,0x16}, +{0x0095,0x08}, +{0x0096,0x00}, +{0x0097,0x10}, +{0x0098,0x11}, +{0x0099,0x12}, +{0x009A,0x16}, +{0x009B,0x34}, +{0x00A0,0x00}, +{0x00A1,0x04}, +{0x011F,0xF7}, +{0x0120,0x37}, +{0x0121,0x83}, +{0x0122,0x7B},//0114 +{0x0123,0xC2}, +{0x0124,0xDE}, +{0x0125,0xFF},//0114 +{0x0126,0x70}, +{0x0128,0x1F}, +{0x0132,0x10}, +{0x0136,0x0A}, +{0x0131,0xBD}, +{0x0140,0x14}, +{0x0141,0x0A}, +{0x0142,0x14}, +{0x0143,0x0A}, +{0x0144,0x06}, +{0x0145,0x00}, +{0x0146,0x20}, +{0x0147,0x0A}, +{0x0148,0x10}, +{0x0149,0x0C}, +{0x014A,0x80}, +{0x014B,0x80}, +{0x014C,0x2E}, +{0x014D,0x2E}, +{0x014E,0x05}, +{0x014F,0x05}, +{0x0150,0x0D}, +{0x0155,0x00}, +{0x0156,0x10}, +{0x0157,0x0A}, +{0x0158,0x0A}, +{0x0159,0x0A}, +{0x015A,0x05}, +{0x015B,0x05}, +{0x015C,0x05}, +{0x015D,0x05}, +{0x015E,0x08}, +{0x015F,0xFF}, +{0x0160,0x50}, +{0x0161,0x20}, +{0x0162,0x14}, +{0x0163,0x0A}, +{0x0164,0x10}, +{0x0165,0x08}, +{0x0166,0x0A}, +{0x018C,0x24}, +{0x018D,0x04}, +{0x018E,0x00}, +{0x018F,0x11}, +{0x0190,0x80}, +{0x0191,0x47}, +{0x0192,0x48}, +{0x0193,0x64}, +{0x0194,0x32}, +{0x0195,0xC8}, +{0x0196,0x96}, +{0x0197,0x64}, +{0x0198,0x32}, +{0x0199,0x14}, +{0x019A,0x20}, +{0x019B,0x14}, +{0x01BA,0x10}, +{0x01BB,0x04}, +{0x01D8,0x40}, +{0x01DE,0x60}, +{0x01E4,0x10}, +{0x01E5,0x10}, +{0x01F2,0x0C}, +{0x01F3,0x14}, +{0x01F8,0x04}, +{0x01F9,0x0C}, +{0x01FE,0x02}, +{0x01FF,0x04}, +{0x0220,0x00}, +{0x0221,0xB0}, +{0x0222,0x00}, +{0x0223,0x80}, +{0x0224,0x8E}, +{0x0225,0x00}, +{0x0226,0x88}, +{0x022A,0x88}, +{0x022B,0x00}, +{0x022C,0x88}, +{0x022D,0x13}, +{0x022E,0x0B}, +{0x022F,0x13}, +{0x0230,0x0B}, +{0x0233,0x13}, +{0x0234,0x0B}, +{0x0235,0x28}, +{0x0236,0x03}, +{0x0237,0x28}, +{0x0238,0x03}, +{0x023B,0x28}, +{0x023C,0x03}, +{0x023D,0x5C}, +{0x023E,0x02}, +{0x023F,0x5C}, +{0x0240,0x02}, +{0x0243,0x5C}, +{0x0244,0x02}, +{0x0251,0x0E}, +{0x0252,0x00}, +{0x0280,0x0A}, +{0x0282,0x14}, +{0x0284,0x2A}, +{0x0286,0x50}, +{0x0288,0x60}, +{0x028A,0x6D}, +{0x028C,0x79}, +{0x028E,0x82}, +{0x0290,0x8A}, +{0x0292,0x91}, +{0x0294,0x9C}, +{0x0296,0xA7}, +{0x0298,0xBA}, +{0x029A,0xCD}, +{0x029C,0xE0}, +{0x029E,0x2D}, +{0x02A0,0x06}, +{0x02E0,0x04}, +{0x02C0,0xB1}, +{0x02C1,0x01}, +{0x02C2,0x7D}, +{0x02C3,0x07}, +{0x02C4,0xD2}, +{0x02C5,0x07}, +{0x02C6,0xC4}, +{0x02C7,0x07}, +{0x02C8,0x79}, +{0x02C9,0x01}, +{0x02CA,0xC4}, +{0x02CB,0x07}, +{0x02CC,0xF7}, +{0x02CD,0x07}, +{0x02CE,0x3B}, +{0x02CF,0x07}, +{0x02D0,0xCF}, +{0x02D1,0x01}, +{0x0302,0x00}, +{0x0303,0x00}, +{0x0304,0x00}, +{0x02F0,0x5E}, +{0x02F1,0x07}, +{0x02F2,0xA0}, +{0x02F3,0x00}, +{0x02F4,0x02}, +{0x02F5,0x00}, +{0x02F6,0xC4}, +{0x02F7,0x07}, +{0x02F8,0x11}, +{0x02F9,0x00}, +{0x02FA,0x2A}, +{0x02FB,0x00}, +{0x02FC,0xA1}, +{0x02FD,0x07}, +{0x02FE,0xB8}, +{0x02FF,0x07}, +{0x0300,0xA7}, +{0x0301,0x00}, +{0x0305,0x00}, +{0x0306,0x00}, +{0x0307,0x7A}, +{0x032D,0x00}, +{0x032E,0x01}, +{0x032F,0x00}, +{0x0330,0x01}, +{0x0331,0x00}, +{0x0332,0x01}, +{0x0333,0x82}, +{0x0334,0x00}, +{0x0335,0x84}, +{0x0336,0x00}, +{0x0337,0x01}, +{0x0338,0x00}, +{0x0339,0x01}, +{0x033A,0x00}, +{0x033B,0x01}, +{0x0340,0x30}, +{0x0341,0x44}, +{0x0342,0x4A}, +{0x0343,0x42}, +{0x0344,0x74}, +{0x0345,0x4F}, +{0x0346,0x67}, +{0x0347,0x5C}, +{0x0348,0x59}, +{0x0349,0x67}, +{0x034A,0x4D}, +{0x034B,0x6E}, +{0x034C,0x44}, +{0x0350,0x80}, +{0x0351,0x80}, +{0x0352,0x18}, +{0x0353,0x18}, +{0x0354,0x6E}, +{0x0355,0x4A}, +{0x0356,0x7A}, +{0x0357,0xC6}, +{0x0358,0x06}, +{0x035A,0x06}, +{0x035B,0xA0}, +{0x035C,0x73}, +{0x035D,0x5A}, +{0x035E,0xC6}, +{0x035F,0xA0}, +{0x0360,0x02}, +{0x0361,0x18}, +{0x0362,0x80}, +{0x0363,0x6C}, +{0x0364,0x00}, +{0x0365,0xF0}, +{0x0366,0x20}, +{0x0367,0x0C}, +{0x0369,0x00}, +{0x036A,0x10}, +{0x036B,0x10}, +{0x036E,0x20}, +{0x036F,0x00}, +{0x0370,0x10}, +{0x0371,0x18}, +{0x0372,0x0C}, +{0x0373,0x38}, +{0x0374,0x3A}, +{0x0375,0x13}, +{0x0376,0x22}, +{0x0380,0xFF},//0114 +{0x0381,0x4A}, +{0x0382,0x36}, +{0x038A,0x40}, +{0x038B,0x08}, +{0x038C,0xC1}, +{0x038E,0x40}, +//{0x038F,0x09}, +//{0x0390,0xD0}, +{0x038F,0x02}, +{0x0390,0x80}, +{0x0391,0x05}, +{0x0393,0x80}, +{0x0395,0x21}, +{0x0398,0x02}, +{0x0399,0x74}, +{0x039A,0x03}, +{0x039B,0x11}, +{0x039C,0x03}, +{0x039D,0xAE}, +{0x039E,0x04}, +{0x039F,0xE8}, +{0x03A0,0x06}, +{0x03A1,0x22}, +{0x03A2,0x07}, +{0x03A3,0x5C}, +{0x03A4,0x09}, +{0x03A5,0xD0}, +{0x03A6,0x0C}, +{0x03A7,0x0E}, +{0x03A8,0x10}, +{0x03A9,0x18}, +{0x03AA,0x20}, +{0x03AB,0x28}, +{0x03AC,0x1E}, +{0x03AD,0x1A}, +{0x03AE,0x13}, +{0x03AF,0x0C}, +{0x03B0,0x0B}, +{0x03B1,0x09}, +{0x03B3,0x10}, +{0x03B4,0x00}, +{0x03B5,0x10}, +{0x03B6,0x00}, +{0x03B7,0xEA}, +{0x03B8,0x00}, +{0x03B9,0x3A}, +{0x03BA,0x01}, +{0x03BB,0x9F}, +{0x03BC,0xCF}, +{0x03BD,0xE7}, +{0x03BE,0xF3}, +{0x03BF,0x01}, +{0x03D0,0xF8}, +{0x03E0,0x04}, +{0x03E1,0x01}, +{0x03E2,0x04}, +{0x03E4,0x10}, +{0x03E5,0x12}, +{0x03E6,0x00}, +{0x03E8,0x21}, +{0x03E9,0x23}, +{0x03EA,0x01}, +{0x03EC,0x21}, +{0x03ED,0x23}, +{0x03EE,0x01}, +{0x03F0,0x20}, +{0x03F1,0x22}, +{0x03F2,0x00}, +{0x0420,0x84}, +{0x0421,0x00}, +{0x0422,0x00}, +{0x0423,0x83}, +{0x0430,0x08}, +{0x0431,0x28}, +{0x0432,0x10}, +{0x0433,0x08}, +{0x0435,0x0C}, +{0x0450,0xFF}, +{0x0451,0xE8}, +{0x0452,0xC4}, +{0x0453,0x88}, +{0x0454,0x00}, +{0x0458,0x98}, +{0x0459,0x03}, +{0x045A,0x00}, +{0x045B,0x28}, +{0x045C,0x00}, +{0x045D,0x68}, +{0x0466,0x14}, +{0x047A,0x00}, +{0x047B,0x00}, +{0x0480,0x58}, +{0x0481,0x06}, +{0x0482,0x0C}, +{0x04B0,0x50}, +{0x04B6,0x30}, +{0x04B9,0x10}, +{0x04B3,0x10}, +{0x04B1,0x8E}, +{0x04B4,0x20}, +{0x0540,0x00}, +{0x0541,0x9D}, +{0x0542,0x00}, +{0x0543,0xBC}, +{0x0580,0x01}, +{0x0581,0x0F}, +{0x0582,0x04}, +{0x0594,0x00}, +{0x0595,0x04}, +{0x05A9,0x03}, +{0x05AA,0x40}, +{0x05AB,0x80}, +{0x05AC,0x0A}, +{0x05AD,0x10}, +{0x05AE,0x0C}, +{0x05AF,0x0C}, +{0x05B0,0x03}, +{0x05B1,0x03}, +{0x05B2,0x1C}, +{0x05B3,0x02}, +{0x05B4,0x00}, +{0x05B5,0x0C}, +{0x05B8,0x80}, +{0x05B9,0x32}, +{0x05BA,0x00}, +{0x05BB,0x80}, +{0x05BC,0x03}, +{0x05BD,0x00}, +{0x05BF,0x05}, +{0x05C0,0x10}, +{0x05C3,0x00}, +{0x05C4,0x0C}, +{0x05C5,0x20}, +{0x05C7,0x01}, +{0x05C8,0x14}, +{0x05C9,0x54}, +{0x05CA,0x14}, +{0x05CB,0xE0}, +{0x05CC,0x20}, +{0x05CD,0x00}, +{0x05CE,0x08}, +{0x05CF,0x60}, +{0x05D0,0x10}, +{0x05D1,0x05}, +{0x05D2,0x03}, +{0x05D4,0x00}, +{0x05D5,0x05}, +{0x05D6,0x05}, +{0x05D7,0x05}, +{0x05D8,0x08}, +{0x05DC,0x0C}, +{0x05D9,0x00}, +{0x05DB,0x00}, +{0x05DD,0x0F}, +{0x05DE,0x00}, +{0x05DF,0x0A}, +#if 0 +{0x05E0,0xAA}, +{0x05E1,0x00}, +{0x05E2,0xE0}, +{0x05E3,0x00}, +#else +//real setting ? +{0x05E0,0xD6}, +{0x05E1,0x00}, +{0x05E2,0x19}, +{0x05E3,0x01}, +#endif + +{0x05E4,0x04}, +{0x05E5,0x00}, +{0x05E6,0x83}, +{0x05E7,0x02}, +{0x05E8,0x06}, +{0x05E9,0x00}, +{0x05EA,0xE5}, +{0x05EB,0x01}, +{0x0660,0x04}, +{0x0661,0x16}, +{0x0662,0x04}, +{0x0663,0x28}, +{0x0664,0x04}, +{0x0665,0x18}, +{0x0666,0x04}, +{0x0667,0x21}, +{0x0668,0x04}, +{0x0669,0x0C}, +{0x066A,0x04}, +{0x066B,0x25}, +{0x066C,0x00}, +{0x066D,0x12}, +{0x066E,0x00}, +{0x066F,0x80}, +{0x0670,0x00}, +{0x0671,0x0A}, +{0x0672,0x04}, +{0x0673,0x1D}, +{0x0674,0x04}, +{0x0675,0x1D}, +{0x0676,0x00}, +{0x0677,0x7E}, +{0x0678,0x01}, +{0x0679,0x47}, +{0x067A,0x00}, +{0x067B,0x73}, +{0x067C,0x04}, +{0x067D,0x14}, +{0x067E,0x04}, +{0x067F,0x28}, +{0x0680,0x00}, +{0x0681,0x22}, +{0x0682,0x00}, +{0x0683,0xA5}, +{0x0684,0x00}, +{0x0685,0x1E}, +{0x0686,0x04}, +{0x0687,0x1D}, +{0x0688,0x04}, +{0x0689,0x19}, +{0x068A,0x04}, +{0x068B,0x21}, +{0x068C,0x04}, +{0x068D,0x0A}, +{0x068E,0x04}, +{0x068F,0x25}, +{0x0690,0x04}, +{0x0691,0x15}, +{0x0698,0x20}, +{0x0699,0x20}, +{0x069A,0x01}, +{0x069C,0x22}, +{0x069D,0x10}, +{0x069E,0x10}, +{0x069F,0x08}, +{0x0B20,0xBE}, +//{0x007C,0x33}, +{0x007C,0x40}, +{0x0B02,0x04}, +{0x0B07,0x25}, +/* +{0x0B08,0x56},// V=342 +{0x0B09,0x01}, + +{0x0B0A,0x5E},// H=606 +{0x0B0B,0x02}, + +{0x0B3E,0x01}, +*/ + + + + +{0x0B0E,0x1D}, +{0x0B0F,0x07}, +{0x0B22,0x02}, +{0x0B39,0x03}, +{0x0B11,0x7F}, +{0x0B12,0x7F}, +{0x0B17,0xE0}, +{0x0B30,0x0F}, +{0x0B31,0x02}, +{0x0B32,0x00}, +{0x0B33,0x00}, +{0x0B39,0x0F}, +{0x0B3B,0x12}, +{0x0B3F,0x01}, +{0x0024,0x40}, +//{0x0028,0x81},//test pattern enable +{0x0028,0xC0}, +{0x0000,0x01}, +{0x0100,0x01}, +{0x0101,0x01}, +{0x0005,0x01}, + +{ 0,0}, +}; + +#else +#endif + +static int hmx2056_write_reg(struct sensor_device *sensor_dev, u16 reg, u8 data) +{ + int ret; + + ret = kdp_drv_i2c_write(I2C_ADAP_0, sensor_dev->addr, reg, 2, data); + + return ret; +} + +void hmx2056_init(struct sensor_device *sensor_dev, struct sensor_init_seq *seq) +{ + struct sensor_device *dev = sensor_dev; + struct sensor_init_seq *init_fnc_ptr; + + for (init_fnc_ptr = seq; ; ++init_fnc_ptr) { + //DSG("dev->adapter=%p dev->addr=%x init_fnc_ptr->addr=%x init_fnc_ptr->value=%x", + //dev->adapter, dev->addr, init_fnc_ptr->addr, init_fnc_ptr->value); + if(init_fnc_ptr->addr == 0 && init_fnc_ptr->value == 0) break; //reaches end + hmx2056_write_reg(dev, init_fnc_ptr->addr , (u8)(init_fnc_ptr->value & 0xFF)); + } +} + +static struct hmx2056_context *to_hmx2056(const struct sensor_device *sensor_dev) +{ + return container_of(framework_drv_get_drvdata(&sensor_dev->pin_ctx), struct hmx2056_context, subdev); +} + +static const struct sensor_win_size *hmx2056_select_win(u32 *width, u32 *height) +{ + int i, default_size = ARRAY_SIZE(hmx2056_supported_win_sizes) - 1; + + for (i = 0; i < ARRAY_SIZE(hmx2056_supported_win_sizes); i++) { + if (hmx2056_supported_win_sizes[i].width >= *width && + hmx2056_supported_win_sizes[i].height >= *height) { + *width = hmx2056_supported_win_sizes[i].width; + *height = hmx2056_supported_win_sizes[i].height; + return &hmx2056_supported_win_sizes[i]; + } + } + + *width = hmx2056_supported_win_sizes[default_size].width; + *height = hmx2056_supported_win_sizes[default_size].height; + return &hmx2056_supported_win_sizes[default_size]; +} + +static +int hmx2056_set_params(struct sensor_device *sensor_dev) +{ + struct hmx2056_context *ctx = to_hmx2056(sensor_dev); + + /* initialize the sensor with default settings */ + hmx2056_init(sensor_dev, hmx2056_init_regs); + + return 0; +} + +static int hmx2056_s_power(struct v2k_subdev *sd, int on) +{ + struct sensor_device *dev = v2k_get_subdevdata(sd); + struct hmx2056_context *ctx = to_hmx2056(dev); + int ret; + + ret = 0; + return ret; +} + +static int hmx2056_reset(struct v2k_subdev *sd) +{ + //struct sensor_device *dev = v2k_get_subdevdata(sd); + //struct hmx2056_context *ctx = to_hmx2056(dev); + //int ret; + + //ret = sys_camera_power_on(&dev->pin_ctx, ssdd); + //if (ret < 0) + // return ret; + + //return ret; + + return 0; +} + +static int hmx2056_s_stream(struct v2k_subdev *sd, int enable) +{ + //struct sensor_device *dev = v2k_get_subdevdata(sd); + + return 0; +} + +static int hmx2056_enum_fmt( + struct v2k_subdev *sd, unsigned int index, unsigned int *code) +{ + if (index >= ARRAY_SIZE(hmx2056_colour_fmts)) + return -KDP_FRAMEWORK_ERRNO_INVALA; + + *code = hmx2056_colour_fmts[index].fourcc; + return 0; +} + +static int hmx2056_get_fmt(struct v2k_subdev *sd, struct v2k_format *format) +{ + //struct sensor_device *dev = v2k_get_subdevdata(sd); + + return 0; +} + +static int hmx2056_set_fmt(struct v2k_subdev *sd, struct v2k_format *format) +{ + struct v2k_format *fmt = format; + struct sensor_device *dev = v2k_get_subdevdata(sd); + + DSG("[%s]", __func__); + + hmx2056_select_win(&fmt->width, &fmt->height); + + return hmx2056_set_params(dev); +} + +static struct v2k_subdev_ops hmx2056_subdev_ops = { + .s_power = hmx2056_s_power, + .reset = hmx2056_reset, + .s_stream = hmx2056_s_stream, + .enum_fmt = hmx2056_enum_fmt, + .get_fmt = hmx2056_get_fmt, + .set_fmt = hmx2056_set_fmt, +}; + + +static int hmx2056_probe(struct sensor_device *sensor_dev) +{ + int ret; + struct hmx2056_context *ctx; + + ctx = calloc(1, sizeof(struct hmx2056_context)); + if (!ctx) + return -KDP_FRAMEWORK_ERRNO_NOMEM; + + v2k_subdev_sensor_init(&ctx->subdev, sensor_dev, &hmx2056_subdev_ops); + + //ctx->fmt = &hmx2056_colour_fmts[0]; + ret = 0; + + return ret; +} + +static int hmx2056_remove(struct sensor_device *sensor_dev) +{ + //free_bus + + return 0; +} + +extern struct core_device hmx2056_link_device; +static struct sensor_driver hmx2056_i2c_driver = { + .driver = { + .name = "sensor-hmx2056", + }, + .probe = hmx2056_probe, + .remove = hmx2056_remove, + .core_dev = &hmx2056_link_device, +}; +KDP_SENSOR_DRIVER_SETUP(hmx2056_i2c_driver); + +#endif diff --git a/platform/dev/sensor/kdev_sensor_hmxrica.c b/platform/dev/sensor/kdev_sensor_hmxrica.c new file mode 100644 index 0000000..176523d --- /dev/null +++ b/platform/dev/sensor/kdev_sensor_hmxrica.c @@ -0,0 +1,207 @@ +#include "config/board_kdp520.h" +#if V2K_ENABLE_TYPE == V2K_ENABLE_HMXRICA +#include +#include "framework/init.h" +#include "framework/framework_driver.h" +#include "framework/v2k.h" +#include "framework/v2k_image.h" +#include "framework/framework_errno.h" + +#include "media/camera/sensor.h" +#include "media/camera/sys_camera.h" +#include "media/v2k_subdev.h" +#include "utility.h" +#include "kmdw_console.h" + + +struct hmxrica_context { + struct v2k_subdev subdev; + const struct hmxrica_datafmt *fmt; +}; + +static const struct sensor_datafmt_info hmxrica_colour_fmts[] = { + { V2K_PIX_FMT_RAW8, V2K_COLORSPACE_RAW }, +}; + +static const struct sensor_win_size hmxrica_supported_win_sizes[] = { + { .width = HMX_RICA_WIDTH, .height = HMX_RICA_HEIGHT, }, +}; + +static struct sensor_init_seq hmxrica_init_regs[] = { + {0xC005, 0x49}, + {0xC073, 0x65}, + //pll PLL_O 200MHZ, MCLK is 24, where MCU SPI clock = 25MHz. + {0xC092, 0x42}, + {0xC093, 0x64}, + //pll PLL_R 200MHZ, where Uploader SPI clock = 50MHz + {0xC0B9, 0x01}, + //{0xC0A2, 0x42}, //dont need to set it , since it is default. + {0xC0A3, 0x64}, + {0xC0AA, 0x06}, + {0xC0BF, 0x03}, + {0xC0A0, 0x01}, + {0xC0BF, 0x03}, + {0xC0A0, 0x03}, + {0xC0BF, 0x03}, + //enable N9 + {0xc004, 0x00}, + {0xc0bf, 0x01}, + {0xc003, 0x00}, + {0xc0b6, 0x01}, // register for selecting group of AE Init Parameater. + {0xc07F, 0x01}, // register for selecting designated package to boot. + {0xc0bf, 0x01}, + {0xc249, 0x000}, + //{0xc24A, 0x011}, //interleave 11 + //{0xc24B, 0x011}, + //{0xc24C, 0x011}, + {0xc24A, 0x012}, //interleave 12 + {0xc24B, 0x012}, //interleave 12 + {0xc24C, 0x012}, //interleave 12 + {0xC0BF, 0x003}, + // Modified new test test pattern + {0xC026, 0x007}, + {0xC0BF, 0x003}, + {0x0, 0x0}, +}; + +static int hmxrica_write_reg(struct sensor_device *sensor_dev, u16 reg, u8 data) +{ + int ret; + + ret = kdp_drv_i2c_write(I2C_ADAP_0, sensor_dev->addr, reg, 2, data); + + return ret; +} + +void hmxrica_init(struct sensor_device *sensor_dev, struct sensor_init_seq *seq) +{ + struct sensor_device *dev = sensor_dev; + struct sensor_init_seq *init_fnc_ptr; + + for (init_fnc_ptr = seq; ; ++init_fnc_ptr) { + if(init_fnc_ptr->addr == 0 && init_fnc_ptr->value == 0) break; //reaches end + hmxrica_write_reg(dev, init_fnc_ptr->addr ,init_fnc_ptr->value); + } +} + +static struct hmxrica_context *to_hmxrica(const struct sensor_device *sensor_dev) +{ + return container_of(framework_drv_get_drvdata(&sensor_dev->pin_ctx), struct hmxrica_context, subdev); +} + +static const struct sensor_win_size *hmxrica_select_win(u32 *width, u32 *height) +{ + int i, default_size = ARRAY_SIZE(hmxrica_supported_win_sizes) - 1; + + for (i = 0; i < ARRAY_SIZE(hmxrica_supported_win_sizes); i++) { + if (hmxrica_supported_win_sizes[i].width >= *width && + hmxrica_supported_win_sizes[i].height >= *height) { + *width = hmxrica_supported_win_sizes[i].width; + *height = hmxrica_supported_win_sizes[i].height; + return &hmxrica_supported_win_sizes[i]; + } + } + + *width = hmxrica_supported_win_sizes[default_size].width; + *height = hmxrica_supported_win_sizes[default_size].height; + return &hmxrica_supported_win_sizes[default_size]; +} + +static +int hmxrica_set_params(struct sensor_device *sensor_dev) +{ + struct hmxrica_context *ctx = to_hmxrica(sensor_dev); + + /* initialize the sensor with default settings */ + + hmxrica_init(sensor_dev, hmxrica_init_regs); + + return 0; +} + +static int hmxrica_s_power(struct v2k_subdev *sd, int on) +{ + + + return 0; +} + +static int hmxrica_s_stream(struct v2k_subdev *sd, int enable) +{ + + + return 0; +} + +static int hmxrica_enum_fmt( + struct v2k_subdev *sd, unsigned int index, unsigned int *code) +{ + if (index >= ARRAY_SIZE(hmxrica_colour_fmts)) + return -KDP_FRAMEWORK_ERRNO_INVALA; + + *code = hmxrica_colour_fmts[index].fourcc; + return 0; +} + +static int hmxrica_get_fmt(struct v2k_subdev *sd, struct v2k_format *format) +{ + return 0; +} + +static int hmxrica_set_fmt(struct v2k_subdev *sd, struct v2k_format *format) +{ + struct v2k_format *fmt = format; + struct sensor_device *sensor_dev = v2k_get_subdevdata(sd); + + //DSG("[%s]", __func__); + + hmxrica_select_win(&fmt->width, &fmt->height); + + return hmxrica_set_params(sensor_dev); +} + +static struct v2k_subdev_ops hmxrica_subdev_ops = { + .s_power = hmxrica_s_power, + .s_stream = hmxrica_s_stream, + .enum_fmt = hmxrica_enum_fmt, + .get_fmt = hmxrica_get_fmt, + .set_fmt = hmxrica_set_fmt, +}; + + +static int hmxrica_probe(struct sensor_device *sensor_dev) +{ + int ret; + struct hmxrica_context *ctx; + + ctx = calloc(1, sizeof(struct hmxrica_context)); + if (!ctx) + return -KDP_FRAMEWORK_ERRNO_NOMEM; + + v2k_subdev_sensor_init(&ctx->subdev, sensor_dev, &hmxrica_subdev_ops); + + ctx->fmt = &hmxrica_colour_fmts[0]; + + ret = 0; + + return ret; +} + +static int hmxrica_remove(struct sensor_device *sensor_dev) +{ + //free_bus + return 0; +} + +extern struct core_device hmxrica_link_device; +struct sensor_driver hmxrica_i2c_driver = { + .driver = { + .name = "sensor-hmxrica", + }, + .probe = hmxrica_probe, + .remove = hmxrica_remove, + .core_dev = &hmxrica_link_device, +}; +KDP_SENSOR_DRIVER_SETUP(hmxrica_i2c_driver); + +#endif diff --git a/platform/dev/sensor/kdev_sensor_ov9286.c b/platform/dev/sensor/kdev_sensor_ov9286.c new file mode 100644 index 0000000..4d2e1b4 --- /dev/null +++ b/platform/dev/sensor/kdev_sensor_ov9286.c @@ -0,0 +1,434 @@ +#include "config/board_kdp520.h" +#if (V2K_ENABLE_TYPE == V2K_ENABLE_OV9286) || (V2K_ENABLE_TYPE == V2K_ENABLE_HMX2056_OV9286) +#include +#include "framework/init.h" +#include "framework/v2k.h" +#include "framework/v2k_image.h" +#include "framework/framework_errno.h" + +#include "media/camera/sensor.h" +#include "media/camera/sys_camera.h" +#include "media/v2k_subdev.h" +#include "utility.h" +#include "kmdw_console.h" + + +struct ov9286_context { + struct v2k_subdev subdev; + const struct sensor_datafmt_info *fmt; +}; + +static const struct sensor_datafmt_info ov9286_colour_fmts[] = { + { V2K_PIX_FMT_RAW10, V2K_COLORSPACE_RAW }, + { V2K_PIX_FMT_RAW8, V2K_COLORSPACE_RAW }, +}; + +static const struct sensor_win_size ov9286_supported_win_sizes[] = { + { .width = TFT43_WIDTH, .height = TFT43_HEIGHT, }, + { .width = VGA_LANDSCAPE_WIDTH, .height = VGA_LANDSCAPE_HEIGHT, }, +}; + +//#define JEFF_SUGGESTION +#define FPS_30 0 +#define FPS_16 1 +#define OV8286_FPS FPS_30 +//#define ORG +struct sensor_init_seq INITDATA ov9286_init_regs[] = { +{0x0100,0x00}, //software standby mode +{0x0103,0x01}, //software_reset +#ifdef ORG + {0x0302,0x32}, + {0x030d,0x50}, + {0x030e,0x02}, +#else + +{0x030A,0x00},//PLL1: pre_div0, 24/1=24MHz +{0x0300,0x01},//PLL1: pre_div, 24/1.5=16MHz +{0x0301,0x00}, +{0x0302,0x32},//PLL1: mul, 16MHz*50=800MHz +{0x0305,0x02},//PLL1: sys_pre_div, 800/5=160MHz +{0x0306,0x01},//PLL1: sys_div, 160/2=80MHz (PLL1 sys clk) +{0x0303,0x00},//PLL1: MIPI pre div, 800/1=800MHz +{0x0304,0x03},//PLL1: MIPI div, 800/8=100MHz, (PLL1 pixclk)(MIPI_PCLK) -> *8=800Mbps(MIPI_CLK) + +{0x0314,0x00},//PLL2: pre_div0, 24/1=24HMz +{0x030B,0x04},//PLL2: pre div, 24/3=8MHz +{0x030C,0x00}, +{0x030D,0x50},//PLL2: mul, 8MHz*80=640MHz +{0x030F,0x03},//PLL2: sys_pre_div, 640/4=160MHz +{0x030E,0x02},//PLL2, sys_div, 160/2=80MHz (PLL2 sys clk) +{0x0313,0x01},//PLL2, ADC div, 640/2=320MHz +{0x0312,0x07},//PLL2, analog div, 640/8=80MHz +#endif + +{0x3001,0x00}, //drive strength control +{0x3004,0x00}, //GPIO2 output enable : input. D9 output enable : input +{0x3005,0x00}, //Bit[0] ~ B it[7] : input +{0x3006,0x04}, //ILPWM : output. D0/PCLK/HREF/Strobe output/VSYNC : input +{0x3011,0x0a}, //mipi_pad : 1, pgm_vcm : high speed common mode voltage +{0x3013,0x18}, //pgm_lptx (Driving strength control of low speed tx), r_iref +{0x301c,0xf0}, //sclk_bist/sclk_srb/sclk_grp : 1 +{0x3022,0x01}, //pd_mipi enable when rst_sync +{0x3030,0x10}, //r_aslp_repeat +{0x3039,0x12}, //mipi_en (0:DVB 1:MIPI) phy_rst (1:Reset PHY when rst_sync) +{0x303a,0x00}, //MIPI lane disable : 0 +{0x3500,0x00}, //exposure + +#ifdef JEFF_SUGGESTION +//second +//{0x3501,0x2a}, //exposure +//{0x3502,0x90}, //exposure time : f +//third +{0x3501,0x38}, //exposure +{0x3502,0x20}, //exposure time : f +#else +{0x3501,0x01}, //exposure +{0x3502,0xf4}, //exposure time : f +#endif + +{0x3503,0x08}, //gain_prec16_en +{0x3505,0x8c}, //gain conversation option. dac_finegain_highbit : 1; +{0x3507,0x03}, //GAIN SHIFT. left shift 3 bit. +{0x3508,0x00}, //Debug mode +{0x3509,0x10}, //Gain. 1x gain +{0x3610,0x80}, +{0x3611,0xa0}, +{0x3620,0x6e}, +{0x3632,0x56}, +{0x3633,0x78}, + +#if IMGSRC_1_FORMAT == IMG_FORMAT_RAW10 +{0x3662,0x00},//RAW10 +#elif IMGSRC_1_FORMAT == IMG_FORMAT_RAW8 +{0x3662,0x02},//RAW8 +#endif + +{0x3666,0x00}, // output selection 0x0:VSYNC. from fsin pin, used for both frame sync and frame rigger function +{0x366f,0x5a}, +{0x3680,0x84}, +{0x3712,0x80}, +{0x372d,0x22}, +{0x3731,0x80}, +{0x3732,0x30}, + +#ifdef JEFF_SUGGESTION +{0x3778,0x00}, // 2x vertical binning enable for monochrome mode +#else +{0x3778,0x10}, // 2x vertical binning enable for monochrome mode +#endif + +{0x377d,0x22}, +{0x3788,0x02}, +{0x3789,0xa4}, +{0x378a,0x00}, +{0x378b,0x4a}, +{0x3799,0x20}, +{0x3800,0x00}, // array horizontal start point high +{0x3801,0x00}, // array horizontal start point low +{0x3802,0x00}, // array vertical start point high +{0x3803,0x00}, // array vertical start point low + +{0x3804,0x05}, // array horizontal end point high byte +{0x3805,0x0f}, // array horizontal end point low byte +{0x3806,0x03}, // array vertical end point high byte +{0x3807,0x2f}, // array vertical end point low byte + +#if IMGSRC_1_RES == SENSOR_RES_640_480 + {0x3808,0x02}, // isp horizontal output width high byte + {0x3809,0x80}, // isp horizontal output width low byte + {0x380a,0x01}, // isp vertical output height high byte + {0x380b,0xe0}, // isp vertical output height low byte +#elif IMGSRC_1_RES == SENSOR_RES_480_272 + {0x3808,0x01}, // isp horizontal output width high byte + {0x3809,0xe0}, // isp horizontal output width low byte + {0x380a,0x01}, // isp vertical output height high byte + {0x380b,0x10}, // isp vertical output height low byte +#endif + + +{0x380c,0x02}, // total horizontal timing size high byte +{0x380d,0xd8}, // total horizontal timing size low byte + +#ifdef JEFF_SUGGESTION + #if OV8286_FPS == FPS_30 + {0x380e,0x0e}, + {0x380f,0x38}, + #elif OV8286_FPS == FPS_16 + {0x380e,0x1a}, + {0x380f,0xb0}, + #endif +#else +{0x380e,0x02}, // total vertical timing size high byte +{0x380f,0x25}, // total vertical timing size low byte +#endif + +#ifdef JEFF_SUGGESTION +{0x3810,0x00}, // isp horizontal windowing offset high byte +{0x3811,0x08}, // isp horizontal windowing offset low byte +{0x3812,0x00}, // isp vertical windowing offset high byte +{0x3813,0x08}, // isp vertical windowing offset low byte +{0x3814,0x11}, // x_odd_inc : 3, x_even_inc : 1 +{0x3815,0x11}, // y_odd_inc : 2, y_even_inc : 2 +{0x3820,0x40}, // Vflip. vflip_blc : 0 +{0x3821,0x00}, // 4x horizontal binning enable +#else +{0x3810,0x00}, // isp horizontal windowing offset high byte +{0x3811,0x54}, // isp horizontal windowing offset low byte +{0x3812,0x00}, // isp vertical windowing offset high byte +{0x3813,0x6c}, // isp vertical windowing offset low byte +{0x3814,0x31}, // x_odd_inc : 3, x_even_inc : 1 +{0x3815,0x22}, // y_odd_inc : 2, y_even_inc : 2 +{0x3820,0x04}, // Vflip. vflip_blc : 0 +{0x3821,0x01}, // 4x horizontal binning enable +#endif + + +{0x382c,0x05}, +{0x382d,0xb0}, +{0x389d,0x00}, +{0x3881,0x42}, +{0x3882,0x01}, +{0x3883,0x00}, +{0x3885,0x02}, +{0x38a8,0x02}, +{0x38a9,0x80}, +{0x38b1,0x00}, +{0x38b3,0x02}, +{0x38c4,0x00}, +{0x38c5,0xc0}, +{0x38c6,0x04}, +{0x38c7,0x80}, +{0x3920,0xff}, // strobe_pattern +{0x4003,0x40}, + +#ifdef JEFF_SUGGESTION +{0x4008,0x04}, // r_up_bl_start_o +{0x4009,0x0b}, // r_up_bl_end_o +#else +{0x4008,0x02}, // r_up_bl_start_o +{0x4009,0x05}, // r_up_bl_end_o +#endif + +{0x400c,0x00}, // r_dn_bl_start_o + +#ifdef JEFF_SUGGESTION +{0x400d,0x07}, // r_dn_bl_end_o +#else +{0x400d,0x03}, // r_dn_bl_end_o +#endif + + +{0x4010,0x40}, // r_gain_chg_trig_en_o +{0x4043,0x40}, // r_bot_blk_in_en_o +{0x4307,0x30}, // embed_st=3 +{0x4317,0x00}, // dvp enable = 0 +{0x4501,0x00}, + +#ifdef JEFF_SUGGESTION +{0x4507,0x00}, +{0x4509,0x00}, +#else +{0x4507,0x03}, +{0x4509,0x80}, +#endif + +{0x450a,0x08}, + +#ifdef JEFF_SUGGESTION +//which one ??? +//first time +//{0x4601,0x4f}, // VFIFO read start point low byte +//second time +{0x4601,0x04}, // VFIFO read start point low byte +#else +{0x4601,0x04}, // VFIFO read start point low byte +#endif + +{0x470f,0x00}, // BYP_SEL, href_sel, bypass_sel = 0 +{0x4f07,0x00}, // r_pchg_st_offs ? +{0x4800,0x00}, // clklane first bit = 8'h55, use falling edge of mipi_pclk_o to generate MIPI bus to PHY +#ifdef JEFF_SUGGESTION +{0x4837,0x14}, +#endif + +#ifdef JEFF_SUGGESTION +{0x5000,0x87}, // isp_sof_sel = 2, bc_en, wc_en, dpc_buf_en, awbg_en, blc_en +#else +{0x5000,0x9f}, // isp_sof_sel = 2, bc_en, wc_en, dpc_buf_en, awbg_en, blc_en +#endif + +{0x5001,0x00}, // bypass_isp0, bypass_isp1 +{0x5e00,0x00}, // disable test pattern +{0x5d00,0x07}, +{0x5d01,0x00}, +{0x4f00,0x04}, // r_psv_mode_en : enable +{0x4f10,0x00}, // ana_psv_pch[15:8] +{0x4f11,0x98}, // ana_psv_pch[7:0] +{0x4f12,0x0f}, // ana_psv_strm +{0x4f13,0xc4}, // ana_psv_strm + +{0x3501,0x20}, // exposure +{0x3502,0x20}, // exposure + +{0x5E00,0x80}, + +{0x0100,0x01}, // streaming +{ 0,0}, +}; + + +static int ov9286_write_reg(struct sensor_device *sensor_dev, u16 reg, u8 data) +{ + int ret; + + ret = kdp_drv_i2c_write(I2C_ADAP_0, sensor_dev->addr, reg, 2, data); + + return ret; +} + +void ov9286_init(struct sensor_device *sensor_device, struct sensor_init_seq *seq) +{ + struct sensor_device *sensor_dev = sensor_device; + struct sensor_init_seq *init_fnc_ptr; + + for (init_fnc_ptr = seq; ; ++init_fnc_ptr) { + if(init_fnc_ptr->addr == 0 && init_fnc_ptr->value == 0) { DSG("byte"); break; }//reaches end + ov9286_write_reg(sensor_dev, init_fnc_ptr->addr , (u8)(init_fnc_ptr->value & 0xFF)); + } + //DSG("%s done", __func__); +} + +static struct ov9286_context *to_ov9286(const struct sensor_device *sensor_dev) +{ + return container_of(framework_drv_get_drvdata(&sensor_dev->pin_ctx), struct ov9286_context, subdev); +} + +static const struct sensor_win_size *ov9286_select_win(u32 *width, u32 *height) +{ + int i, default_size = ARRAY_SIZE(ov9286_supported_win_sizes) - 1; + + for (i = 0; i < ARRAY_SIZE(ov9286_supported_win_sizes); i++) { + if (ov9286_supported_win_sizes[i].width >= *width && + ov9286_supported_win_sizes[i].height >= *height) { + *width = ov9286_supported_win_sizes[i].width; + *height = ov9286_supported_win_sizes[i].height; + return &ov9286_supported_win_sizes[i]; + } + } + + *width = ov9286_supported_win_sizes[default_size].width; + *height = ov9286_supported_win_sizes[default_size].height; + return &ov9286_supported_win_sizes[default_size]; +} + +static +int ov9286_set_params(struct sensor_device *sensor_dev) +{ + struct ov9286_context *ctx = to_ov9286(sensor_dev); + + //DSG("[%s] ctx=%p fourcc=%x", __func__, ctx, fourcc); + DSG("ov9286_init start"); + /* initialize the sensor with default settings */ + ov9286_init(sensor_dev, ov9286_init_regs); + DSG("ov9286_init end"); + + return 0; +} + +static int ov9286_s_power(struct v2k_subdev *sd, int on) +{ + int ret; + + DSG("%s", __func__); + + ret = 0; + + return ret; +} + +static int ov9286_reset(struct v2k_subdev *sd) +{ + //DSG("%s", __func__); + return 0; +} + +static int ov9286_s_stream(struct v2k_subdev *sd, int enable) +{ + return 0; +} + +static int ov9286_enum_fmt( + struct v2k_subdev *sd, unsigned int index, unsigned int *code) +{ + if (index >= ARRAY_SIZE(ov9286_colour_fmts)) + return -KDP_FRAMEWORK_ERRNO_INVALA; + + *code = ov9286_colour_fmts[index].fourcc; + return 0; +} + +static int ov9286_get_fmt(struct v2k_subdev *sd, struct v2k_format *format) +{ + struct sensor_device *sensor_dev = v2k_get_subdevdata(sd); + + return 0; +} + +static int ov9286_set_fmt(struct v2k_subdev *sd, struct v2k_format *format) +{ + struct v2k_format *fmt = format; + struct sensor_device *sensor_dev = v2k_get_subdevdata(sd); + + DSG("[%s]", __func__); + + ov9286_select_win(&fmt->width, &fmt->height); + + return ov9286_set_params(sensor_dev); +} + +static struct v2k_subdev_ops ov9286_subdev_ops = { + .s_power = ov9286_s_power, + .reset = ov9286_reset, + .s_stream = ov9286_s_stream, + .enum_fmt = ov9286_enum_fmt, + .get_fmt = ov9286_get_fmt, + .set_fmt = ov9286_set_fmt, +}; + +static int ov9286_probe(struct sensor_device *sensor_dev) +{ + int ret; + struct ov9286_context *ctx; + + ctx = calloc(1, sizeof(struct ov9286_context)); + if (!ctx) + return -KDP_FRAMEWORK_ERRNO_NOMEM; + + v2k_subdev_sensor_init(&ctx->subdev, sensor_dev, &ov9286_subdev_ops); + + ctx->fmt = &ov9286_colour_fmts[0]; + + ret = 0; + + return ret; +} + +static int ov9286_remove(struct sensor_device *sensor_dev) +{ + //free_bus + + return 0; +} + +extern struct core_device ov9286_link_device; +static struct sensor_driver ov9286_i2c_driver = { + .driver = { + .name = "sensor-ov9286", + }, + .probe = ov9286_probe, + .remove = ov9286_remove, + .core_dev = &ov9286_link_device, +}; +KDP_SENSOR_DRIVER_SETUP(ov9286_i2c_driver); + +#endif diff --git a/platform/dev/sensor/kdev_sensor_sc132gs.c b/platform/dev/sensor/kdev_sensor_sc132gs.c new file mode 100644 index 0000000..890ef8f --- /dev/null +++ b/platform/dev/sensor/kdev_sensor_sc132gs.c @@ -0,0 +1,421 @@ +/* + * Kneron SC132GS sensor driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "utility.h" +#include "board.h" +#include "kmdw_sensor.h" +//#include "kmdw_console.h" +#include "kdev_sensor.h" +#include "kdrv_i2c.h" + +//#define SC132GS_DBG +#ifdef SC132GS_DBG +#define sensor_msg(fmt, ...) err_msg("[%s] " fmt, __func__, ##__VA_ARGS__) +#else +#define sensor_msg(fmt, ...) +#endif +static const struct sensor_datafmt_info sc132gs_colour_fmts[] = { + { PIX_FMT_RAW8, COLORSPACE_RAW }, +}; + +static struct sensor_device sc132gs_dev = { + .addr = 0x30, +}; + +struct sensor_init_seq sc132gs_init_regs[] = { + {0x0103, 0x01}, + {0x0100, 0x00}, + + //PLL bypass + {0x36e9, 0x80}, + {0x36f9, 0x80}, + + {0x0100, 0x00}, + {0x3018, 0x12}, + {0x3019, 0x0e}, + {0x301a, 0xb4}, + {0x3031, 0x08}, // 0X0A:RAW10;0X08:RAW8 + {0x3032, 0x60}, + {0x3038, 0x44}, + {0x3207, 0x17}, + {0x320c, 0x06}, + {0x320d, 0x40}, + //{0x320e, 0x05}, // for 50 frame rate + //{0x320f, 0x46}, + {0x320e, 0x0A}, // for 25 frame rate + {0x320f, 0x8C}, + {0x3250, 0xcc}, + {0x3251, 0x02}, + {0x3252, 0x05}, + {0x3253, 0x41}, + {0x3254, 0x05}, + {0x3255, 0x3b}, + {0x3306, 0x78}, + {0x330a, 0x00}, + {0x330b, 0xc8}, + {0x330f, 0x24}, + {0x3314, 0x80}, + {0x3315, 0x40}, + {0x3317, 0xf0}, + {0x331f, 0x12}, + {0x3364, 0x00}, + {0x3385, 0x41}, + {0x3387, 0x41}, + {0x3389, 0x09}, + {0x33ab, 0x00}, + {0x33ac, 0x00}, + {0x33b1, 0x03}, + {0x33b2, 0x12}, + {0x33f8, 0x02}, + {0x33fa, 0x01}, + {0x3409, 0x08}, + {0x34f0, 0xc0}, + {0x34f1, 0x20}, + {0x34f2, 0x03}, + {0x3622, 0xf5}, + {0x3630, 0x5c}, + {0x3631, 0x80}, + {0x3632, 0xc8}, + {0x3633, 0x32}, + {0x3638, 0x2a}, + {0x3639, 0x07}, + {0x363b, 0x48}, + {0x363c, 0x83}, + {0x363d, 0x10}, + {0x36ea, 0x3a}, + {0x36fa, 0x25}, + {0x36fb, 0x05}, + {0x36fd, 0x04}, + {0x3900, 0x11}, + {0x3901, 0x05}, + {0x3902, 0xc5}, + {0x3904, 0x04}, + {0x3908, 0x91}, + {0x391e, 0x00}, + {0x3e00, 0x00}, // AEC + {0x3e01, 0xA8}, // {0x3e01, 0x53}, + {0x3e02, 0x40}, // {0x3e02, 0xe0}, + //{0x3e08, 0x23}, // AGC = 2 + //{0x3e09, 0x24}, // AGC + //{0x3e08, 0x03}, // AGC = 1 + //{0x3e09, 0x20}, // AGC + {0x3e08, 0x27}, // AGC = 4 + {0x3e09, 0x24}, // AGC + {0x3e0e, 0xd2}, + {0x3e14, 0xb0}, + {0x3e1e, 0x7c}, + {0x3e26, 0x20}, + {0x4418, 0x38}, + {0x4503, 0x10}, + {0x4837, 0x14}, + {0x5000, 0x0e}, + {0x540c, 0x51}, + {0x550f, 0x38}, + {0x5780, 0x67}, + {0x5784, 0x10}, + {0x5785, 0x06}, + {0x5787, 0x02}, + {0x5788, 0x00}, + {0x5789, 0x00}, + {0x578a, 0x02}, + {0x578b, 0x00}, + {0x578c, 0x00}, + {0x5790, 0x00}, + {0x5791, 0x00}, + {0x5792, 0x00}, + {0x5793, 0x00}, + {0x5794, 0x00}, + {0x5795, 0x00}, + {0x5799, 0x04}, + + //Vbin + {0x3220, 0x87}, + {0x3215, 0x22}, + + {0x3213, 0x08}, + {0x320a, 0x02}, // 640 + {0x320b, 0x80}, + + {0x334f, 0xbe}, + {0x3231, 0x0a}, + {0x3230, 0x0c}, + + //Hsum + {0x5000, 0x40}, + {0x5901, 0x14}, + {0x5900, 0xf6}, + + {0x3208, 0x01}, // 480 + {0x3209, 0xe0}, + + {0x36ec, 0x03}, + {0x3211, 0x1e}, + + //2lane mipi + {0x3019, 0x0c}, //[3:0] lane disable + {0x3018, 0x32}, //[6:5] lane num=[6:5]+1 + + {0x0100, 0x01}, + + //PLL set + {0x36e9, 0x24}, + {0x36f9, 0x24}, + + // [gain>=2] + {0x33f8, 0x02}, + {0x3314, 0x80}, + {0x33fa, 0x02}, + {0x3317, 0x00}, + +#ifdef MIPI_EXAMPLE + // test mode + {0x4501, 0xAC}, // Bit[3]:incremental pattern enable + {0x3902, 0x85}, + {0x391d, 0xa8}, + {0x3e06, 0x03}, +#endif + +#if 0 // flip & mirror + {0x323b, 0x01}, // flip on + {0x3221, 0x66}, // bit[6:5]00:flip off,11:flip on; bit[2:1]00:mirror off,11:mirror on; +#endif +#if 1 // flip + {0x323b, 0x03}, // flip on + {0x3221, 0x60}, // bit[6:5]00:flip off,11:flip on; bit[2:1]00:mirror off,11:mirror on; +#endif +#if 0 // mirror + //{0x323b, 0x03}, // flip on + {0x3221, 0x06}, // bit[6:5]00:flip off,11:flip on; bit[2:1]00:mirror off,11:mirror on; +#endif + + { 0x00, 0x00}, +}; +static uint32_t kdev_sensor_get_dev_id(void); +static void nir_set_exp_time(uint8_t ana_gn1, uint8_t ana_gn2) +{ + uint16_t dev_addr = sc132gs_dev.addr; + + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3e01, 2, 1, &ana_gn1); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3e02, 2, 1, &ana_gn2); +} + +static void nir_set_gain(uint8_t ana_gn1, uint8_t ana_gn2) +{ + uint16_t dev_addr = sc132gs_dev.addr; + + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3e08, 2, 1, &ana_gn1); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3e09, 2, 1, &ana_gn2); +} + +static void nir_led_open(void) +{ + uint16_t dev_addr = sc132gs_dev.addr; + uint8_t data = 0x00; + + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3361, 2, 1, &data); +} + +static void nir_led_close(void) +{ + uint16_t dev_addr = sc132gs_dev.addr; + uint8_t data = 0xc0; + + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3361, 2, 1, &data); +} + +static uint32_t sc132gs_write_reg(struct sensor_device *sensor_dev, uint16_t reg, uint8_t data) +{ + uint32_t ret; + + ret = kdrv_i2c_write_register(KDRV_I2C_CTRL_0, sensor_dev->addr, reg, 2, 1, &data); + return ret; +} + +static uint32_t sc132gs_read_reg(struct sensor_device *sensor_dev, uint16_t reg, uint8_t *data) +{ + uint32_t ret; + + ret = kdrv_i2c_read_register(KDRV_I2C_CTRL_0, sensor_dev->addr, reg, 2, 1, data); + return ret; +} + +void sc132gs_init(struct sensor_device *sensor_dev, struct sensor_init_seq *seq) +{ + struct sensor_device *dev = sensor_dev; + struct sensor_init_seq *init_fnc_ptr; + + for (init_fnc_ptr = seq; ; ++init_fnc_ptr) + { + if(init_fnc_ptr->addr == 0 && init_fnc_ptr->value == 0) + break; //reaches end + sc132gs_write_reg(dev, init_fnc_ptr->addr , (uint8_t)(init_fnc_ptr->value & 0xFF)); + } + + uint32_t data = kdev_sensor_get_dev_id(); + sensor_msg(" sc132gs_init sensor id = %x\n", data); +} + +static uint32_t sc132gs_set_params(struct sensor_device *sensor_dev) +{ + /* initialize the sensor with default settings */ + sc132gs_init(sensor_dev, sc132gs_init_regs); + + return 0; +} + +static kdev_status_t kdev_sensor_power(uint32_t on) +{ + sensor_msg(" <%s>\n", __func__); + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_reset() +{ + sensor_msg(" <%s>\n", __func__); + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_stream(uint32_t enable) +{ + sensor_msg(" <%s>\n", __func__); + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_enum_fmt(uint32_t index, uint32_t *code) +{ + if (index >= ARRAY_SIZE(sc132gs_colour_fmts)) + return KDEV_STATUS_ERROR; + + sensor_msg(" <%s>\n", __func__); + *code = sc132gs_colour_fmts[index].fourcc; + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_get_fmt(struct cam_format *format) +{ + sensor_msg(" <%s>\n", __func__); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_set_fmt(struct cam_format *fmt) +{ + sensor_msg(" <%s>\n", __func__); + + return (kdev_status_t)sc132gs_set_params(&sc132gs_dev); +} + +static kdev_status_t kdev_sensor_set_gain(uint32_t gain1, uint32_t gain2) +{ + sensor_msg(" <%s>\n", __func__); + + nir_set_gain(gain1, gain2); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_set_exp_time(uint32_t gain1, uint32_t gain2) +{ + sensor_msg(" <%s>\n", __func__); + + nir_set_exp_time(gain1, gain2); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_led_switch(uint32_t on) +{ + sensor_msg(" <%s>\n", __func__); + + if (on) + nir_led_open(); + else + nir_led_close(); + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_set_mirror(uint32_t enable) +{ + uint16_t dev_addr = sc132gs_dev.addr; + uint8_t data = 0; + + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 0x3221, 2, 1, &data); + data &= ~0x06; + + if (enable) + { + data |= 0x06; + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3221, 2, 1, &data); + } + else + { + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3221, 2, 1, &data); + } + + return KDEV_STATUS_OK; +} + +static kdev_status_t kdev_sensor_set_flip(uint32_t enable) +{ + uint16_t dev_addr = sc132gs_dev.addr; + uint8_t data = 0, data1; + + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, dev_addr, 0x3221, 2, 1, &data); + data &= ~0x60; + + if (enable) + { + data1 = 0x01; + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x323b, 2, 1, &data1); + data |= 0x60; + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3221, 2, 1, &data); + } + else + { + data1 = 0x00; + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x323b, 2, 1, &data1); + kdrv_i2c_write_register(KDRV_I2C_CTRL_0, dev_addr, 0x3221, 2, 1, &data); + } + + return KDEV_STATUS_OK; +} + +static uint32_t kdev_sensor_get_dev_id(void) +{ + uint8_t data = 0; + uint16_t id = 0; + + sc132gs_read_reg(&sc132gs_dev, 0x3107, &data); + id = data<<8; + sc132gs_read_reg(&sc132gs_dev, 0x3108, &data); + id += data; + return (uint32_t)id; +} + +static struct sensor_ops sc132gs_ops = { + .s_power = kdev_sensor_power, + .reset = kdev_sensor_reset, + .s_stream = kdev_sensor_stream, + .enum_fmt = kdev_sensor_enum_fmt, + .get_fmt = kdev_sensor_get_fmt, + .set_fmt = kdev_sensor_set_fmt, + .set_gain = kdev_sensor_set_gain, + .set_aec = NULL, + .set_exp_time = kdev_sensor_set_exp_time, + .get_lux = NULL, + .led_switch = kdev_sensor_led_switch, + .set_mirror = kdev_sensor_set_mirror, + .set_flip = kdev_sensor_set_flip, + .get_dev_id = kdev_sensor_get_dev_id, +}; + +struct sensor_ops* kdev_sensor_sc132gs_get_ops(void) +{ + return &sc132gs_ops; +} diff --git a/platform/dev/wifi/BufList/BufList.c b/platform/dev/wifi/BufList/BufList.c new file mode 100644 index 0000000..1c234be --- /dev/null +++ b/platform/dev/wifi/BufList/BufList.c @@ -0,0 +1,918 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2019 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 12. November 2019 + * $Revision: V1.0 + * + * Project: Buffering using CMSIS-RTOS2 memory pools as storage + * -------------------------------------------------------------------------- */ + +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 +#include "BufList.h" + +/* + Head buffer: first in list, contains oldest buffer, where read operation starts + Tail buffer: last in list, contains newest buffer, where write operation starts +*/ + +typedef struct { + Link_t link; /* Linked list */ + uint16_t wri; /* Buffer write index */ + uint16_t rdi; /* Buffer read index */ + uint8_t data[]; /* Buffered data */ +} MEM_BUF; + +/* Lock buffer access */ +static void Lock (BUF_LIST *p) { + if (p->mutex != NULL) { + osMutexAcquire (p->mutex, osWaitForever); + } +} + +/* Unlock buffer access */ +static void Unlock (BUF_LIST *p) { + if (p->mutex != NULL) { + osMutexRelease (p->mutex); + } +} + +/* Allocate memory block, put it into buffer list and return pointer to buffer */ +static MEM_BUF *Alloc (BUF_LIST *p) { + MEM_BUF *buf_cb; + Link_t *buf_link; + + buf_cb = (MEM_BUF *)osMemoryPoolAlloc (p->mp_id, 0U); + + if (buf_cb != NULL) { + /* Buffer allocated, add it to list */ + buf_link = (Link_t *)buf_cb; + + ListPut (&p->list, buf_link); + + buf_cb->wri = 0U; //Write index + buf_cb->rdi = 0U; //Read index + } + + return (buf_cb); +} + +/* Get buffer from list, free memory block and return next buffer in list */ +static MEM_BUF *Free (BUF_LIST *p) { + MEM_BUF *buf_cb; + + buf_cb = (MEM_BUF *)ListGet (&p->list); + + if (osMemoryPoolFree (p->mp_id, buf_cb) == osOK) { + /* Peek next */ + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + } + + return (buf_cb); +} + +/* Get the size of one block in buffer memory pool */ +static uint16_t Size (BUF_LIST *p) { + uint16_t sz; + + sz = p->bl_sz; + + if (sz != 0U) { + /* Memory pool block size reduced for buffer header */ + sz -= sizeof(MEM_BUF); + } + + return (sz); +} + +/** + Initialize buffer list. +*/ +int32_t BufInit (void *mp_id, void *mutex, BUF_LIST *p) { + int32_t rval; + uint32_t bl_sz; + + if ((p == NULL) || (mp_id == NULL)) { + /* Buffer list or memory pool invalid */ + rval = -1; + } + else { + bl_sz = osMemoryPoolGetBlockSize (mp_id); + + if (bl_sz > UINT16_MAX) { + /* Not supported */ + rval = -1; + } + else { + p->mutex = mutex; + p->mp_id = mp_id; + p->bl_sz = (uint16_t)bl_sz; + + ListInit (&p->list); + + rval = 0; + } + } + + return (rval); +} + +/** + Uninitialize buffer list. +*/ +int32_t BufUninit (BUF_LIST *p) { + int32_t rval; + MEM_BUF *buf_cb; + + if (p == NULL) { + rval = -1; + } + else { + /* Free all blocks */ + do { + buf_cb = Free (p); + } + while (buf_cb != NULL); + + ListInit (&p->list); + + rval = 0; + } + return (rval); +} + + +BUF_MEM *BufAlloc (BUF_LIST *p) { + MEM_BUF *buf_cb; + BUF_MEM *usr_cb; //User control block + + Lock(p); + + buf_cb = Alloc (p); + + if (buf_cb != NULL) { + /* Set pointer to write index */ + usr_cb = (BUF_MEM *)&buf_cb->wri; + } else { + /* Out of memory */ + usr_cb = NULL; + } + + Unlock(p); + + return (usr_cb); +} + + +BUF_MEM *BufFree (BUF_LIST *p) { + MEM_BUF *buf_cb; + BUF_MEM *usr_cb; //User control block + + Lock(p); + + buf_cb = Free (p); + + if (buf_cb != NULL) { + /* Set pointer to write index */ + usr_cb = (BUF_MEM *)&buf_cb->wri; + } else { + /* Should never happen */ + usr_cb = NULL; + } + + Unlock(p); + + return (usr_cb); +} + +/* + - Retrieve current buffer + -- If current buffer is not allocated, allocate it + -- If current buffer is full, allocate new + -- If out of memory, return NULL +*/ +BUF_MEM *BufGetTail (BUF_LIST *p) { + MEM_BUF *buf_cb; + BUF_MEM *usr_cb; //User control block + + Lock(p); + + usr_cb = NULL; + buf_cb = (MEM_BUF *)ListPeekTail(&p->list); + + if (buf_cb != NULL) { + if (buf_cb->wri < Size (p)) { + /* Set pointer to wri member */ + usr_cb = (BUF_MEM *)&buf_cb->wri; + } + } + + if (usr_cb == NULL) { + /* Allocate new buffer */ + usr_cb = BufAlloc (p); + } + + Unlock(p); + + return (usr_cb); +} + + +uint16_t BufGetSize (BUF_LIST *p) { + uint16_t sz; + + Lock(p); + + sz = Size (p); + + Unlock(p); + + return ((uint16_t)sz); +} + +uint32_t BufGetFree (BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t maxi, sz; + + Lock(p); + + /* Size of one buffer (mem pool block - header */ + maxi = Size (p); + + /* Multiplied by the number of free memory pool blocks */ + sz = maxi * osMemoryPoolGetSpace (p->mp_id); + + /* Add number of bytes available in the tail buffer */ + buf_cb = (MEM_BUF *)ListPeekTail(&p->list); + + if (buf_cb != NULL) { + sz += (maxi - buf_cb->wri); + } + + Unlock(p); + + return (sz); +} + +/** + Retrieve number of bytes in the buffer. +*/ +uint32_t BufGetCount (BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t n; + + Lock(p); + + n = 0U; + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + while (buf_cb != NULL) { + /* Determine number of bytes in the current buffer */ + n += (buf_cb->wri - buf_cb->rdi); + + /* Load next buffer */ + buf_cb = (MEM_BUF *)ListPeekNext ((Link_t *)buf_cb); + } + + Unlock(p); + + /* Return total number of bytes in the buffer */ + return (n); +} + + +int32_t BufReadByte (BUF_LIST *p) { + MEM_BUF *buf_cb; + int32_t rval; + + Lock(p); + + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + if (buf_cb != NULL) { + if (buf_cb->rdi == buf_cb->wri) { + /* End of current buffer, free it */ + if (buf_cb->wri == Size(p)) { + buf_cb = Free(p); + } else { + buf_cb = NULL; + } + } + } + + if (buf_cb != NULL) { + /* Return current byte */ + rval = buf_cb->data[buf_cb->rdi++]; + } + else { + /* End of chain */ + rval = -1; + } + + Unlock(p); + + return (rval); +} + +int32_t BufPeekByte (BUF_LIST *p) { + MEM_BUF *buf_cb; + int32_t rval; + + Lock(p); + + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + if (buf_cb != NULL) { + if (buf_cb->rdi == buf_cb->wri) { + /* End of current buffer, free it */ + if (buf_cb->wri == Size(p)) { + buf_cb = Free(p); + } else { + buf_cb = NULL; + } + } + } + + if (buf_cb != NULL) { + if (buf_cb->rdi == buf_cb->wri) { + /* End of current buffer */ + rval = -1; + } + else { + rval = buf_cb->data[buf_cb->rdi]; + } + } + else { + /* No data */ + rval = -1; + } + + Unlock(p); + + return (rval); +} + +int32_t BufPeekOffs (uint32_t offs, BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t rdi = 0; + int32_t n; + + Lock(p); + + n = -1; //End of buffer + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + if (buf_cb != NULL) { + rdi = buf_cb->rdi; + } + + while (buf_cb != NULL) { + + if (rdi == buf_cb->wri) { + /* End of current buffer, peek next */ + buf_cb = (MEM_BUF *)ListPeekNext ((Link_t *)buf_cb); + + if (buf_cb == NULL) { + /* End of buffer */ + n = -1; + } + + /* Reset read index */ + rdi = 0U; + } + else { + if (offs != 0U) { + offs--; + rdi++; + } + else { + /* Return byte at specified offset */ + n = buf_cb->data[rdi]; + break; + } + } + } + + Unlock(p); + + return (n); +} + +int32_t BufFlushByte (BUF_LIST *p) { + MEM_BUF *buf_cb; + int32_t rval; + + Lock(p); + + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + if (buf_cb != NULL) { + if (buf_cb->rdi == buf_cb->wri) { + /* End of current buffer, free it */ + if (buf_cb->wri == Size(p)) { + buf_cb = Free(p); + } else { + buf_cb = NULL; + } + } + } + + if (buf_cb != NULL) { + if (buf_cb->rdi == buf_cb->wri) { + /* End of current buffer */ + rval = -1; + } + else { + /* Read byte and increment read index */ + rval = buf_cb->data[buf_cb->rdi++]; + } + } + else { + /* End of chain */ + rval = -1; + } + + Unlock(p); + + return (rval); +} + +int32_t BufWriteByte (uint8_t data, BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t maxi; + int32_t rval; + + Lock(p); + + maxi = Size (p); + + buf_cb = (MEM_BUF *)ListPeekTail(&p->list); + + if ((buf_cb == NULL) || (buf_cb->wri == maxi)) { + /* Buffer full, allocate new */ + buf_cb = Alloc (p); + } + + if (buf_cb != NULL) { + buf_cb->data[buf_cb->wri++] = data; + + rval = data; + } + else { + rval = -1; + } + + Unlock(p); + + return (rval); +} + +/* + Read num of bytes into buf and return number of bytes actually read. +*/ +int32_t BufRead (uint8_t *buf, uint32_t num, BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t n; + + Lock(p); + + n = 0; + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + while (buf_cb != NULL) { + + if (buf_cb->rdi == buf_cb->wri) { + /* End of current buffer, free current, get next one */ + if (buf_cb->wri == Size(p)) { + buf_cb = Free(p); + } else { + buf_cb = NULL; + } + } + else { + while (n < num) { + buf[n++] = buf_cb->data[buf_cb->rdi++]; + + if (buf_cb->rdi == buf_cb->wri) { + /* End of buffer, go back and reload */ + break; + } + } + + if (n == num) { + break; + } + } + } + + Unlock(p); + + return ((int32_t)n); +} + + +/* + Write num of bytes from buf and return number of bytes actually written. +*/ +int32_t BufWrite (uint8_t *buf, uint32_t num, BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t maxi; + uint32_t n; + + Lock(p); + + maxi = Size (p); + + n = 0U; + buf_cb = (MEM_BUF *)ListPeekTail(&p->list); + + do { + if ((buf_cb == NULL) || (buf_cb->wri == maxi)) { + /* Buffer full, allocate new */ + buf_cb = Alloc (p); + } + + if (buf_cb != NULL) { + + while (n < num) { + buf_cb->data[buf_cb->wri++] = buf[n++]; + + if (buf_cb->wri == maxi) { + /* End of buffer, go back */ + break; + } + } + + if (n == num) { + /* All bytes written */ + break; + } + } + } while (buf_cb != NULL); + + Unlock(p); + + return ((int32_t)n); +} + + +/* + Copy num of bytes from src to dst and return number of bytes actually copied. +*/ +uint32_t BufCopy (BUF_LIST *dst, BUF_LIST *src, uint32_t num) { + MEM_BUF *dst_cb, *src_cb; + uint32_t sz_d, sz_s; + uint32_t i; + uint32_t maxi; + + Lock(dst); + Lock(src); + + i = 0U; + maxi = Size (dst); + + dst_cb = (MEM_BUF *)ListPeekTail(&dst->list); + src_cb = (MEM_BUF *)ListPeekHead(&src->list); + + while (i < num) { + if (src_cb == NULL) { + /* End of source buffer */ + break; + } + + if (dst_cb == NULL) { + /* Allocate new destination buffer */ + dst_cb = Alloc (dst); + + if (dst_cb == NULL) { + break; + } + } + /* Determine free space in current buffers */ + sz_d = maxi - dst_cb->wri; + sz_s = src_cb->wri - src_cb->rdi; + + while ((sz_d > 0) && (sz_s > 0) && (i < num)) { + dst_cb->data[dst_cb->wri++] = src_cb->data[src_cb->rdi++]; + + /* Decrement number of available space/data */ + sz_d--; + sz_s--; + + /* Increment number of copied bytes */ + i++; + } + + if (sz_d == 0) { + /* Destination buffer is full */ + dst_cb = NULL; + } + + if (sz_s == 0) { + /* Source buffer is empty */ + if (src_cb->wri == Size(src)) { + src_cb = Free(src); + } else { + src_cb = NULL; + } + } + } + + Unlock(src); + Unlock(dst); + + /* Return number of copied bytes */ + return (i); +} + + +/* + Flush num of bytes from the list buffer. List buffer is flushed completely when num equals to zero. +*/ +uint32_t BufFlush (uint32_t num, BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t n; + + Lock(p); + + n = 0U; + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + while (buf_cb != NULL) { + + if (buf_cb->rdi == buf_cb->wri) { + /* End of current buffer, free current, get next one */ + if (buf_cb->wri == Size(p)) { + buf_cb = Free(p); + } else { + buf_cb = NULL; + } + } + else { + buf_cb->rdi++; + /* Increment number of bytes flushed */ + n++; + } + + if (num != 0U) { + /* Check if required number of bytes flushed */ + if (n == num) { + break; + } + } + } + + Unlock(p); + + return (n); +} + + +/* + Find the first occurence of a data byte in the list buffer and return its offset from current position. +*/ +int32_t BufFindByte (uint8_t data, BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t offs, rdi; + int32_t n; + + Lock(p); + + n = -1; + rdi = 0U; + offs = 0U; + + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + if (buf_cb != NULL) { + rdi = buf_cb->rdi; + } + + while (buf_cb != NULL) { + + if (rdi == buf_cb->wri) { + /* End of current buffer, peek next */ + buf_cb = (MEM_BUF *)ListPeekNext ((Link_t *)buf_cb); + + /* Reset read index */ + rdi = 0U; + } + else { + /* Check current buffer */ + while (rdi < buf_cb->wri) { + /* Compare data with current buffer content */ + if (data == buf_cb->data[rdi]) { + /* Equal data byte found */ + n = (int32_t)offs; + break; + } + offs++; + rdi++; + } + + if (n != -1) { + break; + } + } + } + + Unlock(p); + + return (n); +} + + +/* + Find the first occurence of a data sequence in the list buffer and return its offset from current position. + + num number of bytes from data to compare +*/ +int32_t BufFind (const uint8_t *data, uint32_t num, BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t offs, rdi; + uint32_t i; + int32_t n; + + Lock(p); + + n = -1; //No match + i = 0U; + rdi = 0U; + offs = 0U; + + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + if (buf_cb != NULL) { + rdi = buf_cb->rdi; + } + + while (buf_cb != NULL) { + + if (rdi == buf_cb->wri) { + /* End of current buffer, peek next */ + buf_cb = (MEM_BUF *)ListPeekNext ((Link_t *)buf_cb); + + /* Reset read index */ + rdi = 0U; + } + else { + /* Check current buffer */ + while (rdi < buf_cb->wri) { + /* Compare data with current buffer content */ + if (data[i] != buf_cb->data[rdi]) { + /* Adjust offset for number of matches */ + if (i == 0) { offs += 1; } + else { offs += i; } + + /* Reset number of matches */ + i = 0U; + } + if (data[i] == buf_cb->data[rdi]) { + /* Equal data byte found */ + i++; + } + + rdi++; + if (i == num) { + /* Compared sequence matches */ + n = (int32_t)offs; + break; + } + } + + if (n != -1) { + break; + } + } + } + + Unlock(p); + + return (n); +} + + +/* + Compare string with buffered data + + \note Does not move buffer pointers +*/ + +int32_t BufCompareString (const char *string, uint32_t offs, BUF_LIST *p) { + MEM_BUF *buf_cb; + uint32_t rdi = 0U; + int32_t n; + + Lock(p); + + n = 0; //No match + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + if (buf_cb != NULL) { + rdi = buf_cb->rdi; + } + + while (buf_cb != NULL) { + + if (rdi == buf_cb->wri) { + /* End of current buffer, peek next */ + buf_cb = (MEM_BUF *)ListPeekNext ((Link_t *)buf_cb); + + if (buf_cb == NULL) { + /* End of buffer */ + n = -1; + } + + /* Reset read index */ + rdi = 0U; + } + else { + if (offs != 0U) { + offs--; + rdi++; + } + else { + while (rdi < buf_cb->wri) { + if (string[n] == '\0') { + /* End of string */ + break; + } + /* Compare string with content of current buffer */ + if (string[n] != buf_cb->data[rdi]) { + /* No match */ + n = 0; + break; + } + n++; + rdi++; + } + + if ((n <= 0) || (string[n] == '\0')) { + /* No match or end of string */ + break; + } + } + } + } + Unlock(p); + + return (n); +} + +int32_t BufGetPos (uint16_t *wri_buf, uint16_t* rdi_buf, BUF_LIST *p) +{ + MEM_BUF *buf_cb; + uint32_t rdi,wri = 0U; + int32_t n; + + Lock(p); + + n = 0; //No match + buf_cb = (MEM_BUF *)ListPeekHead(&p->list); + + if (buf_cb != NULL) { + rdi = buf_cb->rdi; + } + + while (buf_cb != NULL) { + + if (rdi == buf_cb->wri) { + /* End of current buffer, peek next */ + buf_cb = (MEM_BUF *)ListPeekNext ((Link_t *)buf_cb); + + if (buf_cb == NULL) { + /* End of buffer */ + n = -1; + } + + /* Reset read index */ + rdi = 0U; + wri = 0U; + } + else { + rdi = buf_cb->rdi; + wri = buf_cb->wri; + } + } + *wri_buf = wri; + *rdi_buf = rdi; + + n = 0; + Unlock(p); + + return n; +} diff --git a/platform/dev/wifi/BufList/BufList.h b/platform/dev/wifi/BufList/BufList.h new file mode 100644 index 0000000..b42719c --- /dev/null +++ b/platform/dev/wifi/BufList/BufList.h @@ -0,0 +1,188 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2019 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 12. November 2019 + * $Revision: V1.0 + * + * Project: Buffering using CMSIS-RTOS2 memory pools as storage + * -------------------------------------------------------------------------- */ + +#ifndef BUFLIST_H__ +#define BUFLIST_H__ + +#include +#include "LinkList.h" + +typedef struct { + uint16_t wr_idx; /* Buffer write index */ + uint16_t rd_idx; /* Buffer read index */ + uint8_t data[]; /* Buffer data array */ +} BUF_MEM; + +typedef struct { + List_t list; /* Linked list */ + void *mutex; /* Buffer access mutex */ + void *mp_id; /* Memory pool id */ + uint16_t bl_sz; /* Memory pool block size */ + uint16_t rsvd; /* Reserved */ +} BUF_LIST; + +/** + Initialize buffer list. +*/ +extern int32_t BufInit (void *mp_id, void *mutex, BUF_LIST *p); + +/** + Uninitialize buffer list. +*/ +extern int32_t BufUninit (BUF_LIST *p); + +/** + Allocate new buffer, add it into the list and return buffer information. +*/ +extern BUF_MEM *BufAlloc (BUF_LIST *p); + +/** + Remove current buffer from the list and return information about next buffer in list. +*/ +extern BUF_MEM *BufFree (BUF_LIST *p); + +/** + Retrieve current write buffer (last buffer added to the list). +*/ +extern BUF_MEM *BufGetTail (BUF_LIST *p); + +/** + Retrieve common buffer size valid for all buffers in the list. + + Common buffer size is the memory pool block size reduced for handling header. +*/ +extern uint16_t BufGetSize (BUF_LIST *p); + +/** + Retrieve total amount of free space for give buffer list. + + Total amount of free space consists of free space in allocated blocks + and free memory pool blocks. +*/ +extern uint32_t BufGetFree (BUF_LIST *p); + +/** + Retrieve number of bytes in the buffer. +*/ +extern uint32_t BufGetCount (BUF_LIST *p); + +/** + Read a byte from the list buffer. + + \return byte read or -1 if buffer empty +*/ +extern int32_t BufReadByte (BUF_LIST *p); + +/** + Peek a byte from the list buffer. + + \return byte read or -1 if buffer empty +*/ +extern int32_t BufPeekByte (BUF_LIST *p); + +/** + Peek a byte with the specified offset from current position. + + \return byte value or -1 if buffer empty +*/ +extern int32_t BufPeekOffs (uint32_t offs, BUF_LIST *p); + +/** + Flush a byte from the list buffer. + + \return byte flushed or -1 if buffer error. +*/ +extern int32_t BufFlushByte (BUF_LIST *p); + +/** + Write a byte into the list buffer. +*/ +extern int32_t BufWriteByte (uint8_t data, BUF_LIST *p); + +/** + Read num of bytes into buf from the list buffer. + + \param[out] buf data buffer + \param[in] num number of bytes to read + \param[in] p link buffer structure pointer + + \return number of bytes read +*/ +extern int32_t BufRead (uint8_t *buf, uint32_t num, BUF_LIST *p); + +/** + Write num of bytes from buf into the list buffer. +*/ +extern int32_t BufWrite (uint8_t *buf, uint32_t num, BUF_LIST *p); + +/** + Copy num of bytes from the source list buffer into the destination list buffer. + + \return number of bytes copied +*/ +extern uint32_t BufCopy (BUF_LIST *dst, BUF_LIST *src, uint32_t num); + +/** + Flush num of bytes from the list buffer. List buffer is flushed completely when num equals to zero. + + This function increments list buffer read pointer. +*/ +extern uint32_t BufFlush (uint32_t num, BUF_LIST *p); + +/** + Find the first occurence of a data byte in the list buffer and return its offset from current position. + + This function does not move list buffer read pointer. + \return non-zero if data byte was found, -1 otherwise +*/ +extern int32_t BufFindByte (uint8_t data, BUF_LIST *p); + +/** + Find the first occurence of a data sequence in the list buffer and return its offset from current position. + + This function does not move list buffer read pointer. + + \param[in] data data sequence + \param[in] num number of bytes from data to compare + \param[in] p list buffer pointer + \return >=0: offset from the start of data + -1: no match +*/ +extern int32_t BufFind (const uint8_t *data, uint32_t num, BUF_LIST *p); + +/** + Compare string with the data in the list buffer. + + This function does not move list buffer read pointer. + + \param[in] string string to compare + \param[in] offs offset from current position + \param[in] p list buffer pointer + \return >0: match, string length not including null terminator + 0: no match + -1: no match, end of buffer +*/ +extern int32_t BufCompareString (const char *string, uint32_t offs, BUF_LIST *p); + +#endif /* BUFLIST_H__ */ diff --git a/platform/dev/wifi/BufList/LinkList.c b/platform/dev/wifi/BufList/LinkList.c new file mode 100644 index 0000000..7145816 --- /dev/null +++ b/platform/dev/wifi/BufList/LinkList.c @@ -0,0 +1,279 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2019 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 12. November 2019 + * $Revision: V1.0 + * + * Project: Double linked list implementation + * -------------------------------------------------------------------------- */ + +#include "LinkList.h" +#include "RTE_Components.h" +#include CMSIS_device_header + +/* + Usage + ===== + Add an element to the tail and remove it: + + typedef struct Chain { + Link_t link; + void *buf; + } Chain; + + List_t list; + Chain buf; + Chain *p; + + ListInit (&list); + ListPut (&list, (Link_t *)&buf); + + p = (Chain *)ListGet (&list); +*/ + +/** + Initialize linked list + + \param[in] list Linked list pointer + */ +void ListInit (List_t *list) { + + list->head = NULL; + list->tail = NULL; +} + +/** + Put a link at the end of a linked list. + + Used to implement FIFO linked list. + + \param[in] list Linked list pointer + \param[in] link Link pointer +*/ +void ListPut (List_t *list, Link_t *link) { + uint32_t primask = __get_PRIMASK(); + + __disable_irq(); + /* Atomic start */ + + link->prev = list->tail; + link->next = NULL; + + if (list->tail == NULL) { + /* List empty, add head */ + list->head = link; + } + else { + list->tail->next = link; + } + + list->tail = link; + + /* Atomic end */ + if (primask == 0U) { + __enable_irq(); + } +} + +/** + Put a link at the head of a linked list. + + Used to implement LIFO linked list. + + \param[in] list Linked list pointer + \param[in] link Link pointer +*/ +void ListPutHead (List_t *list, Link_t *link) { + uint32_t primask = __get_PRIMASK(); + + __disable_irq(); + /* Atomic start */ + + link->prev = NULL; + link->next = list->head; + + if (list->head == NULL) { + /* List empty, add tail */ + list->tail = link; + } + else { + list->head->prev = link; + } + + list->head = link; + + /* Atomic end */ + if (primask == 0U) { + __enable_irq(); + } +} + +/** + Get the first link in a linked list + + \param[in] list Linked list pointer + \return Pointer to first link in the linked list, NULL if empty +*/ +Link_t *ListGet (List_t *list) { + uint32_t primask = __get_PRIMASK(); + Link_t *link; + + __disable_irq(); + /* Atomic start */ + + link = list->head; + + if (link != NULL) { + list->head = link->next; + + if (link->next == NULL) { + /* List empty, clear tail */ + list->tail = NULL; + } + else { + link->next->prev = NULL; + } + } + + /* Atomic end */ + if (primask == 0U) { + __enable_irq(); + } + + return (link); +} + +/** + Retrieve head link (no remove) + + Can be used to check if list is empty: if (ListGetHead (list) == NULL) { isEmpty = true; } + + Traverse a list from head to tail: + + List_t *list; + Link_t *link; + + for (link = ListPeekHead(list); link != NULL; link = ListPeekNext(link)) { ... } + + \param[in] list Linked list pointer + \return Pointer to head link +*/ +Link_t *ListPeekHead (List_t *list) { + return (list->head); +} + +/** + Retrieve tail link (no remove) + + List_t list; + Link_t *link; + + for (link = ListPeekTail(list); link != NULL; link = ListPeekPrev(link)) { ... } + + \param[in] list Linked list pointer + \return Pointer to tail link +*/ +Link_t *ListPeekTail (List_t *list) { + return (list->tail); +} + +/** + Retrieve next link (no remove) + + \param[in] link Pointer to list link + \return Pointer to next link +*/ +Link_t *ListPeekNext (Link_t *link) { + return (link->next); +} + +/** + Retrieve previous link (no remove) + + \param[in] link Pointer to list link + \return Pointer to next link +*/ +Link_t *ListPeekPrev (Link_t *link) { + return (link->prev); +} + +/** + Insert link in front of an existing link + + \param[in] list Linked list pointer + \param[in] link Existing link + \param[in] lnew Link to insert +*/ +void ListInsert (List_t *list, Link_t *link, Link_t *lnew) { + uint32_t primask = __get_PRIMASK(); + + __disable_irq(); + /* Atomic start */ + + lnew->next = link; + lnew->prev = link->prev; + + if (link->prev == NULL) { + /* No previous link, insert as head */ + list->head = lnew; + } + else { + link->prev->next = lnew; + } + + link->prev = lnew; + + /* Atomic end */ + if (primask == 0U) { + __enable_irq(); + } +} + +/** + Remove link from the linked list + + \param[in] list Linked list pointer + \param[in] link Link to remove +*/ +void ListRemove (List_t *list, Link_t *link) { + uint32_t primask = __get_PRIMASK(); + + __disable_irq(); + /* Atomic start */ + + if (link->next == NULL) { + /* Last link in list */ + list->tail = link->prev; + } + else { + link->next->prev = link->prev; + } + + if (link->prev == NULL) { + /* First link in list */ + list->head = link->next; + } + else { + link->prev->next = link->next; + } + + /* Atomic end */ + if (primask == 0U) { + __enable_irq(); + } +} diff --git a/platform/dev/wifi/BufList/LinkList.h b/platform/dev/wifi/BufList/LinkList.h new file mode 100644 index 0000000..d36f0b0 --- /dev/null +++ b/platform/dev/wifi/BufList/LinkList.h @@ -0,0 +1,123 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2019 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 12. November 2019 + * $Revision: V1.0 + * + * Project: Double linked list implementation + * -------------------------------------------------------------------------- */ + +#ifndef LINKLIST_H__ +#define LINKLIST_H__ + +#include + +/* Linked link structure */ +typedef struct Link_s { + struct Link_s *next; + struct Link_s *prev; +} Link_t; + +/* Linked link list */ +typedef struct { + Link_t *head; + Link_t *tail; +} List_t; + + + /** + Initialize linked list + + \param[in] list Linked list pointer + */ +extern void ListInit (List_t *list); + +/** + Put a link at the end of a linked list + + \param[in] list Linked list pointer + \param[in] link Link pointer +*/ +extern void ListPut (List_t *list, Link_t *link); + +/** + Put a link at the head of a linked list + + \param[in] list Linked list pointer + \param[in] link Link pointer +*/ +void ListPutHead (List_t *list, Link_t *link); + +/** + Get the first link in a linked list + + \param[in] list Linked list pointer + \return Pointer to first link in the linked list, NULL if empty +*/ +extern Link_t *ListGet (List_t *list); + +/** + Retrieve head link (no remove) + + \param[in] list Linked list pointer + \return Pointer to head link +*/ +extern Link_t *ListPeekHead (List_t *list); + +/** + Retrieve tail link (no remove) + + \param[in] list Linked list pointer + \return Pointer to tail link +*/ +extern Link_t *ListPeekTail (List_t *list); + +/** + Retrieve next link (no remove) + + \param[in] link Pointer to list link + \return Pointer to next link +*/ +extern Link_t *ListPeekNext (Link_t *link); + +/** + Retrieve previous link (no remove) + + \param[in] link Pointer to list link + \return Pointer to next link +*/ +extern Link_t *ListPeekPrev (Link_t *link); + +/** + Insert link in front of an existing link + + \param[in] list Linked list pointer + \param[in] link Existing link + \param[in] lnew Link to insert +*/ +extern void ListInsert (List_t *list, Link_t *link, Link_t *lnew); + +/** + Remove link from the linked list + + \param[in] list Linked list pointer + \param[in] link Link to remove +*/ +extern void ListRemove (List_t *list, Link_t *link); + +#endif /* LINKLIST_H__ */ diff --git a/platform/dev/wifi/ESP8266/CMSIS_DV_Results/About.txt b/platform/dev/wifi/ESP8266/CMSIS_DV_Results/About.txt new file mode 100644 index 0000000..f5fc53f --- /dev/null +++ b/platform/dev/wifi/ESP8266/CMSIS_DV_Results/About.txt @@ -0,0 +1,18 @@ +This test report was produced with following configuration: + - Hardware: NXP MIMXRT1064-EVK board with ESP8266EX on SparkFun ESP8266 WiFi Shield + - Firmware: AT Command Set 1.6.2.0 + - Interface: UART at 115200 bps + +Packs used for test: + - ARM::CMSIS 5.6.0 + - ARM::CMSIS-Driver 2.5.0 + - ARM::CMSIS-Driver_Validation 1.4.0 + - Keil::ARM_Compiler 1.6.2 + - NXP MIMXRT1064_DFP 12.0.0 + - NXP EVK-MIMXRT1064_BSP 12.0.0 + +AT Version Information (AT+GMR): + - AT version:1.6.2.0(Apr 13 2018 11:10:59) + - SDK version:2.2.1(6ab97e9) + - compile time:Jun 7 2018 19:34:26 + - Bin version(Wroom 02):1.6.2 diff --git a/platform/dev/wifi/ESP8266/CMSIS_DV_Results/TestReport.txt b/platform/dev/wifi/ESP8266/CMSIS_DV_Results/TestReport.txt new file mode 100644 index 0000000..85f9f80 --- /dev/null +++ b/platform/dev/wifi/ESP8266/CMSIS_DV_Results/TestReport.txt @@ -0,0 +1,61 @@ +CMSIS-Driver WiFi Test Report Dec 2 2019 08:20:03 + +TEST 01: WIFI_GetVersion + DV_WIFI.c (284): [INFO] Driver API version 1.0, Driver version 1.0 + PASSED +TEST 02: WIFI_GetCapabilities PASSED +TEST 03: WIFI_Initialize_Uninitialize PASSED +TEST 04: WIFI_PowerControl + DV_WIFI.c (403): [WARNING] PowerControl (ARM_POWER_LOW) is not supported + PASSED +TEST 05: WIFI_GetModuleInfo PASSED +TEST 06: WIFI_SetOption_GetOption + DV_WIFI.c (534): [WARNING] SetOption ARM_WIFI_BSSID for Access Point is not supported + DV_WIFI.c (590): [WARNING] GetOption ARM_WIFI_BSSID for Access Point is not supported + DV_WIFI.c (867): [WARNING] SetOption ARM_WIFI_DTIM for Station is not supported + DV_WIFI.c (881): [WARNING] SetOption ARM_WIFI_DTIM for Access Point is not supported + DV_WIFI.c (909): [WARNING] GetOption ARM_WIFI_DTIM for Station is not supported + DV_WIFI.c (929): [WARNING] GetOption ARM_WIFI_DTIM for Access Point is not supported + DV_WIFI.c (995): [WARNING] SetOption ARM_WIFI_BEACON for Access Point is not supported + DV_WIFI.c (1027): [WARNING] GetOption ARM_WIFI_BEACON for Access Point is not supported + PASSED +TEST 07: WIFI_Scan PASSED +TEST 08: WIFI_Activate_Deactivate PASSED +TEST 09: WIFI_IsConnected PASSED +TEST 10: WIFI_GetNetInfo PASSED +TEST 11: WIFI_SocketCreate PASSED +TEST 12: WIFI_SocketBind PASSED +TEST 13: WIFI_SocketListen PASSED +TEST 14: WIFI_SocketAccept PASSED +TEST 15: WIFI_SocketConnect + DV_WIFI.c (4337): [WARNING] Non BSD-strict, connect to non-existent port (result ARM_SOCKET_ETIMEDOUT, expected ARM_SOCKET_ECONNREFUSED) + PASSED +TEST 16: WIFI_SocketRecv PASSED +TEST 17: WIFI_SocketRecvFrom PASSED +TEST 18: WIFI_SocketSend PASSED +TEST 19: WIFI_SocketSendTo PASSED +TEST 20: WIFI_SocketGetSockName PASSED +TEST 21: WIFI_SocketGetPeerName PASSED +TEST 22: WIFI_SocketGetOpt PASSED +TEST 23: WIFI_SocketSetOpt PASSED +TEST 24: WIFI_SocketClose PASSED +TEST 25: WIFI_SocketGetHostByName PASSED +TEST 26: WIFI_Ping PASSED +TEST 27: WIFI_Transfer_Fixed PASSED +TEST 28: WIFI_Transfer_Incremental PASSED +TEST 29: WIFI_Send_Fragmented PASSED +TEST 30: WIFI_Recv_Fragmented PASSED +TEST 31: WIFI_Test_Speed PASSED +TEST 32: WIFI_Concurrent_Socket + DV_WIFI.c (8038): [WARNING] Auxiliary Transfer rate low + DV_WIFI.c (8114): [WARNING] Auxiliary Transfer rate low + PASSED +TEST 33: WIFI_Downstream_Rate + DV_WIFI.c (8281): [INFO] Speed 13 KB/s + PASSED +TEST 34: WIFI_Upstream_Rate + DV_WIFI.c (8349): [INFO] Speed 7 KB/s + PASSED + +Test Summary: 34 Tests, 34 Passed, 0 Failed. +Test Result: PASSED diff --git a/platform/dev/wifi/ESP8266/Config/WiFi_ESP8266_Config.h b/platform/dev/wifi/ESP8266/Config/WiFi_ESP8266_Config.h new file mode 100644 index 0000000..e64bd35 --- /dev/null +++ b/platform/dev/wifi/ESP8266/Config/WiFi_ESP8266_Config.h @@ -0,0 +1,90 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2019 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 12. November 2019 + * $Revision: V1.0 + * + * Project: ESP8266 WiFi Driver + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#include "kdrv_uart.h" +// ESP8266 WiFi Driver Configuration + +// WiFi Driver Number (Driver_WiFi#) <0-255> +// Defines exported WiFi driver control block number (Driver_WiFi#) +// Default: 0 +#define WIFI_ESP8266_DRIVER_NUMBER 0 + +// Connect to hardware via Driver_USART# <0-255> +// Defines the serial driver control block number (Driver_USART#) +// Default: 0 +#define WIFI_ESP8266_SERIAL_DRIVER 0 + +// Serial interface baudrate <115200=>115200 +// <230400=>230400 +// <460800=>460800 +// <921600=>921600 +// Defines the serial interface baudrate. +// Default: 115200 +#define WIFI_ESP8266_SERIAL_BAUDRATE 115200 + +// WiFi thread priority <0=>osPriorityLow +// <1=>osPriorityBelowNormal +// <2=>osPriorityNormal +// <3=>osPriorityAboveNormal +// <4=>osPriorityHigh +// <5=>osPriorityRealtime +// Defines the WiFi driver thread priority. +// The priority of the WiFi thread should be higher as application thread priority. +// Default: 3 +#define WIFI_ESP8266_THREAD_PRIORITY 3 + +// WiFi thread stack size [bytes] <96-1073741824:8> +// Defines stack size for the WiFi Thread. +// Default: 512 +#define WIFI_ESP8266_THREAD_STACK_SIZE 512 + +// Socket buffer block size <128-16384:128> +// Defines the size of one memory block used for socket data buffering. +// Socket buffering consists of multiple blocks which are distributed across multiple sockets. +// Default: 512 +#define WIFI_ESP8266_SOCKET_BLOCK_SIZE 512 + +// Socket buffer block count <5-256> +// Defines the total number of memory blocks used for socket data buffering. +// Socket buffering consists of multiple blocks which are distributed across multiple sockets. +// Default: 8 +#define WIFI_ESP8266_SOCKET_BLOCK_COUNT 8 + +// Serial parser buffer block size +// Defines the size of one memory block in serial parser buffer. +// The total size of serial parser buffer is defined by memory block size and number of blocks. +// Default: 256 +#define WIFI_ESP8266_PARSER_BLOCK_SIZE 256 + +// Serial parser buffer block count +// Defines the number of memory blocks in serial parser buffer. +// The total size of serial parser buffer is defined by memory block size and number of blocks. +// Default: 8 +#define WIFI_ESP8266_PARSER_BLOCK_COUNT 8 + +// + +//------------- <<< end of configuration section >>> ------------------------- diff --git a/platform/dev/wifi/ESP8266/ESP8266.c b/platform/dev/wifi/ESP8266/ESP8266.c new file mode 100644 index 0000000..a700b00 --- /dev/null +++ b/platform/dev/wifi/ESP8266/ESP8266.c @@ -0,0 +1,3767 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2019 Arm Limited (or its affiliates). All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * + * $Date: 12. November 2019 + * $Revision: V1.0 + * + * Project: ESP8266 WiFi Driver + * -------------------------------------------------------------------------- */ + +#include +#include +#include +#include + +#include "ESP8266.h" +#include "ESP8266_Serial.h" + +#include "WiFi_ESP8266_Os.h" +#include "kmdw_console.h" +/* Control block */ +static AT_PARSER_HANDLE AT_Cb; + +/* Pointer to parser control block */ +#define pCb (&AT_Cb) + +/* Pointer to parser buffer memory */ +#define pMem (&AT_Cb.mem) + +/* String list definition */ +typedef const struct { + const char *str; +} STRING_LIST_t; + + +/* Static functions */ +static int32_t ReceiveData (void); +static uint8_t AnalyzeLineData (void); +static uint8_t GetCommandCode (BUF_LIST *mem); +static uint8_t GetASCIIResponseCode (BUF_LIST *mem); +static uint8_t GetGMRResponseCode (BUF_LIST *mem); +static uint8_t GetCtrlResponseCode (BUF_LIST *mem); +static int32_t GetRespArg (uint8_t *buf, uint32_t sz); +static int32_t CmdOpen (uint8_t cmd_code, uint32_t cmd_mode, char *buf); +static int32_t CmdSend (uint8_t cmd, char *buf, int32_t num); +static const char *CmdString (uint8_t cmd); +static int32_t CmdSetWFE (uint8_t cmd); +static void AT_Parse_IP (char *buf, uint8_t ip[]); +static void AT_Parse_MAC (char *buf, uint8_t mac[]); + + +/* Command list (see also CommandCode_t) */ +static STRING_LIST_t List_PlusResp[] = { + { "IPD" }, + { "CWLAP" }, + { "CWJAP_CUR" }, + { "CWQAP" }, + { "CWSAP_CUR" }, + { "CWMODE_CUR" }, + { "CIPSTAMAC_CUR" }, + { "CIPAPMAC_CUR" }, + { "RFPOWER" }, + { "CIPSTA_CUR" }, + { "CIPAP_CUR" }, + { "CIPDNS_CUR" }, + { "CWDHCP_CUR" }, + { "CWDHCPS_CUR" }, + { "CWAUTOCONN" }, + { "CWLIF" }, + { "UART_CUR" }, +#if (AT_VARIANT == AT_VARIANT_ESP) +#if (AT_VERSION >= AT_VERSION_1_6_0_0) && (AT_VERSION < AT_VERSION_1_7_0_0) + { "SYSMSG" }, +#elif (AT_VERSION >= AT_VERSION_1_7_0_0) + { "SYSMSG_CUR" }, +#endif +#else + { "SYSMSG_CUR" }, +#endif + { "CIPSTATUS" }, + { "CIPDOMAIN" }, + { "CIPSTART" }, + { "CIPCLOSE" }, + { "PING" }, + { "CIPSEND" }, + { "CIPMUX" }, + { "CIPSERVER" }, + { "CIPSERVERMAXCONN" }, + { "RST" }, + { "GMR" }, + { "LINK_CONN" }, + { "STA_CONNECTED" }, + { "STA_DISCONNECTED" }, + { "SLEEP" }, + { "E" }, + { "" } +}; + +/* Command codes */ +typedef enum { + CMD_IPD = 0, + CMD_CWLAP, + CMD_CWJAP_CUR, + CMD_CWQAP, + CMD_CWSAP_CUR, + CMD_CWMODE_CUR, + CMD_CIPSTAMAC_CUR, + CMD_CIPAPMAC_CUR, + CMD_RFPOWER, + CMD_CIPSTA_CUR, + CMD_CIPAP_CUR, + CMD_CIPDNS_CUR, + CMD_CWDHCP_CUR, + CMD_CWDHCPS_CUR, + CMD_CWAUTOCONN, + CMD_CWLIF, + CMD_UART_CUR, + CMD_SYSMSG_CUR, + CMD_CIPSTATUS, + CMD_CIPDOMAIN, + CMD_CIPSTART, + CMD_CIPCLOSE, + CMD_PING, + CMD_CIPSEND, + CMD_CIPMUX, + CMD_CIPSERVER, + CMD_CIPSERVERMAXCONN, + CMD_RST, + CMD_GMR, + CMD_LINK_CONN, + CMD_STA_CONNECTED, + CMD_STA_DISCONNECTED, + CMD_SLEEP, + CMD_ECHO = 0xFD, /* Command Echo */ + CMD_TEST = 0xFE, /* AT startup (empty command) */ + CMD_UNKNOWN = 0xFF /* Unknown or unhandled command */ +} CommandCode_t; + + +/* Generic responses (see AT_RESP_x definitions) */ +static STRING_LIST_t List_ASCIIResp[] = { + { "OK" }, + { "ERROR" }, + { "FAIL" }, + { "SEND OK" }, + { "SEND FAIL" }, + { "busy p..." }, + { "busy s..." }, + { "ALREADY CONNECTED" }, +/* Generic responses redirected to AT_Notify function */ + { "WIFI CONNECTED" }, + { "WIFI GOT IP" }, + { "WIFI DISCONNECT" }, +/* Ignored */ +#if 0 + { "no change" }, + { "DNS Fail" }, + { "UNLINK" }, +#endif +/* Special responses */ + { "AT" }, + { "ready" }, + { "ERR CODE" }, +}; + + +/* List of strings received in response to AT+GMR */ +static STRING_LIST_t List_Gmr[] = { + { "AT version" }, + { "SDK version" }, + { "compile time" }, + { "Bin version" } +}; + +/* GMR codes */ +#define AT_GMR_AT_VER 0 +#define AT_GMR_SDK_VER 1 +#define AT_GMR_COMP_TIME 2 +#define AT_GMR_BIN_VER 3 +#define AT_GMR_UNKNOWN 0xFF + + +/* Control strings */ +static STRING_LIST_t List_Ctrl[] = { + { "CONNECT" }, + { "CLOSED" } +}; + +/* Control codes */ +#define AT_CTRL_CONNECT 0 +#define AT_CTRL_CLOSED 1 +#define AT_CTRL_UNKNOWN 0xFF + + +/* ------------------------------------------------------------------------- */ + +/* Get pointer to command string */ +static const char *CmdString (uint8_t cmd) { + return (List_PlusResp[cmd].str); +} + +/* ------------------------------------------------------------------------- */ + +/** + Serial callback. +*/ +void Serial_Cb (uint32_t cb_event) { + + if (cb_event & SERIAL_CB_TX_DATA_COMPLETED ) { + /* Serial transmit completed */ + AT_Notify (AT_NOTIFY_TX_DONE, NULL); + } + + if (cb_event & SERIAL_CB_RX_DATA_AVAILABLE) { + /* Serial received data */ + AT_Notify (AT_NOTIFY_EXECUTE, NULL); + + } +} + +/* ------------------------------------------------------------------------- */ + +/** + Initialize parser. +*/ + +int32_t AT_Parser_Initialize (void) { + osMemoryPoolAttr_t mp_attr; + osMemoryPoolId_t mp_id; + int32_t ex, stat; + + stat = -1; + + mp_attr = AT_Parser_MemPool_Attr; + mp_id = osMemoryPoolNew (PARSER_BUFFER_BLOCK_COUNT, PARSER_BUFFER_BLOCK_SIZE, &mp_attr); + if (mp_id != NULL) { + ex = Serial_Initialize (); + if ( ex== 0) { + /* Serial initialized ,pooling mode*/ + stat = 0; + } + else + { + if(ex == 1) + { + stat =1; + } + } + } + if (stat >= 0) { + /* Setup memory pool */ + BufInit (mp_id, NULL, &pCb->mem); + BufInit (mp_id, NULL, &pCb->resp); + + /* Set initial state */ + pCb->state = AT_STATE_ANALYZE; + pCb->cmd_sent = CMD_UNKNOWN; + pCb->gen_resp = 0U; + pCb->msg_code = 0U; + pCb->resp_code = CMD_UNKNOWN; + pCb->resp_len = 0U; + } + + if (stat < 0) { + /* Clean up resources */ + Serial_Uninitialize(); + + if (mp_id != NULL) { + osMemoryPoolDelete (mp_id); + } + } + return (stat); +} + +/** + Uninitialize parser. +*/ +int32_t AT_Parser_Uninitialize (void) { + + Serial_Uninitialize(); + + BufUninit(pMem); + + osMemoryPoolDelete (pMem->mp_id); + + pCb->mem.mp_id = NULL; + pCb->resp.mp_id = NULL; + + return (0); +} + +/** + Set serial baudrate. +*/ +int32_t AT_Parser_SetBaudrate (uint32_t baudrate) { + return Serial_SetBaudrate (baudrate); +} + +/** + Reset parser. +*/ +void AT_Parser_Reset (void) { + + /* Flush parser buffer */ + BufFlush (0, pMem); + + /* Reset state */ + pCb->state = AT_STATE_ANALYZE; + pCb->cmd_sent = CMD_UNKNOWN; + pCb->gen_resp = 0U; + pCb->msg_code = 0U; + pCb->resp_code = CMD_UNKNOWN; + pCb->resp_len = 0U; +} + +/** + Execute AT command parser. +*/ + + +void AT_Parser_Execute (void) { + uint8_t crlf[] = {'\r', '\n'}; + int32_t n; + uint32_t sleep; + uint32_t p; + + sleep = 0U; + while (sleep == 0) { + + /* Receive serial data */ + n = ReceiveData(); + if ( n == 1U) { + /* Out of memory */ + AT_Notify (AT_NOTIFY_OUT_OF_MEMORY, pCb->mem.mp_id); + } + + switch (pCb->state) { + case AT_STATE_ANALYZE: + pCb->state = AnalyzeLineData(); + break; + + case AT_STATE_WAIT: + /* Not enough data in buffer to complete operation */ + sleep = 1U; + + /* Next state */ + pCb->state = AT_STATE_ANALYZE; + break; + + case AT_STATE_FLUSH: + /* Flush current response till first CRLF */ + n = BufFind (crlf, 2, pMem); + + if (n != -1) { + /* Flush buffer including crlf */ + BufFlush ((uint32_t)n + 2, pMem); + } + + /* Start analyzing again */ + pCb->state = AT_STATE_ANALYZE; + break; + + case AT_STATE_RECV_DATA: + /* Copy IPD data */ + /* Set pointer to source memory buffer */ + p = (uint32_t)pMem; + + /* Call notify using pointer to memory buffer */ + AT_Notify (AT_NOTIFY_CONNECTION_RX_DATA, &p); + + /* On return, p must contain number of bytes left to receive */ + if (p == 0) { + /* Packet is received */ + sleep = 1U; + + /* Next state */ + pCb->state = AT_STATE_ANALYZE; + } + else { + if (p == pCb->ipd_rx) { + /* Application did not read anything */ + sleep = 1U; + } + pCb->ipd_rx = p; + } + break; + + case AT_STATE_RESP_DATA: + /* Received +CMD response */ + if (pCb->resp_code == CMD_IPD) { + /* Copy response (including ':' character) */ + BufCopy (&(pCb->resp), &(pCb->mem), pCb->resp_len+1); + + /* Receive network data (+IPD) */ + pCb->ipd_rx = 0U; + + AT_Notify (AT_NOTIFY_CONNECTION_RX_INIT, &(pCb->ipd_rx)); + + if (pCb->ipd_rx == 0) { + /* Socket is out of memory */ + AT_Notify (AT_NOTIFY_OUT_OF_MEMORY, NULL); + } + /* Start receiving data */ + pCb->state = AT_STATE_RECV_DATA; + } + else { + /* Response data arrived */ + if (pCb->resp_code == CMD_PING) { + /* Artificially add '+PING:' string */ + BufWrite ((uint8_t *)"+PING:", 6, &(pCb->resp)); + /* Flush '+' from the original response */ + BufFlushByte (&(pCb->mem)); + /* Adjust response length for the flushed byte */ + pCb->resp_len -= 1U; + } + + BufCopy (&(pCb->resp), &(pCb->mem), pCb->resp_len+2); + + pCb->state = AT_STATE_ANALYZE; + + if (pCb->resp_code == CMD_LINK_CONN) { + /* Connection established (+LINK_CONN) */ + AT_Notify (AT_NOTIFY_CONNECTION_OPEN, NULL); + } + else if (pCb->resp_code == CMD_STA_CONNECTED) { + /* Station connected to local AP (+STA_CONNECTED:) */ + AT_Notify (AT_NOTIFY_STATION_CONNECTED, NULL); + } + else if (pCb->resp_code == CMD_STA_DISCONNECTED) { + /* Station disconnected from local AP (+STA_DISCONNECTED:) */ + AT_Notify (AT_NOTIFY_STATION_DISCONNECTED, NULL); + } + else if (pCb->resp_code != CMD_UNKNOWN) { + /* Command response (+XXX in buffer) */ + pCb->state = AT_STATE_ANALYZE; + } + else { + /* Response unknown/unhandled */ + pCb->state = AT_STATE_FLUSH; + } + } + break; + + case AT_STATE_RESP_GMR: + /* +GMR: copy response into response buffer */ + BufCopy (&(pCb->resp), &(pCb->mem), pCb->resp_len+2); + + pCb->state = AT_STATE_ANALYZE; + break; + + case AT_STATE_RESP_GEN: + switch (pCb->msg_code) { + case AT_RESP_OK: + case AT_RESP_ERROR: + case AT_RESP_ALREADY_CONNECTED: + case AT_RESP_SEND_OK: + case AT_RESP_SEND_FAIL: + /* Set generic command response */ + pCb->gen_resp = pCb->msg_code; + + /* Application waits for response */ + AT_Notify (AT_NOTIFY_RESPONSE_GENERIC, NULL); + if(BufGetCount(pMem) == 0) + sleep = 1U; + /* Set next state */ + //pCb->state = AT_STATE_FLUSH; + break; + + case AT_RESP_BUSY_P: + case AT_RESP_BUSY_S: + /* Busy processing or busy sending */ + break; + + case AT_RESP_WIFI_CONNECTED: + AT_Notify (AT_NOTIFY_CONNECTED, NULL); + break; + + case AT_RESP_WIFI_GOT_IP: + AT_Notify (AT_NOTIFY_GOT_IP, NULL); + break; + + case AT_RESP_WIFI_DISCONNECT: + AT_Notify (AT_NOTIFY_DISCONNECTED, NULL); + break; + + case AT_RESP_READY: + pCb->gen_resp = pCb->msg_code; + + AT_Notify (AT_NOTIFY_READY, NULL); + sleep = 1U; + break; + case AT_RESP_ERR_CODE: + /* Error code received */ + /* Artificially add '+' character and copy response */ + BufWriteByte ('+', &(pCb->resp)); + BufCopy (&(pCb->resp), &(pCb->mem), pCb->resp_len+2); + + AT_Notify (AT_NOTIFY_ERR_CODE, NULL); + break; + + default: + case AT_RESP_UNKNOWN: + /* Unknown response */ + break; + } + /* Set next state */ + pCb->state = AT_STATE_FLUSH; + break; + + case AT_STATE_SEND_DATA: + + /* Received '>' character */ + AT_Notify (AT_NOTIFY_REQUEST_TO_SEND, NULL); + sleep = 1U; + + /* Next state */ + pCb->state = AT_STATE_FLUSH; + break; + + case AT_STATE_RESP_CTRL: + /* Control code arrived */ + if (pCb->ctrl_code == AT_CTRL_CONNECT) { + /* ,CONNECT */ + AT_Notify (AT_NOTIFY_CONNECTION_OPEN, NULL); + } + else if (pCb->ctrl_code == AT_CTRL_CLOSED) { + /* ,CLOSED */ + AT_Notify (AT_NOTIFY_CONNECTION_CLOSED, NULL); + } + + /* Next state */ + pCb->state = AT_STATE_FLUSH; + break; + + case AT_STATE_RESP_ECHO: + /* Command echo received */ + /* Next state */ + pCb->state = AT_STATE_FLUSH; + break; + + default: + break; + } + } +} + + +/* + Retrieve data from the serial interface and copy the data into the buffer. +*/ +static int32_t ReceiveData (void) { + static uint32_t sz_buf; + //static uint32_t n_prev; + BUF_MEM *buf; + uint32_t n, cnt, num; + int32_t err; + + + if (sz_buf == 0) { + sz_buf = BufGetSize(pMem); + } + + err = 0; + num = 0U; + + n = Serial_GetRxCount(); + + while (num < n) { + /* Determine free space in the buffer */ + buf = BufGetTail (pMem); + + if (buf != NULL) { + cnt = sz_buf - buf->wr_idx; + } else { + cnt = 0U; + } + + if (cnt != 0U) { + /* We can read cnt bytes in one pass */ + + if (n < cnt) { + /* Number of bytes received is less than we can read */ + cnt = n; + } + + /* Read actual data */ + cnt = (uint32_t)Serial_ReadBuf (&buf->data[buf->wr_idx], cnt); + + /*dbg_msg_console("usart read buf :%s,%d\n",&buf->data[buf->wr_idx],buf->wr_idx); + if(strstr(&buf->data[buf->wr_idx],"OK")!= NULL) + { + //dbg_msg_console("usart2 read buf :%s,%d\n",&buf->data[buf->wr_idx],buf->wr_idx); + }*/ + if (cnt != 0) { + buf->wr_idx += cnt; + num += cnt; + } else { + /* Serial buffer empty? */ + err = 2U; + } + } + else { + /* Out of memory */ + err = 1U; + } + + if (err != 0U) { + break; + } + } + //memset(RxBuf,0,n); + Serial_uart_read(); + //Serial_uart_read(); + return (err); +} + +#define AT_LINE_NODATA (1U << 0) /* Line is empty */ +#define AT_LINE_INCOMPLETE (1U << 1) /* Line contains incomplete response */ +#define AT_LINE_PLUS (1U << 2) /* Line starts with '+' response */ +#define AT_LINE_COLON (1U << 3) /* Line contains ':' character */ +#define AT_LINE_ASCII (1U << 4) /* Line starts with ASCII characters */ +#define AT_LINE_CRLF (1U << 5) /* Line contains CRLF characters */ +#define AT_LINE_TXREQ (1U << 6) /* Line starts with '>' character */ +#define AT_LINE_CTRL (1U << 7) /* Line starts with numeric character */ +#define AT_LINE_NUMBER (1U << 8) /* Line contains numeric character */ + +/** + Analyze received data and set AT_LINE_n flags based on the line content. + + \return AT_LINE flags +*/ +static uint32_t AnalyzeLine (BUF_LIST *mem) { + uint8_t crlf[] = {'\r', '\n'}; + uint8_t b; /* Received byte */ + uint32_t flags; /* Analysis flags */ + int32_t val; + + flags = 0U; + + do { + /* Peek current byte from list buffer */ + val = BufPeekByte (mem); + + if (val < 0) { + /* Buffer empty */ + flags |= AT_LINE_NODATA; + break; + } + + b = (uint8_t)val; + + if (b == '+') { + /* Found: +command response */ + flags |= AT_LINE_PLUS; + + /* Check if colon is received */ + val = BufFindByte (':', mem); + + if (val != -1) { + flags |= AT_LINE_COLON; + } else { + /* Not terminated */ + flags |= AT_LINE_INCOMPLETE; + + /* Check if next character is a number (PING response) */ + val = BufPeekOffs(1, mem); + + if (val != -1) { + b = (uint8_t)val; + + if ((b >= '0') && (b <= '9')) { + flags &= ~AT_LINE_INCOMPLETE; + flags |= AT_LINE_NUMBER; + } + } + } + } + else if (b == '>') { + /* Found: data input request */ + flags |= AT_LINE_TXREQ; + } + else if (((b >= 'A') && (b <= 'Z')) || ((b >= 'a') && (b <= 'z'))) { + /* Found: command ASCII response */ + flags |= AT_LINE_ASCII; + + /* Check if terminated */ + val = BufFind (crlf, 2, mem); + + if (val != -1) { + pCb->resp_len = (uint8_t)val; + + flags |= AT_LINE_CRLF; + } else { + /* Not terminated */ + flags |= AT_LINE_INCOMPLETE; + } + } + else if ((b >= '0') && (b <= '9')) { + /* [,] CLOSED response ? */ + flags |= AT_LINE_CTRL; + + /* Check if terminated */ + val = BufFind (crlf, 2, mem); + + if (val != -1) { + pCb->resp_len = (uint8_t)val; + flags |= AT_LINE_CRLF; + } else { + /* Not terminated */ + flags |= AT_LINE_INCOMPLETE; + } + } + else { + /* Unknown character, flush it and continue */ + BufFlushByte(mem); + } + } while (flags == 0U); + + /* Return analysis result */ + return (flags); +} + +/* -------------------------------------------------------------------- */ +/** + Analyze the received content and decide what to do with it. + + \return next parser state, see AT_STATE_ definitions. +*/ +bool analyze_fin = true; + +static uint8_t AnalyzeLineData (void) { + uint8_t crlf[] = {'\r', '\n'}; + uint8_t code; + uint8_t rval; + int32_t n; + uint32_t flags; + + flags = AnalyzeLine(pMem); + + if ((flags & AT_LINE_NODATA) || (flags & AT_LINE_INCOMPLETE)) { + /* No data or incomplete response */ + rval = AT_STATE_WAIT; + } + else if (flags & AT_LINE_PLUS) { + /* Comand response with data */ + if (flags & AT_LINE_COLON) { + /* Line contains colon, string compare can be performed */ + pCb->resp_code = GetCommandCode (pMem); + + if (pCb->resp_code == CMD_IPD) { + /* Receive network data (+IPD) */ + /* Find colon, there is no CRLF after +IPD */ + pCb->resp_len = (uint8_t)BufFindByte (':', pMem); + + rval = AT_STATE_RESP_DATA; + } + else { + /* Check if line is terminated */ + n = BufFind (crlf, 2, pMem); + + if (n == -1) { + /* Not terminated, wait for more data */ + rval = AT_STATE_WAIT; + } + else { + /* Line terminator found */ + pCb->resp_len = (uint8_t)n; + + rval = AT_STATE_RESP_DATA; + } + } + } + else if (flags & AT_LINE_NUMBER) { + /* Response contains plus and a number, ping response (+x) */ + pCb->resp_code = CMD_PING; + + /* Check if line is terminated */ + n = BufFind (crlf, 2, pMem); + + if (n == -1) { + /* Not terminated, wait for more data */ + rval = AT_STATE_WAIT; + } + else { + /* Line terminator found */ + pCb->resp_len = (uint8_t)n; + + rval = AT_STATE_RESP_DATA; + } + } + else { + /* No colon, out of sync */ + rval = AT_STATE_FLUSH; + } + } + else if (flags & AT_LINE_ASCII) { + /* Line contains ascii characters */ + if (flags & AT_LINE_CRLF) { + /* Line is terminated, string compare can be performed */ + code = GetGMRResponseCode(pMem); + + if (code != AT_GMR_UNKNOWN) { + rval = AT_STATE_RESP_GMR; + } + else { + code = GetASCIIResponseCode (pMem); + if (code == AT_RESP_ECHO) { + /* Command echo received */ + rval = AT_STATE_RESP_ECHO; + } + else if (code != AT_RESP_UNKNOWN) { + /* Generic response received */ + rval = AT_STATE_RESP_GEN; + } + else { + /* Unknown */ + rval = AT_STATE_FLUSH; + } + } + + /* Save response code */ + pCb->msg_code = code; + } + else { + /* No line termination */ + rval = AT_STATE_FLUSH; + } + } + else if (flags & AT_LINE_CTRL) { + /* Line contains ascii number */ + if (flags & AT_LINE_CRLF) { + /* Line is terminated, check content */ + code = GetCtrlResponseCode (pMem); + + pCb->ctrl_code = code; + + rval = AT_STATE_RESP_CTRL; + } + else { + /* Out of sync */ + rval = AT_STATE_FLUSH; + } + } + else if (flags & AT_LINE_TXREQ) { + /* Line contains data request character */ + rval = AT_STATE_SEND_DATA; + } + else { + /* Unknown */ + rval = AT_STATE_FLUSH; + } + + return (rval); +} + + +/** + Compare received data with predefined strings and return corresponding command code. + + \return CommandCode_t +*/ +static uint8_t GetCommandCode (BUF_LIST *mem) { + uint8_t i, maxi, code; + int32_t val; + + code = CMD_UNKNOWN; + maxi = sizeof(List_PlusResp)/sizeof(List_PlusResp[0]); + + for (i = 0; i < maxi; i++) { + val = BufCompareString (List_PlusResp[i].str, 1U, mem); + + if (val > 0) { + /* String matches */ + code = i; + break; + } + } + return (code); +} + + +/** + Compare received data with predefined strings and return corresponding response code. + + \return Generic response code, see AT_RESP_ definitions +*/ + +static uint8_t GetASCIIResponseCode (BUF_LIST *mem) { + uint8_t i, maxi, code; + int32_t val; + + code = AT_RESP_UNKNOWN; + maxi = sizeof(List_ASCIIResp)/sizeof(List_ASCIIResp[0]); + + for (i = 0; i < maxi; i++) { + /* Search for responses (OK, ERROR, FAIL, SEND OK, ...) */ + val = BufCompareString (List_ASCIIResp[i].str, 0U, mem); + if (val > 0) { + /* String matches */ + code = i; + break; + } + } + return (code); +} + +/** + Compare received data with predefined strings and return corresponding response code. + + \return GMR code, see ESP_GMR_ definitions +*/ +static uint8_t GetGMRResponseCode (BUF_LIST *mem) { + uint8_t i, maxi, code; + int32_t val; + + code = AT_GMR_UNKNOWN; + maxi = sizeof(List_Gmr)/sizeof(List_Gmr[0]); + + for (i = 0; i < maxi; i++) { + /* Search for responses */ + val = BufCompareString (List_Gmr[i].str, 0U, mem); + + if (val > 0) { + /* String matches */ + code = i; + break; + } + } + + return (code); +} + + +/** + Compare received data with predefined strings and return corresponding control code. + + Currently supported control strings: + ,CONNECT + ,CLOSED + + \return ESP_CTRL_CONNECT, ESP_CTRL_CLOSED +*/ +//static uint32_t GetCtrlResponseCode (BUF_LIST *mem) { +static uint8_t GetCtrlResponseCode (BUF_LIST *mem) { + uint8_t i, maxi, code; + int32_t val; + + code = AT_CTRL_UNKNOWN; + maxi = sizeof(List_Ctrl)/sizeof(List_Ctrl[0]); + + for (i = 0; i < maxi; i++) { + val = BufCompareString (List_Ctrl[i].str, 2U, mem); + + if (val > 0) { + /* String matches */ + code = i; + break; + } + } + return (code); +} + +/* ------------------------------------------------------------------------- */ + +/** + Get response argument. + + The return value should indicate continuation pattern. For example when there + are multiple responses, as + +CWLAP:,,,,,\r\n + +CWLAP:,,,,,\r\n + +CWLAP:,,,,,\r\n + +CWLAP:,,,,,\r\nOK + + the return value should indicate what follows after \r\n termination: + - in case if '+' follows, there is another response to be processed + - in case if "OK" follows, response was processed completely. + + Note that +IPD response format is different and there is no \r\n terminator. + + \return -2: failed, specified buffer too small (sz of buf) + -1: response incomplete, rx buffer empty + 0: retrieved, last delimiter: ',' + 1: retrieved, last delimiter: ':' + 2: retrieved, last delimiter: '\r', response pending ('+') + 3: retrieved, last delimiter: '\r', last response ("OK") +*/ +static int32_t GetRespArg (uint8_t *buf, uint32_t sz) { + uint32_t i; /* argument size */ + uint32_t str; /* string indicator */ + int32_t val; + uint8_t b; + uint8_t d[] = {',', ':', '\r'}; + int32_t del; + + if (BufPeekByte(&(pCb->resp)) == '+') { + /* Sync till the first ':' after +command string */ + do { + val = BufReadByte (&(pCb->resp)); + + if (val == -1) { + return -1; + } + if (val == ',') { + /* Handle "+IPD," response format */ + break; + } + } + while (val != ':'); + } + + /* Initialize number of delimiters, string indicator (str) and argument size (i) */ + del = sizeof(d); + str = 0U; + i = 0U; + + do { + if (i == sz) { + /* Specified buffer too small */ + val = -2; + } + else { + /* Read one byte from response buffer */ + val = BufReadByte (&(pCb->resp)); + } + + if (val < 0) { + break; + } + + b = (uint8_t)val; + + if (b == '"') { + /* Toggle string indicator */ + str ^= 1U; + } + + if ((str == 0U) && ((b == '(') || (b == ')'))) { + /* Ignore characters if not within string */ + } + else { + if (str == 0U) { + /* Check delimiters (when outside of string) */ + for (val = 0; val < del; val++) { + if (b == d[val]) { + /* Found delimiter, set null terminator */ + b = '\0'; + break; + } + } + } + buf[i] = b; + + i++; + } + } + while (val >= del); + + if (val == 2) { + /* Check if this is the last response */ + + /* Clear '\n' character */ + BufFlushByte (&(pCb->resp)); + + /* Peek what is next */ + b = (uint8_t)BufPeekByte (&(pCb->resp)); + + if (b != '+') { + val = 3; + } + } + + return (val); +} + +/* ------------------------------------------------------------------------- */ + + +/** + Retrieve incomming data. + + Response: +IPD,,[,, ]: + + This response does not have CRLF terminator, is the number of bytes in . + Also note that the format of +IPD is also different in how argument are provided. + + \param[out] link_id connection ID + \param[out] len data length + \param[out] remote_ip remote IP (enabled by command AT+CIPDINFO=1) + \param[out] remote_port remote port (enabled by command AT+CIPDINFO=1) + + + \return 0: ok, len of data shall be read from buffer + negative: buffer empty or packet incomplete +*/ +int32_t AT_Resp_IPD (uint32_t *link_id, uint32_t *len, uint8_t *remote_ip, uint16_t *remote_port) { + char *p; + uint8_t buf[32]; + int32_t val; + uint32_t a; /* Argument counter */ + uint32_t uval; /* Unsigned value storage */ + + a = 0U; + + do { + /* Retrieve response argument */ + val = GetRespArg (buf, sizeof(buf)); + + if (val < 0) { + break; + } + + p = (char *)&buf[0]; + + /* Got valid argument */ + if (a == 0) { + /* Read (buf = integer) */ + uval = strtoul (p, &p, 10); + + *link_id = uval; + } + else if (a == 1) { + /* Read (buf = integer) */ + uval = strtoul (p, &p, 10); + + *len = uval; + } + else if (a == 2) { + /* Read (buf = "xxx.xxx.xxx.xxx") */ + if (remote_ip != NULL) { + AT_Parse_IP (p, remote_ip); + } + } + else if (a == 3) { + /* Read (buf = integer?) */ + uval = strtoul (p, &p, 10); + + if (remote_port != NULL) { + *remote_port = (uint16_t)uval; + } + } + else { + /* ??? */ + break; + } + + /* Increment number of arguments */ + a++; + + if (val == 1) { + /* At the ':' delimiter */ + val = 0; + break; + } + } + while (val >= 0); + + return (val); +} + + +/** + Get +LINK_CONN response parameters (see +SYSMSG_CUR). + + +LINK_CONN:,,"UDP/TCP/SSL",,, + , +*/ +int32_t AT_Resp_LinkConn (uint32_t *status, AT_DATA_LINK_CONN *conn) { + char *p; + uint8_t buf[32]; + int32_t val; + uint32_t a; /* Argument counter */ + uint32_t uval; /* Unsigned value storage */ + + a = 0U; + + do { + /* Retrieve response argument */ + val = GetRespArg (buf, sizeof(buf)); + + if (val < 0) { + break; + } + + /* Ignore ':' delimiter */ + if (val != -1) { + p = (char *)&buf[0]; + + /* Got valid argument */ + if (a == 0) { + /* Read (buf = integer) */ + uval = strtoul (p, &p, 10); + + *status = uval; + } + else if (a == 1) { + /* Read (buf = integer) */ + uval = strtoul (p, &p, 10); + + conn->link_id = (uint8_t)uval; + } + else if (a == 2) { + /* Read type string "UDP/TCP/SSL" */ + strcpy (conn->type, p); + } + else if (a == 3) { + /* Read client/server flag */ + uval = strtoul (p, &p, 10); + + conn->c_s = (uint8_t)uval; + } + else if (a == 4) { + /* Read (buf = "xxx.xxx.xxx.xxx") */ + AT_Parse_IP (p, conn->remote_ip); + } + else if (a == 5) { + /* Read (buf = integer) */ + uval = strtoul (p, &p, 10); + + conn->remote_port = (uint16_t)uval; + } + else if (a == 6) { + /* Read (buf = integer) */ + uval = strtoul (p, &p, 10); + + conn->local_port = (uint16_t)uval; + } + else { + /* ??? */ + break; + } + + /* Increment number of arguments */ + a++; + } + } + while ((val != 2) && (val != 3)); + + if (val == 3) { + /* Last response */ + val = 0; + } + else { + if (val == 2) { + /* Response is pending */ + val = 1; + } + } + + return (val); +} + +/** + Get connection number from the ,CONNECT or ,CLOSED response. + + \param[in] conn_id connection ID + \return execution status: + -1: no response (buffer empty) + 0: connection number retrieved +*/ +int32_t AT_Resp_CtrlConn (uint32_t *conn_id) { + int32_t val; + uint8_t b; + + val = BufReadByte (pMem); + + if (val != -1) { + b = (uint8_t)val; + + *conn_id = b - '0'; + val = 0; + } + + return (val); +} + +/** + Get +STA_CONNECTED and +STA_DISCONNECTED response (mac). + + +STA_CONNECTED:crlf + +STA_DISCONNECTED"crlf +*/ +int32_t AT_Resp_StaMac (uint8_t mac[]) { + char *p; + uint8_t buf[32]; + int32_t val; + + /* Retrieve response argument */ + val = GetRespArg (buf, sizeof(buf)); + + if (val > 1) { + p = (char *)&buf[0]; + + /* Read (buf = "xx:xx:xx:xx:xx:xx") */ + AT_Parse_MAC (p, mac); + + val = 0; + } + + return (val); +} + +/** + Get ERR_CODE:0x... response. + + \param[out] err_code Pointer to 32-bit variable where error code will be stored. + \return execution status: + -1: no response (buffer empty) + 0: error code retrieved +*/ +int32_t AT_Resp_ErrCode (uint32_t *err_code) { + char *p; + uint8_t buf[32]; + int32_t val; + uint32_t uval; /* Unsigned value storage */ + + /* Retrieve response argument */ + val = GetRespArg (buf, sizeof(buf)); + + if (val > 1) { + p = (char *)&buf[0]; + + /* Read error code (buf = hex integer) */ + uval = strtoul (p, &p, 16); + + *err_code = uval; + + val = 0; + } + + return (val); +} + + +/** + Get standalone generic response. + + Standalone generic responses are responses that come without +CMD:data. Parser detect them and + deliver them into internal variable. + + \return generic response code AT_RESP_x +*/ +int32_t AT_Resp_Generic (void) { + + /* Return generic response */ + return (pCb->gen_resp); +} + + +/** + Test AT startup + + Generic response is expected. + + \return 0:OK, -1: error +*/ +int32_t AT_Cmd_TestAT (void) { + char out[8]; + int32_t n; + + /* Open AT command (AT+ */ + n = sprintf (out, "%s", "AT"); + + /* Append CRLF and send command */ + return (CmdSend(CMD_UART_CUR, out, n)); +} + +/** + Restarts the module + + Generic response is expected. + + Format: AT+RST + + \return 0:OK, -1: error +*/ +int32_t AT_Cmd_Reset (void) { + char out[16]; + int32_t n; + + /* Open AT command (AT+ */ + n = CmdOpen (CMD_RST, AT_CMODE_EXEC, out); + + /* Append CRLF and send command */ + return (CmdSend(CMD_RST, out, n)); +} + +/** + Check version information + + Generic response is expected. + + Format: AT+GMR + + \return 0:OK, -1: error +*/ +int32_t AT_Cmd_GetVersion (void) { + char out[16]; + int32_t n; + + /* Open AT command (AT+ */ + n = CmdOpen (CMD_GMR, AT_CMODE_EXEC, out); + + /* Append CRLF and send command */ + return (CmdSend(CMD_GMR, out, n)); +} + +/** + Get response to GetVersion command + + \param[out] buf data buffer + \param[in] len data buffer size +*/ +int32_t AT_Resp_GetVersion (uint8_t *buf, uint32_t len) { + uint8_t crlf[] = {'\r', '\n'}; + int32_t cnt = (int32_t)len; + int32_t val; + int32_t n; + + /* Initialize total number of read bytes */ + val = 0U; + + while (val < cnt) { + /* Check if we can find crlf */ + n = BufFind (crlf, 2, &(pCb->resp)); + + if (n < 0) { + break; + } + + /* Add crlf */ + n += 2; + + /* Check if len is ok */ + if ((val + n) > cnt) { + n = (cnt - val); + } + val += BufRead(&buf[val], (uint32_t)n, &(pCb->resp)); + } + + /* Flush any leftovers */ + do { + n = BufReadByte(&(pCb->resp)); + } + while (n != -1); + + return (val); +} + + +/** + Enable or disable command echo. + + Received commands can be echoed. + Generic response is expected. + + \param[in] enable Echo enable(1) or disable(0) + \return 0:OK, -1: error +*/ +int32_t AT_Cmd_Echo (uint32_t enable) { + char out[8]; + int32_t n; + + /* Open AT command (AT+ */ + n = sprintf (out, "%s%d", "ATE", enable); + + /* Append CRLF and send command */ + return (CmdSend(CMD_UART_CUR, out, n)); +} + +/** + Set/Query the current UART configuration + + Format S: AT+UART_CUR=,,,, + Format Q: AT+UART_CUR? + + Example S: AT+UART_CUR=115200,8,1,0,0\r\n + + \param[in] at_cmode Command mode (inquiry, set, exec) + \param[in] baudrate + \param[in] databits + \param[in] stop_par_flowc stopbits[5:4], parity[3:2], flow control[1:0] + \return 0:OK, -1: error +*/ +int32_t AT_Cmd_ConfigUART (uint32_t at_cmode, uint32_t baudrate, uint32_t databits, uint32_t stop_par_flowc) { + char out[32]; + uint32_t stopbits, parity, flow_ctrl; + int32_t n; + + /* Open AT command (AT+ */ + n = CmdOpen (CMD_UART_CUR, AT_CMODE_SET, out); + + if (at_cmode == AT_CMODE_SET) { + stopbits = (stop_par_flowc >> 4) & 0x3; + parity = (stop_par_flowc >> 2) & 0x3; + flow_ctrl = (stop_par_flowc >> 0) & 0x3; + + /* Add command arguments */ + n += sprintf (&out[n], "%d,%d,%d,%d,%d", baudrate, databits, stopbits, parity, flow_ctrl); + } + + /* Append CRLF and send command */ + return (CmdSend(CMD_UART_CUR, out, n)); +} + +/** + Get response to ConfigUART command + + Response Q: +UART_CUR:,,,,\r\n\r\n\OK + + \param[out] baudrate + \param[out] databits + \param[out] stop_par_flowc stopbits[5:4], parity[3:2], flow control[1:0] + \return +*/ +int32_t AT_Resp_ConfigUART (uint32_t *baudrate, uint32_t *databits, uint32_t *stop_par_flowc) { + char *p; + uint8_t buf[32]; + int32_t val; + uint32_t a; /* Argument counter */ + uint32_t uval; /* Unsigned value storage */ + uint32_t spf; + + a = 0U; + + do { + /* Retrieve response argument */ + val = GetRespArg (buf, sizeof(buf)); + + if (val < 0) { + break; + } + + /* Ignore ':' delimiter */ + if (val != -1) { + p = (char *)&buf[0]; + + /* Got valid argument */ + if (a == 0) { + /* Read */ + uval = strtoul (p, &p, 10); + + /* Note: if S was 115200, Q might return 115273 */ + *baudrate = uval; + } + else if (a == 1) { + /* Read */ + uval = strtoul (p, &p, 10); + + *databits = uval; + } + else if (a == 2) { + /* Read */ + uval = strtoul (p, &p, 10); + + spf = (uval & 0x3) << 4; + } + else if (a == 3) { + /* Read */ + uval = strtoul (p, &p, 10); + + spf = (uval & 0x3) << 2; + } + else if (a == 4) { + /* Read */ + uval = strtoul (p, &p, 10); + + spf = (uval & 0x3); + + *stop_par_flowc = spf; + } + else { + /* Ignore unknown arguments */ + break; + } + + /* Increment number of arguments */ + a++; + } + } + while ((val != 2) && (val != 3)); + + if (val == 3) { + /* Last response */ + val = 0; + } + else { + if (val == 2) { + /* Response is pending */ + val = 1; + } + } + + return (val); +} + +/** + Configure the sleep modes. + + Format: AT+SLEEP= + + \note Command can be used only in Station mode. Modem-sleep is the default mode. + + \param[in] sleep_mode sleep mode (0: disabled, 1: Light-sleep, 2: Modem-sleep) + \return 0: ok, -1: error +*/ +int32_t AT_Cmd_Sleep (uint32_t at_cmode, uint32_t sleep_mode) { + char out[32]; + int32_t n; + + /* Open AT command (AT+ */ + n = CmdOpen (CMD_SLEEP, AT_CMODE_SET, out); + + if (at_cmode == AT_CMODE_SET) { + /* Add command arguments */ + n += sprintf (&out[n], "%d", sleep_mode); + } + + /* Append CRLF and send command */ + return (CmdSend(CMD_SLEEP, out, n)); +} + +/** + Get response to AutoConnectAP command. + + Response Q: +SLEEP: + Example Q: +SLEEP:2\r\n\r\nOK\r\n\ + + \param[out] sleep_mode Pointer to variable the where sleep mode is stored + \return execution status + - negative: error + - 0: OK, response retrieved, no more data +*/ +int32_t AT_Resp_Sleep (uint32_t *sleep_mode) { + uint8_t buf[32]; + int32_t val; + char *p; + + do { + /* Retrieve response argument */ + val = GetRespArg (buf, sizeof(buf)); + + if (val < 0) { + break; + } + + if (val != 1) { + /* Set pointer to extracted value */ + p = (char *)&buf[0]; + + /* Read */ + *sleep_mode = p[0] - '0'; + break; + } + } + while (val != 3); + + if (val < 0) { + val = -1; + } else { + val = 0; + } + + return (val); +} + +/** + Set maximum value of RF TX power (dBm). + + Power range for + ESP8266: range [0:82], units 0.25dBm + ESP32: + AT 1.2.0: range[0:11] = {19.5, 19, 18.5, 17, 15, 13, 11, 8.5, 7, 5, 2, -1}dBm + AT 2.0.0: range[40,82], units 0.25dBm (value 78 means RF power 78*0.25dBm = 19.5dBm) + + Response: Generic + + \param[in] tx_power power value + \return 0: ok, -1: error +*/ +int32_t AT_Cmd_TxPower (uint32_t tx_power) { + char out[32]; + int32_t n; + + /* Open AT command (AT+ */ + n = CmdOpen (CMD_RFPOWER, AT_CMODE_SET, out); + + /* Add command arguments */ + n += sprintf (&out[n], "%d", tx_power); + + /* Append CRLF and send command */ + return (CmdSend(CMD_RFPOWER, out, n)); +} + +/** + Set current system messages. + + Command: SYSMSG/SYSMSG_CUR + Response: Generic + + Bit 0: configure the message of quitting passthrough transmission + Bit 1: configure the message of establishing a network connection + 0 - ,CONNECT + 1 - +LINK_CONN:,,"UDP/TCP/SSL",, + , + + \note Only AT set command is available. + + \param[in] n message configuration bit mask [0:1] +*/ +int32_t AT_Cmd_SysMessages (uint32_t n) { + char out[32]; + int32_t k; + + /* Open AT command (AT+ */ + k = CmdOpen (CMD_SYSMSG_CUR, AT_CMODE_SET, out); + + /* Add command arguments */ + k += sprintf (&out[k], "%d", n); + + /* Append CRLF and send command */ + return (CmdSend(CMD_SYSMSG_CUR, out, k)); +} + + +/** + Set/Query the current Wi-Fi mode + + Format S: AT+CWMODE_CUR= + + Response Q: AT_Resp_CurrentMode + + \param[in] at_cmode Command mode (inquiry, set, exec) + \param[in] mode Mode, 0: RF disabled (ESP32), 1: station, 2: soft AP, 3: soft AP + station + \return 0: OK, -1: error (invalid mode, etc) +*/ +int32_t AT_Cmd_CurrentMode (uint32_t at_cmode, uint32_t mode) { + char out[32]; + int32_t n; + + /* Open AT command (AT+ */ + n = CmdOpen (CMD_CWMODE_CUR, at_cmode, out); + + if (at_cmode == AT_CMODE_SET) { + /* Add command arguments */ + n += sprintf (&out[n], "%d", mode); + } + + /* Append CRLF and send command */ + return (CmdSend(CMD_CWMODE_CUR, out, n)); +} + +/** + Get response to CurrentMode command + + Response Q: +CWMODE_CUR: + Example Q: +CWMODE_CUR:3\r\n\r\n\OK + + \param[in] mode Mode, 1: station, 2: soft AP, 3: soft AP + station + \return 0: OK, -1: error (invalid mode, etc) +*/ +int32_t AT_Resp_CurrentMode (uint32_t *mode) { + uint8_t buf[32]; + int32_t val; + char *p; + + do { + /* Retrieve response argument */ + val = GetRespArg (buf, sizeof(buf)); + + if (val < 0) { + break; + } + + if (val != 1) { + /* Set pointer to extracted value */ + p = (char *)&buf[0]; + + /* Read */ + *mode = p[0] - '0'; + break; + } + } + while (val != 2); + + if (val < 0) { + val = -1; + } else { + val = 0; + } + + return (val); +} + + +/** + Set/Query connected access point or access point to connect to + + Format S: AT+CWJAP_CUR=,[,] + Format Q: AT+CWJAP_CUR? + + Response S: + "WIFI CONNECTED" + "WIFI GOT IP" + "" + "OK" + + Response Q: AT_Resp_ConnectAP + + \param[in] ssid + \param[in] pwd + \param[in] bssid + \return 0: ok, -1: error +*/ +int32_t AT_Cmd_ConnectAP (uint32_t at_cmode, const char *ssid, const char *pwd, const char *bssid) { + char out[64]; + int32_t n; + + /* Open AT command (AT+ */ + n = CmdOpen (CMD_CWJAP_CUR, at_cmode, out); + + if (at_cmode == AT_CMODE_SET) { + /* Add command arguments */ + n += sprintf (&out[n], "\"%s\",\"%s\"", ssid, pwd); + + if (bssid != NULL) { + n += sprintf (&out[n], ",\"%s\"", bssid); + } + } + + /* Append CRLF and send command */ + return (CmdSend(CMD_CWJAP_CUR, out, n)); +} + +/** + Response to ESP_ConnectAP command. + + Response Q: +CWJAP_CUR:,,, + Example Q: +CWJAP_CUR:"AP_SSID","xx:xx:xx:xx:xx:xx",6,-60 + + \todo Handle SET response + + \return - 1: connection timeout + - 2: wrong password + - 3: cannot find the target AP + - 4: connection failed +*/ +int32_t AT_Resp_ConnectAP (AT_DATA_CWJAP *ap) { + char *p; + uint8_t buf[32+1]; + int32_t val; + uint32_t a; /* Argument counter */ + uint32_t uval; /* Unsigned value storage */ + + a = 0U; + + do { + /* Retrieve response argument */ + val = GetRespArg (buf, sizeof(buf)); + + if (val < 0) { + break; + } + + if(ap == NULL) + { + /* Extract and return error code */ + return (buf[0] - 0x30); + } + /* Ignore ':' delimiter */ + if (val != -1) { + p = (char *)&buf[0]; + + /* Got valid argument */ + if (a == 0) { + /* Read (buf = "string") */ + strcpy (ap->ssid, (const char *)buf); + } + else if (a == 1) { + /* Read (buf = "xx:xx:xx:xx:xx:xx") */ + AT_Parse_MAC (p, ap->bssid); + } + else if (a == 2) { + /* Read */ + uval = strtoul (p, &p, 10); + + ap->ch = (uint8_t)uval; + } + else if (a == 3) { + /* Read */ + uval = strtoul (p, &p, 10); + + ap->rssi = (uint8_t)uval; + } + else { + /* Unknown arguments */ + } + + /* Increment number of arguments */ + a++; + } + } + while ((val != 2) && (val != 3)); + + if (val == 3) { + /* Last response */ + val = 0; + } + else { + if (val == 2) { + /* Response is pending */ + val = 1; + } + } + + return (val); +} + + +/** + Disconnect from current Access Point (CWQAP) + + \return 0:ok, -1: error +*/ +int32_t AT_Cmd_DisconnectAP (void) { + char out[32]; + int32_t n; + + /* Open AT command (AT+ */ + n = CmdOpen (CMD_CWQAP, AT_CMODE_EXEC, out); + + /* Append CRLF and send command */ + return (CmdSend(CMD_CWQAP, out, n)); +} + + +/** + Configure local access point (SoftAP must be active) + + Format: AT+CWSAP_CUR=,,,[,][,