599 lines
18 KiB
C
599 lines
18 KiB
C
/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
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*
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* The information contained herein is property of Kneron, Inc.
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* Terms and conditions of usage are described in detail in Kneron
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* STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information.
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* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
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* from the file.
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*/
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/******************************************************************************
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* Filename:
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* ---------
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* ipc.h
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*
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* Description:
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* ------------
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*
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*
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******************************************************************************/
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#ifndef _IPC_H_
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#define _IPC_H_
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/******************************************************************************
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Head Block of The File
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******************************************************************************/
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#include <stdint.h>
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#include "model_type.h"
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#include "model_res.h"
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#include "base.h"
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//#include "extend_intf.h"
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#ifndef BOOLEAN_DEFINED
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#ifndef boolean
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typedef char boolean;
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#endif
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#define BOOLEAN_DEFINED
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#endif
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#if _BOARD_SN720HAPS_H_ == 1
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#define ADDR_ADJUST_OFFSET_FOR_HAPS 0x01d2b000
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// Sec 2: Constant Definitions, Imported Symbols, miscellaneous
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/* IPC memory */
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//----------------------------
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/* Used for KL720 */
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#define SCPU_IPC_MEM_ADDR (0x85060000 + ADDR_ADJUST_OFFSET_FOR_HAPS)
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#define SCPU_IPC_MEM_ADDR2 (0x85061000 + ADDR_ADJUST_OFFSET_FOR_HAPS)
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#define IPC_NPU_REQ_IMG_MSG_ADDR (SCPU_IPC_MEM_ADDR2+0x100)
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#else
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#include "membase.h"
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#define SCPU_IPC_MEM_ADDR DDR_MEM_IPC_ADDR
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#define SCPU_IPC_MEM_ADDR2 (SCPU_IPC_MEM_ADDR + 0x1C00)
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#endif
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#define SCPU2NCPU_ID ('s'<<24 | 'c'<<16 | 'p'<<8 | 'u')
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#define NCPU2SCPU_ID ('n'<<24 | 'c'<<16 | 'p'<<8 | 'u')
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#define MULTI_MODEL_MAX 16 /* Max active models in memory */
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#define IPC_IMAGE_ACTIVE_MAX 2 /* Max active images for NCPU/NPU */
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#define IPC_IMAGE_MAX 10 /* Max cycled buffer for images */
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#define IPC_MODEL_MAX (MULTI_MODEL_MAX * IPC_IMAGE_ACTIVE_MAX)
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/* Image process cmd_flags set by scpu, TODO: Check all state command */
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#define IMAGE_STATE_INACTIVE 0
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#define IMAGE_STATE_ACTIVE 1
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#define IMAGE_STATE_NPU_DONE 2
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#define IMAGE_STATE_DONE 3
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#define IMAGE_STATE_JPEG_ENC_DONE 4
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#define IMAGE_STATE_JPEG_DEC_DONE 5
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#define IMAGE_STATE_ERR_DSP_BUSY 6
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#define IMAGE_STATE_JPEG_ENC_FAIL 7
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#define IMAGE_STATE_JPEG_DEC_FAIL 8
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#define IMAGE_STATE_RECEIVING 9 //need check with mozart firmware
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#define IMAGE_STATE_TOF_DEC_DONE 10
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#define IMAGE_STATE_TOF_DEC_FAIL 11
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/* Image process status set by ncpu */
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#define IMAGE_STATE_IDLE 0
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#define IMAGE_STATE_NPU_BUSY 1
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//#define IMAGE_STATE_NPU_DONE 2
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#define IMAGE_STATE_POST_PROCESSING IMAGE_STATE_NPU_DONE
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#define IMAGE_STATE_POST_PROCESSING_DONE 3
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//#define IMAGE_STATE_DONE IMAGE_STATE_POST_PROCESSING_DONE
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#define IMAGE_STATE_ERR (-1)
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#define IMAGE_STATE_TIMEOUT (7)
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/* Image format flags and config values */
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typedef enum {
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/* normalization control
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* ------------------*/
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IMAGE_FORMAT_SUB128 = (int)BIT31, /* 1: sub 128 for each value */
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IMAGE_FORMAT_RIGHT_SHIFT_ONE_BIT = BIT22, /* 1: right shift for 1-bit (normalization)*/
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/* cv rotate control
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* ------------------*/
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IMAGE_FORMAT_ROT_MASK = (BIT30 | BIT29),
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IMAGE_FORMAT_ROT_SHIFT = 29,
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/* -- setting values of ROT -- */
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IMAGE_FORMAT_ROT_CLOCKWISE = 0x01, /* ROT 90 */
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IMAGE_FORMAT_ROT_COUNTER_CLOCKWISE = 0x02, /* ROT 270 */
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IMAGE_FORMAT_ROT_180 = 0x03, // TODO, ROT 180
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/* flow control
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* ------------------*/
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//IMAGE_FORMAT_RAW_OUTPUT = BIT28 !!! move to "bypass control"
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IMAGE_FORMAT_PARALLEL_PROC = BIT27, /* 1: parallel execution of NPU and NCPU */
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//IMAGE_FORMAT_NOT_KEEP_RATIO = BIT26, // TODO, duplicated
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//IMAGE_FORMAT_MODEL_AGE_GENDER = BIT24, // TODO, should remove
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/* scale/crop control
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* -------------------*/
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//IMAGE_FORMAT_RIGHT_SHIFT_ONE_BIT = BIT22, !!! move to "normalization functions"
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IMAGE_FORMAT_SYMMETRIC_PADDING = BIT21, /* 1: symmetic padding;
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0: corner padding */
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IMAGE_FORMAT_CHANGE_ASPECT_RATIO = BIT20, /* 1: scale without padding;
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0: scale with padding */
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/* flow control - 2
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* ------------------*/
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IMAGE_FORMAT_BYPASS_PRE = BIT19, /* 1: bypass pre-process */
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IMAGE_FORMAT_BYPASS_NPU_OP = BIT18, /* 1: bypass NPU OP */
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IMAGE_FORMAT_BYPASS_CPU_OP = BIT17, /* 1: bypass CPU OP */
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IMAGE_FORMAT_BYPASS_POST = BIT16, /* 1: bypass post-process (output NPU result directly) */
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IMAGE_FORMAT_RAW_OUTPUT = BIT28, /* 1: bypass post-process (include meta data for data parsing )*/
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/* supported image foramts BIT7 - BIT0
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* --------------------------------------*/
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IMAGE_FORMAT_NPU = 0x00FF, /* settings: NPU_FORMAT_XXXX */
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} dsp_img_fmt_t;
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/*********************************************
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* settings for IMAGE_FORMAT_NPU
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*********************************************/
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#define NPU_FORMAT_RGBA8888 0x00
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#define NPU_FORMAT_YUV422 0x10 /* similiar to Y0CBY1CR */
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#define NPU_FORMAT_NIR 0x20
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/* Determine the exact format with the data byte sequence in DDR memory:
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* [lowest byte]...[highest byte]
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*/
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#define NPU_FORMAT_YCBCR422 0x30 /* alias of CRY1CBY0 */
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#define NPU_FORMAT_YCBCR422_CRY1CBY0 0x30
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#define NPU_FORMAT_YCBCR422_CBY1CRY0 0x31
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#define NPU_FORMAT_YCBCR422_Y1CRY0CB 0x32
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#define NPU_FORMAT_YCBCR422_Y1CBY0CR 0x33
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#define NPU_FORMAT_YCBCR422_CRY0CBY1 0x34
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#define NPU_FORMAT_YCBCR422_CBY0CRY1 0x35
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#define NPU_FORMAT_YCBCR422_Y0CRY1CB 0x36
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#define NPU_FORMAT_YCBCR422_Y0CBY1CR 0x37 /* Y0CbY1CrY2CbY3Cr... */
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#define NPU_FORMAT_YUV444 0x40
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#define NPU_FORMAT_YCBCR444 0x50
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#define NPU_FORMAT_RGB565 0x60
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#define NPU_FORMAT_YUV420 0x70
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// ------------------------------------------
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#define MAX_CNN_NODES 45 //NetputNode, CPU nodes, Out Nodes, etc
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#define MAX_OUT_NODES 40 //max Out Nodes
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#define MAX_INT_FOR_ALIGN 0x10000000
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#define NCPU_CLOCK_CNT_PER_MS 500000
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#define KP_DEBUG_BUF_SIZE (8 * 1024 * 1024) // FIXME, max is 1920x1080 RGB8888
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/******************************************************************************
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Declaration of External Variables & Functions
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******************************************************************************/
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// Sec 3: declaration of external variable
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// Sec 4: declaration of external function prototype
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/******************************************************************************
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Declaration of data structure
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******************************************************************************/
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// Sec 5: structure, uniou, enum, linked list
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/* Model structure */
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typedef struct kdp_model_s {
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/* Model type */
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uint32_t model_type; //defined in model_type.h
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/* Model version */
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uint32_t model_version;
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/* Input in memory */
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uint32_t input_mem_addr;
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int32_t input_mem_len;
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/* Output in memory */
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uint32_t output_mem_addr;
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int32_t output_mem_len;
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/* Working buffer */
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uint32_t buf_addr;
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int32_t buf_len;
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/* command.bin in memory */
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uint32_t cmd_mem_addr;
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int32_t cmd_mem_len;
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/* weight.bin in memory */
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uint32_t weight_mem_addr;
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int32_t weight_mem_len;
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/* setup.bin in memory */
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uint32_t setup_mem_addr;
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int32_t setup_mem_len;
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} kdp_model_t;
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typedef struct kdp_model_s kdp_model_info_t;
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/* Result structure of a model */
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typedef struct result_buf_s {
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int32_t model_id;
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uint32_t result_mem_addr;
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int32_t result_mem_len;
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int32_t result_ret_len;
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} result_buf_t;
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#define MAX_PARAMS_LEN 40 /* uint32_t */
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#define MAX_INPUT_NODE_COUNT 5
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/* Parameter structure of a raw image */
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typedef struct parameter_s {
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/* Crop parameters or other purposes */
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int crop_top;
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int crop_bottom;
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int crop_left;
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int crop_right;
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/* Pad parameters or other purposes */
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int pad_top;
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int pad_bottom;
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int pad_left;
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int pad_right;
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float scale_width;
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float scale_height;
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/* IE driver padding mode for pre-processing
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0:change aspect ratio(no padding).
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1:keep aspect ratio, allow scaling, pad corner(right or bottom)
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2:keep aspect ratio, allow scaling, pad center(top/down or right/left)
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3:keep aspect ratio, not allow scaling, pad corner(right or bottom)
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4:keep aspect ratio, not allow scaling, pad center(top/down, or right/left)
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*/
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uint32_t ie_pad_mode;
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int32_t angle;
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int flip_face;
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} parameter_t;
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typedef struct kdp_img_info_s {
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/* input image in memory */
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uint32_t image_mem_addr;
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int32_t image_mem_len;
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/* raw image dimensions */
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uint32_t input_row;
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uint32_t input_col;
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uint32_t input_channel;
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/* Raw image format and pre-process flags
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* refer to dsp_img_fmt_t
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*/
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uint32_t format;
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/* Parameter structure */
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struct parameter_s params_s;
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} kdp_img_info_t;
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struct kdp_img_cfg {
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uint32_t num_image;
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kdp_img_info_t image_list[MAX_INPUT_NODE_COUNT];
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uint32_t inf_format;
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uint32_t image_buf_active_index; // scpu_to_ncpu->active_img_index
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};
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struct kdp_crop_box_s {
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int32_t top;
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int32_t bottom;
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int32_t left;
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int32_t right;
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};
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struct kdp_pad_value_s {
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int32_t pad_top;
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int32_t pad_bottom;
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int32_t pad_left;
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int32_t pad_right;
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};
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typedef struct {
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uint32_t w;
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uint32_t h;
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uint32_t c;
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} img_dim_t;
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/* scpu_to_ncpu: cmd */
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typedef enum {
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CMD_INVALID,
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CMD_INIT,
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CMD_RUN_NPU,
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CMD_SLEEP_NPU,
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CMD_JPEG_ENCODE,
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CMD_JPEG_DECODE,
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CMD_CROP_RESIZE,
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CMD_TOF_DECODE,
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CMD_SCPU_NCPU_TOTAL,
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CMD_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} scpu_ncpu_cmd_t;
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/* in every IPC interrupt triggered by NCPU, SCPU check in_comm_p to see the data type */
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typedef enum {
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NCPU_REQUEST_NEW_IMG = 1,
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NCPU_EXEC_RESULT,
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MSG_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} ncpu_scpu_ipc_msg_type_t;
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/* overall SCPU/DSP status*/
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typedef enum {
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NCPU_STS_READY = 0, //DSP is ready to run new task
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NCPU_STS_BUSY, // one of CNN/JPEG ENC/JPEG DEC is running, cannot accept new task now
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NCPU_STS_INVALID_PARAM, // invalid IPC parameters
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STS_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} ncpu_status_t;
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typedef enum {
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POST_PROC_FAIL = -1,
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POST_PROC_SUCCESS = 0,
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RET_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} post_proc_return_sts_t;
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/* Raw image structure */
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typedef struct kdp_img_raw_s {
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/* Image state: 1 = active, 0 = inactive */
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int state;
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/* Image sequence number */
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int seq_num;
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/* Image ref index */
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int ref_idx;
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/* List of raw images */
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uint32_t num_image;
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kdp_img_info_t image_list[MAX_INPUT_NODE_COUNT];
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/* Parallel and raw output flags
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* refer to dsp_img_fmt_t
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*/
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uint32_t inf_format;
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/* Shared parameters for raw image */
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uint32_t ext_params[MAX_PARAMS_LEN];
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struct result_buf_s result;
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/* Test: SCPU total */
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uint32_t tick_start;
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uint32_t tick_end;
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uint32_t tick_got_ncpu_ack;
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/* Test: NCPU processes */
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uint32_t tick_start_parse;
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uint32_t tick_end_parse;
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uint32_t tick_start_inproc;
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uint32_t tick_end_inproc;
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uint32_t tick_start_pre;
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uint32_t tick_end_pre;
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uint32_t tick_start_npu;
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uint32_t tick_cnn_interrupt_rvd;
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uint32_t tick_end_npu;
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uint32_t tick_start_post;
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uint32_t tick_end_post;
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uint32_t tick_start_dram_copy;
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uint32_t tick_end_dram_copy;
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uint32_t tick_rslt_got_scpu_ack;
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uint32_t tick_ncpu_img_req;
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uint32_t tick_ncpu_img_ack;
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uint32_t tick_last_img_req;
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} kdp_img_raw_t;
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/* Image result structure */
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typedef struct kdp_img_result_s {
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post_proc_return_sts_t status __attribute__((aligned (4)));
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/* Image sequence number */
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int seq_num;
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/* result memory addr */
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//dummy information
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uint32_t result_mem_addr;
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} kdp_img_result_t;
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typedef struct {
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uint32_t fmt;
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parameter_t param;
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img_dim_t src_dim;
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img_dim_t dst_dim;
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uint32_t src_addr;
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uint32_t src_data_len;
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uint32_t dst_addr;
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uint32_t dst_buf_size;
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uint32_t dst_filled_len;
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int32_t seq_num;
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int32_t bUseHwInproc; /* 1: use NPU HW inproc; 0: use DSP SW solution */
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uint32_t tmp_buf_addr; /* this tmp_buf_addr is needed for SW crop/resize, not for HW inproc */
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} crop_resize_param_t;
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typedef enum {
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CROP_RESIZE_OPERATION_FAILED = -1, /* Failure in doing operation */
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CROP_RESIZE_OPERATION_SUCCESS = 1, /* Operation Succeded */
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CROP_RESIZE_OPERATION_INVALID_PARM, /* Inavlid parameter provided */
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RESIZE_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} crop_resize_oper_sts_t;
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typedef struct {
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int32_t rslt_type; //NCPU_TO_SCPU_RESULT_TYPE
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crop_resize_oper_sts_t sts __attribute__((aligned (4)));
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/* output buf */
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uint32_t out_addr;
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uint32_t out_len;
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int32_t seq_num;
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} crop_resize_result_t;
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/* Structure of nCPU->sCPU IPC Message data */
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typedef struct ncpu_to_scpu_req_img_s {
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int32_t bHandledByScpu;
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int32_t ipc_type; //ncpu_scpu_ipc_msg_type_t
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int32_t sts; //ncpu_status_t
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} ncpu_to_scpu_req_img_t;
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typedef struct
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{
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int model_id;
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uint32_t tick_before_preprocess;
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uint32_t sum_ticks_preprocess;
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uint32_t tick_before_inference;
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uint32_t sum_ticks_inference;
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uint32_t tick_before_postprocess;
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uint32_t sum_ticks_postprocess;
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uint32_t tick_before_cpu_op;
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uint32_t sum_ticks_cpu_op;
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uint32_t sum_cpu_op_count;
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uint32_t sum_frame_count;
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} kp_model_profile_t;
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/* Structure of sCPU->nCPU Message */
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typedef struct scpu_to_ncpu_s {
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uint32_t id; /* = 'scpu' */
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volatile uint32_t bNcpuReceived;
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uint32_t cmd; // scpu_ncpu_cmd_t
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/*
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* debug control flags (dbg.h):
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* bits 19-16: scpu debug level
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* bits 03-00: ncpu debug level
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*/
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uint32_t debug_flags;
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uint32_t kp_dbg_checkpoinots;
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/* Active models in memory and running */
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int32_t num_models; //usually, num_models=1 (only one active model)
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struct kdp_model_s models[IPC_MODEL_MAX]; //to save active modelInfo
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int32_t models_type[IPC_MODEL_MAX]; //to save model type
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int32_t model_slot_index;
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/* working buffer in case in-proc is necessary, raw img will copy to here for in-proc,
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in-proc output will be placed in the input mem address in setup.bin */
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uint32_t input_mem_addr2;
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int32_t input_mem_len2;
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/* Memory for DME */
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uint32_t output_mem_addr2;
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int32_t output_mem_len2;
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|
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/* Memory for post processing (shared) */
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uint32_t output_mem_addr3;
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kdp_img_raw_t *pRawimg; //SCPU need to alloc for every image
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uint32_t ncpu_img_req_msg_addr; // ncpu_to_scpu_req_img_t *, SCPU always get result from here
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uint32_t log_buf_base;
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int32_t log_buf_len;
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|
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/* support features extension or for standalone non-cnn features */
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void* pExtInParam; //pointer to extended parameter data structure
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int32_t nLenExtInParam; //length of extended parameter data structure
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void* pExtOutRslt; //pointer to extended feature result data structure
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int32_t nLenExtOutRslt; //Length of extended feature result data
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void* pCpuNodeBuffer; // pointer to working buffer for Cpu Node
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int32_t nLenCpuNodeBuffer; // Length of working buffer for Cpu Node
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|
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/* Raw image information */
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|
struct kdp_img_raw_s raw_images[IPC_IMAGE_MAX];
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|
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/* Memory for post processing (shared) */
|
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uint32_t output_mem_addr4;
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|
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void * kp_dbg_buffer;
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|
|
|
uint32_t kp_dbg_enable_profile; // 1: enable, 0: disable
|
|
kp_model_profile_t kp_model_profile_records[MULTI_MODEL_MAX];
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} scpu_to_ncpu_t;
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|
|
|
typedef enum {
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|
NCPU_NONE_RESULT = -1,
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NCPU_POSTPROC_RESULT = 1,
|
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NCPU_JPEG_ENC_RESULT,
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NCPU_JPEG_DEC_RESULT,
|
|
NCPU_CROP_RESIZE_RESULT,
|
|
NCPU_TOF_DEC_RESULT,
|
|
NCPU_RESULT_TYPE_MAX,
|
|
RES_ALIGN_32 = MAX_INT_FOR_ALIGN,
|
|
} ncpu_to_scpu_result_type;
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|
|
|
/* Structure of nCPU->sCPU IPC Message data */
|
|
typedef struct ncpu_to_scpu_postproc_result_s {
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int32_t model_slot_index; // RUN which model for this image
|
|
kdp_img_result_t img_result;
|
|
uint32_t OrigRawImgAddr;
|
|
} ncpu_to_scpu_postproc_result_t;
|
|
|
|
typedef struct ncpu_to_scpu_s {
|
|
volatile boolean print_log;
|
|
uint8_t *p_log_buf_base;
|
|
uint32_t id; /* = 'ncpu' */
|
|
int32_t bHandledByScpu;
|
|
ncpu_scpu_ipc_msg_type_t ipc_type __attribute__((aligned (4))); //ncpu_scpu_ipc_msg_type_t
|
|
ncpu_status_t sts __attribute__((aligned (4))); //overall NCPU/DSP status
|
|
ncpu_to_scpu_result_type out_type __attribute__((aligned (4)));
|
|
|
|
ncpu_to_scpu_postproc_result_t postproc;
|
|
uint32_t extRsltAddr;
|
|
|
|
ncpu_to_scpu_req_img_t req_img;
|
|
volatile int32_t kp_dbg_status;
|
|
} ncpu_to_scpu_result_t;
|
|
|
|
/*50k log buffer*/
|
|
#define MAX_LOG_LENGTH 256
|
|
#define LOG_QUEUE_NUM 200
|
|
#define FLAG_LOGGER_SCPU_IN (1U << 0)
|
|
#define FLAG_LOGGER_NCPU_IN (1U << 1)
|
|
|
|
enum {
|
|
LOGGER_SCPU_IN = 0,
|
|
LOGGER_NCPU_IN,
|
|
LOGGER_OUT,
|
|
LOGGER_TOTAL
|
|
};
|
|
|
|
typedef struct {
|
|
volatile boolean init_done;
|
|
volatile boolean willing[LOGGER_TOTAL];
|
|
volatile uint8_t w_idx;
|
|
volatile uint8_t r_idx;
|
|
volatile uint8_t turn;
|
|
uint8_t *p_msg;
|
|
} logger_mgt_t;
|
|
|
|
|
|
#endif //_IPC_H_
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