438 lines
19 KiB
C
438 lines
19 KiB
C
#include "kdpio.h"
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#define ADDR_NPU_CODE 0x30ff0000
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#define ADDR_NPU_CLEN 0x30ff0004
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#define ADDR_NPU_RUN 0x30ff0008
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#define ADDR_NPU_ELEN 0x30ff000c
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#define ADDR_NPU_VER 0x30ff0010
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#define ADDR_NPU_MODE 0x30ff0014
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#define ADDR_NPU_DMA 0x30ff0018
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#define ADDR_NPU_RDMA0_SRC0 0x30ff001c
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#define ADDR_NPU_RDMA0_SRC1 0x30ff0020
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#define ADDR_NPU_RDMA0_SRC2 0x30ff0024
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#define ADDR_NPU_RDMA0_DST 0x30ff0028
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#define ADDR_NPU_RDMA0_BLK 0x30ff002c
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#define ADDR_NPU_RDMA1_SRC0 0x30ff0030
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#define ADDR_NPU_RDMA1_SRC1 0x30ff0034
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#define ADDR_NPU_RDMA1_SRC2 0x30ff0038
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#define ADDR_NPU_RDMA1_DST 0x30ff003c
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#define ADDR_NPU_RDMA1_BLK 0x30ff0040
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#define ADDR_NPU_RDMA2_SRC0 0x30ff0044
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#define ADDR_NPU_RDMA2_SRC1 0x30ff0048
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#define ADDR_NPU_RDMA2_SRC2 0x30ff004c
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#define ADDR_NPU_RDMA2_SRC3 0x30ff0050
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#define ADDR_NPU_RDMA2_DST 0x30ff0054
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#define ADDR_NPU_RDMA2_BLK 0x30ff0058
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#define ADDR_NPU_GETW0 0x30ff005c
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#define ADDR_NPU_GETW1 0x30ff0060
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#define ADDR_NPU_GETW2 0x30ff0064
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#define ADDR_NPU_WDMA0_SRC 0x30ff0068
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#define ADDR_NPU_WDMA0_DST0 0x30ff006c
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#define ADDR_NPU_WDMA0_DST1 0x30ff0070
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#define ADDR_NPU_WDMA0_DST2 0x30ff0074
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#define ADDR_NPU_WDMA0_BLK 0x30ff0078
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#define ADDR_NPU_WDMA1_SRC 0x30ff007c
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#define ADDR_NPU_WDMA1_DST0 0x30ff0080
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#define ADDR_NPU_WDMA1_DST1 0x30ff0084
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#define ADDR_NPU_WDMA1_DST2 0x30ff0088
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#define ADDR_NPU_WDMA1_BLK 0x30ff008c
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#define ADDR_NPU_NMEM_FM0 0x30ff0090
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#define ADDR_NPU_NMEM_FM1 0x30ff0094
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#define ADDR_NPU_NMEM_FM2 0x30ff0098
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#define ADDR_NPU_NMEM_PS0 0x30ff009c
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#define ADDR_NPU_NMEM_PS1 0x30ff00a0
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#define ADDR_NPU_NMEM_PS2 0x30ff00a4
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#define ADDR_NPU_NMEM_ST0 0x30ff00a8
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#define ADDR_NPU_NMEM_ST1 0x30ff00ac
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#define ADDR_NPU_NMEM_ST2 0x30ff00b0
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#define ADDR_NPU_NMEM_RDMA0 0x30ff00b4
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#define ADDR_NPU_NMEM_RDMA1 0x30ff00b8
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#define ADDR_NPU_NMEM_RDMA2 0x30ff00bc
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#define ADDR_NPU_NMEM_WDMA0 0x30ff00c0
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#define ADDR_NPU_NMEM_WDMA1 0x30ff00c4
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#define ADDR_NPU_NMEM_WDMA2 0x30ff00c8
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#define ADDR_NPU_NMEM_WT 0x30ff00cc
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#define ADDR_NPU_NMEM_LB 0x30ff00d0
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#define ADDR_NPU_CONV 0x30ff00d4
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#define ADDR_NPU_FMAP0 0x30ff00d8
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#define ADDR_NPU_FMAP1 0x30ff00dc
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#define ADDR_NPU_ZPAD 0x30ff00e0
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#define ADDR_NPU_NEXT0 0x30ff00e4
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#define ADDR_NPU_NEXT1 0x30ff00e8
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#define ADDR_NPU_NEXT2 0x30ff00ec
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#define ADDR_NPU_LWT 0x30ff00f0
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#define ADDR_NPU_STORE 0x30ff00f4
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#define ADDR_NPU_TRIM 0x30ff00f8
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#define ADDR_NPU_TRIM0 0x30ff00fc
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#define ADDR_NPU_RESHAPE 0x30ff0100
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#define ADDR_NPU_PCONV 0x30ff0104
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#define ADDR_NPU_BN 0x30ff0108
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#define ADDR_NPU_RELU 0x30ff010c
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#define ADDR_NPU_RELU6 0x30ff0110
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#define ADDR_NPU_POOL 0x30ff0114
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#define ADDR_NPU_GAP 0x30ff0118
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#define ADDR_NPU_FORMAT 0x30ff011c
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#define ADDR_NPU_RESIZE 0x30ff0120
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#define ADDR_NPU_RESIZE_SRC 0x30ff0124
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#define ADDR_NPU_RESIZE_DST 0x30ff0128
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#define ADDR_NPU_RESIZE_RATIO0 0x30ff012c
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#define ADDR_NPU_RESIZE_RATIO1 0x30ff0130
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#define ADDR_NPU_CHAN 0x30ff0134
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#define ADDR_NPU_PREP0 0x30ff0138
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#define ADDR_NPU_PREP1 0x30ff013c
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#define ADDR_NPU_PREP2 0x30ff0140
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#define ADDR_NPU_ENCRYPT 0x30ff0144
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#define ADDR_NPU_KEY 0x30ff0148
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#define ADDR_NPU_INTEN 0x30ff014c
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#define ADDR_NPU_INT 0x30ff0150
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#define ADDR_NPU_DBG0 0x30ff0154
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#define ADDR_NPU_DBG1 0x30ff0158
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#define ADDR_NPU_DBG2 0x30ff015c
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#define ADDR_NPU_REGM 0x30ff0160
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#define ADDR_NPU_DUMMY_0 0x30ff0164
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#define ADDR_NPU_DUMMY_1 0x30ff0168
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#define ADDR_NPU_DUMMY_2 0x30ff016c
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#define VAL_ACL(x) (((x)&0xffff))
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#define VAL_ACH(x) (((x)>>16)&0xffff)
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#define ACL_NPU_MODE 0xa
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#define ACH_NPU_MODE 0xb
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#define ACL_NPU_RDMA0_SRC0 0xe
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#define ACH_NPU_RDMA0_SRC0 0xf
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#define ACL_NPU_RDMA0_SRC1 0x10
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#define ACH_NPU_RDMA0_SRC1 0x11
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#define ACL_NPU_RDMA0_SRC2 0x12
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#define ACH_NPU_RDMA0_SRC2 0x13
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#define ACL_NPU_RDMA0_DST 0x14
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#define ACH_NPU_RDMA0_DST 0x15
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#define ACL_NPU_RDMA0_BLK 0x16
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#define ACH_NPU_RDMA0_BLK 0x17
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#define ACL_NPU_RDMA1_SRC0 0x18
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#define ACH_NPU_RDMA1_SRC0 0x19
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#define ACL_NPU_RDMA1_SRC1 0x1a
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#define ACH_NPU_RDMA1_SRC1 0x1b
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#define ACL_NPU_RDMA1_SRC2 0x1c
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#define ACH_NPU_RDMA1_SRC2 0x1d
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#define ACL_NPU_RDMA1_DST 0x1e
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#define ACH_NPU_RDMA1_DST 0x1f
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#define ACL_NPU_RDMA1_BLK 0x20
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#define ACH_NPU_RDMA1_BLK 0x21
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#define ACL_NPU_RDMA2_SRC0 0x22
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#define ACH_NPU_RDMA2_SRC0 0x23
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#define ACL_NPU_RDMA2_SRC1 0x24
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#define ACH_NPU_RDMA2_SRC1 0x25
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#define ACL_NPU_RDMA2_SRC2 0x26
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#define ACH_NPU_RDMA2_SRC2 0x27
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#define ACL_NPU_RDMA2_SRC3 0x28
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#define ACH_NPU_RDMA2_SRC3 0x29
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#define ACL_NPU_RDMA2_DST 0x2a
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#define ACH_NPU_RDMA2_DST 0x2b
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#define ACL_NPU_RDMA2_BLK 0x2c
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#define ACH_NPU_RDMA2_BLK 0x2d
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#define ACL_NPU_GETW0 0x2e
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#define ACH_NPU_GETW0 0x2f
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#define ACL_NPU_GETW1 0x30
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#define ACH_NPU_GETW1 0x31
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#define ACL_NPU_GETW2 0x32
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#define ACH_NPU_GETW2 0x33
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#define ACL_NPU_WDMA0_SRC 0x34
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#define ACH_NPU_WDMA0_SRC 0x35
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#define ACL_NPU_WDMA0_DST0 0x36
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#define ACH_NPU_WDMA0_DST0 0x37
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#define ACL_NPU_WDMA0_DST1 0x38
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#define ACH_NPU_WDMA0_DST1 0x39
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#define ACL_NPU_WDMA0_DST2 0x3a
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#define ACH_NPU_WDMA0_DST2 0x3b
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#define ACL_NPU_WDMA0_BLK 0x3c
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#define ACH_NPU_WDMA0_BLK 0x3d
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#define ACL_NPU_WDMA1_SRC 0x3e
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#define ACH_NPU_WDMA1_SRC 0x3f
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#define ACL_NPU_WDMA1_DST0 0x40
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#define ACH_NPU_WDMA1_DST0 0x41
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#define ACL_NPU_WDMA1_DST1 0x42
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#define ACH_NPU_WDMA1_DST1 0x43
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#define ACL_NPU_WDMA1_DST2 0x44
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#define ACH_NPU_WDMA1_DST2 0x45
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#define ACL_NPU_WDMA1_BLK 0x46
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#define ACH_NPU_WDMA1_BLK 0x47
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#define ACL_NPU_NMEM_FM0 0x48
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#define ACH_NPU_NMEM_FM0 0x49
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#define ACL_NPU_NMEM_FM1 0x4a
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#define ACH_NPU_NMEM_FM1 0x4b
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#define ACL_NPU_NMEM_FM2 0x4c
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#define ACH_NPU_NMEM_FM2 0x4d
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#define ACL_NPU_NMEM_PS0 0x4e
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#define ACH_NPU_NMEM_PS0 0x4f
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#define ACL_NPU_NMEM_PS1 0x50
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#define ACH_NPU_NMEM_PS1 0x51
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#define ACL_NPU_NMEM_PS2 0x52
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#define ACH_NPU_NMEM_PS2 0x53
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#define ACL_NPU_NMEM_ST0 0x54
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#define ACH_NPU_NMEM_ST0 0x55
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#define ACL_NPU_NMEM_ST1 0x56
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#define ACH_NPU_NMEM_ST1 0x57
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#define ACL_NPU_NMEM_ST2 0x58
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#define ACH_NPU_NMEM_ST2 0x59
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#define ACL_NPU_NMEM_RDMA0 0x5a
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#define ACH_NPU_NMEM_RDMA0 0x5b
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#define ACL_NPU_NMEM_RDMA1 0x5c
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#define ACH_NPU_NMEM_RDMA1 0x5d
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#define ACL_NPU_NMEM_RDMA2 0x5e
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#define ACH_NPU_NMEM_RDMA2 0x5f
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#define ACL_NPU_NMEM_WDMA0 0x60
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#define ACH_NPU_NMEM_WDMA0 0x61
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#define ACL_NPU_NMEM_WDMA1 0x62
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#define ACH_NPU_NMEM_WDMA1 0x63
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#define ACL_NPU_NMEM_WDMA2 0x64
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#define ACH_NPU_NMEM_WDMA2 0x65
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#define ACL_NPU_NMEM_WT 0x66
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#define ACH_NPU_NMEM_WT 0x67
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#define ACL_NPU_NMEM_LB 0x68
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#define ACH_NPU_NMEM_LB 0x69
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#define ACL_NPU_CONV 0x6a
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#define ACH_NPU_CONV 0x6b
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#define ACL_NPU_FMAP0 0x6c
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#define ACH_NPU_FMAP0 0x6d
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#define ACL_NPU_FMAP1 0x6e
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#define ACH_NPU_FMAP1 0x6f
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#define ACL_NPU_ZPAD 0x70
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#define ACH_NPU_ZPAD 0x71
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#define ACL_NPU_NEXT0 0x72
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#define ACH_NPU_NEXT0 0x73
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#define ACL_NPU_NEXT1 0x74
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#define ACH_NPU_NEXT1 0x75
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#define ACL_NPU_NEXT2 0x76
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#define ACH_NPU_NEXT2 0x77
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#define ACL_NPU_LWT 0x78
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#define ACH_NPU_LWT 0x79
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#define ACL_NPU_STORE 0x7a
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#define ACH_NPU_STORE 0x7b
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#define ACL_NPU_TRIM 0x7c
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#define ACH_NPU_TRIM 0x7d
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#define ACL_NPU_TRIM0 0x7e
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#define ACH_NPU_TRIM0 0x7f
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#define ACL_NPU_RESHAPE 0x80
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#define ACH_NPU_RESHAPE 0x81
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#define ACL_NPU_PCONV 0x82
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#define ACH_NPU_PCONV 0x83
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#define ACL_NPU_BN 0x84
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#define ACH_NPU_BN 0x85
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#define ACL_NPU_RELU 0x86
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#define ACH_NPU_RELU 0x87
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#define ACL_NPU_RELU6 0x88
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#define ACH_NPU_RELU6 0x89
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#define ACL_NPU_POOL 0x8a
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#define ACH_NPU_POOL 0x8b
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#define ACL_NPU_GAP 0x8c
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#define ACH_NPU_GAP 0x8d
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#define ACL_NPU_FORMAT 0x8e
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#define ACH_NPU_FORMAT 0x8f
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#define ACL_NPU_RESIZE 0x90
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#define ACH_NPU_RESIZE 0x91
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#define ACL_NPU_RESIZE_SRC 0x92
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#define ACH_NPU_RESIZE_SRC 0x93
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#define ACL_NPU_RESIZE_DST 0x94
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#define ACH_NPU_RESIZE_DST 0x95
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#define ACL_NPU_RESIZE_RATIO0 0x96
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#define ACH_NPU_RESIZE_RATIO0 0x97
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#define ACL_NPU_RESIZE_RATIO1 0x98
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#define ACH_NPU_RESIZE_RATIO1 0x99
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#define ACL_NPU_CHAN 0x9a
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#define ACH_NPU_CHAN 0x9b
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#define ACL_NPU_PREP0 0x9c
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#define ACH_NPU_PREP0 0x9d
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#define ACL_NPU_PREP1 0x9e
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#define ACH_NPU_PREP1 0x9f
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#define ACL_NPU_PREP2 0xa0
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#define ACH_NPU_PREP2 0xa1
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#define NPU_CODE_a(x) (((x)&0xffffffff)<<0)
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#define NPU_CLEN_l(x) (((x)&0xfffff)<<0)
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#define NPU_RUN_conv(x) (((x)&0x1)<<23)
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#define NPU_RUN_getw(x) (((x)&0x1)<<22)
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#define NPU_RUN_wdma(x) (((x)&0x1)<<21)
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#define NPU_RUN_rdma(x) (((x)&0x1)<<20)
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#define NPU_RUN_wfc(x) (((x)&0x1)<<17)
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#define NPU_RUN_busy(x) (((x)&0x1)<<16)
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#define NPU_RUN_slp(x) (((x)&0x1)<<9)
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#define NPU_RUN_ret(x) (((x)&0x1)<<8)
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#define NPU_RUN_conti(x) (((x)&0x1)<<1)
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#define NPU_RUN_go(x) (((x)&0x1)<<0)
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#define NPU_ELEN_l(x) (((x)&0xfffff)<<0)
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#define NPU_VER_num(x) (((x)&0xffff)<<0)
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#define NPU_MODE_8b_3x3_conv(x) (((x)&0x1)<<0)
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#define NPU_DMA_bl(x) (((x)&0x1fff)<<0)
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#define NPU_RDMA0_SRC0_sa(x) (((x)&0xffffffff)<<0)
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#define NPU_RDMA0_SRC1_pitch(x) (((x)&0xffffff)<<0)
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#define NPU_RDMA0_SRC2_len(x) (((x)&0xffff)<<0)
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#define NPU_RDMA0_DST_dl(x) (((x)&0xffff)<<0)
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#define NPU_RDMA0_BLK_line(x) (((x)&0xffff)<<0)
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#define NPU_RDMA1_SRC0_sa(x) (((x)&0xffffffff)<<0)
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#define NPU_RDMA1_SRC1_pitch(x) (((x)&0xffffff)<<0)
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#define NPU_RDMA1_SRC2_len(x) (((x)&0xffff)<<0)
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#define NPU_RDMA1_DST_dl(x) (((x)&0xffff)<<0)
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#define NPU_RDMA1_BLK_line(x) (((x)&0xffff)<<0)
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#define NPU_RDMA2_SRC0_sa(x) (((x)&0xffffffff)<<0)
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#define NPU_RDMA2_SRC1_pitch(x) (((x)&0xffffff)<<0)
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#define NPU_RDMA2_SRC2_len(x) (((x)&0xffff)<<0)
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#define NPU_RDMA2_SRC3_base(x) (((x)&0xffffffff)<<0)
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#define NPU_RDMA2_DST_dl(x) (((x)&0xffff)<<0)
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#define NPU_RDMA2_BLK_line(x) (((x)&0xffff)<<0)
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#define NPU_GETW0_sa(x) (((x)&0xffffffff)<<0)
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#define NPU_GETW1_len(x) (((x)&0xfffffff)<<0)
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#define NPU_GETW2_back(x) (((x)&0x7fff)<<0)
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#define NPU_WDMA0_SRC_sl(x) (((x)&0xffff)<<0)
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#define NPU_WDMA0_DST0_da(x) (((x)&0xffffffff)<<0)
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#define NPU_WDMA0_DST1_pitch(x) (((x)&0xffffff)<<0)
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#define NPU_WDMA0_DST2_len(x) (((x)&0xffff)<<0)
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#define NPU_WDMA0_BLK_line(x) (((x)&0xffff)<<0)
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#define NPU_WDMA1_SRC_sl(x) (((x)&0xffff)<<0)
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#define NPU_WDMA1_DST0_da(x) (((x)&0xffffffff)<<0)
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#define NPU_WDMA1_DST1_pitch(x) (((x)&0xffffff)<<0)
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#define NPU_WDMA1_DST2_len(x) (((x)&0xffff)<<0)
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#define NPU_WDMA1_BLK_line(x) (((x)&0xffff)<<0)
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#define NPU_NMEM_FM0_offset_x(x) (((x)&0xfff)<<16)
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#define NPU_NMEM_FM0_offset_y(x) (((x)&0x3f)<<8)
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#define NPU_NMEM_FM0_config(x) (((x)&0xf)<<0)
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#define NPU_NMEM_FM1_h(x) (((x)&0xffff)<<16)
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#define NPU_NMEM_FM1_w(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_FM2_l(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_PS0_offset_x(x) (((x)&0xfff)<<16)
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#define NPU_NMEM_PS0_offset_y(x) (((x)&0x3f)<<8)
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#define NPU_NMEM_PS0_config(x) (((x)&0xf)<<0)
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#define NPU_NMEM_PS1_h(x) (((x)&0xffff)<<16)
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#define NPU_NMEM_PS1_w(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_PS2_l(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_ST0_offset_x(x) (((x)&0xfff)<<16)
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#define NPU_NMEM_ST0_offset_y(x) (((x)&0x3f)<<8)
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#define NPU_NMEM_ST0_config(x) (((x)&0xf)<<0)
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#define NPU_NMEM_ST1_h(x) (((x)&0xffff)<<16)
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#define NPU_NMEM_ST1_w(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_ST2_l(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_RDMA0_offset_x(x) (((x)&0xfff)<<16)
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#define NPU_NMEM_RDMA0_offset_y(x) (((x)&0x3f)<<8)
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#define NPU_NMEM_RDMA0_config(x) (((x)&0xf)<<0)
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#define NPU_NMEM_RDMA1_h(x) (((x)&0xffff)<<16)
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#define NPU_NMEM_RDMA1_w(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_RDMA2_l(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_WDMA0_offset_x(x) (((x)&0xfff)<<16)
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#define NPU_NMEM_WDMA0_offset_y(x) (((x)&0x3f)<<8)
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#define NPU_NMEM_WDMA0_config(x) (((x)&0xf)<<0)
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#define NPU_NMEM_WDMA1_h(x) (((x)&0xffff)<<16)
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#define NPU_NMEM_WDMA1_w(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_WDMA2_l(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_WT_restart(x) (((x)&0x1)<<31)
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#define NPU_NMEM_WT_sa(x) (((x)&0xfff)<<16)
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#define NPU_NMEM_WT_ea(x) (((x)&0xfff)<<0)
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#define NPU_NMEM_LB_restart(x) (((x)&0x1)<<31)
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#define NPU_NMEM_LB_sa(x) (((x)&0xfff)<<16)
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#define NPU_NMEM_LB_ea(x) (((x)&0xfff)<<0)
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#define NPU_CONV_en(x) (((x)&0x1)<<31)
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#define NPU_CONV_ch_resume(x) (((x)&0x1)<<30)
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#define NPU_CONV_full_ch(x) (((x)&0x1)<<29)
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#define NPU_CONV_ps_och(x) (((x)&0x1)<<28)
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#define NPU_CONV_add_shift(x) (((x)&0x1)<<20)
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#define NPU_CONV_pformat(x) (((x)&0x3)<<16)
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#define NPU_CONV_zero(x) (((x)&0x1)<<10)
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#define NPU_CONV_step(x) (((x)&0x1)<<9)
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#define NPU_CONV_hstride2(x) (((x)&0x1)<<8)
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#define NPU_CONV_mode(x) (((x)&0xff)<<0)
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#define NPU_FMAP0_row(x) (((x)&0x1fff)<<16)
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#define NPU_FMAP0_col(x) (((x)&0x1fff)<<0)
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#define NPU_FMAP1_ch(x) (((x)&0x1fff)<<0)
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#define NPU_ZPAD_b(x) (((x)&0xf)<<12)
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#define NPU_ZPAD_r(x) (((x)&0xf)<<8)
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#define NPU_ZPAD_l(x) (((x)&0xf)<<4)
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#define NPU_ZPAD_t(x) (((x)&0xf)<<0)
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#define NPU_NEXT0_ch_end(x) (((x)&0x1fff)<<16)
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#define NPU_NEXT0_ch_start(x) (((x)&0x1fff)<<0)
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#define NPU_NEXT1_ch_total(x) (((x)&0x1fff)<<16)
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#define NPU_NEXT1_format(x) (((x)&0xf)<<0)
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#define NPU_NEXT2_line(x) (((x)&0xfff)<<0)
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#define NPU_LWT_prefetch(x) (((x)&0x1)<<2)
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#define NPU_LWT_w16b(x) (((x)&0x1)<<1)
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#define NPU_LWT_decomp(x) (((x)&0x1)<<0)
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#define NPU_STORE_en(x) (((x)&0x1)<<31)
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#define NPU_TRIM_wo(x) (((x)&0xf)<<24)
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#define NPU_TRIM_wv(x) (((x)&0xf)<<20)
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#define NPU_TRIM_w(x) (((x)&0xf)<<16)
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#define NPU_TRIM_ho(x) (((x)&0xf)<<4)
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#define NPU_TRIM_hm(x) (((x)&0xf)<<0)
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#define NPU_TRIM0_hc(x) (((x)&0xffff)<<16)
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#define NPU_TRIM0_wc(x) (((x)&0xffff)<<0)
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#define NPU_RESHAPE_ch(x) (((x)&0xffff)<<16)
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#define NPU_RESHAPE_ch_max(x) (((x)&0xffff)<<0)
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#define NPU_PCONV_en(x) (((x)&0x1)<<31)
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#define NPU_PCONV_shift(x) (((x)&0x1f)<<8)
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#define NPU_PCONV_pool(x) (((x)&0x1)<<6)
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#define NPU_PCONV_relu(x) (((x)&0x1)<<5)
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#define NPU_PCONV_bn(x) (((x)&0x1)<<4)
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#define NPU_PCONV_order(x) (((x)&0x7)<<0)
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#define NPU_BN_mode(x) (((x)&0xff)<<0)
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#define NPU_RELU_mode(x) (((x)&0x7)<<0)
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#define NPU_RELU6_clamp(x) (((x)&0xffffffff)<<0)
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#define NPU_POOL_zpad_r(x) (((x)&0x3)<<22)
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#define NPU_POOL_zpad_l(x) (((x)&0x3)<<20)
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#define NPU_POOL_zpad_b(x) (((x)&0x3)<<18)
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#define NPU_POOL_zpad_t(x) (((x)&0x3)<<16)
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#define NPU_POOL_stride(x) (((x)&0x3)<<8)
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#define NPU_POOL_size(x) (((x)&0x1)<<3)
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#define NPU_POOL_mode(x) (((x)&0x3)<<0)
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#define NPU_GAP_shift(x) (((x)&0x1f)<<16)
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#define NPU_GAP_mul(x) (((x)&0xffff)<<0)
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#define NPU_FORMAT_en(x) (((x)&0x1)<<31)
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#define NPU_FORMAT_uv_sub_128(x) (((x)&0x1)<<9)
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#define NPU_FORMAT_y_sub_128(x) (((x)&0x1)<<8)
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#define NPU_FORMAT_mode(x) (((x)&0xff)<<0)
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#define NPU_RESIZE_en(x) (((x)&0x1)<<31)
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#define NPU_RESIZE_restart(x) (((x)&0x1)<<30)
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#define NPU_RESIZE_SRC_offset(x) (((x)&0x3)<<0)
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#define NPU_RESIZE_DST_h(x) (((x)&0x1ff)<<16)
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#define NPU_RESIZE_DST_w(x) (((x)&0x1ff)<<0)
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#define NPU_RESIZE_RATIO0_w(x) (((x)&0xfffff)<<0)
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#define NPU_RESIZE_RATIO1_h(x) (((x)&0xfffff)<<0)
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#define NPU_CHAN_en(x) (((x)&0x1)<<31)
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#define NPU_CHAN_16b(x) (((x)&0x1)<<0)
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#define NPU_PREP0_sub(x) (((x)&0xffff)<<16)
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#define NPU_PREP0_pad(x) (((x)&0xffff)<<0)
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#define NPU_PREP1_pad_r(x) (((x)&0xff)<<24)
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#define NPU_PREP1_pad_l(x) (((x)&0xff)<<16)
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#define NPU_PREP1_pad_b(x) (((x)&0xff)<<8)
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#define NPU_PREP1_pad_t(x) (((x)&0xff)<<0)
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#define NPU_PREP2_shift(x) (((x)&0xf)<<0)
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#define NPU_ENCRYPT_wt(x) (((x)&0x1)<<1)
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#define NPU_ENCRYPT_inst(x) (((x)&0x1)<<0)
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#define NPU_KEY_k(x) (((x)&0xffffffff)<<0)
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#define NPU_INTEN_err_inst(x) (((x)&0x1)<<11)
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#define NPU_INTEN_err_wt(x) (((x)&0x1)<<10)
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#define NPU_INTEN_err_config(x) (((x)&0x1)<<9)
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#define NPU_INTEN_err_ahb(x) (((x)&0x1)<<8)
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#define NPU_INTEN_int(x) (((x)&0xff)<<0)
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#define NPU_INT_err_inst(x) (((x)&0x1)<<11)
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#define NPU_INT_err_wt(x) (((x)&0x1)<<10)
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#define NPU_INT_err_config(x) (((x)&0x1)<<9)
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#define NPU_INT_err_ahb(x) (((x)&0x1)<<8)
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#define NPU_INT_int(x) (((x)&0xff)<<0)
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#define NPU_DBG0_m(x) (((x)&0xff)<<0)
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#define NPU_DBG1_v(x) (((x)&0xffffffff)<<0)
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#define NPU_DBG2_step(x) (((x)&0x1)<<0)
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#define NPU_REGM_c(x) (((x)&0xffffffff)<<0)
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#define NPU_DUMMY_0_b(x) (((x)&0xffffffff)<<0)
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#define NPU_DUMMY_1_b(x) (((x)&0xffffffff)<<0)
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#define NPU_DUMMY_2_b(x) (((x)&0xffffffff)<<0)
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void kdp_init_npu(void);
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void kdp_exit_npu(void);
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void kdp_enable_npu(struct kdp_image_s *image_p, uint32_t key);
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void kdp_enable_npu_cont(void);
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int kdp_read_data_size(void);
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int kdp_get_pixel_size(uint32_t format);
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uint32_t kdp_get_channel_size(uint32_t format);
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void kdp_enable_npu_int(void);
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void kdp_disable_npu_int(void);
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void kdp_enable_npu_preproc(uint32_t cmd_addr, int len);
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int kdp_wait_for_npu_done(int timeout_count);
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int kdp_handle_int(void);
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