106 lines
5.0 KiB
C
106 lines
5.0 KiB
C
/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
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*
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* The information contained herein is property of Kneron, Inc.
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* Terms and conditions of usage are described in detail in Kneron
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* STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information.
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* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
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* from the file.
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*/
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#ifndef _REGBASE_H_
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#define _REGBASE_H_
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#include <stdint.h>
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/* ================================================================================ */
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/* ================ Peripheral memory map ================ */
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/* ================================================================================ */
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// base on Kneron_bus_v013.xlsx
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/* ---------------------------- SAHB Peripheral Device --------------------------------*/
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#define SiRAM_MEM_BASE 0x10100000
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#define SiRAM_MEM_SIZE 0x18000/*new*/
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#define SdRAM_MEM_BASE 0x10200000
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#define SdRAM_MEM_SIZE 0x18000/*new*/
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#define SPIF_XIP_BASE 0x18000000
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#define DDR_MEM_BASE 0x60000000
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#define DDR_MEM_SIZE 0x40000000/*new*/
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#define SPI_FTSPI020_PA_BASE 0xA0000000
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#define DMAC_FTDMAC020_PA_BASE 0xA0100000
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/* ---------------------------- NAHB Peripheral Device --------------------------------*/
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#define NiRAM_MEM_BASE 0x28000000/*new*/
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#define NiRAM_MEM_SIZE 0x10000/*new*/
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#define NdRAM_MEM_BASE 0x0FFF0000/*new*/
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#define NdRAM_MEM_SIZE 0x10000/*new*/
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#define NPU_PA_BASE 0x30000000
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#define DMAC_FTDMAC020_1_PA_BASE 0xB0200000
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/* ---------------------------- PAHB Peripheral Device --------------------------------*/
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#define SDC_FTSDC021_PA_BASE 0xC0000000
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#define USB_FOTG210_PA_BASE 0xC0100000
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/* ---------------------------- APB0 Peripheral Device --------------------------------*/
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/* IIC */
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#define IIC_FTIIC010_0_PA_BASE 0xC1000000
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#define IIC_FTIIC010_1_PA_BASE 0xC1100000
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#define IIC_FTIIC010_2_PA_BASE 0xC1200000
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#define IIC_FTIIC010_3_PA_BASE 0xC1300000
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/* UART */
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#define UART_FTUART010_0_PA_BASE 0xC1400000
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#define UART_FTUART010_1_PA_BASE 0xC1500000
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#define UART_FTUART010_1_1_PA_BASE 0xC1600000
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#define UART_FTUART010_1_2_PA_BASE 0xC1700000
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#define UART_FTUART010_1_3_PA_BASE 0xC1800000
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/* SSP */
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#define I2S_FTSSP010_0_PA_BASE 0xC1900000
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#define I2S_FTSSP010_1_PA_BASE 0xC1A00000
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#define SPI_FTSSP010_0_PA_BASE 0xC1B00000
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#define SPI_FTSSP010_1_PA_BASE 0xC1C00000
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/* GPIO */
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#define GPIO_FTGPIO010_PA_BASE 0xC1D00000
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/* WDT */
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#define WDT_FTWDT010_PA_BASE 0xC1E00000
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/* PWM/TMR */
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#define PWM_FTPWMTMR010_PA_BASE 0xC1F00000
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#define TMR_FTPWMTMR010_0_PA_BASE 0xC2000000
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#define TMR_FTPWMTMR010_1_PA_BASE 0xC2100000
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/* eFuse */
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#define EFUSE_PA_BASE 0xC2200000
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/* SCU */
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#define SCU_FTSCU100_PA_BASE 0xC2300000
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#define SCU_EXTREG_PA_BASE 0xC2380000
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/* ---------------------------- APB1 Peripheral Device --------------------------------*/
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/* ADC */
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#define ADC_FTTSC010_0_PA_BASE 0xC3000000
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/* OTG-PHY */
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#define OTGPHY_FOTG210_0_PA_BASE 0xC3100000
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/* DDRC */
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#define DDRC_FTDDR3030_PA_BASE 0xC3200000
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/* LCDC */
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#define LCD_FTLCDC210_PA_BASE 0xC3300000
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#define SLCD_FTLCDC210_PA_BASE 0xC3400000
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/* MIPI */
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#define CSIRX_FTCSIRX100_PA_BASE 0xC3500000
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#define CSIRX_FTCSIRX100_1_PA_BASE 0xC3600000
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#define MIPIRX_PHY_CSR_PA_BASE 0xC3700000
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#define MIPIRX_PHY_CSR_1_PA_BASE 0xC3800000
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#define DPI2AHB_CSR_PA_BASE 0xC3900000
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#define DPI2AHB_CSR_1_PA_BASE 0xC3A00000
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#define CSITX_CSR_PA_BASE 0xC3B00000
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#define DSITX_CSR_PA_BASE 0xC3C00000
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#define MIPI_TX_PHY_PA_BASE 0xC3D00000
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#define LCD_FRAMEBUFFER_BASE 0x60000000
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#define LCD_FRAMEBUFFER_BASE1 0x60100000
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#define LCD_FRAMEBUFFER_BASE2 0x60200000
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#define LCD_FRAMEBUFFER_BASE3 0x60300000
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/* ---------------------------- APB1 Peripheral Device --------------------------------*/
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#endif //_REGBASE_H_
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