458 lines
13 KiB
C
458 lines
13 KiB
C
/*
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* Kneron IPC Header for KL520
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*
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* Copyright (C) 2018-2019 Kneron, Inc. All rights reserved.
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*
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*/
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#ifndef KNERON_IPC_H
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#define KNERON_IPC_H
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#include <stdint.h>
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#include "model_type.h"
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#include "model_res.h"
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#ifdef USE_64
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typedef uint64_t kdp_size_t;
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#else
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typedef uint32_t kdp_size_t;
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#endif
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#ifndef BOOLEAN_DEFINED
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#ifndef boolean
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typedef char boolean;
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#endif
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#define BOOLEAN_DEFINED
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#endif
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/* IPC memory */
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//----------------------------
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/* N i/d RAM */
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#ifdef TARGET_NCPU
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#define S_D_RAM_ADDR 0x20200000
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#define N_D_RAM_ADDR 0x0FFF0000
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#endif
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#ifdef TARGET_SCPU
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#define S_D_RAM_ADDR 0x10200000
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#define N_D_RAM_ADDR 0x2FFF0000
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#endif
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#define S_D_RAM_SIZE 0x18000 /* 96 KB */
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#define N_D_RAM_SIZE 0x10000 /* 64 KB */
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#define IPC_RAM_SIZE 0x2000 /* 8K Bytes : split 7 : 1 */
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#define IPC_MEM_OFFSET (S_D_RAM_SIZE - IPC_RAM_SIZE)
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#define IPC_MEM_OFFSET2 (S_D_RAM_SIZE - IPC_RAM_SIZE / 8)
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#define IPC_MEM_ADDR (S_D_RAM_ADDR + IPC_MEM_OFFSET)
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#define IPC_MEM_ADDR2 (S_D_RAM_ADDR + IPC_MEM_OFFSET2)
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#define SCPU_IPC_MEM_ADDR IPC_MEM_ADDR
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#define SCPU_IPC_MEM_ADDR2 IPC_MEM_ADDR2
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//----------------------------
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#define SCPU2NCPU_ID ('s'<<24 | 'c'<<16 | 'p'<<8 | 'u')
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#define NCPU2SCPU_ID ('n'<<24 | 'c'<<16 | 'p'<<8 | 'u')
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#define MULTI_MODEL_MAX 16 /* Max active models in memory */
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#define IPC_IMAGE_ACTIVE_MAX 2 /* Max active images for NCPU/NPU */
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#define IPC_IMAGE_MAX 5 /* Max cycled buffer for images */
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#define IPC_MODEL_MAX (MULTI_MODEL_MAX * IPC_IMAGE_ACTIVE_MAX)
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/* Image process cmd_flags set by scpu */
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#define IMAGE_STATE_INACTIVE 0
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#define IMAGE_STATE_ACTIVE 1
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#define IMAGE_STATE_NPU_DONE 2
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#define IMAGE_STATE_DONE 3
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#define IMAGE_STATE_JPEG_ENC_DONE 4
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#define IMAGE_STATE_JPEG_DEC_DONE 5
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#define IMAGE_STATE_ERR_DSP_BUSY 6
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#define IMAGE_STATE_JPEG_ENC_FAIL 7
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#define IMAGE_STATE_JPEG_DEC_FAIL 8
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#define IMAGE_STATE_RECEIVING 9 //need check with mozart firmware
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#define IMAGE_STATE_TOF_DEC_DONE 10
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#define IMAGE_STATE_TOF_DEC_FAIL 11
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/* Image process status set by ncpu */
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#define IMAGE_STATE_IDLE 0
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#define IMAGE_STATE_NPU_BUSY 1
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// #define IMAGE_STATE_NPU_DONE 2
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#define IMAGE_STATE_POST_PROCESSING IMAGE_STATE_NPU_DONE
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#define IMAGE_STATE_POST_PROCESSING_DONE 3
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// #define IMAGE_STATE_DONE IMAGE_STATE_POST_PROCESSING_DONE
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#define IMAGE_STATE_TIMEOUT (7)
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#define IMAGE_STATE_PREPROC_ERROR (-1)
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#define IMAGE_STATE_NPU_ERROR (-2)
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#define IMAGE_STATE_POSTPROC_ERROR (-3)
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/* NPU error code (sync with kp_struct.h) */
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#define IMAGE_STATE_NCPU_ERR_BEGIN 200
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#define IMAGE_STATE_NCPU_INVALID_IMAGE 201
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/* Image format flags */
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#define IMAGE_FORMAT_SUB128 BIT31
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#define IMAGE_FORMAT_ROT_MASK (BIT30 | BIT29)
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#define IMAGE_FORMAT_ROT_SHIFT 29
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#define IMAGE_FORMAT_ROT_CLOCKWISE 0x01
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#define IMAGE_FORMAT_ROT_COUNTER_CLOCKWISE 0x02
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/* raw output format:
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* ([output_num][height_outnode1][channel_outnode1][width_outnode1][radix_outnode1][scale_outnode1][h2][c2][w2][r2][s2][...]
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* [h_n][c_n][w_n][r_n][s_n][fixed_point_datanode1][fixed_point_datanode2][...][fixed_point_datanodeN])
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* 1 byte for each fixed-point data. 4 bytes for each of other data.
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* fixed-point data is converted to float data with formula of fp_value / (scale * (2 ^ radix)).
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*/
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#define IMAGE_FORMAT_RAW_OUTPUT BIT28
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#define IMAGE_FORMAT_PARALLEL_PROC BIT27
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#define IMAGE_FORMAT_MODEL_AGE_GENDER BIT24
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/* right shift for 1-bit if 1 */
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#define IMAGE_FORMAT_RIGHT_SHIFT_ONE_BIT BIT22
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#define IMAGE_FORMAT_SYMMETRIC_PADDING BIT21
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#define IMAGE_FORMAT_PAD_SHIFT 21
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#define IMAGE_FORMAT_CHANGE_ASPECT_RATIO BIT20
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#define IMAGE_FORMAT_BYPASS_PRE BIT19
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#define IMAGE_FORMAT_BYPASS_NPU_OP BIT18
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#define IMAGE_FORMAT_BYPASS_CPU_OP BIT17
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#define IMAGE_FORMAT_BYPASS_POST BIT16
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#define IMAGE_FORMAT_NPU 0x00FF
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#define NPU_FORMAT_RGBA8888 0x00
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#define NPU_FORMAT_NIR 0x20
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/* Support YCBCR (YUV) */
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#define NPU_FORMAT_YCBCR422 0x30
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#define NPU_FORMAT_YCBCR444 0x50
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#define NPU_FORMAT_RGB565 0x60
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/* Determine the exact format with the data byte sequence in DDR memory: [lowest byte]...[highest byte] */
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#define NPU_FORMAT_YCBCR422_CRY1CBY0 0x30
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#define NPU_FORMAT_YCBCR422_CBY1CRY0 0x31
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#define NPU_FORMAT_YCBCR422_Y1CRY0CB 0x32
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#define NPU_FORMAT_YCBCR422_Y1CBY0CR 0x33
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#define NPU_FORMAT_YCBCR422_CRY0CBY1 0x34
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#define NPU_FORMAT_YCBCR422_CBY0CRY1 0x35
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#define NPU_FORMAT_YCBCR422_Y0CRY1CB 0x36
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#define NPU_FORMAT_YCBCR422_Y0CBY1CR 0x37 // Y0CbY1CrY2CbY3Cr...
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#define MAX_INT_FOR_ALIGN 0x10000000
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/* Model structure */
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struct kdp_model_s {
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/* Model type */
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uint32_t model_type; //defined in model_type.h
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/* Model version */
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uint32_t model_version;
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/* Input in memory */
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uint32_t input_mem_addr;
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int32_t input_mem_len;
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/* Output in memory */
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uint32_t output_mem_addr;
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int32_t output_mem_len;
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/* Working buffer */
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uint32_t buf_addr;
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int32_t buf_len;
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/* command.bin in memory */
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uint32_t cmd_mem_addr;
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int32_t cmd_mem_len;
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/* weight.bin in memory */
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uint32_t weight_mem_addr;
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int32_t weight_mem_len;
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/* setup.bin in memory */
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uint32_t setup_mem_addr;
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int32_t setup_mem_len;
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};
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typedef struct kdp_model_s kdp_model_info_t;
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/* Result structure of a model */
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struct result_buf_s {
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int32_t model_id;
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uint32_t result_mem_addr;
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int32_t result_mem_len;
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int32_t result_ret_len;
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};
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#define MAX_PARAMS_LEN 40 /* uint32_t */
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#define MAX_INPUT_NODE_COUNT 5
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/* Parameter structure of a raw image */
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typedef struct parameter_s {
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/* Crop parameters or other purposes */
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int crop_top;
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int crop_bottom;
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int crop_left;
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int crop_right;
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/* Pad parameters or other purposes */
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int pad_top;
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int pad_bottom;
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int pad_left;
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int pad_right;
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float scale_width;
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float scale_height;
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} parameter_t;
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typedef struct kdp_img_info_s {
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/* input image in memory */
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uint32_t image_mem_addr;
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int32_t image_mem_len;
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/* raw image dimensions */
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uint32_t input_row;
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uint32_t input_col;
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uint32_t input_channel;
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/* Raw image format and pre-process flags
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* bit-31: = 1 : subtract 128
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* bit 30:29 00: no rotation; 01: rotate clockwise; 10: rotate counter clockwise; 11: reserved
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* bit 7:0: format
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*/
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uint32_t format;
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/* Parameter structure */
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struct parameter_s params_s;
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} kdp_img_info_t;
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struct kdp_img_cfg {
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uint32_t num_image;
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kdp_img_info_t image_list[MAX_INPUT_NODE_COUNT];
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uint32_t inf_format;
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uint32_t image_buf_active_index; // scpu_to_ncpu->active_img_index
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};
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struct kdp_crop_box_s {
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int32_t top;
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int32_t bottom;
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int32_t left;
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int32_t right;
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};
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struct kdp_pad_value_s {
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int32_t pad_top;
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int32_t pad_bottom;
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int32_t pad_left;
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int32_t pad_right;
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};
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/* Raw image structure */
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typedef struct kdp_img_raw_s {
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/* Image state: 1 = active, 0 = inactive */
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int state;
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/* Image sequence number */
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int seq_num;
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/* Image ref index */
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int ref_idx;
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/* List of raw images */
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uint32_t num_image;
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kdp_img_info_t image_list[MAX_INPUT_NODE_COUNT];
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/* Parallel and raw output flags
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* refer to dsp_img_fmt_t
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*/
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uint32_t inf_format;
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/* Shared parameters for raw image */
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uint32_t ext_params[MAX_PARAMS_LEN];
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struct result_buf_s results[MULTI_MODEL_MAX];
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/* Test: SCPU total */
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uint32_t tick_start;
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uint32_t tick_end;
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/* Test: NCPU processes */
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uint32_t tick_start_pre;
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uint32_t tick_end_pre;
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uint32_t tick_start_npu;
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uint32_t tick_end_npu;
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uint32_t tick_start_post;
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uint32_t tick_end_post;
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} kdp_img_raw_t;
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/* Image result structure */
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typedef struct kdp_img_result_s {
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/* Processing status: 2 = done, 1 = running, 0 = unused */
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int status;
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/* Image sequence number */
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int seq_num;
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/* result memory addr */
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//dummy information
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uint32_t result_mem_addr;
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} kdp_img_result_t;
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/* Structure of nCPU->sCPU IPC Message data */
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typedef struct ncpu_to_scpu_req_img_s {
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int32_t bHandledByScpu;
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int32_t ipc_type; //ncpu_scpu_ipc_msg_type_t
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int32_t sts; //ncpu_status_t
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} ncpu_to_scpu_req_img_t;
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/* in every IPC interrupt triggered by NCPU, SCPU check in_comm_p to see the data type */
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typedef enum {
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NCPU_REQUEST_NEW_IMG = 1,
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NCPU_EXEC_RESULT,
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MSG_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} ncpu_scpu_ipc_msg_type_t;
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/* overall SCPU/DSP status*/
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typedef enum {
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NCPU_STS_ERROR = -1,
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NCPU_STS_READY = 0, //DSP is ready to run new task
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NCPU_STS_BUSY, // one of CNN/JPEG ENC/JPEG DEC is running, cannot accept new task now
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NCPU_STS_INVALID_PARAM, // invalid IPC parameters
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STS_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} ncpu_status_t;
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typedef struct
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{
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int model_id;
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uint32_t tick_before_preprocess;
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uint32_t sum_ticks_preprocess;
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uint32_t tick_before_inference;
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uint32_t sum_ticks_inference;
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uint32_t tick_before_postprocess;
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uint32_t sum_ticks_postprocess;
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uint32_t tick_before_cpu_op;
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uint32_t sum_ticks_cpu_op;
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uint32_t sum_cpu_op_count;
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uint32_t sum_frame_count;
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} kp_model_profile_t;
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/* Structure of sCPU->nCPU Message */
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typedef struct scpu_to_ncpu_s {
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uint32_t id; /* = 'scpu' */
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volatile uint32_t bNcpuReceived;
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uint32_t cmd; // Run / Stop
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/*
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* debug control flags (dbg.h):
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* bits 19-16: scpu debug level
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* bits 03-00: ncpu debug level
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*/
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uint32_t debug_flags;
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uint32_t kp_dbg_checkpoinots;
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int32_t active_img_index_rgb_liveness;
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/* Active models in memory and running */
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int32_t num_models; //usually, num_models=1 (only one active model)
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struct kdp_model_s models[IPC_MODEL_MAX]; //to save active modelInfo
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int32_t models_type[IPC_MODEL_MAX]; //to save model type
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int32_t model_slot_index;
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/* Raw image information */
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struct kdp_img_raw_s raw_images[IPC_IMAGE_MAX];
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kdp_img_raw_t *pRawimg; //SCPU need to alloc for every image
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uint32_t active_img_index;
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uint32_t ncpu_img_req_msg_addr; // ncpu_to_scpu_req_img_t *, SCPU always get result from here
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/* Input/Output working buffers for NPU */
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uint32_t input_mem_addr2;
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int32_t input_mem_len2;
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/* Memory for parallel processing */
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uint32_t output_mem_addr2;
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int32_t output_mem_len2;
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/* Memory for pre processing command */
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uint32_t inproc_mem_addr;
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/* Memory for post processing parameters */
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uint32_t output_mem_addr3;
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uint32_t output_mem_addr4;
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void * kp_dbg_buffer;
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uint32_t kp_dbg_enable_profile; // 1: enable, 0: disable
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kp_model_profile_t kp_model_profile_records[MULTI_MODEL_MAX];
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} scpu_to_ncpu_t;
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typedef enum {
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NCPU_NONE_RESULT = -1,
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NCPU_POSTPROC_RESULT = 1,
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NCPU_JPEG_ENC_RESULT,
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NCPU_JPEG_DEC_RESULT,
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NCPU_CROP_RESIZE_RESULT,
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NCPU_TOF_DEC_RESULT,
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NCPU_RESULT_TYPE_MAX,
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RES_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} NCPU_TO_SCPU_RESULT_TYPE;
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/* Structure of nCPU->sCPU IPC Message data */
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typedef struct ncpu_to_scpu_postproc_result_s {
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int32_t model_slot_index; // RUN which model for this image
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kdp_img_result_t img_result;
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uint32_t OrigRawImgAddr;
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} ncpu_to_scpu_postproc_result_t;
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/* Structure of nCPU->sCPU Message */
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typedef struct ncpu_to_scpu_s {
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uint32_t id; /* = 'ncpu' */
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int32_t bHandledByScpu;
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ncpu_scpu_ipc_msg_type_t ipc_type __attribute__((aligned (4))); //ncpu_scpu_ipc_msg_type_t
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ncpu_status_t sts __attribute__((aligned (4))); //overall NCPU/DSP status
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NCPU_TO_SCPU_RESULT_TYPE out_type __attribute__((aligned (4)));
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union {
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ncpu_to_scpu_postproc_result_t postproc;
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} result;
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/* Images result info corresponding to raw_images[] */
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struct kdp_img_result_s img_results[IPC_IMAGE_MAX];
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ncpu_to_scpu_req_img_t req_img;
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volatile int32_t kp_dbg_status;
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} ncpu_to_scpu_result_t;
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/* scpu_to_ncpu: cmd */
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typedef enum {
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CMD_INVALID,
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CMD_INIT,
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CMD_RUN_NPU,
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CMD_SLEEP_NPU,
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CMD_JPEG_ENCODE,
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CMD_JPEG_DECODE,
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CMD_CROP_RESIZE,
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CMD_TOF_DECODE,
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CMD_SCPU_NCPU_TOTAL,
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CMD_ALIGN_32 = MAX_INT_FOR_ALIGN,
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} scpu_ncpu_cmd_t;
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struct nir_camera_tune_s {
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uint32_t init_tile;
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uint32_t led_flag;
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uint32_t nir_mode;
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float init_nir_gain;
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float nir_gain;
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uint32_t nir_cur_exp_time;
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uint32_t calibration_count;
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float registered_offsetX;
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float registered_offsetY;
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};
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struct lv_params_s {
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uint32_t dual_landmarks[DUAL_LAND_MARK_POINTS * 2];
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struct nir_camera_tune_s nir_tune;
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};
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#endif
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