165 lines
11 KiB
C
165 lines
11 KiB
C
/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved.
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*
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* The information contained herein is property of Kneron, Inc.
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* Terms and conditions of usage are described in detail in Kneron
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* STANDARD SOFTWARE LICENSE AGREEMENT.
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*
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* Licensees are granted free, non-transferable use of the information.
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* NO WARRANTY of ANY KIND is provided. This heading must NOT be removed
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* from the file.
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*/
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/******************************************************************************
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* Filename:
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* ---------
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* project.h
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*
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* Description:
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* ------------
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*
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*
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******************************************************************************/
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#ifndef _PROJECT_H_
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#define _PROJECT_H_
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/*=============================================================================
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asic setting
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=============================================================================*/
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#include "membase.h"
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/*=============================================================================
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board setting
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=============================================================================*/
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#include "board.h"
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#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR
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#define FLASH_SIZE FLASH_SIZE_256MBIT
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#define FLASH_COMM FLASH_COMM_SPEED_25MHZ
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#define FLASH_DRV FLASH_DRV_NORMAL_MODE
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/*=============================================================================
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COMM setting
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=============================================================================*/
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#define UART_NUM 1
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#define MSG_PORT COMM_PORT_ID_0
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#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200
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/*=============================================================================
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Pinmux setting
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=============================================================================*/
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#define PIN_NUM 38
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#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090
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#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
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#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
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#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
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#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
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#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040
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#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081
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#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089
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#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
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#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
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#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
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#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008
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#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
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#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000
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#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080
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#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\
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KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\
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KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\
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KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\
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KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\
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KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\
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KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\
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KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG};
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/*=============================================================================
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fw setting
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=============================================================================*/
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#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/
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/*=============================================================================
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DDR configuration
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=============================================================================*/
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/* DDR table */
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#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/
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#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */
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/** Reserve for all_models.bin */
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//#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */
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//#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */
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/** Resseve for DDR heap. Allocation direction from END to BEGIN */
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//#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */
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//#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */
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/** Reserve for system information, 188KB */
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//#define DDR_SYSTEM_RESERVE_BEGIN 0x63FD0000 /**< space head for system info */
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//#define DDR_SYSTEM_RESERVE_END 0x63FFEFFF /**< space end for system info */
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/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/
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//#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */
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//#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */
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//#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END
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//#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE )
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/*=============================================================================
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Flash configuration
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=============================================================================*/
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/* Flash table */
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//#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */
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//#define FLASH_FW_NCPU0_ADDR 0x00016000 /**< fw_ncpu.bin */
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//#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */
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//#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */
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//#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */
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//#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */
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//#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */
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//#define FLASH_MDDEL_ALL_ADDR 0x00560000 /**< all_models.bin */
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//#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */
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//#define FLASH_MINI_BLOCK_SIZE (4 * 1024)
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/*=============================================================================
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mdw setting
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=============================================================================*/
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/* scpu/ncpu image size */
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#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000)
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#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE
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/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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-->critical setting<--
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Below setting is for RD tuning or testing.
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**Don't touch anything if you don't know what you are doing**
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!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
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#endif //_PROJECT_H_
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