From 042e609cc9caa21d68dedc8b3e2707420a9a32e6 Mon Sep 17 00:00:00 2001 From: Dereck Hao Date: Wed, 17 Dec 2025 17:14:20 +0800 Subject: [PATCH] =?UTF-8?q?Feat:=20=E6=96=B0=E5=A2=9E=20KL520=20IP=20?= =?UTF-8?q?=E8=87=AA=E5=8B=95=E9=A9=97=E8=AD=89=E6=B8=AC=E8=A9=A6=E5=A5=97?= =?UTF-8?q?=E4=BB=B6?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - 實作 GPIO, SPI, I2C, PWM-ADC 功能驗證模組 - 新增互動式 Console 選單 (ip_test_all) 與 README 接線說明 --- .../solution_kdp2_evb_verify/main_ncpu/main.c | 33 + .../main_ncpu/model_ftr_table.c | 58 + .../main_ncpu/user_post_process.c | 466 +++++++ .../main_ncpu/user_pre_process.c | 52 + .../main_scpu/application_init.c | 94 ++ .../main_scpu/device_init.c | 25 + .../main_scpu/driver_init.c | 28 + .../main_scpu/hw_test_i2c.c | 140 ++ .../main_scpu/hw_test_pwm_adc.c | 127 ++ .../main_scpu/hw_test_spi.c | 141 ++ .../main_scpu/include/application_init.h | 31 + .../main_scpu/include/device_init.h | 29 + .../main_scpu/include/driver_init.h | 29 + .../main_scpu/include/ip_test_all.h | 6 + .../main_scpu/include/middleware_init.h | 29 + .../main_scpu/include/system_init.h | 28 + .../main_scpu/include/task_handler.h | 86 ++ .../main_scpu/ip_test_all.c | 113 ++ .../main_scpu/ip_test_gpio.c | 125 ++ .../solution_kdp2_evb_verify/main_scpu/main.c | 57 + .../main_scpu/middleware_init.c | 31 + .../main_scpu/system_init.c | 23 + .../sn52096/ncpu_keil/ncpu.sct | 19 + .../sn52096/ncpu_keil/ncpu.uvoptx | 576 ++++++++ .../sn52096/ncpu_keil/ncpu.uvprojx | 557 ++++++++ .../sn52096/ncpu_keil/post_build.bat | 10 + .../sn52096/proj.uvmpw | 20 + .../sn52096/project.h | 163 +++ .../sn52096/scpu_keil/kdp2_scpu_jlink.ini | 13 + .../sn52096/scpu_keil/post_build.bat | 12 + .../sn52096/scpu_keil/pre_build.bat | 1 + .../sn52096/scpu_keil/scpu.uvoptx | 1197 +++++++++++++++++ .../sn52096/scpu_keil/scpu.uvprojx | 898 +++++++++++++ utils/JLink_programmer/bin/fw_ncpu.bin | Bin 39908 -> 39868 bytes utils/JLink_programmer/bin/fw_scpu.bin | Bin 52568 -> 61860 bytes utils/bin_gen/flash_bin/fw_ncpu.bin | Bin 39908 -> 39868 bytes utils/bin_gen/flash_bin/fw_scpu.bin | Bin 52568 -> 61860 bytes 37 files changed, 5217 insertions(+) create mode 100644 build/solution_kdp2_evb_verify/main_ncpu/main.c create mode 100644 build/solution_kdp2_evb_verify/main_ncpu/model_ftr_table.c create mode 100644 build/solution_kdp2_evb_verify/main_ncpu/user_post_process.c create mode 100644 build/solution_kdp2_evb_verify/main_ncpu/user_pre_process.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/application_init.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/device_init.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/driver_init.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/hw_test_i2c.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/hw_test_pwm_adc.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/hw_test_spi.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/include/application_init.h create mode 100644 build/solution_kdp2_evb_verify/main_scpu/include/device_init.h create mode 100644 build/solution_kdp2_evb_verify/main_scpu/include/driver_init.h create mode 100644 build/solution_kdp2_evb_verify/main_scpu/include/ip_test_all.h create mode 100644 build/solution_kdp2_evb_verify/main_scpu/include/middleware_init.h create mode 100644 build/solution_kdp2_evb_verify/main_scpu/include/system_init.h create mode 100644 build/solution_kdp2_evb_verify/main_scpu/include/task_handler.h create mode 100644 build/solution_kdp2_evb_verify/main_scpu/ip_test_all.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/ip_test_gpio.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/main.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/middleware_init.c create mode 100644 build/solution_kdp2_evb_verify/main_scpu/system_init.c create mode 100644 build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.sct create mode 100644 build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.uvoptx create mode 100644 build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.uvprojx create mode 100644 build/solution_kdp2_evb_verify/sn52096/ncpu_keil/post_build.bat create mode 100644 build/solution_kdp2_evb_verify/sn52096/proj.uvmpw create mode 100644 build/solution_kdp2_evb_verify/sn52096/project.h create mode 100644 build/solution_kdp2_evb_verify/sn52096/scpu_keil/kdp2_scpu_jlink.ini create mode 100644 build/solution_kdp2_evb_verify/sn52096/scpu_keil/post_build.bat create mode 100644 build/solution_kdp2_evb_verify/sn52096/scpu_keil/pre_build.bat create mode 100644 build/solution_kdp2_evb_verify/sn52096/scpu_keil/scpu.uvoptx create mode 100644 build/solution_kdp2_evb_verify/sn52096/scpu_keil/scpu.uvprojx diff --git a/build/solution_kdp2_evb_verify/main_ncpu/main.c b/build/solution_kdp2_evb_verify/main_ncpu/main.c new file mode 100644 index 0000000..fb0021a --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_ncpu/main.c @@ -0,0 +1,33 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2019 Kneron Inc. All rights reserved. + * + * Name: main.c + * Purpose: Kneron NCPU + * + *---------------------------------------------------------------------------*/ + + +#include "cmsis_os2.h" +#include "kdpio.h" + +extern void SystemCoreClockUpdate(void); + +/*---------------------------------------------------------------------------- + * Main: Initialize OS Kernel and NCPU SDK + *---------------------------------------------------------------------------*/ +int main(void) +{ + SystemCoreClockUpdate(); + osKernelInitialize(); + + /* init NCPU */ + kdpio_sdk_init(); + + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + ; +} diff --git a/build/solution_kdp2_evb_verify/main_ncpu/model_ftr_table.c b/build/solution_kdp2_evb_verify/main_ncpu/model_ftr_table.c new file mode 100644 index 0000000..18a3d31 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_ncpu/model_ftr_table.c @@ -0,0 +1,58 @@ +/* -------------------------------------------------------------------------- + * Copyright (c) 2018-2020 Kneron Inc. All rights reserved. + * + * Name: ncpu_extend_ftr.c + * Purpose: Extend new features implementation + * + *---------------------------------------------------------------------------*/ + +#include "kdpio.h" +#include "model_type.h" +#include "model_ppp.h" + +extern int user_pre_yolo(struct kdp_image_s *image_p); +extern int user_post_yolo(struct kdp_image_s *image_p); + +/********************************************************************************* + Registered model pre-process features list + +only need to register functions for models that default builtin pre-proc can't support +*********************************************************************************/ +model_pre_post_func_t model_pre_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < pre-process function > */ + /* -------------------------------------------------------------------------- */ + 0 // no pre-process function is specified + + /* Put customized pre-process functions below: */ + //demo only + //{ TINY_YOLO_V3_224_224_3, user_pre_yolo }, + + /* + { CUSTOMER_MODEL_1, preproc_customer_model_1 }, + { CUSTOMER_MODEL_2, preproc_customer_model_2 }, + { CUSTOMER_MODEL_3, preproc_customer_model_3 }, + */ +}; + +/********************************************************************************* + Registered model post-process features list +*********************************************************************************/ +model_pre_post_func_t model_post_proc_fns[MAX_MODEL_REGISTRATIONS] = { + /* < model type ID > < post-process function > */ + /* -------------------------------------------------------------------------- */ + + /* user post-process function example*/ + { TINY_YOLO_V3_224_224_3, user_post_yolo }, + + /* use builtin post-process function example*/ + //for face_detection and landmark here using Kneron app functions + { KNERON_FD_MASK_MBSSD_200_200_3, post_ssd_face_detection }, + { KNERON_LM_5PTS_ONET_56_56_3, post_face_landmark_onet_5p }, + + + /* Put customized post-process functions below:*/ + //{ CUSTOMER_MODEL_1, post_customer_model_1 }, + //{ CUSTOMER_MODEL_2, post_customer_model_2 }, + //{ CUSTOMER_MODEL_3, post_customer_model_3 }, +}; + diff --git a/build/solution_kdp2_evb_verify/main_ncpu/user_post_process.c b/build/solution_kdp2_evb_verify/main_ncpu/user_post_process.c new file mode 100644 index 0000000..6af9bb0 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_ncpu/user_post_process.c @@ -0,0 +1,466 @@ +/* + * Kneron Example Post-Processing driver + * + * Copyright (C) 2018-2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include "base.h" +#include "model_res.h" +#include "post_processing.h" + +#define YOLO_CLASS_MAX 80 /* max result box number per class */ +#define YOLO_GOOD_BOX_MAX 80 /* max result box number for one time inference */ +#define YOLO_BOX_FIX_CH 5 /* x, y, w, h, confidence score */ + +#define YOLO_V3_GRID_W 14 /* max output feature map width */ +#define YOLO_V3_GRID_H 14 /* max output feature map higheit */ +#define YOLO_V3_GRID_MAX (YOLO_V3_GRID_W * YOLO_V3_GRID_H) /* max predict box number per channel */ +#define YOLO_V3_CELL_BOX_NUM 3 /* number of anchors on each output node */ +#define YOLO_V3_MAX_BOX_NUM MIN(500, YOLO_V3_GRID_MAX * YOLO_V3_CELL_BOX_NUM) + +#define KDP_COL_MIN 16 /* hardware 16 bytes alignment, i.e. 128 bits */ + +/* YOLO default parameters */ +const float ex_unpass_score = -999.0; // used as box filter + +const float ex_anchors_v0[3][2] = {{116 ,90}, {156, 198}, {373, 326}}; +const float ex_anchors_v1[3][2] = {{30, 61}, {62, 45}, {59, 119}}; +const float ex_anchors_v2[3][2] = {{10, 13}, {16, 30}, {33, 23}}; + +/* Output node layout */ +struct ex_output_node { + int8_t *base_ptr; + uint32_t ch; + uint32_t row; + uint32_t col; + uint32_t col_len; + uint32_t radix; + uint32_t scale; +}; + +/* Shared global variable area among models */ +struct ex_yolo_v3_post_globals_s { + float box_class_probs[YOLO_CLASS_MAX]; + struct bounding_box_s bboxes_v3[YOLO_V3_GRID_MAX * YOLO_V3_CELL_BOX_NUM]; + struct bounding_box_s result_tmp_s[YOLO_V3_MAX_BOX_NUM]; +}; + +/* Model globals */ +static struct ex_yolo_v3_post_globals_s *ex_yolov3_gp; + +void *get_gp(void **gp, size_t len); + +static inline struct ex_yolo_v3_post_globals_s *get_yolov3_gp(void) { + return (struct ex_yolo_v3_post_globals_s *)get_gp((void **)&ex_yolov3_gp, sizeof(struct ex_yolo_v3_post_globals_s)); +} + +/* Post-Processing utils functions */ +float ex_do_div_scale_optim(float v, float scale) { + return (v * scale); +} + +uint32_t ex_round_up(uint32_t num) { + return ((num + (KDP_COL_MIN - 1)) & ~(KDP_COL_MIN - 1)); +} + +float ex_sigmoid(float x) { + float exp_value; + float return_value; + + exp_value = expf(-x); + + return_value = 1 / (1 + exp_value); + + return return_value; +} + +int ex_float_comparator(float a, float b) { + float diff = a - b; + + if (diff < 0) + return 1; + else if (diff > 0) + return -1; + return 0; +} + +int ex_box_score_comparator(const void *pa, const void *pb) { + float a, b; + + a = ((struct bounding_box_s *) pa)->score; + b = ((struct bounding_box_s *) pb)->score; + + return ex_float_comparator(a, b); +} + +float ex_overlap(float l1, float r1, float l2, float r2) { + float left = l1 > l2 ? l1 : l2; + float right = r1 < r2 ? r1 : r2; + return right - left; +} + +float ex_box_intersection(struct bounding_box_s *a, struct bounding_box_s *b) { + float w, h, area; + + w = ex_overlap(a->x1, a->x2, b->x1, b->x2); + h = ex_overlap(a->y1, a->y2, b->y1, b->y2); + + if (w < 0 || h < 0) + return 0; + + area = w * h; + return area; +} + +float ex_box_union(struct bounding_box_s *a, struct bounding_box_s *b) { + float i, u; + + i = ex_box_intersection(a, b); + u = (a->y2 - a->y1) * (a->x2 - a->x1) + (b->y2 - b->y1) * (b->x2 - b->x1) - i; + + return u; +} + +float ex_box_iou(struct bounding_box_s *a, struct bounding_box_s *b) { + /* origin iou */ + + float c; + float intersection_a_b = ex_box_intersection(a, b); + float union_a_b = ex_box_union(a, b); + + c = intersection_a_b / union_a_b; + + return c; +} + +/* Get the output node information */ +void ex_get_output_node(struct ex_output_node *out_node, struct kdp_image_s *image_p, int node_num) { + struct out_node_s *out_p; + out_p = (struct out_node_s *)((kdp_size_t)POSTPROC_OUT_NODE(image_p) + node_num * sizeof(struct out_node_s)); + + out_node->base_ptr = (int8_t *)OUT_NODE_ADDR(out_p); + out_node->ch = OUT_NODE_CH(out_p); + out_node->row = OUT_NODE_ROW(out_p); + out_node->col = OUT_NODE_COL(out_p); + out_node->col_len = ex_round_up(out_node->col); + out_node->radix = OUT_NODE_RADIX(out_p); + out_node->scale = OUT_NODE_SCALE(out_p); +} + +/* Get the index corresponding to given channel, row, and column indices */ +uint32_t ex_get_index(struct ex_output_node node, uint32_t ch_idx, uint32_t row_idx, uint32_t col_idx) { + uint32_t index = row_idx * node.ch * node.col_len + ch_idx * node.col_len + col_idx; + return index; +} + +/* Get the data pointer corresponding to given channel, row, and column indices */ +int8_t *ex_get_data(struct ex_output_node node, uint32_t ch_idx, uint32_t row_idx, uint32_t col_idx) { + uint32_t index = ex_get_index(node, ch_idx, row_idx, col_idx); + return node.base_ptr + index; +} + +/* Performs NMS on the potential boxes */ +static int ex_nms_bbox_for_post_yolov3_no_sigmoid(struct bounding_box_s *potential_boxes, + struct bounding_box_s *temp_results, + int class_num, + int good_box_count, + int max_boxes, + int single_class_max_boxes, + struct bounding_box_s *results, + float score_thresh, + float iou_thresh) { + int good_result_count = 0; + + // check overlap between only boxes from same class + for (int i = 0; i < class_num; i++) { + int class_good_result_count = 0; + if (good_result_count == max_boxes) // break out of outer loop as well for future classes + break; + + int class_good_box_count = 0; + + // find all boxes of a specific class + for (int j = 0; j < good_box_count; j++) { + if (potential_boxes[j].class_num == i) { + memcpy(&temp_results[class_good_box_count], &potential_boxes[j], sizeof(struct bounding_box_s)); + class_good_box_count++; + } + } + + if (class_good_box_count == 1) { + memcpy(&results[good_result_count], temp_results, sizeof(struct bounding_box_s)); + good_result_count++; + } else if (class_good_box_count >= 2) { + // sort boxes based on the score + qsort(temp_results, class_good_box_count, sizeof(struct bounding_box_s), ex_box_score_comparator); + for (int j = 0; j < class_good_box_count; j++) { + // if the box score is too low or is already filtered by previous box + if (temp_results[j].score < score_thresh) + continue; + + // filter out overlapping, lower score boxes + for (int k = j + 1; k < class_good_box_count; k++) + if (ex_box_iou(&temp_results[j], &temp_results[k]) > iou_thresh) + temp_results[k].score = ex_unpass_score; + + // keep boxes with highest scores, up to a certain amount + if ((good_result_count == max_boxes) || (class_good_result_count == single_class_max_boxes)) + break; + memcpy(&results[good_result_count], &temp_results[j], sizeof(struct bounding_box_s)); + good_result_count++; + class_good_result_count++; + } + } + } + + return good_result_count; +} + +/** + * Update candidate bbox list, reserve top max_candidate_num candidate bbox. + */ +static int ex_update_candidate_bbox_list(struct bounding_box_s *new_candidate_bbox, + int max_candidate_num, + struct bounding_box_s *candidate_bbox_list, + int *candidate_bbox_num, + int *max_candidate_idx, + int *min_candidate_idx) { + + if ((NULL == new_candidate_bbox) || (NULL == candidate_bbox_list)) + return -1; + + int update_idx = -1; + + if (0 == *candidate_bbox_num) { + /** add 1-th bbox */ + *max_candidate_idx = 0; + *min_candidate_idx = 0; + update_idx = 0; + (*candidate_bbox_num)++; + memcpy(&candidate_bbox_list[update_idx], new_candidate_bbox, sizeof(struct bounding_box_s)); + } else { + if (max_candidate_num > *candidate_bbox_num) { + /** directly add bbox when the candidate bbox list is not filled */ + update_idx = *candidate_bbox_num; + + if (new_candidate_bbox->score > candidate_bbox_list[*max_candidate_idx].score) + *max_candidate_idx = update_idx; + else if (new_candidate_bbox->score < candidate_bbox_list[*min_candidate_idx].score) + *min_candidate_idx = update_idx; + + (*candidate_bbox_num)++; + + if (0 <= update_idx) + memcpy(&candidate_bbox_list[update_idx], new_candidate_bbox, sizeof(struct bounding_box_s)); + } else { + /** update candidate bbox list when candidate bbox list is filled */ + if (new_candidate_bbox->score >= candidate_bbox_list[*max_candidate_idx].score) { + /** update the largest score candidate index */ + update_idx = *min_candidate_idx; + *max_candidate_idx = *min_candidate_idx; + } else if (new_candidate_bbox->score > candidate_bbox_list[*min_candidate_idx].score) { + update_idx = *min_candidate_idx; + } + + if (0 <= update_idx) { + memcpy(&candidate_bbox_list[update_idx], new_candidate_bbox, sizeof(struct bounding_box_s)); + + for (int i = 0; i < *candidate_bbox_num; i++) { + /** update the smallest score candidate index */ + if (candidate_bbox_list[i].score < candidate_bbox_list[*min_candidate_idx].score) + *min_candidate_idx = i; + } + } + } + } + + return 0; +} + +/* Remap one bounding box to original image coordinates */ +void ex_remap_bbox(struct kdp_image_s *image_p, struct bounding_box_s *box, int need_scale) { + // original box values are percentages, scale to model sizes + if (need_scale) { + box->x1 *= DIM_INPUT_COL(image_p); + box->y1 *= DIM_INPUT_ROW(image_p); + box->x2 *= DIM_INPUT_COL(image_p); + box->y2 *= DIM_INPUT_ROW(image_p); + } + + // scale from model sizes to original input sizes + box->x1 = (box->x1 - RAW_PAD_LEFT(image_p)) * RAW_SCALE_WIDTH(image_p) + RAW_CROP_LEFT(image_p); + box->y1 = (box->y1 - RAW_PAD_TOP(image_p)) * RAW_SCALE_HEIGHT(image_p) + RAW_CROP_TOP(image_p); + box->x2 = (box->x2 - RAW_PAD_LEFT(image_p)) * RAW_SCALE_WIDTH(image_p) + RAW_CROP_LEFT(image_p); + box->y2 = (box->y2 - RAW_PAD_TOP(image_p)) * RAW_SCALE_HEIGHT(image_p) + RAW_CROP_TOP(image_p); + + // clip to boundaries of image + box->x1 = (int)((box->x1 < 0 ? 0 : box->x1) + (float)0.5); + box->y1 = (int)((box->y1 < 0 ? 0 : box->y1) + (float)0.5); + box->x2 = (int)((box->x2 > RAW_INPUT_COL(image_p) ? RAW_INPUT_COL(image_p) : box->x2) + (float)0.5); + box->y2 = (int)((box->y2 > RAW_INPUT_ROW(image_p) ? RAW_INPUT_ROW(image_p) : box->y2) + (float)0.5); +} + +/* YOLO parameters */ +static float iou_threshold = 0.45; +static float score_threshold = 0.6; +static uint32_t max_detection_box_num = YOLO_V3_MAX_BOX_NUM; +static uint32_t anchors[3][3][2] = {{{0}}}; + +/* User YOLO post processing */ +int user_post_yolo(struct kdp_image_s *image_p) +{ + /************************* Input parameters ******************************/ + host_od_post_params_t *pHostParam = (host_od_post_params_t *)POSTPROC_PARAMS_P(image_p); + + if (pHostParam->prob_thresh > 0) + score_threshold = pHostParam->prob_thresh; + + if (pHostParam->nms_thresh > 0) + iou_threshold = pHostParam->nms_thresh; + + if (pHostParam->max_detection_per_class > 0) + { + max_detection_box_num = pHostParam->max_detection_per_class; + if (max_detection_box_num > YOLO_V3_MAX_BOX_NUM) + max_detection_box_num = YOLO_V3_MAX_BOX_NUM; + } + + // use passed anchor table + uint32_t *p_anchors = (uint32_t *)pHostParam->data; + if (pHostParam->anchor_row * pHostParam->anchor_col > 0 && pHostParam->anchor_row <= 3 && pHostParam->anchor_col <= 6) + { + for (int i = 0; i < pHostParam->anchor_row; i++) + { + for (int j = 0; j < (pHostParam->anchor_col / 2); j++) + { + anchors[i][j][0] = *p_anchors++; + anchors[i][j][1] = *p_anchors++; + } + } + } + else + { + memcpy(anchors[0], ex_anchors_v0, sizeof(float) * 6); + memcpy(anchors[1], ex_anchors_v1, sizeof(float) * 6); + memcpy(anchors[2], ex_anchors_v2, sizeof(float) * 6); + } + + /*************************************************************************/ + + // get result buffer + struct yolo_result_s *result = (struct yolo_result_s *)(POSTPROC_RESULT_MEM_ADDR(image_p)); + struct ex_yolo_v3_post_globals_s *gp = get_yolov3_gp(); + struct bounding_box_s *bbox = gp->bboxes_v3; + struct ex_output_node node_yolo; + int good_box_count = 0; + int max_candidate_idx = 0; + int min_candidate_idx = 0; + + ex_get_output_node(&node_yolo, image_p, 0); + int class_num = node_yolo.ch / YOLO_V3_CELL_BOX_NUM - YOLO_BOX_FIX_CH; + result->class_count = class_num; + + for (int idx = 0; idx < POSTPROC_OUTPUT_NUM(image_p); idx++) { + // get output node parameters + ex_get_output_node(&node_yolo, image_p, idx); + + // get radix and scale for floating conversion + float div = pow(2, node_yolo.radix); + float scale = *(float *)&node_yolo.scale; + + // convert threshold to fp for fast comparison + int prob_thresh_yolov3_fp = floor(-log(1.f / score_threshold - 1.f) * div * scale); + scale = 1.0f / (div * scale); + + for (int ch = 0; ch < YOLO_V3_CELL_BOX_NUM; ch++) { + for (int row = 0; row < node_yolo.row; row++) { + for (int col = 0; col < node_yolo.col; col++) { + // check if the score (4th channel) better than threshold + int8_t box_confidence_fp = *ex_get_data(node_yolo, ch * (class_num + 5) + 4, row, col); + + // filter out small box score + if (box_confidence_fp <= prob_thresh_yolov3_fp) + continue; + + // find maximum score among all classes + // get the predicted class and score in fixed + int max_score_class = 0; + int8_t max_score_int = *ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 5, row, col); + for (int i = 1; i < class_num; i++) { + int8_t cur_score = *ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 5 + i, row, col); + if (cur_score > max_score_int) { + max_score_int = cur_score; + max_score_class = i; + } + } + + // filter out small class number + if (max_score_int <= prob_thresh_yolov3_fp) + continue; + + // get the confidence score in floating + float box_confidence = ex_sigmoid(ex_do_div_scale_optim(box_confidence_fp, scale)); + float max_score = ex_sigmoid(ex_do_div_scale_optim(max_score_int, scale)); + float score = max_score * box_confidence; + + // check if score is larger than threshold we set in floating + if (score > score_threshold) { + if ((YOLO_V3_MAX_BOX_NUM == good_box_count) && (score <= bbox[min_candidate_idx].score)) + continue; + float box_x = (float)*ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH), row, col); + float box_y = (float)*ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 1, row, col); + float box_w = (float)*ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 2, row, col); + float box_h = (float)*ex_get_data(node_yolo, ch * (class_num + YOLO_BOX_FIX_CH) + 3, row, col); + + box_x = ex_do_div_scale_optim(box_x, scale); + box_y = ex_do_div_scale_optim(box_y, scale); + box_w = ex_do_div_scale_optim(box_w, scale); + box_h = ex_do_div_scale_optim(box_h, scale); + + box_x = (ex_sigmoid(box_x) + col) * (DIM_INPUT_COL(image_p) / node_yolo.col); + box_y = (ex_sigmoid(box_y) + row) * (DIM_INPUT_ROW(image_p) / node_yolo.row); + box_w = expf(box_w) * anchors[idx][ch][0]; + box_h = expf(box_h) * anchors[idx][ch][1]; + + struct bounding_box_s new_candidate_bbox = {0}; + new_candidate_bbox.x1 = (box_x - (box_w / 2)); + new_candidate_bbox.y1 = (box_y - (box_h / 2)); + new_candidate_bbox.x2 = (box_x + (box_w / 2)); + new_candidate_bbox.y2 = (box_y + (box_h / 2)); + + new_candidate_bbox.score = score; + new_candidate_bbox.class_num = max_score_class; + + ex_update_candidate_bbox_list(&new_candidate_bbox, + YOLO_V3_MAX_BOX_NUM, + bbox, + &good_box_count, + &max_candidate_idx, + &min_candidate_idx); + } + } + } + } + } + + // do NMS + result->box_count = ex_nms_bbox_for_post_yolov3_no_sigmoid(gp->bboxes_v3, + gp->result_tmp_s, + class_num, + good_box_count, + max_detection_box_num, + max_detection_box_num, + result->boxes, + 0, + iou_threshold); + + // remap boxes to original coordinates + for (int i = 0; i < result->box_count; i++) + ex_remap_bbox(image_p, &result->boxes[i], 0); + + return result->box_count; +} diff --git a/build/solution_kdp2_evb_verify/main_ncpu/user_pre_process.c b/build/solution_kdp2_evb_verify/main_ncpu/user_pre_process.c new file mode 100644 index 0000000..8e2ea1d --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_ncpu/user_pre_process.c @@ -0,0 +1,52 @@ +/* + * Kneron Example Pre-Processing driver + * + * Copyright (C) 2019 Kneron, Inc. All rights reserved. + * + */ + +#include +#include +#include +#include "base.h" +#include "kdpio.h" +#include "ipc.h" + +inline static int pad_up_16(int a) +{ + return ceil((float)a / 16) * 16; +} + +static void pre_proc_unsign_right_shift(uint8_t *src_p, uint8_t *dst_p, int row, int col, int bit_shift) +{ + int unit = 4; + unsigned int r; + int pad_col = pad_up_16(col); + + int len = pad_col * row * unit; + for (r = 0; r < len; r++) { + *(dst_p + r) = (*(src_p + r)) >> bit_shift; + } + return; +} + +// This function is to right-shift the input RGBA image (HeightxWidthxChannel: 224x224x4) for 1 bit +int user_pre_yolo(struct kdp_image_s *image_p) +{ + int out_row, out_col; + int input_radix, bit_shift; + uint8_t *src_p, *dst_p; + + out_row = DIM_INPUT_ROW(image_p); + out_col = DIM_INPUT_COL(image_p); + + input_radix = PREPROC_INPUT_RADIX(image_p); + bit_shift = 8 - input_radix; // 1 byte (8 bits) for every R/G/B/A data + + src_p = (uint8_t *)RAW_IMAGE_MEM_ADDR(image_p); + dst_p = (uint8_t *)PREPROC_INPUT_MEM_ADDR(image_p); + pre_proc_unsign_right_shift(src_p, dst_p, out_row, out_col, bit_shift); + + return 0; +} + diff --git a/build/solution_kdp2_evb_verify/main_scpu/application_init.c b/build/solution_kdp2_evb_verify/main_scpu/application_init.c new file mode 100644 index 0000000..db6df5c --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/application_init.c @@ -0,0 +1,94 @@ +/* + * Kneron Application initialization + * + * Copyright (C) 2022 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" + +// power manager +#include "kmdw_power_manager.h" + +// inference core +#include "kp_struct.h" +#include "kmdw_console.h" +#include "kmdw_inference_app.h" + +// inference app +#include "kdp2_inf_app_yolo.h" +#include "demo_customize_inf_single_model.h" +#include "demo_customize_inf_multiple_models.h" + +// inference client +#include "kdp2_usb_companion.h" + +#include "ip_test_all.h" + +#define MAX_IMAGE_COUNT 10 /**< MAX inference input queue slot count */ +#define MAX_RESULT_COUNT 10 /**< MAX inference output queue slot count */ + + +/** + * @brief To register AI applications + * @param[in] num_input_buf number of data inputs in list + * @param[in] inf_input_buf_list list of data input for inference task + * @return N/A + * @note Add a switch case item for a new inf_app application + */ +static void _app_func(int num_input_buf, void** inf_input_buf_list); + + +void _app_func(int num_input_buf, void** inf_input_buf_list) +{ + // check header stamp + if (0 >= num_input_buf) { + kmdw_printf("No input buffer for app function\n"); + return; + } + + kp_inference_header_stamp_t *header_stamp = (kp_inference_header_stamp_t *)inf_input_buf_list[0]; + uint32_t job_id = header_stamp->job_id; + + switch (job_id) + { + case KDP2_INF_ID_APP_YOLO: + kdp2_app_yolo_inference(job_id, num_input_buf, inf_input_buf_list); + break; + case KDP2_JOB_ID_APP_YOLO_CONFIG_POST_PROC: + kdp2_app_yolo_config_post_process_parameters(job_id, num_input_buf, inf_input_buf_list); + break; + case DEMO_KL520_CUSTOMIZE_INF_SINGLE_MODEL_JOB_ID: // a demo code implementation in SCPU for user-defined/customized infernece from one model + demo_customize_inf_single_model(job_id, num_input_buf, inf_input_buf_list); + break; + case DEMO_KL520_CUSTOMIZE_INF_MULTIPLE_MODEL_JOB_ID: // a demo code implementation in SCPU for user-defined/customized infernece from two models + demo_customize_inf_multiple_models(job_id, num_input_buf, inf_input_buf_list); + break; + default: + kmdw_inference_app_send_status_code(job_id, KP_FW_ERROR_UNKNOWN_APP); + break; + } +} + + +void app_initialize(void) +{ + info_msg(">> Start running KL520 KDP2 companion mode ...\n"); + + /* for shutdown command */ + kmdw_power_manager_init(); + + /* initialize inference app */ + /* register APP functions */ + /* specify depth of inference queues */ + kmdw_inference_app_init(_app_func, MAX_IMAGE_COUNT, MAX_RESULT_COUNT); + + /* companion mode init */ + kdp2_usb_companion_init(); + + /* IP verification tests */ + ip_test_all_init(); + + return; +} diff --git a/build/solution_kdp2_evb_verify/main_scpu/device_init.c b/build/solution_kdp2_evb_verify/main_scpu/device_init.c new file mode 100644 index 0000000..bbfa991 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/device_init.c @@ -0,0 +1,25 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +#include "project.h" +#if defined(FLASH_TYPE) && (FLASH_TYPE == FLASH_TYPE_NULL) +#include "kdev_flash_null.h" +#else +#include "kdev_flash.h" +#endif + +//Function +void dev_initialize(void) +{ + kdev_flash_initialize(); +} + diff --git a/build/solution_kdp2_evb_verify/main_scpu/driver_init.c b/build/solution_kdp2_evb_verify/main_scpu/driver_init.c new file mode 100644 index 0000000..481a97b --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/driver_init.c @@ -0,0 +1,28 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kdrv_uart.h" +#include "kdrv_ddr.h" +#include "kdrv_pinmux.h" +//#include "kdrv_power.h" + +static uint32_t pinmux_array[PIN_NUM] = PINMUX_ARRAY; + +void drv_initialize(void) +{ + kdrv_uart_initialize(); + kdrv_pinmux_initialize(PIN_NUM, pinmux_array); + kdrv_ddr_system_init(DDR_INIT_ALL); // TODO, not 720 style +} + diff --git a/build/solution_kdp2_evb_verify/main_scpu/hw_test_i2c.c b/build/solution_kdp2_evb_verify/main_scpu/hw_test_i2c.c new file mode 100644 index 0000000..3b6b501 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/hw_test_i2c.c @@ -0,0 +1,140 @@ +/* + * Kneron Hardware Test: I2C + * + * Copyright (C) 2023 Kneron, Inc. All rights reserved. + */ + +#include "cmsis_os2.h" +#include "kdrv_i2c.h" +#include "kdrv_pinmux.h" +#include "kmdw_console.h" + +// OV5647 Sensor specific defines +#define OV5647_I2C_ADDR 0x36 +#define OV5647_CHIP_ID_H_REG 0x300A +#define OV5647_CHIP_ID_L_REG 0x300B +#define OV5647_SYS_CTRL0_REG 0x0100 +#define OV5647_SW_RESET_REG 0x0103 + +// VEYE-MIPI-IMX462 Sensor specific defines +#define VEYE_IMX462_I2C_ADDR 0x3B + +int hw_test_i2c_run(void) +{ + kdrv_status_t status; + uint8_t found_devices = 0; + int result = -1; + + kmdw_printf("Starting I2C Bus Scan Test...\n"); + + // 1. Configure Pinmux for I2C0 + kmdw_printf("Configuring pins for I2C0...\n"); + kdrv_pinmux_config(KDRV_PIN_I2C0_SCL, PIN_MODE_0, PIN_PULL_NONE, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_I2C0_SDA, PIN_MODE_0, PIN_PULL_NONE, PIN_DRIVING_8MA); + + // 2. Initialize I2C0 + kmdw_printf("Initializing I2C0 at 100kHz...\n"); + status = kdrv_i2c_initialize(KDRV_I2C_CTRL_0, KDRV_I2C_SPEED_100K); + if (status != KDRV_STATUS_OK) { + kmdw_printf("I2C initialization failed. Status: %d\n", status); + return -1; + } + + // kmdw_printf("=========================================================\n"); + // kmdw_printf("Scanning I2C bus (addresses 0x01 to 0x7F)...\n"); + // kmdw_printf("=========================================================\n"); + + // for (uint16_t addr = 1; addr < 128; addr++) { + // // 3. Try to write a single null byte to probe the address. + // // The kdrv_i2c_write_register function is a bit complex for a simple probe. + // // A simpler `kdrv_i2c_master_write` or `kdrv_i2c_probe` would be ideal. + // // Let's try to use kdrv_i2c_write_register with a dummy write. + // // We send 0 bytes of data, but the address is sent on the bus. + // status = kdrv_i2c_write_register(KDRV_I2C_CTRL_0, addr, 0, 0, 0, NULL); + + // if (status == KDRV_STATUS_OK) { + // kmdw_printf("Found I2C device at address: 0x%02X\n", addr); + // found_devices++; + // } + + // // A short delay between probes + // osDelay(10); + // } + + // kmdw_printf("=========================================================\n"); + // kmdw_printf("I2C Bus Scan Summary:\n"); + // kmdw_printf(" Found %d device(s).\n", found_devices); + + kmdw_printf("=========================================================\n"); + kmdw_printf("Checking for OV5647 sensor at address 0x%02X...\n", OV5647_I2C_ADDR); + + uint8_t chip_id_h, chip_id_l; + uint16_t chip_id; + + // Read Chip ID High Byte + status = kdrv_i2c_read_register(KDRV_I2C_CTRL_0, OV5647_I2C_ADDR, OV5647_CHIP_ID_H_REG, 2, 1, &chip_id_h); + if (status != KDRV_STATUS_OK) { + kmdw_printf("Failed to communicate with device at 0x%02X. It might not be an OV5647 or is not connected.\n", OV5647_I2C_ADDR); + } else { + // Read Chip ID Low Byte + kdrv_i2c_read_register(KDRV_I2C_CTRL_0, OV5647_I2C_ADDR, OV5647_CHIP_ID_L_REG, 2, 1, &chip_id_l); + chip_id = ((uint16_t)chip_id_h << 8) | chip_id_l; + kmdw_printf(" Read Chip ID: 0x%04X\n", chip_id); + + if (chip_id == 0x5647) { + kmdw_printf(" OV5647 sensor detected successfully!\n"); + + result = 0; // Passed + // --- Additional Status Checks --- + // 1. Check System Status (Standby/Streaming) + uint8_t sys_status; + status = kdrv_i2c_read_register(KDRV_I2C_CTRL_0, OV5647_I2C_ADDR, OV5647_SYS_CTRL0_REG, 2, 1, &sys_status); + if (status == KDRV_STATUS_OK) { + kmdw_printf(" System Status (0x0100): 0x%02X -> %s\n", sys_status, (sys_status == 0x01) ? "Streaming" : "Standby"); + } else { + kmdw_printf(" Failed to read system status register (0x0100).\n"); + } + + // 2. Perform Software Reset and re-check ID + kmdw_printf(" Performing software reset...\n"); + uint8_t reset_val = 0x01; + status = kdrv_i2c_write_register(KDRV_I2C_CTRL_0, OV5647_I2C_ADDR, OV5647_SW_RESET_REG, 2, 1, &reset_val); + if (status != KDRV_STATUS_OK) { + kmdw_printf(" Failed to write software reset command.\n"); + } else { + osDelay(100); // Wait for the sensor to reset + status = kdrv_i2c_read_register(KDRV_I2C_CTRL_0, OV5647_I2C_ADDR, OV5647_CHIP_ID_H_REG, 2, 1, &chip_id_h); + if (status == KDRV_STATUS_OK) { + kmdw_printf(" Sensor responded after reset. -> PASSED\n"); + } else { + kmdw_printf(" Sensor did NOT respond after reset. -> FAILED\n"); + } + } + + } else { + kmdw_printf(" Device at 0x%02X is not an OV5647 (unexpected chip ID).\n", OV5647_I2C_ADDR); + } + } + +// kmdw_printf("---------------------------------------------------------\n"); +// kmdw_printf("Checking for VEYE-MIPI-IMX462 sensor at address 0x%02X...\n", VEYE_IMX462_I2C_ADDR); + +// // Probe for VEYE-MIPI-IMX462 +// // We use a 0-length write to check if the device ACKs the address. +// status = kdrv_i2c_write_register(KDRV_I2C_CTRL_0, VEYE_IMX462_I2C_ADDR, 0, 0, 0, NULL); + +// if (status == KDRV_STATUS_OK) { +// kmdw_printf(" VEYE-MIPI-IMX462 detected at 0x%02X! -> PASSED\n", VEYE_IMX462_I2C_ADDR); +// result = 0; // Passed if at least one supported sensor is found +// } else { +// kmdw_printf(" No response at 0x%02X. (Not connected or different address)\n", VEYE_IMX462_I2C_ADDR); +// } + + kmdw_printf("=========================================================\n"); + kmdw_printf("Test finished. Returning to main menu...\n"); + + // Uninitialize I2C controller + kdrv_i2c_uninitialize(KDRV_I2C_CTRL_0); + + return result; +} diff --git a/build/solution_kdp2_evb_verify/main_scpu/hw_test_pwm_adc.c b/build/solution_kdp2_evb_verify/main_scpu/hw_test_pwm_adc.c new file mode 100644 index 0000000..4199da4 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/hw_test_pwm_adc.c @@ -0,0 +1,127 @@ +#include "cmsis_os2.h" +#include "kdrv_gpio.h" +#include +#include "kdrv_uart.h" +#include "base.h" +#include "kmdw_console.h" +#include "kdrv_pinmux.h" +#include "kdrv_pwm.h" +#include "kdrv_adc.h" +#include "kdrv_timer.h" + +/*************************************************************************************************/ +/* Macro-Definitions */ +/*************************************************************************************************/ +/* + * !! Please modify the following definitions according to your hardware design !! + * You must use a jumper to actually connect the pins corresponding to PWM_PIN and ADC_PIN. + */ + +// 1. Select the physical PIN to use (refer to kdrv_pinmux.h for pin names) +#define PWM_PIN (KDRV_PIN_LC_DATA_12) // FIXME: Please replace with your actual PWM output pin + +// 2. Select PIN_MODE for the required function (refer to kdrv_pinmux.h or chip datasheet) +#define PWM_PIN_MODE (PIN_MODE_2) // FIXME: Please replace with the PWM mode corresponding to your selected pin + +// 3. Find the PWM channel and ADC channel corresponding to the selected PIN +#define PWM_CHANNEL (PWMTIMER6) // FIXME: Please replace with the corresponding PWM timer channel +#define ADC_CHANNEL (3) // FIXME: Please replace with the corresponding ADC channel + +// 4. Test parameters +#define PWM_FREQUENCY_HZ (1000) // PWM Frequency (Hz) +#define PWM_POLARITY (PWM_POLARITY_INVERSED) // 0 for active-high, 1 for active-low + +#define ADC_MAX_VALUE (1023) // ADC max value (e.g., 4095 for 12-bit, 1023 for 10-bit) +#define TEST_VOLTAGE_TOLERANCE (50) // Allowed ADC reading tolerance (e.g., allow 50 error within 0-4095 range) + +/*************************************************************************************************/ +/* Function Declarations */ +/*************************************************************************************************/ + +/** + * @brief Initialize hardware components, including Pinmux, UART, ADC, and PWM. + */ +static void hw_test_initialize(void) +{ + // Initialize UART for debug output + // kmdw_console_init() is usually called at system startup, so it is not repeated here + kmdw_printf("\n[ADC-PWM Loopback Test] Initializing...\n"); + + // -- Key Step: Configure Pin Function -- + // Configure PWM pin + kdrv_pinmux_config(PWM_PIN, PWM_PIN_MODE, PIN_PULL_NONE, PIN_DRIVING_8MA); + kmdw_printf("Pinmux configured: PWM on pin %d (mode %d)\n", PWM_PIN, PWM_PIN_MODE); + + // Initialize ADC peripheral + if (kdrv_adc_initialize() != KDRV_STATUS_OK) { + kmdw_printf("Error: ADC peripheral initialization failed!\n"); + while(1); + } + kmdw_printf("ADC Initialized\n"); + + kmdw_printf("Initialization complete. Please connect pin P29 to pin ADC3 with a jumper wire.\n"); + osDelay(3000); // Give user time to read message and connect wires +} + +/** + * @brief Run PWM to ADC loopback test + */ +int hw_test_pwm_adc_run(void) +{ + hw_test_initialize(); + + const uint32_t duty_cycles[] = {10, 40, 70, 90}; + const uint32_t num_steps = sizeof(duty_cycles) / sizeof(duty_cycles[0]); + uint32_t pass_count = 0, adc_value = 0; + + // Calculate period based on expected frequency (Unit: 10ns) + // Period (10ns) = (1 / Frequency Hz) / (1 / System Clock Hz) / 10ns + // = 1,000,000,000 ns / Frequency Hz / 10ns + const uint32_t period_10ns = 100000000 / PWM_FREQUENCY_HZ; + + kmdw_printf("\n======== Starting PWM-ADC Loopback Test ========\n"); + + for (int i = 0; i < num_steps; i++) { + uint32_t duty_percentage = duty_cycles[i]; + + // Calculate duty cycle (Unit: 10ns) + uint32_t duty_10ns = (period_10ns * duty_percentage) / 100; + + // 1. Configure PWM output + kdrv_pwm_config(PWM_CHANNEL, PWM_POLARITY, duty_10ns, period_10ns, 0); + + // Enable PWM channel + kdrv_pwm_enable(PWM_CHANNEL); + + // Delay to wait for voltage stability + osDelay(200); + + // 2. Read ADC value + adc_value = kdrv_adc_read(ADC_CHANNEL); + // 3. Compare with expected value + // Note: 100% duty cycle might not produce ADC_MAX_VALUE, depending on whether Vref is the same. This is an approximation. + uint32_t expected_value = (ADC_MAX_VALUE * duty_percentage) / 100; + int32_t diff = abs((int)adc_value - (int)expected_value); + + kmdw_printf("Test [Duty %3u%%]: Expected ADC ~%4u, Got ADC = %4u, Diff = %3d ... ", + duty_percentage, expected_value, adc_value, diff); + + if (diff <= TEST_VOLTAGE_TOLERANCE) { + kmdw_printf("PASS\n"); + pass_count++; + } else { + kmdw_printf("FAIL\n"); + } + kdrv_pwm_disable(PWM_CHANNEL); + osDelay(200); + } + + kmdw_printf("======== Test Cycle Complete ========\n"); + if (pass_count == num_steps) { + kmdw_printf("Result: ALL TESTS PASSED.\n"); + return 0; + } else { + kmdw_printf("Result: %u/%u tests FAILED. Check hardware connection/functionality.\n", num_steps - pass_count, num_steps); + return -1; + } +} diff --git a/build/solution_kdp2_evb_verify/main_scpu/hw_test_spi.c b/build/solution_kdp2_evb_verify/main_scpu/hw_test_spi.c new file mode 100644 index 0000000..22622d9 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/hw_test_spi.c @@ -0,0 +1,141 @@ +/* + * Kneron Hardware Test: SPI Loopback + * + * Copyright (C) 2023 Kneron, Inc. All rights reserved. + */ + +#include "cmsis_os2.h" +#include "kdrv_ssp.h" +#include "kdrv_pinmux.h" +#include "kdrv_clock.h" +#include "kdrv_gpio.h" +#include "kmdw_console.h" +#include + +#define SPI_PORT SSP_SPI_PORT0 +#define SPI_TEST_DATA_SIZE 16 + +extern struct st_ssp_spi driver_ssp_master_ctx; + +uint8_t kmdw_ssp_api_spi_init(kdrv_ssp_spi_dev_id_t handle, enum e_spi edata) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_master_ctx, edata, NULL ) == e_spi_ret_init_done ){ + return 1; + } + return 0; +} +uint8_t kmdw_ssp_api_spi_transfer(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_master_ctx, e_spi_tx, NULL ) == e_spi_ret_txbusy ){ + return 1; //rx data correct + } + else{ + return 0; //rx data fail + } +} + +uint8_t kmdw_ssp_api_spi_transfer_checks(kdrv_ssp_spi_dev_id_t handle) +{ + if( kdrv_ssp_statemachine( handle, &driver_ssp_master_ctx, e_spi_tx_status_check, NULL ) == e_spi_ret_txbusy ) + { + return 0; + } + else + { + return 1; + } +} + +void kmdw_ssp_api_spi_write_tx_buff( uint8_t *src, uint16_t nlen ) +{ + kdrv_ssp_write_buff( &driver_ssp_master_ctx, src, nlen ); +} +/** + * @brief SPI Master thread to send data and verify the loopback data. + */ +int hw_test_spi_run(void) +{ + uint8_t tx_data[SPI_TEST_DATA_SIZE]; + uint8_t rx_data[SPI_TEST_DATA_SIZE]; + int result = -1; + + kmdw_printf("[SPI TEST] External Loopback Test Thread started.\n"); + osDelay(10); + + kmdw_printf("Configuring pins for SPI0 Loopback...\n"); + kmdw_printf("Please connect pins: LC_DATA_6 (MOSI) <-> LC_DATA_7 (MISO)\n"); + + // 1. Enable SSP clocks. This is crucial for the SPI peripheral to work. + kdrv_clock_enable(CLK_SSP0_0_SSPCLK); + kdrv_clock_enable(CLK_SSP0_1_SSPCLK); + + kdrv_clock_enable(CLK_SSP1_0_SSPCLK); + kdrv_clock_enable(CLK_SSP1_1_SSPCLK); + + // 2. Configure Pinmux for SSP0. + kdrv_pinmux_config(KDRV_PIN_LC_DATA_4, PIN_MODE_4, PIN_PULL_NONE, PIN_DRIVING_8MA); // SSP0_CLK + kdrv_pinmux_config(KDRV_PIN_LC_DATA_5, PIN_MODE_4, PIN_PULL_NONE, PIN_DRIVING_8MA); // SSP0_CS + kdrv_pinmux_config(KDRV_PIN_LC_DATA_6, PIN_MODE_4, PIN_PULL_NONE, PIN_DRIVING_8MA); // SSP0_MOSI + kdrv_pinmux_config(KDRV_PIN_LC_DATA_7, PIN_MODE_4, PIN_PULL_UP, PIN_DRIVING_8MA); // SSP0_MISO + + // 1. Prepare test data + for (int i = 0; i < SPI_TEST_DATA_SIZE; i++) { + tx_data[i] = (uint8_t)(0xA0 + i); + } + memset(rx_data, 0, SPI_TEST_DATA_SIZE); + + // 2. Initialize SSP in master mode + kmdw_printf("[SPI TEST] Initializing SSP0 in master mode...\n"); + if (kmdw_ssp_api_spi_init(SPI_PORT, e_spi_init_master) != 1) { + kmdw_printf("[SPI TEST] SSP0 initialization failed.\n"); + return -1; + } + + // 3. Perform transfer + kmdw_printf("[SPI TEST] Transferring data...\n"); + kmdw_ssp_api_spi_write_tx_buff(tx_data, SPI_TEST_DATA_SIZE); + + kdrv_ssp_spi_CS_set(KDRV_PIN_LC_DATA_5, SPI_CS_LOW); + kmdw_ssp_api_spi_transfer(SPI_PORT); + + uint32_t timeout = 1000; // 1000ms timeout + while (!kmdw_ssp_api_spi_transfer_checks(SPI_PORT) && timeout > 0) { + osDelay(1); + timeout--; + } + if (timeout == 0) { + kmdw_printf("[SPI TEST] Error: Transfer timed out!\n"); + } + + // Add a robust check to ensure the SPI bus is no longer busy. + // while (kdrv_ssp_busy(SPI_PORT)); + + kdrv_ssp_spi_CS_set(KDRV_PIN_LC_DATA_5, SPI_CS_HI); + + // 4. Read received data from FIFO + uint8_t nsize = kdrv_ssp_rxfifo_valid_entries(driver_ssp_master_ctx.port_no); + if (nsize) { + driver_ssp_master_ctx.Rx_buffer_index = 0; + kdrv_ssp_rx_polling_receive_all(&driver_ssp_master_ctx); + memcpy(rx_data, (void *)driver_ssp_master_ctx.Rx_buffer, nsize); + } + + // 5. Compare results + if (memcmp(tx_data, rx_data, SPI_TEST_DATA_SIZE) == 0) { + kmdw_printf("-> SPI Loopback Test PASSED\n"); + result = 0; + } else { + kmdw_printf("-> SPI Loopback Test FAILED\n"); + kmdw_printf(" TX Data: "); + for(int i=0; i +#include +#include +#include "cmsis_os2.h" +#include "kmdw_console.h" + +extern int hw_test_gpio_run(void); +extern int hw_test_spi_run(void); +extern int hw_test_i2c_run(void); +extern int hw_test_pwm_adc_run(void); + +void ip_test_all_thread(void *arg) { + int res_gpio, res_spi, res_i2c, res_pwm_adc; + + osDelay(1000); + + kmdw_printf("\n\n"); + kmdw_printf("************************************************\n"); + kmdw_printf("* KL520 IP Verification Auto-Test *\n"); + kmdw_printf("************************************************\n"); + kmdw_printf("Please ensure all loopback jumpers are connected:\n"); + kmdw_printf("1. GPIO Loopbacks (P37-P36, P34-P32, P27-P26, P35-P38)\n"); + kmdw_printf("2. SPI0 Loopback (MOSI - MISO)\n"); + kmdw_printf("3. PWM-ADC Loopback (P29 - ADC3)\n"); + kmdw_printf("4. I2C Sensor connected (OV5647)\n"); + kmdw_printf("Test starting in 3 seconds...\n"); + osDelay(3000); + + kmdw_printf("\n>>> Running GPIO Test...\n"); + res_gpio = hw_test_gpio_run(); + + kmdw_printf("\n>>> Running SPI Test...\n"); + osDelay(10); + res_spi = hw_test_spi_run(); + + kmdw_printf("\n>>> Running I2C Test...\n"); + osDelay(10); + res_i2c = hw_test_i2c_run(); + + kmdw_printf("\n>>> Running PWM-ADC Test...\n"); + osDelay(10); + res_pwm_adc = hw_test_pwm_adc_run(); + + kmdw_printf("\n\n"); + kmdw_printf("================================================\n"); + kmdw_printf(" Auto-Test Summary \n"); + kmdw_printf("================================================\n"); + kmdw_printf(" GPIO Test : %s\n", res_gpio == 0 ? "PASS" : "FAIL"); + kmdw_printf(" SPI Test : %s\n", res_spi == 0 ? "PASS" : "FAIL"); + kmdw_printf(" I2C Test : %s\n", res_i2c == 0 ? "PASS" : "FAIL"); + kmdw_printf(" PWM-ADC Test : %s\n", res_pwm_adc == 0 ? "PASS" : "FAIL"); + kmdw_printf("================================================\n"); + osDelay(10); + while (1) { + kmdw_printf("\n"); + kmdw_printf("--------------------------------\n"); + kmdw_printf(" IP Verification Menu \n"); + kmdw_printf("--------------------------------\n"); + kmdw_printf(" [1] GPIO Test\n"); + kmdw_printf(" [2] SPI Test\n"); + kmdw_printf(" [3] I2C Test\n"); + kmdw_printf(" [4] PWM-ADC Test\n"); + kmdw_printf(" [5] Run All Auto-Test Again\n"); + kmdw_printf("--------------------------------\n"); + kmdw_printf("Select test: "); + osDelay(10); + + char buf[64]; + int ch = 0; + + memset(buf, 0, sizeof(buf)); + kmdw_console_echo_gets(buf, sizeof(buf)); + + char *token = strtok(buf, " \r\n\t"); + if (token) ch = atoi(token); + + switch (ch) { + case 1: hw_test_gpio_run(); break; + case 2: hw_test_spi_run(); break; + case 3: hw_test_i2c_run(); break; + case 4: hw_test_pwm_adc_run(); break; + case 5: + kmdw_printf("\n>>> Running GPIO Test...\n"); + res_gpio = hw_test_gpio_run(); + kmdw_printf("\n>>> Running SPI Test...\n"); + res_spi = hw_test_spi_run(); + kmdw_printf("\n>>> Running I2C Test...\n"); + res_i2c = hw_test_i2c_run(); + kmdw_printf("\n>>> Running PWM-ADC Test...\n"); + res_pwm_adc = hw_test_pwm_adc_run(); + + kmdw_printf("================================================\n"); + kmdw_printf(" GPIO: %s | SPI: %s | I2C: %s | PWM-ADC: %s\n", + res_gpio == 0 ? "PASS" : "FAIL", + res_spi == 0 ? "PASS" : "FAIL", + res_i2c == 0 ? "PASS" : "FAIL", + res_pwm_adc == 0 ? "PASS" : "FAIL"); + break; + default: kmdw_printf("Invalid selection.\n"); break; + } + osDelay(500); + } +} + +void ip_test_all_init(void) { + + const osThreadAttr_t attr = { + .name = "IP_Test_All", + .stack_size = 2048, + .priority = osPriorityNormal, + }; + osThreadNew(ip_test_all_thread, NULL, &attr); +} diff --git a/build/solution_kdp2_evb_verify/main_scpu/ip_test_gpio.c b/build/solution_kdp2_evb_verify/main_scpu/ip_test_gpio.c new file mode 100644 index 0000000..35137c2 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/ip_test_gpio.c @@ -0,0 +1,125 @@ +/* + * Kneron Hardware Test: GPIO + * + * Copyright (C) 2023 Kneron, Inc. All rights reserved. + */ + +#include "cmsis_os2.h" +#include "kdrv_pinmux.h" +#include "kdrv_gpio.h" +#include "kmdw_console.h" + +// Define a structure to hold a pair of GPIO pins for loopback testing. +typedef struct { + uint32_t pin_a_num; + const char* pin_a_name; + uint32_t pin_b_num; + const char* pin_b_name; +} gpio_pair_t; + +// Centralize all GPIO test pairs in one array. +static const gpio_pair_t gpio_test_pairs[] = { + {GPIO_PIN_25, "P37", GPIO_PIN_26, "P36"}, + {GPIO_PIN_23, "P34", GPIO_PIN_4, "P32"}, + {GPIO_PIN_21, "P27", GPIO_PIN_20, "P26"}, + {GPIO_PIN_27, "P35", GPIO_PIN_24, "P38"} +}; +static const int num_pairs = sizeof(gpio_test_pairs) / sizeof(gpio_test_pairs[0]); + +// Helper function to run a single test case. +static void run_gpio_test_case(uint32_t output_pin_num, const char* output_pin_name, uint32_t input_pin_num, const char* input_pin_name, bool output_val, uint32_t *pass_count, uint32_t *fail_count) +{ + kdrv_gpio_write_pin((kdrv_gpio_pin_t)output_pin_num, output_val); + kmdw_printf("Set %-3s output to: %s, ", output_pin_name, output_val ? "High" : "Low"); + osDelay(10); // Short delay to ensure signal stability. + + uint32_t input_val = 0; + + kdrv_gpio_read_pin((kdrv_gpio_pin_t)input_pin_num, (bool *)&input_val); + + bool passed = ((bool)input_val == output_val); + kmdw_printf("Read %-3s input as: %s -> %s\n", input_pin_name, input_val ? "High" : "Low", passed ? "PASSED" : "FAILED"); + + if (passed) { + (*pass_count)++; + } else { + (*fail_count)++; + } +} + +int hw_test_gpio_run(void) +{ + // 1. Configure Pinmux + // Note: The comments for GPIO numbers seem to be copy-paste errors and may not be accurate. + // It's recommended to verify them against the hardware documentation. + kdrv_pinmux_config(KDRV_PIN_SD_DAT_1, PIN_MODE_3, PIN_PULL_NONE, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_SD_DAT_2, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_SD_CMD, PIN_MODE_3, PIN_PULL_NONE, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_LC_DATA_15, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_LC_DATA_10, PIN_MODE_3, PIN_PULL_NONE, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_LC_DATA_9, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_SD_DAT_3, PIN_MODE_3, PIN_PULL_NONE, PIN_DRIVING_8MA); + kdrv_pinmux_config(KDRV_PIN_SD_DAT_0, PIN_MODE_3, PIN_PULL_UP, PIN_DRIVING_8MA); + + // 2. Initialize GPIO controller + kdrv_gpio_initialize(); + + kmdw_printf("\n"); + kmdw_printf("=========================================================\n"); + kmdw_printf("Please connect GPIO pairs for loopback test:\n"); + kmdw_printf("P37-P36, P34-P32, P27-P26, P35-P38\n"); + kmdw_printf("The test will start in 1 seconds...\n"); + kmdw_printf("=========================================================\n"); + osDelay(1000); + + uint32_t pass_count = 0; + uint32_t fail_count = 0; + + // 3. First pass: Pin A is output, Pin B is input + kmdw_printf("--- Test Pass 1: A->B ---\n"); + for (int i = 0; i < num_pairs; i++) { + kdrv_gpio_set_attribute((kdrv_gpio_pin_t)gpio_test_pairs[i].pin_a_num, GPIO_DIR_OUTPUT); + kdrv_gpio_set_attribute((kdrv_gpio_pin_t)gpio_test_pairs[i].pin_b_num, GPIO_DIR_INPUT); + } + + for (int i = 0; i < num_pairs; i++) { + const gpio_pair_t* pair = &gpio_test_pairs[i]; + run_gpio_test_case(pair->pin_a_num, pair->pin_a_name, pair->pin_b_num, pair->pin_b_name, false, &pass_count, &fail_count); // Test Low + run_gpio_test_case(pair->pin_a_num, pair->pin_a_name, pair->pin_b_num, pair->pin_b_name, true, &pass_count, &fail_count); // Test High + kmdw_printf("\n"); + osDelay(50); + } + + kmdw_printf("=========================================================\n"); + kmdw_printf("Now swapping input/output roles and testing again...\n"); + kmdw_printf("=========================================================\n"); + osDelay(1000); + + // 4. Second pass: Pin B is output, Pin A is input (roles swapped) + kmdw_printf("--- Test Pass 2: B->A ---\n"); + for (int i = 0; i < num_pairs; i++) { + kdrv_gpio_set_attribute((kdrv_gpio_pin_t)gpio_test_pairs[i].pin_a_num, GPIO_DIR_INPUT); + kdrv_gpio_set_attribute((kdrv_gpio_pin_t)gpio_test_pairs[i].pin_b_num, GPIO_DIR_OUTPUT); + } + + for (int i = 0; i < num_pairs; i++) { + const gpio_pair_t* pair = &gpio_test_pairs[i]; + run_gpio_test_case(pair->pin_b_num, pair->pin_b_name, pair->pin_a_num, pair->pin_a_name, false, &pass_count, &fail_count); // Test Low + run_gpio_test_case(pair->pin_b_num, pair->pin_b_name, pair->pin_a_num, pair->pin_a_name, true, &pass_count, &fail_count); // Test High + kmdw_printf("\n"); + osDelay(50); + } + + kmdw_printf("=========================================================\n"); + kmdw_printf("GPIO Test Summary:\n"); + kmdw_printf(" PASSED: %d\n", pass_count); + kmdw_printf(" FAILED: %d\n", fail_count); + kmdw_printf("=========================================================\n"); + kmdw_printf("Test finished. Returning to main menu...\n"); + osDelay(1000); + if (fail_count == 0) { + return 0; + } else { + return -1; + } +} diff --git a/build/solution_kdp2_evb_verify/main_scpu/main.c b/build/solution_kdp2_evb_verify/main_scpu/main.c new file mode 100644 index 0000000..60e1db3 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/main.c @@ -0,0 +1,57 @@ +/* + * Kneron Main Entry driver + * + * Copyright (C) 2020 Kneron, Inc. All rights reserved. + * + */ + +#include +#include "cmsis_os2.h" // ARM::CMSIS:RTOS2:Keil RTX5 + +#include "project.h" +#include "version.h" + +// Customized configration and implimentation +#include "system_init.h" +#include "driver_init.h" +#include "device_init.h" +#include "middleware_init.h" +#include "application_init.h" + +#include "kmdw_console.h" + +extern void task_initialize(void); + +/** + * @brief main, main function + */ +int main(void) +{ + osKernelInitialize(); // Initialize CMSIS-RTOS + sys_initialize(); + drv_initialize(); /* customize driver initialization, see driver_init.c */ + dev_initialize(); /* customize device initialization, see device_init.c */ + mdw_initialize(); /* customize middleware initialization, see middlewre_init.c */ + + + printf("SDK v%u.%u.%u-:build.%03u\n", + (uint8_t)(IMG_FW_MAJOR), + (uint8_t)(IMG_FW_MINOR), + (uint8_t)(IMG_FW_UPDATE), + (uint32_t)(IMG_FW_BUILD)); + + app_initialize(); /* customize application initialization, see application_init.c */ + + /* New task threads */ + task_initialize(); + + /* Start RTOS Kernel */ + if (osKernelGetState() == osKernelReady) + { + osKernelStart(); + } + + while (1) + { + } +} diff --git a/build/solution_kdp2_evb_verify/main_scpu/middleware_init.c b/build/solution_kdp2_evb_verify/main_scpu/middleware_init.c new file mode 100644 index 0000000..fcdb7b3 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/middleware_init.c @@ -0,0 +1,31 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + +#include "project.h" + +#include "kmdw_memory.h" +#include "kmdw_model.h" +#include "kmdw_dfu.h" +#include "kmdw_console.h" + +void mdw_initialize(void) +{ + kmdw_ddr_init(DDR_HEAP_BEGIN, DDR_HEAP_END); + kmdw_ddr_store_system_reserve(DDR_SYSTEM_RESERVED_BEGIN, DDR_SYSTEM_RESERVED_END); + kmdw_uart_console_init(MSG_PORT, MSG_PORT_BAUDRATE); // uart console + kmdw_dfu_init(NULL, NULL); + kmdw_model_init(); + + // FW is loaded by fw_loader + //load_ncpu_fw(1/*reset_flag*/); // (kmdw_system.h) load ncpu fw from flash +} + diff --git a/build/solution_kdp2_evb_verify/main_scpu/system_init.c b/build/solution_kdp2_evb_verify/main_scpu/system_init.c new file mode 100644 index 0000000..a89c8f3 --- /dev/null +++ b/build/solution_kdp2_evb_verify/main_scpu/system_init.c @@ -0,0 +1,23 @@ +/******************************************************************** + * Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + ********************************************************************/ + //Include +//#include "project.h" +#include "kdrv_system.h" + + + //Function +void sys_initialize(void) +{ + /* SDK main init for companion mode */ + kdrv_system_init(); + kdrv_system_init_ncpu(); +} diff --git a/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.sct b/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.sct new file mode 100644 index 0000000..0260f1e --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.sct @@ -0,0 +1,19 @@ +#!armcc -E +#define DRAM_START 0x0FFF0000 +#define DRAM_SIZE 0x00010000 + +LR_IROM1 0x00000000 0x00010000 { ; load region size_region + ER_IROM1 0x00000000 0x00010000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 DRAM_START DRAM_SIZE-8 { ; RW data + .ANY (+RW +ZI) + } + + RW_IRAM2 AlignExpr(+0,8) { + .ANY (misc_data) + } +} + diff --git a/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.uvoptx b/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.uvoptx new file mode 100644 index 0000000..1ad4186 --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.uvoptx @@ -0,0 +1,576 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + ncpu + 0x4 + ARM-ADS + + 250000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + DLGDARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ULP2CM3 + -UAny -O905 -S0 -C0 -P00 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP18 -TDX0 -TDD0 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO3 -FD20000000 -FC1000 -FN0 + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + -T0 + + + 0 + JL2CM3 + -U63610859 -O1 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST1 -N00("ARM CoreSight JTAG-DP") -D00(4BA00477) -L00(4) -N01("ARM CoreSight JTAG-DP") -D01(4BA00477) -L01(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO1 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + + + + + 0 + 0 + 169 + 1 +
0
+ 0 + 0 + 0 + 0 + 0 + 0 + D:\3_code\mozart_sw_kdp2.git\scpu\project\companion_kdp2\main\main.c + + + + + + + 1 + 2 + 0x30ff0140 + 0 + + + + + 2 + 2 + 0x61000000 + 0 + + + + + 3 + 2 + 0xa0000000 + 0 + + + + + 4 + 2 + 0 + 0 + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + main + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\main.c + main.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\user_pre_process.c + user_pre_process.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\user_post_process.c + user_post_process.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\main_ncpu\model_ftr_table.c + model_ftr_table.c + 0 + 0 + + + + + libs + 1 + 0 + 0 + 0 + + 2 + 5 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + kdp2_ncpu_sdk.lib + 0 + 0 + + + 2 + 6 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + kdp2_ncpu_model_ppp.lib + 0 + 0 + + + + + rtx + 0 + 0 + 0 + 0 + + 3 + 7 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + irq_cm4f.s + 0 + 0 + + + 3 + 8 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + os_systick.c + 0 + 0 + + + 3 + 9 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + RTX_Config.c + 0 + 0 + + + 3 + 10 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + rtx_delay.c + 0 + 0 + + + 3 + 11 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + rtx_evflags.c + 0 + 0 + + + 3 + 12 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + rtx_evr.c + 0 + 0 + + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + rtx_kernel.c + 0 + 0 + + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + rtx_lib.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + rtx_memory.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + rtx_mempool.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + rtx_msgqueue.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + rtx_mutex.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + rtx_semaphore.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + rtx_system.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + rtx_thread.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + + + startup + 1 + 0 + 0 + 0 + + 4 + 23 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + startup.c + 0 + 0 + + + 4 + 24 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + diff --git a/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.uvprojx b/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.uvprojx new file mode 100644 index 0000000..dad3df7 --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/ncpu.uvprojx @@ -0,0 +1,557 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + ncpu + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.6.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + Mozart_ncpu + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_ncpu.bin" + post_build.bat fw_ncpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x10000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0xfff0000 + 0x10000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + ARM_MATH_CM4, TARGET_NCPU, LOG_ENABLE, KL520 + + ..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\ncpu\rtos\rtx\include;..\..\..\..\platform\kl520\ncpu\drv\include;..\..\..\..\platform\kl520\ncpu\model_ppp\include;..\..\..\..\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + --cpreproc + + + ..\..\..\..\include + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x00000000 + 0x20000000 + + ..\..\..\..\platform\kl520\ncpu\mozart_ncpu.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_ncpu\main.c + + + user_pre_process.c + 1 + ..\..\main_ncpu\user_pre_process.c + + + user_post_process.c + 1 + ..\..\main_ncpu\user_post_process.c + + + model_ftr_table.c + 1 + ..\..\main_ncpu\model_ftr_table.c + + + + + libs + + + kdp2_ncpu_sdk.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_sdk.lib + + + kdp2_ncpu_model_ppp.lib + 4 + ..\..\..\..\lib\kdp2_ncpu_model_ppp.lib + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\ncpu\rtos\rtx\rtx_timer.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\ncpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\ncpu\startup\startup_asm.s + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + diff --git a/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/post_build.bat b/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/post_build.bat new file mode 100644 index 0000000..1ac5a9c --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/ncpu_keil/post_build.bat @@ -0,0 +1,10 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_ncpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ diff --git a/build/solution_kdp2_evb_verify/sn52096/proj.uvmpw b/build/solution_kdp2_evb_verify/sn52096/proj.uvmpw new file mode 100644 index 0000000..c38cafd --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/proj.uvmpw @@ -0,0 +1,20 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + + .\scpu_keil\scpu.uvprojx + 1 + + + + .\ncpu_keil\ncpu.uvprojx + + + diff --git a/build/solution_kdp2_evb_verify/sn52096/project.h b/build/solution_kdp2_evb_verify/sn52096/project.h new file mode 100644 index 0000000..b677458 --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/project.h @@ -0,0 +1,163 @@ +/* Copyright (c) 2020 Kneron, Inc. All Rights Reserved. + * + * The information contained herein is property of Kneron, Inc. + * Terms and conditions of usage are described in detail in Kneron + * STANDARD SOFTWARE LICENSE AGREEMENT. + * + * Licensees are granted free, non-transferable use of the information. + * NO WARRANTY of ANY KIND is provided. This heading must NOT be removed + * from the file. + */ + +/****************************************************************************** +* Filename: +* --------- +* project.h +* +* Description: +* ------------ +* +* +******************************************************************************/ + +#ifndef _PROJECT_H_ +#define _PROJECT_H_ + + +/*============================================================================= +asic setting +=============================================================================*/ +#include "membase.h" + +/*============================================================================= +board setting +=============================================================================*/ +#include "board.h" + +#define FLASH_TYPE FLASH_TYPE_WINBOND_NOR +#define FLASH_SIZE FLASH_SIZE_256MBIT +#define FLASH_COMM FLASH_COMM_SPEED_25MHZ +#define FLASH_DRV FLASH_DRV_NORMAL_MODE + +/*============================================================================= +COMM setting +=============================================================================*/ +#define UART_NUM 1 +#define MSG_PORT COMM_PORT_ID_0 +#define MSG_PORT_BAUDRATE COMM_UART_BAUDRATE_115200 + +/*============================================================================= +Pinmux setting +=============================================================================*/ +#define PIN_NUM 38 +#define KDRV_PIN_SPI_WP_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_SPI_HOLD_N_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TRST_N_REG PIN_MODE_0 | (PIN_PULL_DOWN << 3) | (PIN_DRIVING_12MA << 6) //0x00000090 +#define KDRV_PIN_JTAG_TDI_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWDITMS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_SWCLKTCK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_JTAG_TDO_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_LC_PCLK_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_VS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_HS_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DE_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_1_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_2_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_LC_DATA_3_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_4_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_5_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_6_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_7_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_8_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_9_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_10_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_11_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_12_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_13_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_14_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_LC_DATA_15_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_8MA << 6) //0x00000040 +#define KDRV_PIN_SD_CLK_REG PIN_MODE_1 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000081 +#define KDRV_PIN_SD_CMD_REG PIN_MODE_1 | (PIN_PULL_UP << 3) | (PIN_DRIVING_12MA << 6) //0x00000089 +#define KDRV_PIN_SD_DAT_0_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_1_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_2_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_SD_DAT_3_REG PIN_MODE_0 | (PIN_PULL_UP << 3) | (PIN_DRIVING_4MA << 6) //0x00000008 +#define KDRV_PIN_UART0_RX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_UART0_TX_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define KDRV_PIN_I2C0_SCL_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_I2C0_SDA_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_4MA << 6) //0x00000000 +#define KDRV_PIN_PWM0_REG PIN_MODE_0 | (PIN_PULL_NONE << 3) | (PIN_DRIVING_12MA << 6) //0x00000080 +#define PINMUX_ARRAY {KDRV_PIN_SPI_WP_N_REG, KDRV_PIN_SPI_HOLD_N_REG, KDRV_PIN_JTAG_TRST_N_REG, KDRV_PIN_JTAG_TDI_REG, KDRV_PIN_JTAG_SWDITMS_REG,\ + KDRV_PIN_JTAG_SWCLKTCK_REG, KDRV_PIN_JTAG_TDO_REG, KDRV_PIN_LC_PCLK_REG, KDRV_PIN_LC_VS_REG, KDRV_PIN_LC_HS_REG,\ + KDRV_PIN_LC_DE_REG, KDRV_PIN_LC_DATA_0_REG, KDRV_PIN_LC_DATA_1_REG, KDRV_PIN_LC_DATA_2_REG, KDRV_PIN_LC_DATA_3_REG,\ + KDRV_PIN_LC_DATA_4_REG, KDRV_PIN_LC_DATA_5_REG, KDRV_PIN_LC_DATA_6_REG, KDRV_PIN_LC_DATA_7_REG, KDRV_PIN_LC_DATA_8_REG,\ + KDRV_PIN_LC_DATA_9_REG, KDRV_PIN_LC_DATA_10_REG, KDRV_PIN_LC_DATA_11_REG, KDRV_PIN_LC_DATA_12_REG, KDRV_PIN_LC_DATA_13_REG,\ + KDRV_PIN_LC_DATA_14_REG, KDRV_PIN_LC_DATA_15_REG, KDRV_PIN_SD_CLK_REG, KDRV_PIN_SD_CMD_REG, KDRV_PIN_SD_DAT_0_REG,\ + KDRV_PIN_SD_DAT_1_REG, KDRV_PIN_SD_DAT_2_REG, KDRV_PIN_SD_DAT_3_REG, KDRV_PIN_UART0_RX_REG, KDRV_PIN_UART0_TX_REG,\ + KDRV_PIN_I2C0_SCL_REG, KDRV_PIN_I2C0_SDA_REG, KDRV_PIN_PWM0_REG}; + + +/*============================================================================= +fw setting +=============================================================================*/ +#define OS_DYNAMIC_MEM_SIZE (1024*32) /**< available memory size in RTX*/ + +/*============================================================================= +DDR configuration +=============================================================================*/ +/* DDR table */ +#define DDR_BEGIN DDR_MEM_BASE /**< = 0x60000000, definded in regbase.h*/ +#define DDR_END (DDR_MEM_BASE + DDR_MEM_SIZE - 1) /**< DDR end address */ + +/** Reserve for all_models.bin */ +#define DDR_MODEL_RESERVED_BEGIN KDP_DDR_BASE /**< space head for model data */ +#define DDR_MODEL_RESERVED_END 0x613FFFFF /**< space end for model data(initial boundary) */ + +/** Resseve for DDR heap. Allocation direction from END to BEGIN */ +#define DDR_HEAP_BEGIN 0x61400000 /**< space head for HEAP (initial boundary) */ +#define DDR_HEAP_END 0x63FCFFFF /**< space end for HEAP */ + +/** Reserve for system information, 188KB */ +#define DDR_SYSTEM_RESERVED_BEGIN 0x63FD0000 /**< space head for system info */ +#define DDR_SYSTEM_RESERVED_END 0x63FFEFFF /**< space end for system info */ + +/** Definition of snapshot image address and size, for kdrv_lcdc debug only*/ +#define KDP_DDR_SNAPSHOT_RGB_IMG_SIZE 0x96000 /* 640x480x2(RGB565) */ +#define KDP_DDR_SNAPSHOT_NIR_IMG_SIZE 0x4B000 /* 480x640x1(RAW8) */ +#define KDP_DDR_SNAPSHOT_RGB_IMG_ADDR DDR_MODEL_RESERVED_END +#define KDP_DDR_SNAPSHOT_NIR_IMG_ADDR (DDR_MODEL_RESERVED_END + KDP_DDR_SNAPSHOT_RGB_IMG_SIZE ) + +/*============================================================================= +Flash configuration +=============================================================================*/ +/* Flash table */ +#define FLASH_FW_SCPU0_ADDR 0x00002000 /**< fw_scpu.bin */ +#define FLASH_FW_NCPU0_ADDR 0x00018000 /**< fw_ncpu.bin */ +#define FLASH_FW_CFG0_ADDR 0x00028000 /**< boot_cfg0.bin */ +#define FLASH_FW_SCPU1_ADDR 0x00041000 /**< fw_scpu1.bin */ +#define FLASH_FW_NCPU1_ADDR 0x00057000 /**< fw_ncpu1.bin */ +#define FLASH_FW_CFG1_ADDR 0x00067000 /**< boot_cfg1.bin */ +#define FLASH_MODEL_FW_INFO_ADDR 0x00300000 /**< fw_info.bin */ +#define FLASH_MODEL_ALL_ADDR 0x00301000 /**< all_models.bin */ +#define FLASH_END_ADDR 0x01FFFFFF /**< end addr of 32MB flash */ + +#define FLASH_MINI_BLOCK_SIZE (4 * 1024) + +/*============================================================================= +mdw setting +=============================================================================*/ +/* scpu/ncpu image size */ +#define SCPU_IMAGE_SIZE (SiRAM_MEM_SIZE - 0x2000) +#define NCPU_IMAGE_SIZE NiRAM_MEM_SIZE + +/*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! +-->critical setting<-- +Below setting is for RD tuning or testing. +**Don't touch anything if you don't know what you are doing** +!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/ + + + + +#endif //_PROJECT_H_ diff --git a/build/solution_kdp2_evb_verify/sn52096/scpu_keil/kdp2_scpu_jlink.ini b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/kdp2_scpu_jlink.ini new file mode 100644 index 0000000..d4099c3 --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/kdp2_scpu_jlink.ini @@ -0,0 +1,13 @@ +MEMSET(0x10200000, 0x18000, 0) +MEMSET(0x10210000, 0x08000, 0) + +// to let USB know this is running in JTAG mode +MEMSET(0x10100000, 1, 0x01) +MEMSET(0x10100001, 1, 0xBA) +MEMSET(0x10100002, 1, 0xDC) +MEMSET(0x10100003, 1, 0xFE) + +_WDWORD(0xE000ED08, 0x10102000); +SP=_RDWORD(0x10104000) // Set Stack Pointer +PC=_RDWORD(0x10104004) // Set Program Counter = Reset_Handler +BS main \ No newline at end of file diff --git a/build/solution_kdp2_evb_verify/sn52096/scpu_keil/post_build.bat b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/post_build.bat new file mode 100644 index 0000000..f839167 --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/post_build.bat @@ -0,0 +1,12 @@ +@ECHO OFF +REM SET BIN_IN=%1 +REM SET BIN_OUT=fw_scpu.bin + +SET BIN_OUT=%1 + +SET UTILS_PATH=..\..\..\..\utils + +copy .\Objects\%BIN_OUT% %UTILS_PATH%\JLink_programmer\bin\ +copy .\Objects\%BIN_OUT% %UTILS_PATH%\bin_gen\flash_bin\ + + diff --git a/build/solution_kdp2_evb_verify/sn52096/scpu_keil/pre_build.bat b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/pre_build.bat new file mode 100644 index 0000000..dba1dc6 --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/pre_build.bat @@ -0,0 +1 @@ +REM "prebuild script" diff --git a/build/solution_kdp2_evb_verify/sn52096/scpu_keil/scpu.uvoptx b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/scpu.uvoptx new file mode 100644 index 0000000..260c18d --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/scpu.uvoptx @@ -0,0 +1,1197 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + dev + 0x4 + ARM-ADS + + 200000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 7 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + .\kdp2_scpu_jlink.ini + Segger\JL2CM3.dll + + + + 0 + DLGUARM + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(1012=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + JL2CM3 + -U59700618 -O64 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO5 -FD20000000 -FC1000 -FN0 + + + 0 + UL2CM3 + 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+ + 8 + 56 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\os_systick.c + os_systick.c + 0 + 0 + + + 8 + 57 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\RTX_Config.c + RTX_Config.c + 0 + 0 + + + 8 + 58 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_delay.c + rtx_delay.c + 0 + 0 + + + 8 + 59 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evflags.c + rtx_evflags.c + 0 + 0 + + + 8 + 60 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evr.c + rtx_evr.c + 0 + 0 + + + 8 + 61 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_kernel.c + rtx_kernel.c + 0 + 0 + + + 8 + 62 + 1 + 1 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_lib.c + rtx_lib.c + 0 + 0 + + + 8 + 63 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_memory.c + rtx_memory.c + 0 + 0 + + + 8 + 64 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mempool.c + rtx_mempool.c + 0 + 0 + + + 8 + 65 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_msgqueue.c + rtx_msgqueue.c + 0 + 0 + + + 8 + 66 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mutex.c + rtx_mutex.c + 0 + 0 + + + 8 + 67 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_semaphore.c + rtx_semaphore.c + 0 + 0 + + + 8 + 68 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_system.c + rtx_system.c + 0 + 0 + + + 8 + 69 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_thread.c + rtx_thread.c + 0 + 0 + + + 8 + 70 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + rtx_timer.c + 0 + 0 + + + 8 + 71 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + task_handler.c + 0 + 0 + + + + + startup + 0 + 0 + 0 + 0 + + 9 + 72 + 1 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + startup.c + 0 + 0 + + + 9 + 73 + 2 + 0 + 0 + 0 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + startup_asm.s + 0 + 0 + + + + + libs + 0 + 0 + 0 + 0 + + 10 + 74 + 4 + 0 + 0 + 0 + ..\..\..\..\lib\system_520.lib + system_520.lib + 0 + 0 + + + + diff --git a/build/solution_kdp2_evb_verify/sn52096/scpu_keil/scpu.uvprojx b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/scpu.uvprojx new file mode 100644 index 0000000..e9de7c0 --- /dev/null +++ b/build/solution_kdp2_evb_verify/sn52096/scpu_keil/scpu.uvprojx @@ -0,0 +1,898 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + dev + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + ARMCM4_FP + ARM + ARM.CMSIS.5.7.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000) + 0 + $$Device:ARMCM4_FP$Device\ARM\ARMCM4\Include\ARMCM4_FP.h + + + + + + + + + + $$Device:ARMCM4_FP$Device\ARM\SVD\ARMCM4.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + scpu_fw + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + pre_build.bat + + 0 + 0 + 0 + 0 + + + 1 + 1 + fromelf.exe --bin "!L" --output ".\Objects\fw_scpu.bin" + post_build.bat fw_scpu.bin + 0 + 0 + 0 + 0 + + 1 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 0 + 1 + 4099 + + 0 + Segger\JL2CM3.dll + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x0 + 0x40000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x10102000 + 0x16000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x10200000 + 0x16000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 4 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + --gnu + ARM_MATH_CM4, KL520, TARGET_SCPU, LOG_ENABLE + + ..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\kl520\scpu\drv\include;..\..\..\..\platform\kl520\scpu\rtos\rtx\include;..\..\..\..\platform\board\board_sn52096;..\..\..\..\platform\dev\include;..\..\..\..\mdw\include;..\..\..\..\mdw\inference;..\..\..\..\app;..\..\main_scpu\include;..\;..\..\..\lib\system_520\main_scpu\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + --cpreproc + + + ..\..\sn52096;..\..\..\..\include;..\..\..\..\platform\kl520\common;..\..\..\..\platform\board\board_sn52096 + + + + 0 + 0 + 0 + 0 + 0 + 0 + 0x10100000 + 0x10200000 + + ..\..\..\..\platform\kl520\scpu\scatter_load.sct + + + + + + + + + + + main + + + main.c + 1 + ..\..\main_scpu\main.c + + + project.h + 5 + ..\project.h + + + task_handler.h + 5 + ..\..\main_scpu\include\task_handler.h + + + application_init.c + 1 + ..\..\main_scpu\application_init.c + + + system_init.c + 1 + ..\..\main_scpu\system_init.c + + + device_init.c + 1 + ..\..\main_scpu\device_init.c + + + driver_init.c + 1 + ..\..\main_scpu\driver_init.c + + + middleware_init.c + 1 + ..\..\main_scpu\middleware_init.c + + + + + ip_verify + + + hw_test_i2c.c + 1 + ..\..\main_scpu\hw_test_i2c.c + + + hw_test_pwm_adc.c + 1 + ..\..\main_scpu\hw_test_pwm_adc.c + + + hw_test_spi.c + 1 + ..\..\main_scpu\hw_test_spi.c + + + ip_test_all.c + 1 + ..\..\main_scpu\ip_test_all.c + + + ip_test_gpio.c + 1 + ..\..\main_scpu\ip_test_gpio.c + + + + + inf_app + + + demo_customize_inf_single_model.c + 1 + ..\..\..\..\app\demo_customize_inf_single_model.c + + + demo_customize_inf_multiple_models.c + 1 + ..\..\..\..\app\demo_customize_inf_multiple_models.c + + + kdp2_inf_app_yolo.c + 1 + ..\..\..\..\app\kdp2_inf_app_yolo.c + + + + + inf_client + + + kdp2_cmd_handler_520.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_cmd_handler_520.c + + + kdp2_usb_companion.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_usb_companion.c + + + usbd_hal_520.c + 1 + ..\..\..\..\mdw\usb_companion\usbd_hal_520.c + + + kdp2_usb_log.c + 1 + ..\..\..\..\mdw\usb_companion\kdp2_usb_log.c + + + + + middleware + + + kmdw_memory.c + 1 + ..\..\..\..\mdw\memory\kmdw_memory.c + + + kmdw_memxfer.c + 1 + ..\..\..\..\mdw\flash\kmdw_memxfer.c + + + kmdw_console.c + 1 + ..\..\..\..\mdw\console\kmdw_console.c + + + kmdw_power_manager.c + 1 + ..\..\..\..\mdw\power\kmdw_power_manager.c + + + kmdw_dfu.c + 1 + ..\..\..\..\mdw\dfu\kmdw_dfu.c + + + kdp_crc.c + 1 + ..\..\..\..\mdw\utils\kmdw_utils_crc.c + + + kmdw_system.c + 1 + ..\..\..\..\mdw\system\kmdw_system.c + + + kmdw_ipc.c + 1 + ..\..\..\..\mdw\ipc\kmdw_ipc.c + + + kmdw_model.c + 1 + ..\..\..\..\mdw\model\kmdw_model.c + + + dual_fifo2.c + 1 + ..\..\..\..\mdw\inference\dual_fifo2.c + + + kdp2_inf_generic_raw.c + 1 + ..\..\..\..\mdw\inference\kdp2_inf_generic_raw.c + + + kmdw_inference_520.c + 1 + ..\..\..\..\mdw\inference\kmdw_inference_520.c + + + kmdw_fifoq_manager.c + 1 + ..\..\..\..\mdw\inference\kmdw_fifoq_manager.c + + + kdrv_i2c.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_i2c.c + + + kdrv_adc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_adc.c + + + kdrv_ssp.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ssp.c + + + + + device + + + kdev_flash_winbond.c + 1 + ..\..\..\..\platform\dev\flash\kdev_flash_winbond.c + + + + + driver + + + kdrv_pinmux.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pinmux.c + + + kdrv_gpio.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gpio.c + + + kdrv_spif.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_spif.c + + + kdrv_uart.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_uart.c + + + kdrv_ipc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ipc.c + + + kdrv_ncpu.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ncpu.c + + + 2 + 0 + 0 + 0 + 0 + 0 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + kdrv_usbd2.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2.c + + + kdrv_usbd2v.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_usbd2v.c + + + kdrv_clock.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_clock.c + + + kdrv_mpu.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_mpu.c + + + kdrv_ddr.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_ddr.c + + + kdrv_power.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_power.c + + + kdrv_system.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_system.c + + + kdrv_wdt.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_wdt.c + + + kdrv_gdma.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_gdma.c + + + rtc.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\rtc.c + + + kdrv_pwm.c + 1 + ..\..\..\..\platform\kl520\scpu\drv\kdrv_pwm.c + + + + + rtx + + + irq_cm4f.s + 2 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\irq_cm4f.s + + + os_systick.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\os_systick.c + + + RTX_Config.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\RTX_Config.c + + + rtx_delay.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_delay.c + + + rtx_evflags.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evflags.c + + + rtx_evr.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_evr.c + + + rtx_kernel.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_kernel.c + + + rtx_lib.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_lib.c + + + rtx_memory.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_memory.c + + + rtx_mempool.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mempool.c + + + rtx_msgqueue.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_msgqueue.c + + + rtx_mutex.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_mutex.c + + + rtx_semaphore.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_semaphore.c + + + rtx_system.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_system.c + + + rtx_thread.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_thread.c + + + rtx_timer.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\rtx_timer.c + + + task_handler.c + 1 + ..\..\..\..\platform\kl520\scpu\rtos\rtx\task_handler.c + + + + + startup + + + startup.c + 1 + ..\..\..\..\platform\kl520\scpu\startup\startup.c + + + startup_asm.s + 2 + ..\..\..\..\platform\kl520\scpu\startup\startup_asm.s + + + + + libs + + + system_520.lib + 4 + ..\..\..\..\lib\system_520.lib + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + RTE\Device\ARMCM4_FP\startup_ARMCM4.s + + + + + + RTE\Device\ARMCM4_FP\system_ARMCM4.c + + + + + + + + + + + scpu + 1 + + + + + diff --git a/utils/JLink_programmer/bin/fw_ncpu.bin b/utils/JLink_programmer/bin/fw_ncpu.bin index 6cc6d9278b77e379db4fc2e5f8c605af2aafb6ee..95def3b2e609a6bc11c9c98c67681160ff527859 100644 GIT binary patch delta 7415 zcmZWu30PD|wywIp(;!V0yV<*0q!CfTAUehf2$#(biBV@XN{kU)##YA!lS$B+j1srT ziV<-PW^tl3$tdb;+DHJ_VhtMMUEQU`5e3rszIeZ@d+pR@tr9#hxXK_nensy@$nsqHJ zziwG)Bt_Vi{`nq+{-H)F1b@|~)AO&0CO7i@EQBghd1W0!hwh+tE(boT$@qh}^BOMd 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